coreboot-gerrit December 2017

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Change in coreboot[master]: intel/bd82x6x: Add GBE ACPI device
by build bot (Jenkins) (Code Review) 10 Dec '17

10 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22807 ) Change subject: intel/bd82x6x: Add GBE ACPI device ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19166/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64352/ : SUCCESS -- To view, visit https://review.coreboot.org/22807 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I02613169498eed3d6d9ea5963ea3c2c08a40ef99 Gerrit-Change-Number: 22807 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Dec 2017 18:00:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nuvoton/nct6776: Add ACPI declarations
by build bot (Jenkins) (Code Review) 10 Dec '17

10 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22808 ) Change subject: nuvoton/nct6776: Add ACPI declarations ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19167/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64353/ : SUCCESS -- To view, visit https://review.coreboot.org/22808 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idb76b2e99e90a213e2695efc1afd4fa9069c134f Gerrit-Change-Number: 22808 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Dec 2017 17:39:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/sandybridge: Add RAM voltage hooks
by build bot (Jenkins) (Code Review) 10 Dec '17

10 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22806 ) Change subject: intel/sandybridge: Add RAM voltage hooks ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19165/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64351/ : SUCCESS -- To view, visit https://review.coreboot.org/22806 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic714c0717a66089dad4423d4eca5a0a29b7af817 Gerrit-Change-Number: 22806 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Dec 2017 17:39:27 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nuvoton/nct6776: Add ACPI declarations
by Tobias Diedrich (Code Review) 10 Dec '17

10 Dec '17

Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22808 Change subject: nuvoton/nct6776: Add ACPI declarations ...................................................................... nuvoton/nct6776: Add ACPI declarations Add ACPI declarations to be incorporated into ACPI tables for mainboards with this super I/O. Tested on Intel NUC DCP847SKE, Linux 4.13.14. SuperIO resources show up as reserved in /proc/ioports and friends. Change-Id: Idb76b2e99e90a213e2695efc1afd4fa9069c134f Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- M src/mainboard/intel/dcp847ske/acpi/superio.asl A src/superio/nuvoton/nct6776/acpi/superio.asl 2 files changed, 193 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/22808/1 diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl index 09f905e..aefb51d 100644 --- a/src/mainboard/intel/dcp847ske/acpi/superio.asl +++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl @@ -1 +1,28 @@ -/* Dummy file required by pch.asl - No license necessary. */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x4e + +#if !IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS) +#define NCT6776_SHOW_SP1 1 +#endif +#define NCT6776_SHOW_HWM 1 +#define NCT6776_SHOW_GPIO 1 + +#include "superio/nuvoton/nct6776/acpi/superio.asl" diff --git a/src/superio/nuvoton/nct6776/acpi/superio.asl b/src/superio/nuvoton/nct6776/acpi/superio.asl new file mode 100644 index 0000000..155917d --- /dev/null +++ b/src/superio/nuvoton/nct6776/acpi/superio.asl @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013, 2016 secunet Security Networks AG + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the NCT6886 SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x2 SP1 Implemented, untested + * 0x5 KBCK Implemented, untested + * 0x8 GPIO Implemented, untested + * 0xb HWM Implemented, untested + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * NCT6776_SHOW_SP1 If defined, Serial Port 1 will be exposed. + * NCT6776_SHOW_KBCK If defined, the Keyboard Controller will be exposed. + * NCT6776_SHOW_GPIO If defined, GPIO support will be exposed. + * NCT6776_SHOW_HWM If defined, the Environment Controller will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME NCT6776 +#include <superio/acpi/pnp.asl> + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Nuvoton NCT6776 Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8, + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + ACT1, 1, /* Logical device activation */ + ACT2, 1, /* Logical device activation */ + ACT3, 1, /* Logical device activation */ + ACT4, 1, /* Logical device activation */ + ACT5, 1, /* Logical device activation */ + ACT6, 1, /* Logical device activation */ + ACT7, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x64), + PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ + PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + } + + Method (_CRS) + { + /* Announce the used I/O ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + +#ifdef NCT6776_SHOW_SP1 + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef NCT6776_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 + #include <superio/acpi/pnp_kbc.asl> +#endif + +#ifdef NCT6776_SHOW_HWM + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_LDN 11 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IO1 0x08, 0x08 + #define SUPERIO_PNP_IRQ0 + #include <superio/acpi/pnp_generic.asl> +#endif + +#ifdef NCT6776_SHOW_GPIO + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #undef PNP_DEVICE_ACTIVE + #define PNP_DEVICE_ACTIVE ACT3 + #define SUPERIO_PNP_LDN 8 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #include <superio/acpi/pnp_generic.asl> +#endif +} -- To view, visit https://review.coreboot.org/22808 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idb76b2e99e90a213e2695efc1afd4fa9069c134f Gerrit-Change-Number: 22808 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>

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Change in coreboot[master]: intel/dcp847ske: Add Intel NUC DCP847SKE
by build bot (Jenkins) (Code Review) 10 Dec '17

10 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22683 ) Change subject: intel/dcp847ske: Add Intel NUC DCP847SKE ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19164/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64350/ : SUCCESS -- To view, visit https://review.coreboot.org/22683 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90 Gerrit-Change-Number: 22683 Gerrit-PatchSet: 5 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Dec 2017 17:30:18 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/bd82x6x: Add GBE ACPI device
by Tobias Diedrich (Code Review) 10 Dec '17

10 Dec '17

Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22807 Change subject: intel/bd82x6x: Add GBE ACPI device ...................................................................... intel/bd82x6x: Add GBE ACPI device Tested on Intel NUC DCP847SKE: systemd default network interface name changes from enp0s25 to eno1, which matches the Intel BIOS (though there it is due to SMBIOS data). Change-Id: I02613169498eed3d6d9ea5963ea3c2c08a40ef99 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- A src/southbridge/intel/bd82x6x/acpi/gbe.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl 2 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/22807/1 diff --git a/src/southbridge/intel/bd82x6x/acpi/gbe.asl b/src/southbridge/intel/bd82x6x/acpi/gbe.asl new file mode 100644 index 0000000..09a8318 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/gbe.asl @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel PCH Gigabit Ethernet 0:19.0 */ + +Device (GLAN) +{ + Name (_ADR, 0x00190000) + + // Power Resources for Wake + Name (_PRW, Package(){ + 13, // Bit 13 of GPE + 4 // Can wake from S4 state. + }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + * Arg3 - Function Arg + */ + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + // Device label GUID, used by systemd for naming. + If (Arg0 == ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D")) + { + Switch (ToInteger(Arg2)) { + // Function 0 (Report supported functions) + Case (0) { + // Supports functions 7 & 0 + Return (Buffer() { 0x81 }) + } + // Function 7 (DEVICE_LABEL_DSM) + Case (7) { + Return (Package(){ + 1, // Instance number + "LAN", // Optional name + }) + } + } + } + + // No functions supported for the given GUID + Return (Buffer() { 0 }) + } +} diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index cfa27d2..7d8d5df 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -234,6 +234,9 @@ } } +// Gigabit Ethernet 0:19.0 +#include "gbe.asl" + // High Definition Audio (Azalia) 0:1b.0 #include "audio.asl" -- To view, visit https://review.coreboot.org/22807 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I02613169498eed3d6d9ea5963ea3c2c08a40ef99 Gerrit-Change-Number: 22807 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>

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Change in coreboot[master]: intel/sandybridge: Add RAM voltage hooks
by Tobias Diedrich (Code Review) 10 Dec '17

10 Dec '17

Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22806 Change subject: intel/sandybridge: Add RAM voltage hooks ...................................................................... intel/sandybridge: Add RAM voltage hooks Some boards support low-voltage DDR3. This adds a hook for native raminit that is called before ram training and allows the romstage to set the RAM voltage first. Tested: - Measured voltage on Intel NUC DCP847SKE changes from 1.5V to 1.35V when the RAM SPD claims support Known issues: - Native raminit fails timC calibration with the RAM I have - Non-native raminit will continue to use the default voltage Change-Id: Ic714c0717a66089dad4423d4eca5a0a29b7af817 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- M src/mainboard/intel/dcp847ske/romstage.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/sandybridge/raminit_native.h M src/northbridge/intel/sandybridge/raminit_sandy.c 6 files changed, 32 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/22806/1 diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index ad31bba..cef6094 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -16,7 +16,9 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <stdint.h> +#include <southbridge/intel/common/gpio.h> #include <northbridge/intel/sandybridge/sandybridge.h> #if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) #include <northbridge/intel/sandybridge/raminit_native.h> @@ -24,7 +26,20 @@ #include <northbridge/intel/sandybridge/raminit.h> #endif -#if !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +void mainboard_set_dram_voltage(dimm_flags_t flags) +{ + if (flags.operable_1_35V) { + // GPIO8 default from gpio.c is LOW (1.5V). + // Set to HIGH to lower ram voltage to 1.35V. + set_gpio(8, 1); + } else if (!flags.operable_1_50V) { + // 1.50V _should_ be supported by any DDR3 ram that fits + // the connector... + printk(BIOS_ERR, "RAM does not support 1.35V or 1.5V!\n"); + } +} +#else void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index eaef5f7..92bd9c5 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -138,12 +138,16 @@ dimm_info *dimms = &ctrl->info; ctrl->cas_supported = (1 << (MAX_CAS - MIN_CAS + 1)) - 1; + ctrl->flags.raw = 0xffffffff; valid_dimms = 0; FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { const dimm_attr *dimm = &dimms->dimm[channel][slot]; if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) continue; valid_dimms++; + + /* Find common flags */ + ctrl->flags.raw &= dimm->flags.raw; /* Find all possible CAS combinations */ ctrl->cas_supported &= dimm->cas_supported; @@ -3363,3 +3367,7 @@ write32(DEFAULT_MCHBAR + 0x4ea8, 0); } + +void __attribute__((weak)) mainboard_set_dram_voltage(dimm_flags_t flags) +{ +} diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index ab6e592..c9f5c25 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -81,6 +81,7 @@ /* DDR base_freq = 100 Mhz / 133 Mhz */ u8 base_freq; + dimm_flags_t flags; u16 cas_supported; /* tLatencies are in units of ns, scaled by x256 */ u32 tCK; diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 675ac71..3df68c5 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -646,6 +646,9 @@ dram_dimm_mapping(ctrl); } + /* Set DRAM voltage */ + mainboard_set_dram_voltage(ctrl->flags); + /* Set MCU frequency */ dram_freq(ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index 2a91772..4744edd 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h @@ -22,5 +22,6 @@ /* The order is ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB. */ void read_spd(spd_raw_data *spd, u8 addr, bool id_only); void mainboard_get_spd(spd_raw_data *spd, bool id_only); +void mainboard_set_dram_voltage(dimm_flags_t flags); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index 3acc563..231159f 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -416,6 +416,9 @@ dram_dimm_mapping(ctrl); } + /* Set DRAM voltage */ + mainboard_set_dram_voltage(ctrl->flags); + /* Set MCU frequency */ dram_freq(ctrl); -- To view, visit https://review.coreboot.org/22806 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic714c0717a66089dad4423d4eca5a0a29b7af817 Gerrit-Change-Number: 22806 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>

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Change in coreboot[master]: sb/intel/common: Add function to automatically generate ACPI PIRQ
by Arthur Heymans (Code Review) 10 Dec '17

10 Dec '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/22803 ) Change subject: sb/intel/common: Add function to automatically generate ACPI PIRQ ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/22803/3/src/southbridge/intel/common/acpi_p… File src/southbridge/intel/common/acpi_pirq_gen.c: https://review.coreboot.org/#/c/22803/3/src/southbridge/intel/common/acpi_p… PS3, Line 43: } : > I'd suggest adding the acpigen here with a flag, so you can call this below what about defining it as a macro? https://review.coreboot.org/#/c/22803/3/src/southbridge/intel/common/acpi_p… PS3, Line 83: int_pin - 1 > pin to pirq mapping should be looked up in the register settings, in case i I know but that is too much of a mess to implement. bailing out on non reset default DxxIR might be a good idea though... -- To view, visit https://review.coreboot.org/22803 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2b5d68adabf0840162c6f295af8d10d8d3007a34 Gerrit-Change-Number: 22803 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Dec 2017 16:07:02 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: sb/intel/common: Add function to automatically generate ACPI PIRQ
by Tobias Diedrich (Code Review) 10 Dec '17

10 Dec '17

Tobias Diedrich has posted comments on this change. ( https://review.coreboot.org/22803 ) Change subject: sb/intel/common: Add function to automatically generate ACPI PIRQ ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/#/c/22803/3/src/southbridge/intel/common/acpi_p… File src/southbridge/intel/common/acpi_pirq_gen.c: https://review.coreboot.org/#/c/22803/3/src/southbridge/intel/common/acpi_p… PS3, Line 37: dublicate Typo: duplicate (below as well) https://review.coreboot.org/#/c/22803/3/src/southbridge/intel/common/acpi_p… PS3, Line 43: } : I'd suggest adding the acpigen here with a flag, so you can call this below instead of duplicating the loop twice, which seems error prone. https://review.coreboot.org/#/c/22803/3/src/southbridge/intel/common/acpi_p… PS3, Line 83: int_pin - 1 pin to pirq mapping should be looked up in the register settings, in case it was modified by the boards setup code. -- To view, visit https://review.coreboot.org/22803 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2b5d68adabf0840162c6f295af8d10d8d3007a34 Gerrit-Change-Number: 22803 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Dec 2017 16:01:12 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: sb/intel/i82801{g, j}x: Use common ACPI PIRQ function
by build bot (Jenkins) (Code Review) 10 Dec '17

10 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22805 ) Change subject: sb/intel/i82801{g,j}x: Use common ACPI PIRQ function ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19163/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64349/ : SUCCESS -- To view, visit https://review.coreboot.org/22805 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I456dca61419be9f2efd06fa966343a4b5ad6d5c6 Gerrit-Change-Number: 22805 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Dec 2017 15:25:12 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017