coreboot-gerrit November 2017

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Change in coreboot[master]: soc/intel/{APL, GLK}: Use Intel SRAM common code.
by build bot (Jenkins) (Code Review) 27 Nov '17

27 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22608 ) Change subject: soc/intel/{APL,GLK}: Use Intel SRAM common code. ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18678/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63800/ : SUCCESS -- To view, visit https://review.coreboot.org/22608 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If9f5d400df09b4a0aa4b464d7f1f24320696b0aa Gerrit-Change-Number: 22608 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 27 Nov 2017 07:26:48 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add Intel SRAM common code support
by build bot (Jenkins) (Code Review) 27 Nov '17

27 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22607 ) Change subject: soc/intel/common: Add Intel SRAM common code support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18677/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63799/ : SUCCESS -- To view, visit https://review.coreboot.org/22607 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7870a3ca09ac7b57eb551d5eb42d8361d22f362a Gerrit-Change-Number: 22607 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 27 Nov 2017 07:17:40 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/{APL, GLK}: Use Intel SRAM common code.
by V Sowmya (Code Review) 27 Nov '17

27 Nov '17

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/22608 Change subject: soc/intel/{APL,GLK}: Use Intel SRAM common code. ...................................................................... soc/intel/{APL,GLK}: Use Intel SRAM common code. Change-Id: If9f5d400df09b4a0aa4b464d7f1f24320696b0aa Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc D src/soc/intel/apollolake/sram.c 3 files changed, 1 insertion(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/22608/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index f568799..b21354e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -88,6 +88,7 @@ select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_SPI_FLASH_PROTECT + select SOC_INTEL_COMMON_BLOCK_SRAM select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 14932dd..5fc07ae 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -62,7 +62,6 @@ ramstage-y += pmutil.c ramstage-y += pmc.c ramstage-y += reset.c -ramstage-y += sram.c ramstage-y += xdci.c ramstage-y += sd.c diff --git a/src/soc/intel/apollolake/sram.c b/src/soc/intel/apollolake/sram.c deleted file mode 100644 index 70e1330..0000000 --- a/src/soc/intel/apollolake/sram.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/pci_devs.h> -#include <soc/iomap.h> - -static void read_resources(device_t dev) -{ - struct resource *res; - pci_dev_read_resources(dev); - - res = new_resource(dev, PCI_BASE_ADDRESS_0); - res->base = SRAM_BASE_0; - res->size = SRAM_SIZE_0; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, PCI_BASE_ADDRESS_2); - res->base = SRAM_BASE_2; - res->size = SRAM_SIZE_2; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void set_resources(device_t dev) -{ - struct resource *res; - pci_dev_set_resources(dev); - - res = find_resource(dev, PCI_BASE_ADDRESS_0); - pci_write_config32(dev, res->index, res->base); - dev->command |= PCI_COMMAND_MEMORY; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, " SRAM BAR 0"); - - res = find_resource(dev, PCI_BASE_ADDRESS_2); - pci_write_config32(dev, res->index, res->base); - dev->command |= PCI_COMMAND_MEMORY; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, " SRAM BAR 2"); -} - -static const struct device_operations device_ops = { - .read_resources = read_resources, - .set_resources = set_resources, - .enable_resources = pci_dev_enable_resources, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_INTEL_APL_SRAM, - PCI_DEVICE_ID_INTEL_GLK_SRAM, - 0, -}; - -static const struct pci_driver pmc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices= pci_device_ids, -}; -- To view, visit https://review.coreboot.org/22608 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If9f5d400df09b4a0aa4b464d7f1f24320696b0aa Gerrit-Change-Number: 22608 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com>

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Change in coreboot[master]: soc/intel/common: Add Intel SRAM common code support
by V Sowmya (Code Review) 27 Nov '17

27 Nov '17

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/22607 Change subject: soc/intel/common: Add Intel SRAM common code support ...................................................................... soc/intel/common: Add Intel SRAM common code support Add SRAM code support in intel/common/block to read and use fixed resources on BAR0 and BAR2 for SRAM. Change-Id: I7870a3ca09ac7b57eb551d5eb42d8361d22f362a Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- A src/soc/intel/common/block/sram/Kconfig A src/soc/intel/common/block/sram/Makefile.inc A src/soc/intel/common/block/sram/sram.c 3 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/22607/1 diff --git a/src/soc/intel/common/block/sram/Kconfig b/src/soc/intel/common/block/sram/Kconfig new file mode 100644 index 0000000..bfd1a8a --- /dev/null +++ b/src/soc/intel/common/block/sram/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_SRAM + bool + help + Intel Processor common SRAM support diff --git a/src/soc/intel/common/block/sram/Makefile.inc b/src/soc/intel/common/block/sram/Makefile.inc new file mode 100644 index 0000000..a490d91 --- /dev/null +++ b/src/soc/intel/common/block/sram/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SRAM) += sram.c diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c new file mode 100644 index 0000000..ab51c07 --- /dev/null +++ b/src/soc/intel/common/block/sram/sram.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/iomap.h> + +static void read_resources(device_t dev) +{ + struct resource *res; + pci_dev_read_resources(dev); + + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = SRAM_BASE_0; + res->size = SRAM_SIZE_0; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, PCI_BASE_ADDRESS_2); + res->base = SRAM_BASE_2; + res->size = SRAM_SIZE_2; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void set_resources(device_t dev) +{ + struct resource *res; + pci_dev_set_resources(dev); + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_MEMORY; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " SRAM BAR 0"); + + res = find_resource(dev, PCI_BASE_ADDRESS_2); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_MEMORY; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " SRAM BAR 2"); +} + +static const struct device_operations device_ops = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_APL_SRAM, + PCI_DEVICE_ID_INTEL_GLK_SRAM, + 0, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/22607 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7870a3ca09ac7b57eb551d5eb42d8361d22f362a Gerrit-Change-Number: 22607 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com>

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Change in coreboot[master]: mb/google/fizz: Enable Wake-on-Lan feature
by Furquan Shaikh (Code Review) 27 Nov '17

27 Nov '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/22606 ) Change subject: mb/google/fizz: Enable Wake-on-Lan feature ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/22606 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1178a776db2cdb448fe6650d49ae6c0281ac1128 Gerrit-Change-Number: 22606 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kevin Cheng <kevin.cheng(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 27 Nov 2017 06:53:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/fizz: Enable Wake-on-Lan feature
by build bot (Jenkins) (Code Review) 27 Nov '17

27 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22606 ) Change subject: mb/google/fizz: Enable Wake-on-Lan feature ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18676/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63798/ : SUCCESS -- To view, visit https://review.coreboot.org/22606 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1178a776db2cdb448fe6650d49ae6c0281ac1128 Gerrit-Change-Number: 22606 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kevin Cheng <kevin.cheng(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 27 Nov 2017 05:04:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/fizz: Enable Wake-on-Lan feature
by Gaggery Tsai (Code Review) 27 Nov '17

27 Nov '17

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/22606 Change subject: mb/google/fizz: Enable Wake-on-Lan feature ...................................................................... mb/google/fizz: Enable Wake-on-Lan feature This patch enables WOL feature. BUG=b:69290148 BRANCH=None TEST=powerd_dbus_suspend && sudo etherwake -i eth0 $MAC to make sure the system could be woken up by WOL packet. Change-Id: I1178a776db2cdb448fe6650d49ae6c0281ac1128 Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/22606/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 73a5c50..998b977 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -305,6 +305,7 @@ device pci 1c.0 on # PCI Express Port 1 chip drivers/net register "customized_leds" = "0x0fa7" + register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end end # PCI Express Port 1 -- To view, visit https://review.coreboot.org/22606 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1178a776db2cdb448fe6650d49ae6c0281ac1128 Gerrit-Change-Number: 22606 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: correct the SIO_EC_ENABLE_P2SK typo
by build bot (Jenkins) (Code Review) 27 Nov '17

27 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22586 ) Change subject: mb/google/poppy/variants/nautilus: correct the SIO_EC_ENABLE_P2SK typo ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18673/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63795/ : SUCCESS -- To view, visit https://review.coreboot.org/22586 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaded458e202bc975c73cd295f7b363e2c9bfa861 Gerrit-Change-Number: 22586 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Wang <chriswang(a)ami.com.tw> Gerrit-Reviewer: Chris Wang <chriswang(a)ami.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: shkim <sh_.kim(a)samsung.com> Gerrit-Comment-Date: Mon, 27 Nov 2017 03:21:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: set I2C speed to 400KHz
by build bot (Jenkins) (Code Review) 27 Nov '17

27 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22589 ) Change subject: mb/google/poppy/variants/nautilus: set I2C speed to 400KHz ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18675/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63797/ : SUCCESS -- To view, visit https://review.coreboot.org/22589 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icb48733b87cefc92577547b1eab661a8cbb12be6 Gerrit-Change-Number: 22589 Gerrit-PatchSet: 4 Gerrit-Owner: Chris Wang <chriswang(a)ami.com.tw> Gerrit-Reviewer: Chris Wang <chriswang(a)ami.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: shkim <sh_.kim(a)samsung.com> Gerrit-Comment-Date: Mon, 27 Nov 2017 03:19:54 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Change IA/GT/SA slow slew rate set...
by build bot (Jenkins) (Code Review) 27 Nov '17

27 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22588 ) Change subject: mb/google/poppy/variants/nautilus: Change IA/GT/SA slow slew rate settings ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18674/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63796/ : SUCCESS -- To view, visit https://review.coreboot.org/22588 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibf11aba7bafb3b02c510905d7d904507eee6394b Gerrit-Change-Number: 22588 Gerrit-PatchSet: 3 Gerrit-Owner: Chris Wang <chriswang(a)ami.com.tw> Gerrit-Reviewer: Chris Wang <chriswang(a)ami.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: shkim <sh_.kim(a)samsung.com> Gerrit-Comment-Date: Mon, 27 Nov 2017 03:16:46 +0000 Gerrit-HasComments: No

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coreboot-gerrit November 2017