coreboot-gerrit November 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_table
by build bot (Jenkins) (Code Review) 27 Nov '17

27 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22587 ) Change subject: mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_table ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18682/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63807/ : SUCCESS -- To view, visit https://review.coreboot.org/22587 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6 Gerrit-Change-Number: 22587 Gerrit-PatchSet: 5 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 27 Nov 2017 12:21:34 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_table
by build bot (Jenkins) (Code Review) 27 Nov '17

27 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22587 ) Change subject: mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_table ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/63806/ : SUCCESS -- To view, visit https://review.coreboot.org/22587 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6 Gerrit-Change-Number: 22587 Gerrit-PatchSet: 5 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 27 Nov 2017 12:17:24 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_table
by build bot (Jenkins) (Code Review) 27 Nov '17

27 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22587 ) Change subject: mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_table ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/63805/ : SUCCESS -- To view, visit https://review.coreboot.org/22587 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6 Gerrit-Change-Number: 22587 Gerrit-PatchSet: 5 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 27 Nov 2017 12:13:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_table
by Divya Chellappa (Code Review) 27 Nov '17

27 Nov '17

Divya Chellappa has uploaded a new patch set (#5). ( https://review.coreboot.org/22587 ) Change subject: mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_table ...................................................................... mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_table On shutdown, Soraka enters Deep S5 and not S5 state. Setting pad reset config of a gpio to RSMRST will not preserve the gpio config across deepSx and the gpio should be configured again. The WLAN_PE_RST signal should be brought up early in the bootflow for giving the device enough time to initialized before PCIE init in FSP-S. Hence, the gpio WLAN_PE_RST (GPP_B8) pad configuration is done in early pad configuration in bootblock also. BUG=b:64386481 BRANCH=none TEST= WiFi functionality across S5, S3, DeepS3, S0ix and warm/cold reboot. Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6 Signed-off-by: Divya Chellap <divya.chellappa(a)intel.com> --- M src/mainboard/google/poppy/variants/soraka/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/22587/5 -- To view, visit https://review.coreboot.org/22587 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6 Gerrit-Change-Number: 22587 Gerrit-PatchSet: 5 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: intel/common/block: Add SKL CSME device ID
by build bot (Jenkins) (Code Review) 27 Nov '17

27 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22610 ) Change subject: intel/common/block: Add SKL CSME device ID ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18680/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63802/ : SUCCESS -- To view, visit https://review.coreboot.org/22610 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic229c60e434d83eb4a3e5392ce90a7d47fddbd73 Gerrit-Change-Number: 22610 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 27 Nov 2017 08:13:10 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Make use of Intel common DSP block
by build bot (Jenkins) (Code Review) 27 Nov '17

27 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22609 ) Change subject: soc/intel/skylake: Make use of Intel common DSP block ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18679/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63801/ : SUCCESS -- To view, visit https://review.coreboot.org/22609 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8be2a90dc4e4c5eb196af57045d2a46b7f0c9722 Gerrit-Change-Number: 22609 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 27 Nov 2017 08:07:54 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/common/block: Add SKL CSME device ID
by Subrata Banik (Code Review) 27 Nov '17

27 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22610 Change subject: intel/common/block: Add SKL CSME device ID ...................................................................... intel/common/block: Add SKL CSME device ID This patch ensures SKL code is using CSME common PCI driver. TEST=Build and boot soraka/eve. Change-Id: Ic229c60e434d83eb4a3e5392ce90a7d47fddbd73 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cse/cse.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/22610/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 9fe7681..4a16143 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2911,6 +2911,7 @@ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a #define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a #define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0 +#define PCI_DEVICE_ID_INTEL_SKL_CSE0 0x9d3a /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d8a781e..77a9b63 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -508,6 +508,7 @@ PCI_DEVICE_ID_INTEL_APL_CSE0, PCI_DEVICE_ID_INTEL_GLK_CSE0, PCI_DEVICE_ID_INTEL_CNL_CSE0, + PCI_DEVICE_ID_INTEL_SKL_CSE0, 0, }; -- To view, visit https://review.coreboot.org/22610 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic229c60e434d83eb4a3e5392ce90a7d47fddbd73 Gerrit-Change-Number: 22610 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Make use of Intel common DSP block
by Subrata Banik (Code Review) 27 Nov '17

27 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22609 Change subject: soc/intel/skylake: Make use of Intel common DSP block ...................................................................... soc/intel/skylake: Make use of Intel common DSP block TEST=Build and boot soraka/eve. Change-Id: I8be2a90dc4e4c5eb196af57045d2a46b7f0c9722 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc D src/soc/intel/skylake/dsp.c M src/soc/intel/skylake/include/soc/pci_devs.h 6 files changed, 3 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/22609/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 0c78fab..9fe7681 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2905,6 +2905,7 @@ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 #define PCI_DEVICE_ID_INTEL_GLK_AUDIO 0x3198 #define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8 +#define PCI_DEVICE_ID_INTEL_SKL_AUDIO 0x9d70 /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 06384c7..5b4f932 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -29,6 +29,7 @@ PCI_DEVICE_ID_INTEL_APL_AUDIO, PCI_DEVICE_ID_INTEL_CNL_AUDIO, PCI_DEVICE_ID_INTEL_GLK_AUDIO, + PCI_DEVICE_ID_INTEL_SKL_AUDIO, 0, }; diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index e5cc4f7..053239a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -55,6 +55,7 @@ select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_CSE + select SOC_INTEL_COMMON_BLOCK_DSP select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index da45ec5..3a6dd2d 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -46,7 +46,6 @@ ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c ramstage-y += cpu.c -ramstage-y += dsp.c ramstage-y += elog.c ramstage-y += finalize.c ramstage-y += gpio.c diff --git a/src/soc/intel/skylake/dsp.c b/src/soc/intel/skylake/dsp.c deleted file mode 100644 index 13051a0..0000000 --- a/src/soc/intel/skylake/dsp.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/ramstage.h> - -static struct device_operations dsp_dev_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_static_bus, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver skylake_dsp __pci_driver = { - .ops = &dsp_dev_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x9d70 -}; diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 28f2f39..4fc8807 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -44,10 +44,6 @@ #define SA_DEVFN_IGD _SA_DEVFN(IGD) #define SA_DEV_IGD _SA_DEV(IGD) -#define SA_DEV_SLOT_DSP 0x04 -#define SA_DEVFN_DSP _SA_DEVFN(DSP) -#define SA_DEV_DSP _SA_DEV(DSP) - /* PCH Devices */ #define PCH_DEV_SLOT_ISH 0x13 -- To view, visit https://review.coreboot.org/22609 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8be2a90dc4e4c5eb196af57045d2a46b7f0c9722 Gerrit-Change-Number: 22609 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/{APL, GLK}: Use Intel SRAM common code.
by Subrata Banik (Code Review) 27 Nov '17

27 Nov '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/22608 ) Change subject: soc/intel/{APL,GLK}: Use Intel SRAM common code. ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/22608/1/src/soc/intel/apollolake/Kconfig File src/soc/intel/apollolake/Kconfig: https://review.coreboot.org/#/c/22608/1/src/soc/intel/apollolake/Kconfig@91 PS1, Line 91: order? -- To view, visit https://review.coreboot.org/22608 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If9f5d400df09b4a0aa4b464d7f1f24320696b0aa Gerrit-Change-Number: 22608 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 27 Nov 2017 07:46:24 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common: Add Intel SRAM common code support
by Subrata Banik (Code Review) 27 Nov '17

27 Nov '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/22607 ) Change subject: soc/intel/common: Add Intel SRAM common code support ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/22607/1/src/soc/intel/common/block/sram/sra… File src/soc/intel/common/block/sram/sram.c: https://review.coreboot.org/#/c/22607/1/src/soc/intel/common/block/sram/sra… PS1, Line 58: read_resources sram_read_resources https://review.coreboot.org/#/c/22607/1/src/soc/intel/common/block/sram/sra… PS1, Line 59: set_resources this can be replaced with pci_dev_set_resources as this one looks generic https://review.coreboot.org/#/c/22607/1/src/soc/intel/common/block/sram/sra… PS1, Line 60: .enable_resources = pci_dev_enable_resources, why no .init function here? its always better to have weak link for .init https://review.coreboot.org/#/c/22607/1/src/soc/intel/common/block/sram/sra… PS1, Line 69: pmc sram -- To view, visit https://review.coreboot.org/22607 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7870a3ca09ac7b57eb551d5eb42d8361d22f362a Gerrit-Change-Number: 22607 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 27 Nov 2017 07:45:50 +0000 Gerrit-HasComments: Yes

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coreboot-gerrit November 2017