coreboot-gerrit November 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: amd/stoneyridge: Add PSP definitions southbridge and iomap
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22250 ) Change subject: amd/stoneyridge: Add PSP definitions southbridge and iomap ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/62986/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/17948/ : SUCCESS -- To view, visit https://review.coreboot.org/22250 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I59a0ec59b7c6bbc6468b3096ec8d025832349f44 Gerrit-Change-Number: 22250 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 16:50:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Select fanless SMU firmware
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22251 ) Change subject: google/kahlee: Select fanless SMU firmware ...................................................................... Patch Set 3: No Builds Executed -- To view, visit https://review.coreboot.org/22251 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0761266f2a4026ebc251b64074c10481118734a2 Gerrit-Change-Number: 22251 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 16:50:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Add northbridge register macros
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22339 ) Change subject: amd/stoneyridge: Add northbridge register macros ...................................................................... Patch Set 1: No Builds Executed -- To view, visit https://review.coreboot.org/22339 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d Gerrit-Change-Number: 22339 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 16:50:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Add northbridge register macros
by Marshall Dawson (Code Review) 04 Nov '17

04 Nov '17

Marshall Dawson has uploaded a new patch set (#2). ( https://review.coreboot.org/22339 ) Change subject: amd/stoneyridge: Add northbridge register macros ...................................................................... amd/stoneyridge: Add northbridge register macros Add helpers for determining the D18F1 offset for MMIO base and limit, and I/O base/limit registers. Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/northbridge.h 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22339/2 -- To view, visit https://review.coreboot.org/22339 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d Gerrit-Change-Number: 22339 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: amd/stoneyridge: Remove fixme.c
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22297 ) Change subject: amd/stoneyridge: Remove fixme.c ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17945/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62983/ : SUCCESS -- To view, visit https://review.coreboot.org/22297 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3 Gerrit-Change-Number: 22297 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 16:48:57 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/common/psp: Require PSP PCI definition in SOC
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22249 ) Change subject: soc/amd/common/psp: Require PSP PCI definition in SOC ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17943/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62981/ : SUCCESS -- To view, visit https://review.coreboot.org/22249 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie41dfa348b04f655640b4259b1aa518376655251 Gerrit-Change-Number: 22249 Gerrit-PatchSet: 4 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 16:47:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Remove amdlib functions from fixme.c
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22248 ) Change subject: amd/stoneyridge: Remove amdlib functions from fixme.c ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17944/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62982/ : SUCCESS -- To view, visit https://review.coreboot.org/22248 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I87b258f3187db4247b291c848b5f0366d3303c75 Gerrit-Change-Number: 22248 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 16:42:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Add northbridge register macros
by Marshall Dawson (Code Review) 04 Nov '17

04 Nov '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22339 Change subject: amd/stoneyridge: Add northbridge register macros ...................................................................... amd/stoneyridge: Add northbridge register macros Add helpers for determining the D18F1 offset for MMIO base and limit, and I/O base/limit registers. Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/northbridge.h 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22339/1 diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 9113878..5cf911e 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -26,15 +26,35 @@ # define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */ /* D18F1 - Address Map Registers */ + +/* MMIO base and limit */ #define D18F1_MMIO_BASE0_LO 0x80 # define MMIO_WE (1 << 1) # define MMIO_RE (1 << 0) #define D18F1_MMIO_LIMIT0_LO 0x84 # define MMIO_NP (1 << 7) +#define D18F1_MMIO_BASELIM0_HI 0x180 +#define D18F1_MMIO_BASE8_LO 0x1a0 +#define D18F1_MMIO_LIMIT8_LO 0x1a4 +#define D18F1_MMIO_BASELIM8_HI 0x1c0 +#define NB_MMIO_BASE_LO(reg) ((reg) * 2 * sizeof(uint32_t) + ((reg < 8) \ + ? D18F1_MMIO_BASE0_LO \ + : D18F1_MMIO_BASE8_LO \ + - 8 * sizeof(uint64_t))) +#define NB_MMIO_LIMIT_LO(reg) (NB_MMIO_BASE_LO(reg) + sizeof(uint32_t)) +#define NB_MMIO_BASELIM_HI(reg) ((reg) * sizeof(uint32_t) + ((reg < 8) \ + ? D18F1_MMIO_BASELIM0_HI \ + : D18F1_MMIO_BASELIM8_HI \ + - 8 * sizeof(uint32_t))) +/* I/O base and limit */ #define D18F1_IO_BASE0 0xc0 # define IO_WE (1 << 1) # define IO_RE (1 << 0) #define D18F1_IO_LIMIT0 0xc4 +#define NB_IO_BASE(reg) ((reg) * 2 * sizeof(uint32_t) + D18F1_IO_BASE0) +#define NB_IO_LIMIT(reg) (NB_IO_BASE(reg) + sizeof(uint32_t)) + + #define D18F1_DRAM_HOLE 0xf0 # define DRAM_HOIST_VALID (1 << 1) # define DRAM_HOLE_VALID (1 << 0) -- To view, visit https://review.coreboot.org/22339 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d Gerrit-Change-Number: 22339 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: nb/intel/sandybridge/peg: Add PEG driver
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22337 ) Change subject: nb/intel/sandybridge/peg: Add PEG driver ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17940/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62978/ : SUCCESS -- To view, visit https://review.coreboot.org/22337 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1 Gerrit-Change-Number: 22337 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 15:37:18 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/sandybridge/peg: Add PEG driver
by Patrick Rudolph (Code Review) 04 Nov '17

04 Nov '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/22337 to look at the new patch set (#2). Change subject: nb/intel/sandybridge/peg: Add PEG driver ...................................................................... nb/intel/sandybridge/peg: Add PEG driver Required for other ACPI generators, like the one used for _ROM. * Add ACPI code for PEG10/PEG11/PEG12/PEG60 and include it on all platforms. * Add PCIe driver for PEG. The driver returns ACPI names for ssdt generators and includes an ACPI generator to write _STA method. Needs test on real hardware. Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/Makefile.inc A src/northbridge/intel/sandybridge/acpi/peg.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl A src/northbridge/intel/sandybridge/pcie.c 4 files changed, 269 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/22337/2 -- To view, visit https://review.coreboot.org/22337 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1 Gerrit-Change-Number: 22337 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit November 2017