coreboot-gerrit October 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Add all the SOC level DSDT tables
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21860 ) Change subject: soc/intel/cannonlake: Add all the SOC level DSDT tables ...................................................................... Patch Set 5: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61523/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16639/ : SUCCESS -- To view, visit https://review.coreboot.org/21860 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9 Gerrit-Change-Number: 21860 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Oct 2017 19:30:21 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: chromeec: Remove checks for EC in RO
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21711 ) Change subject: chromeec: Remove checks for EC in RO ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61522/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16638/ : SUCCESS -- To view, visit https://review.coreboot.org/21711 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Gerrit-Change-Number: 21711 Gerrit-PatchSet: 10 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Oct 2017 19:27:55 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: src/mainboard/Kconfig: Add support for 10240 KiB ROM chips
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21863 ) Change subject: src/mainboard/Kconfig: Add support for 10240 KiB ROM chips ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61521/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16637/ : SUCCESS -- To view, visit https://review.coreboot.org/21863 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6365b0cda67fa1213c20337890157e5d658094d1 Gerrit-Change-Number: 21863 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <cp_public(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Oct 2017 19:14:57 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: src/mainboard/Kconfig: Add support for 10240 KiB ROM chips
by Jonathan Neuschäfer (Code Review) 03 Oct '17

03 Oct '17

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21863 Change subject: src/mainboard/Kconfig: Add support for 10240 KiB ROM chips ...................................................................... src/mainboard/Kconfig: Add support for 10240 KiB ROM chips The Dell Optiplex 790 desktop board has a logical 10MiB flash, so it needs to select BOARD_ROMSIZE_KB_10240. Provide it, so it can be used. Change-Id: I6365b0cda67fa1213c20337890157e5d658094d1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/mainboard/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/21863/1 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 47338ac..04dca4a 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -29,6 +29,8 @@ bool config BOARD_ROMSIZE_KB_8192 bool +config BOARD_ROMSIZE_KB_10240 + bool config BOARD_ROMSIZE_KB_12288 bool config BOARD_ROMSIZE_KB_16384 @@ -49,6 +51,7 @@ default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 + default COREBOOT_ROMSIZE_KB_10240 if BOARD_ROMSIZE_KB_10240 default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 default COREBOOT_ROMSIZE_KB_32768 if BOARD_ROMSIZE_KB_32768 @@ -99,6 +102,11 @@ help Choose this option if you have a 8192 KB (8 MB) ROM chip. +config COREBOOT_ROMSIZE_KB_10240 + bool "10240 KB (10 MB)" + help + Choose this option if you have a 10240 KB (10 MB) ROM chip. + config COREBOOT_ROMSIZE_KB_12288 bool "12288 KB (12 MB)" help @@ -132,6 +140,7 @@ default 2048 if COREBOOT_ROMSIZE_KB_2048 default 4096 if COREBOOT_ROMSIZE_KB_4096 default 8192 if COREBOOT_ROMSIZE_KB_8192 + default 10240 if COREBOOT_ROMSIZE_KB_10240 default 12288 if COREBOOT_ROMSIZE_KB_12288 default 16384 if COREBOOT_ROMSIZE_KB_16384 default 32768 if COREBOOT_ROMSIZE_KB_32768 @@ -148,6 +157,7 @@ default 0x200000 if COREBOOT_ROMSIZE_KB_2048 default 0x400000 if COREBOOT_ROMSIZE_KB_4096 default 0x800000 if COREBOOT_ROMSIZE_KB_8192 + default 0xa00000 if COREBOOT_ROMSIZE_KB_10240 default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 default 0x2000000 if COREBOOT_ROMSIZE_KB_32768 -- To view, visit https://review.coreboot.org/21863 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6365b0cda67fa1213c20337890157e5d658094d1 Gerrit-Change-Number: 21863 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: soc/intel/cannonlake: Disable CPU ratio override
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21709 ) Change subject: soc/intel/cannonlake: Disable CPU ratio override ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61520/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16636/ : SUCCESS -- To view, visit https://review.coreboot.org/21709 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b Gerrit-Change-Number: 21709 Gerrit-PatchSet: 6 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Oct 2017 18:57:45 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add all the SOC level DSDT tables
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21860 ) Change subject: soc/intel/cannonlake: Add all the SOC level DSDT tables ...................................................................... Patch Set 4: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/61518/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/16634/ : SUCCESS -- To view, visit https://review.coreboot.org/21860 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9 Gerrit-Change-Number: 21860 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Oct 2017 18:52:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add all the SOC level DSDT tables
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21860 ) Change subject: soc/intel/cannonlake: Add all the SOC level DSDT tables ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/61517/ : FAILURE -- To view, visit https://review.coreboot.org/21860 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9 Gerrit-Change-Number: 21860 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Oct 2017 18:51:57 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add all the SOC level DSDT tables
by Lijian Zhao (Code Review) 03 Oct '17

03 Oct '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21860 Change subject: soc/intel/cannonlake: Add all the SOC level DSDT tables ...................................................................... soc/intel/cannonlake: Add all the SOC level DSDT tables Add all the SOC level DSDT tables. Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- A src/soc/intel/cannonlake/acpi/ipu.asl A src/soc/intel/cannonlake/acpi/lpc.asl A src/soc/intel/cannonlake/acpi/pch_hda.asl A src/soc/intel/cannonlake/acpi/platform.asl A src/soc/intel/cannonlake/acpi/serialio.asl A src/soc/intel/cannonlake/acpi/smbus.asl M src/soc/intel/cannonlake/acpi/southbridge.asl A src/soc/intel/cannonlake/acpi/xhci.asl 8 files changed, 634 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/21860/4 diff --git a/src/soc/intel/cannonlake/acpi/ipu.asl b/src/soc/intel/cannonlake/acpi/ipu.asl new file mode 100644 index 0000000..d5a2089 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/ipu.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* IPU3 input system - Device 05, Function 0 */ +Device (IMGU) +{ + Name (_ADR, 0x00050000) + Name (_DDN, "Imaging Unit") + Name (_CCA, ZERO) + Name (CAMD, 0x01) +} \ No newline at end of file diff --git a/src/soc/intel/cannonlake/acpi/lpc.asl b/src/soc/intel/cannonlake/acpi/lpc.asl new file mode 100644 index 0000000..f1c1bf3 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/lpc.asl @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (LPCB) +{ + Name (_ADR, 0x001f0000) + Name (_DDN, "LPC Bus Device") + + Device (FWH) + { + Name (_HID, EISAID ("INT0800")) + Name (_DDN, "Firmware Hub") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) + }) + } + + Device (HPET) + { + Name (_HID, EISAID ("PNP0103")) + Name (_DDN, "High Precision Event Timer") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) + }) + Method (_STA, 0) + { + Return (0xf) + } + } + + Device (PIC) + { + Name (_HID, EISAID ("PNP0000")) + Name (_DDN, "8259 Interrupt Controller") + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x20, 0x20, 0x01, 0x02) + IO (Decode16, 0x24, 0x24, 0x01, 0x02) + IO (Decode16, 0x28, 0x28, 0x01, 0x02) + IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) + IO (Decode16, 0x30, 0x30, 0x01, 0x02) + IO (Decode16, 0x34, 0x34, 0x01, 0x02) + IO (Decode16, 0x38, 0x38, 0x01, 0x02) + IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) + IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) + IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) + IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) + IO (Decode16, 0xac, 0xac, 0x01, 0x02) + IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) + IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) + IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) + IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) + IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) + IRQNoFlags () { 2 } + }) + } + + Device (LDRC) + { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 2) + Name (_DDN, "Legacy Device Resources") + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO + IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO + IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status + IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post + IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, + 0x1, 0xff) + }) + } + + Device (RTC) + { + Name (_HID, EISAID ("PNP0B00")) + Name (_DDN, "Real Time Clock") + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x70, 0x70, 1, 8) + }) + } + + Device (TIMR) + { + Name (_HID, EISAID ("PNP0100")) + Name (_DDN, "8254 Timer") + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x40, 0x40, 0x01, 0x04) + IO (Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags () {0} + }) + } + +} diff --git a/src/soc/intel/cannonlake/acpi/pch_hda.asl b/src/soc/intel/cannonlake/acpi/pch_hda.asl new file mode 100644 index 0000000..97967ab --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/pch_hda.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Audio Controller - Device 31, Function 3 */ + +Device (HDAS) +{ + Name (_ADR, 0x001f0003) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, NonCacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (LEqual (Arg2, Zero)) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If (LAnd (LEqual (Arg1, One), + LAnd (LNotEqual (NHLA, Zero), + LNotEqual (NHLL, Zero)))) { + Return (Buffer (One) { 0x03 }) + } Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (LEqual (Arg2, One)) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + + Store (NHLA, NBAS) + Store (NHLA, NMAS) + Store (NHLL, NLEN) + + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +} diff --git a/src/soc/intel/cannonlake/acpi/platform.asl b/src/soc/intel/cannonlake/acpi/platform.asl new file mode 100644 index 0000000..17a19d9 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/platform.asl @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method (_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store (Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Return (Package (){ 0, 0 }) +} diff --git a/src/soc/intel/cannonlake/acpi/serialio.asl b/src/soc/intel/cannonlake/acpi/serialio.asl new file mode 100644 index 0000000..0a9b15c --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/serialio.asl @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel Serial IO Devices */ + +Device (I2C0) +{ + Name (_ADR, 0x00150000) + Name (_DDN, "Serial IO I2C Controller 0") +} + +Device (I2C1) +{ + Name (_ADR, 0x00150001) + Name (_DDN, "Serial IO I2C Controller 1") +} + +Device (I2C2) +{ + Name (_ADR, 0x00150002) + Name (_DDN, "Serial IO I2C Controller 2") +} + +Device (I2C3) +{ + Name (_ADR, 0x00150003) + Name (_DDN, "Serial IO I2C Controller 3") +} + +Device (I2C4) +{ + Name (_ADR, 0x00190000) + Name (_DDN, "Serial IO I2C Controller 4") +} + +Device (I2C5) +{ + Name (_ADR, 0x00190001) + Name (_DDN, "Serial IO I2C Controller 5") +} + +Device (SPI0) +{ + Name (_ADR, 0x001e0002) + Name (_DDN, "Serial IO SPI Controller 0") +} + +Device (SPI1) +{ + Name (_ADR, 0x001e0003) + Name (_DDN, "Serial IO SPI Controller 1") +} + +Device (SPI2) +{ + Name (_ADR, 0x00120006) + Name (_DDN, "Serial IO SPI Controller 2") +} + +Device (UAR0) +{ + Name (_ADR, 0x001e0000) + Name (_DDN, "Serial IO UART Controller 0") +} + +Device (UAR1) +{ + Name (_ADR, 0x001e0001) + Name (_DDN, "Serial IO UART Controller 1") +} + +Device (UAR2) +{ + Name (_ADR, 0x00190002) + Name (_DDN, "Serial IO UART Controller 2") +} diff --git a/src/soc/intel/cannonlake/acpi/smbus.asl b/src/soc/intel/cannonlake/acpi/smbus.asl new file mode 100644 index 0000000..cd5ba2c --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/smbus.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Intel SMBus Controller 0:1f.4 + +Device (SBUS) +{ + Name (_ADR, 0x001f0004) +} diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 408c31b..fdba171 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -27,3 +27,21 @@ /* GPIO controller */ #include "gpio.asl" + +/* LPC 0:1f.0 */ +#include "lpc.asl" + +/* PCH HDA */ +#include "pch_hda.asl" + +/* Serial IO */ +#include "serialio.asl" + +/* SMBus 0:1f.3 */ +#include "smbus.asl" + +/* USB XHCI 0:14.0 */ +#include "xhci.asl" + +/* PCI _OSC */ +#include <soc/intel/common/acpi/pci_osc.asl> diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl new file mode 100644 index 0000000..93acb40 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/xhci.asl @@ -0,0 +1,214 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * USB Port Wake Enable (UPWE) on usb attach/detach + * Arg0 - Port Number + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UPWE, 3, Serialized) +{ + /* Local0 = Arg1 + ((Arg0 - 1) * 0x10) */ + Add (Arg1, Multiply (Subtract (Arg0, 1), 0x10), Local0) + + /* Map ((XMEM << 16) + Local0 in PSCR */ + OperationRegion (PSCR, SystemMemory, + Add (ShiftLeft (Arg2, 16), Local0), 0x10) + Field (PSCR, AnyAcc, NoLock, Preserve) + { + , 25, + UPCE, 1, + UPDE, 1, + } + Store (One, UPCE) + Store (One, UPDE) +} + +/* + * USB Wake Enable Setup (UWES) + * Arg0 - Port enable bitmap + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UWES, 3, Serialized) +{ + Store (Arg0, Local0) + + While (One) { + FindSetRightBit (Local0, Local1) + If (LEqual (Local1, Zero)) { + Break + } + UPWE (Local1, Arg1, Arg2) + /* + * Clear the lowest set bit in Local0 since it was + * processed. + * Local0 = Local0 & (Local0 - 1) + */ + And (Local0, Subtract (Local0, 1), Local0) + } +} + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Method (_DSW, 3) + { + Store (Arg0, PMEE) + UWES (And (\U2WE, 0x3FF), 0x480, XMEM) + UWES (And (\U3WE, 0x3F), 0x540, XMEM) + } + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S4D, 3) /* D3 supported in S4 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + Name (_S4W, 3) /* D3 can wake system from S4 */ + + OperationRegion (XPRT, PCI_Config, 0x00, 0x100) + Field (XPRT, AnyAcc, NoLock, Preserve) + { + Offset (0x0), + DVID, 16, /* VENDORID */ + Offset (0x10), + , 16, + XMEM, 16, /* MEM_BASE */ + Offset (0x50), /* XHCLKGTEN */ + , 2, + STGE, 1, /* SS Link Trunk clock gating enable */ + Offset (0x74), + D0D3, 2, /* POWERSTATE */ + , 6, + PMEE, 1, /* PME_EN */ + , 6, + PMES, 1, /* PME_STS */ + Offset (0xA2), + , 2, + D3HE, 1, /* D3_hot_en */ + } + + OperationRegion (XREG, SystemMemory, + Add (ShiftLeft (XMEM, 16), 0x8000), 0x200) + Field (XREG, DWordAcc, Lock, Preserve) + { + Offset (0x1c4), /* USB2PMCTRL */ + , 2, + UPSW, 2, /* U2PSUSPGP */ + } + + Method (_PSC, 0, Serialized) + { + Return (^D0D3) + } + + Method (_PS0, 0, Serialized) + { + If (LEqual (^DVID, 0xFFFF)) { + Return + } + If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + Return + } + + /* Disable d3hot and SS link trunk clock gating */ + Store(Zero, ^D3HE) + Store(Zero, ^STGE) + + /* If device is in D3, set back to D0 */ + If (LEqual (^D0D3, 3)) { + Store (Zero, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) + } + + /* Disable USB2 PHY SUS Well Power Gating */ + Store (Zero, ^UPSW) + } + + Method (_PS3, 0, Serialized) + { + If (LEqual (^DVID, 0xFFFF)) { + Return + } + If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + Return + } + + /* Clear PME Status */ + Store (1, ^PMES) + + /* Enable PME */ + Store (1, ^PMEE) + + /* If device is in D3, set back to D0 */ + If (LEqual (^D0D3, 3)) { + Store (Zero, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) + } + + /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ + Store (3, ^UPSW) + + /* Enable d3hot and SS link trunk clock gating */ + Store(One, ^D3HE) + Store(One, ^STGE) + + /* Now put device in D3 */ + Store (3, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) + } + + /* Root Hub for Cannonlake-LP PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + Device (HS11) { Name (_ADR, 11) } + Device (HS12) { Name (_ADR, 12) } + + /* USBr */ + Device (USR1) { Name (_ADR, 11) } + Device (USR2) { Name (_ADR, 12) } + + /* USB3 */ + Device (SS01) { Name (_ADR, 13) } + Device (SS02) { Name (_ADR, 14) } + Device (SS03) { Name (_ADR, 15) } + Device (SS04) { Name (_ADR, 16) } + Device (SS05) { Name (_ADR, 17) } + Device (SS06) { Name (_ADR, 18) } + } +} -- To view, visit https://review.coreboot.org/21860 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9 Gerrit-Change-Number: 21860 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common/block: Manage power state variable from common PMC b...
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21851 ) Change subject: soc/intel/common/block: Manage power state variable from common PMC block ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61516/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16633/ : SUCCESS -- To view, visit https://review.coreboot.org/21851 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If65341c1492e3a35a1a927100e0d893f923b9e68 Gerrit-Change-Number: 21851 Gerrit-PatchSet: 4 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Oct 2017 18:35:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/soraka: Reduce Wacom resume time
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21692 ) Change subject: mainboard/google/soraka: Reduce Wacom resume time ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61515/ : SUCCESS -- To view, visit https://review.coreboot.org/21692 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I59d070977a95316414018af69d5b43e3147ccf4e Gerrit-Change-Number: 21692 Gerrit-PatchSet: 3 Gerrit-Owner: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Gerrit-Reviewer: Anshuman Gupta <anshuman.gupta(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Oct 2017 18:10:58 +0000 Gerrit-HasComments: No

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coreboot-gerrit October 2017