coreboot-gerrit October 2017

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Change in coreboot[master]: soraka:[DEBUGONLY] Disable LTR for Wifi
by Rizwan Qureshi (Code Review) 04 Oct '17

04 Oct '17

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/21870 Change subject: soraka:[DEBUGONLY] Disable LTR for Wifi ...................................................................... soraka:[DEBUGONLY] Disable LTR for Wifi Change-Id: Id757b287f841265829dec63774fa76b506b7165e Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/poppy/variants/soraka/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/21870/1 diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 902b202..5879c6f 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -155,7 +155,7 @@ # RP 1, Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[0]" = "0" # RP 1, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "0" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port -- To view, visit https://review.coreboot.org/21870 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id757b287f841265829dec63774fa76b506b7165e Gerrit-Change-Number: 21870 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: soraka:[DEBUGONLY] disable AER
by Rizwan Qureshi (Code Review) 04 Oct '17

04 Oct '17

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/21869 Change subject: soraka:[DEBUGONLY] disable AER ...................................................................... soraka:[DEBUGONLY] disable AER Change-Id: I6861f57f58e54721ce8cd5ff3fabf8be231d8350 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/poppy/variants/soraka/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/21869/1 diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index f6948d9..902b202 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -153,7 +153,7 @@ # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "0" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" -- To view, visit https://review.coreboot.org/21869 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6861f57f58e54721ce8cd5ff3fabf8be231d8350 Gerrit-Change-Number: 21869 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: src/device: Update LTR configuration scheme
by build bot (Jenkins) (Code Review) 04 Oct '17

04 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21868 ) Change subject: src/device: Update LTR configuration scheme ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61546/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16659/ : SUCCESS -- To view, visit https://review.coreboot.org/21868 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe Gerrit-Change-Number: 21868 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 04 Oct 2017 07:21:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add config for mbx command for Intersil VR C-state...
by build bot (Jenkins) (Code Review) 04 Oct '17

04 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21680 ) Change subject: soc/intel/skylake: Add config for mbx command for Intersil VR C-state issues ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61545/ : SUCCESS -- To view, visit https://review.coreboot.org/21680 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibcced31b7ba473ffa7368c90c945d07a81a368d4 Gerrit-Change-Number: 21680 Gerrit-PatchSet: 4 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 07:11:34 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: FSP.2.7.2: Update FSP header files version 2.7.2
by build bot (Jenkins) (Code Review) 04 Oct '17

04 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21679 ) Change subject: FSP.2.7.2: Update FSP header files version 2.7.2 ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61544/ : SUCCESS -- To view, visit https://review.coreboot.org/21679 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151 Gerrit-Change-Number: 21679 Gerrit-PatchSet: 4 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 07:10:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: src/device: Update LTR configuration scheme
by Aamir Bohra (Code Review) 04 Oct '17

04 Oct '17

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/21868 Change subject: src/device: Update LTR configuration scheme ...................................................................... src/device: Update LTR configuration scheme This patch moves out LTR programming under L1 substate to pchexp_tune_device function, as substate programming and LTR programming are independent. LTR programming scheme is updated to check LTR is enabled and supported for entire link and only then LTR for device needs to be enabled to comply with PCI base specification (rev 3.1a, section 6.18). And remove explicit LTR enable programming for root device under L1 substate. BRANCH=none BUG=b:66722364 TEST=Verify LTR is configured for end point device only when all parent devices in link has LTR enabled and max snoop latency gets configured. Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/device/pciexp_device.c M src/include/device/pci_def.h 2 files changed, 43 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/21868/1 diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 40c3f8c..e3859d8 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -149,16 +149,49 @@ root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4); } -static void pciexp_enable_ltr(device_t dev) +static unsigned int pciexp_is_ltrenable(device_t dev) { unsigned int cap; cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); - if(!cap) { + if (cap && pci_read_config16(dev, cap + PCI_EXP_DEV_CAP2_OFFSET) & + 1 << 11 && pci_read_config16(dev, cap + +PCI__EXP_DEV_CTL_STS2_CAP_OFFSET) & 1 << 10) + return 1; + + return 0; +} + +static void pciexp_enable_ltr(device_t dev) +{ + unsigned int cap; + device_t root; + + cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); + /* Check if capibility pointer is valid and dev ltrms is enabled*/ + if (!cap && pci_read_config16(dev, cap + PCI_EXP_DEV_CAP2_OFFSET) & + 1 << 11) { printk(BIOS_INFO, "Failed to enable LTR for dev = %s\n", dev_path(dev)); return; } - pci_update_config32(dev, cap + 0x28, ~(1 << 10), 1 << 10); + for (root = dev->bus->dev; root->path.type != DEVICE_PATH_DOMAIN; + root = root->bus->dev) { + if (pciexp_is_ltrenable(root)) + continue; + break; + } + if (root->path.type == DEVICE_PATH_DOMAIN) { + pci_update_config32(dev, cap + + PCI__EXP_DEV_CTL_STS2_CAP_OFFSET, + ~(1 << 10), 1 << 10); + pciexp_config_max_latency(dev->bus->dev, dev); + } + else + printk(BIOS_INFO, + " Failed to enable LTR for dev %s" + "as link ltr support is disabled\n", + dev_path(dev)); + return; } static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap, @@ -232,8 +265,6 @@ printk(BIOS_INFO, "Power On Value = 0x%x, Power On Scale = 0x%x\n", endp_power_on_value, power_on_scale); - pciexp_enable_ltr(root); - pci_update_config32(root, root_cap + 0x08, ~0xff00, (comm_mode_rst_time << 8)); @@ -255,10 +286,6 @@ pci_update_config32(dev_t, end_cap + 0x08, ~0x1f, L1SubStateSupport); - - pciexp_enable_ltr(dev_t); - - pciexp_config_max_latency(root, dev_t); } } @@ -391,6 +418,9 @@ if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE)) pciexp_config_L1_sub_state(root, dev); + /* Check for LTR support and enable */ + pciexp_enable_ltr(dev); + /* Check for and enable ASPM */ if (IS_ENABLED(CONFIG_PCIEXP_ASPM)) pciexp_enable_aspm(root, root_cap, dev, cap); diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 1674ee1..a7e032c 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -373,6 +373,10 @@ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ +/* Device Capabilities 2 offset */ +#define PCI_EXP_DEV_CAP2_OFFSET 0x24 +/* Device Control Status 2 offset*/ +#define PCI__EXP_DEV_CTL_STS2_CAP_OFFSET 0x28 #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ -- To view, visit https://review.coreboot.org/21868 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe Gerrit-Change-Number: 21868 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Manage power state variable from common PMC b...
by build bot (Jenkins) (Code Review) 04 Oct '17

04 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21851 ) Change subject: soc/intel/common/block: Manage power state variable from common PMC block ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61543/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16658/ : SUCCESS -- To view, visit https://review.coreboot.org/21851 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If65341c1492e3a35a1a927100e0d893f923b9e68 Gerrit-Change-Number: 21851 Gerrit-PatchSet: 7 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 06:46:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: FSP.2.7.2: Update FSP header files version 2.7.2
by build bot (Jenkins) (Code Review) 04 Oct '17

04 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21679 ) Change subject: FSP.2.7.2: Update FSP header files version 2.7.2 ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61542/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16656/ : SUCCESS -- To view, visit https://review.coreboot.org/21679 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151 Gerrit-Change-Number: 21679 Gerrit-PatchSet: 3 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 05:35:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add config for mbx command for Intersil VR C-state...
by build bot (Jenkins) (Code Review) 04 Oct '17

04 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21680 ) Change subject: soc/intel/skylake: Add config for mbx command for Intersil VR C-state issues ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61541/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16657/ : SUCCESS -- To view, visit https://review.coreboot.org/21680 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibcced31b7ba473ffa7368c90c945d07a81a368d4 Gerrit-Change-Number: 21680 Gerrit-PatchSet: 3 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 05:34:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ifdtool: Port the feature to jail ME from me_cleaner
by build bot (Jenkins) (Code Review) 04 Oct '17

04 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21607 ) Change subject: ifdtool: Port the feature to jail ME from me_cleaner ...................................................................... Patch Set 22: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61540/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16655/ : SUCCESS -- To view, visit https://review.coreboot.org/21607 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I00533f4e2569c4763fbfc302bb460db1e60e5564 Gerrit-Change-Number: 21607 Gerrit-PatchSet: 22 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 01:24:27 +0000 Gerrit-HasComments: No

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coreboot-gerrit October 2017