coreboot-gerrit October 2017

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Change in coreboot[master]: NOTFORMERGE amd/stoneyridge: Jam sleep states for testing
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21884 ) Change subject: NOTFORMERGE amd/stoneyridge: Jam sleep states for testing ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61573/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16683/ : SUCCESS -- To view, visit https://review.coreboot.org/21884 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6abd1a924d62f218aaa743b538faa7d9bf0dc147 Gerrit-Change-Number: 21884 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 22:47:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Add conversion of PmControl to SLP_TYP_Sx
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21883 ) Change subject: amd/stoneyridge: Add conversion of PmControl to SLP_TYP_Sx ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61572/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16682/ : SUCCESS -- To view, visit https://review.coreboot.org/21883 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib804f4544d04fe08fefa493d75e0375de7cf9348 Gerrit-Change-Number: 21883 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 22:44:27 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Add function to find PmControl register
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21882 ) Change subject: amd/stoneyridge: Add function to find PmControl register ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61571/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16681/ : SUCCESS -- To view, visit https://review.coreboot.org/21882 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibb608dcaa7801af067d6edd86f92c117c2ac08a6 Gerrit-Change-Number: 21882 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 22:42:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Add SMI apmc handler
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21880 ) Change subject: google/kahlee: Add SMI apmc handler ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61568/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16679/ : SUCCESS -- To view, visit https://review.coreboot.org/21880 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id724c1abf15617ad1ba28f2c0247455b014c1867 Gerrit-Change-Number: 21880 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 22:42:08 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Add SMI sleep handler
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21881 ) Change subject: google/kahlee: Add SMI sleep handler ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61570/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16680/ : SUCCESS -- To view, visit https://review.coreboot.org/21881 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I025e268a4f806d827348d91effff43a6a339a148 Gerrit-Change-Number: 21881 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 22:41:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: WIP amd/stoneridge: Enable SMI trap on SlpTyp
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21752 ) Change subject: WIP amd/stoneridge: Enable SMI trap on SlpTyp ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61567/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16678/ : SUCCESS -- To view, visit https://review.coreboot.org/21752 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229 Gerrit-Change-Number: 21752 Gerrit-PatchSet: 4 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 22:36:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: NOTFORMERGE amd/stoneyridge: Jam sleep states for testing
by Marshall Dawson (Code Review) 05 Oct '17

05 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21884 Change subject: NOTFORMERGE amd/stoneyridge: Jam sleep states for testing ...................................................................... NOTFORMERGE amd/stoneyridge: Jam sleep states for testing Let the OS send us an S3 request. Currently there are build errors when HAVE_ACPI_RESUME is selected. This change allows us to quickly proceed with power measurements but the system can never resume. Change-Id: I6abd1a924d62f218aaa743b538faa7d9bf0dc147 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/sleepstates.asl 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/21884/1 diff --git a/src/soc/amd/stoneyridge/acpi/sleepstates.asl b/src/soc/amd/stoneyridge/acpi/sleepstates.asl index 2f36738..4b0962d 100644 --- a/src/soc/amd/stoneyridge/acpi/sleepstates.asl +++ b/src/soc/amd/stoneyridge/acpi/sleepstates.asl @@ -18,7 +18,11 @@ #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) Name (SSFG, 0x0D) #else -Name (SSFG, 0x09) +/* Name (SSFG, 0x09) + * Do not merge this change! This is only to tell the OS that S3 is available + * for a test, but S3 is not yet supported. + */ +Name (SSFG, 0x0D) #endif /* Supported sleep states: */ -- To view, visit https://review.coreboot.org/21884 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6abd1a924d62f218aaa743b538faa7d9bf0dc147 Gerrit-Change-Number: 21884 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add conversion of PmControl to SLP_TYP_Sx
by Marshall Dawson (Code Review) 05 Oct '17

05 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21883 Change subject: amd/stoneyridge: Add conversion of PmControl to SLP_TYP_Sx ...................................................................... amd/stoneyridge: Add conversion of PmControl to SLP_TYP_Sx Convert a value, which may be read from the PmControl register, into an intended sleep state. This mimics the Intel function in arch/x86 but uses values specific to the AMD FCH. Change-Id: Ib804f4544d04fe08fefa493d75e0375de7cf9348 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/21883/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index d506af9..917bd60 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -66,6 +66,14 @@ #define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE #define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define SLP_EN (1 << 13) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 3 +#define SLP_TYP_S4 4 +#define SLP_TYP_S5 5 #define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */ #define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */ @@ -203,6 +211,7 @@ void smi_write16(u8 reg, u16 value); void smi_write32(u8 reg, u32 value); uint16_t pm_acpi_pm_cnt_blk(void); +int acpi_sleep_from_pm1(uint32_t pm1_cnt); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); void s3_resume_init_data(void *FchParams); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index bdb199a..acfa41c 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <soc/southbridge.h> void pm_write8(u8 reg, u8 value) @@ -69,3 +70,15 @@ { return pm_read16(PM1_CNT_BLK); } + +int acpi_sleep_from_pm1(uint32_t pm1_cnt) +{ + switch (((pm1_cnt) & SLP_TYP) >> SLP_TYP_SHIFT) { + case SLP_TYP_S0: return ACPI_S0; + case SLP_TYP_S1: return ACPI_S1; + case SLP_TYP_S3: return ACPI_S3; + case SLP_TYP_S4: return ACPI_S4; + case SLP_TYP_S5: return ACPI_S5; + } + return -1; +} -- To view, visit https://review.coreboot.org/21883 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib804f4544d04fe08fefa493d75e0375de7cf9348 Gerrit-Change-Number: 21883 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add function to find PmControl register
by Marshall Dawson (Code Review) 05 Oct '17

05 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21882 Change subject: amd/stoneyridge: Add function to find PmControl register ...................................................................... amd/stoneyridge: Add function to find PmControl register Find the PmControl register's I/O address by checking the hardware in PMx62. Don't rely on the address being the coreboot default. PmControl is the first register in the AcpiPm1CntBlk. Change-Id: Ibb608dcaa7801af067d6edd86f92c117c2ac08a6 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/21882/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index ebfee24..d506af9 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -202,6 +202,7 @@ u32 smi_read32(u8 reg); void smi_write16(u8 reg, u16 value); void smi_write32(u8 reg, u32 value); +uint16_t pm_acpi_pm_cnt_blk(void); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); void s3_resume_init_data(void *FchParams); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 87bff70..bdb199a 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -64,3 +64,8 @@ { write16((void *)(APU_SMI_BASE + offset), value); } + +uint16_t pm_acpi_pm_cnt_blk(void) +{ + return pm_read16(PM1_CNT_BLK); +} -- To view, visit https://review.coreboot.org/21882 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibb608dcaa7801af067d6edd86f92c117c2ac08a6 Gerrit-Change-Number: 21882 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: google/kahlee: Add SMI sleep handler
by Marshall Dawson (Code Review) 05 Oct '17

05 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21881 Change subject: google/kahlee: Add SMI sleep handler ...................................................................... google/kahlee: Add SMI sleep handler Notify the EC the system is going to sleep. Change-Id: I025e268a4f806d827348d91effff43a6a339a148 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/kahlee/smihandler.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/21881/1 diff --git a/src/mainboard/google/kahlee/smihandler.c b/src/mainboard/google/kahlee/smihandler.c index 454b42e..f1c66a6 100644 --- a/src/mainboard/google/kahlee/smihandler.c +++ b/src/mainboard/google/kahlee/smihandler.c @@ -20,6 +20,13 @@ #include <soc/smi.h> #include "ec.h" +void mainboard_smi_sleep(u8 slp_typ) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + int mainboard_smi_apmc(u8 apmc) { if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) -- To view, visit https://review.coreboot.org/21881 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I025e268a4f806d827348d91effff43a6a339a148 Gerrit-Change-Number: 21881 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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coreboot-gerrit October 2017