coreboot-gerrit October 2017

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Change in coreboot[master]: soc/amd/stoneyridge: SMBUS code simplify
by Richard Spiegel (Code Review) 05 Oct '17

05 Oct '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/21887 Change subject: soc/amd/stoneyridge: SMBUS code simplify ...................................................................... soc/amd/stoneyridge: SMBUS code simplify Solve issues left from review 19722. Unify code: smbus.c to have the actual execution code, sm.c and smbus_spd.c call functions within smbus.c. Include file smbus.h should only be used by sm.c, smbus.c and smbus_spd.c. BUG=b:62200225 Change-Id: Ibd55560c95b6752652a4f255b04198e7a4e77d05 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/smbus.h M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/smbus.c M src/soc/amd/stoneyridge/smbus_spd.c M src/soc/amd/stoneyridge/southbridge.c 5 files changed, 92 insertions(+), 153 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/21887/1 diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h index 727f72e..e1b4c5f 100644 --- a/src/soc/amd/stoneyridge/include/soc/smbus.h +++ b/src/soc/amd/stoneyridge/include/soc/smbus.h @@ -18,57 +18,60 @@ #include <stdint.h> -#define SMBHSTSTAT 0x0 -#define SMBHST_STAT_FAILED 0x10 -#define SMBHST_STAT_COLLISION 0x08 +#define SMBHSTSTAT 0x0 +#define SMBHST_STAT_FAILED 0x10 +#define SMBHST_STAT_COLLISION 0x08 #define SMBHST_STAT_ERROR 0x04 -#define SMBHST_STAT_INTERRUPT 0x02 +#define SMBHST_STAT_INTERRUPT 0x02 #define SMBHST_STAT_BUSY 0x01 #define SMBHST_STAT_CLEAR 0xff -#define SMBHST_STAT_NOERROR 0x02 +#define SMBHST_STAT_NOERROR 0x02 +#define SMBHST_STAT_VAL_BITS 0x1f +#define SMBHST_STAT_ERROR_BITS 0x1c -#define SMBSLVSTAT 0x1 +#define SMBSLVSTAT 0x1 #define SMBSLV_STAT_ALERT 0x20 -#define SMBSLV_STAT_SHADOW2 0x10 -#define SMBSLV_STAT_SHADOW1 0x08 -#define SMBSLV_STAT_SLV_STS 0x04 -#define SMBSLV_STAT_SLV_INIT 0x02 -#define SMBSLV_STAT_SLV_BUSY 0x01 +#define SMBSLV_STAT_SHADOW2 0x10 +#define SMBSLV_STAT_SHADOW1 0x08 +#define SMBSLV_STAT_SLV_STS 0x04 +#define SMBSLV_STAT_SLV_INIT 0x02 +#define SMBSLV_STAT_SLV_BUSY 0x01 #define SMBSLV_STAT_CLEAR 0x1f -#define SMBHSTCTRL 0x2 +#define SMBHSTCTRL 0x2 #define SMBHST_CTRL_RST 0x80 #define SMBHST_CTRL_STRT 0x40 -#define SMBHST_CTRL_QCK_RW 0x00 -#define SMBHST_CTRL_BTE_RW 0x04 -#define SMBHST_CTRL_BDT_RW 0x08 -#define SMBHST_CTRL_WDT_RW 0x0c -#define SMBHST_CTRL_BLK_RW 0x14 +#define SMBHST_CTRL_QCK_RW 0x00 +#define SMBHST_CTRL_BTE_RW 0x04 +#define SMBHST_CTRL_BDT_RW 0x08 +#define SMBHST_CTRL_WDT_RW 0x0c +#define SMBHST_CTRL_BLK_RW 0x14 #define SMBHST_CTRL_KILL 0x02 #define SMBHST_CTRL_IEN 0x01 +#define SMBHST_CTRL_MODE_BITS 0x1c -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc -#define SMBTIMING 0xe +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc +#define SMBTIMING 0xe -#define SMB_BASE_ADDR 0xb00 +#define SMB_BASE_ADDR 0xb00 -#define AX_INDXC 0 -#define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 -#define RC_INDXC 1 -#define RC_INDXP 3 +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 -#define AB_INDX 0xcd8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX+4) /* * Between 1-10 seconds, We should never timeout normally diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 0c31a3e..3898a1f 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -108,20 +108,12 @@ .write_byte = lsmbus_write_byte, }; -static void sm_read_resources(device_t dev) -{ -} - -static void sm_set_resources(struct device *dev) -{ -} - static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations smbus_ops = { - .read_resources = sm_read_resources, - .set_resources = sm_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = pci_dev_enable_resources, .init = sm_init, .scan_bus = scan_smbus, diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index b216f1e..855f86c 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -24,7 +24,7 @@ do { u8 val; val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; + val &= SMBHST_STAT_VAL_BITS; if (val == 0) { /* ready now */ return 0; } @@ -41,10 +41,10 @@ u8 val; val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; /* mask off reserved bits */ - if (val & 0x1c) + val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */ + if (val & SMBHST_STAT_ERROR_BITS) return -5; /* error */ - if (val == 0x02) { + if (val == SMBHST_STAT_NOERROR) { outb(val, smbus_io_base + SMBHSTSTAT); /* clear sts */ return 0; } @@ -63,8 +63,8 @@ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data R/W cmd, start the command */ + byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ + byte |= SMBHST_CTRL_STRT + SMBHST_CTRL_BTE_RW; /* set mode, start */ outb(byte, smbus_io_base + SMBHSTCTRL); /* poll for transaction completion */ @@ -72,7 +72,7 @@ return -3; /* timeout or error */ /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); + byte = inb(smbus_io_base + SMBHSTDAT0); return byte; } @@ -91,8 +91,8 @@ outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data R/W cmd, start command */ + byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ + byte |= SMBHST_CTRL_STRT + SMBHST_CTRL_BTE_RW; /* set mode, start */ outb(byte, smbus_io_base + SMBHSTCTRL); /* poll for transaction completion */ @@ -102,8 +102,7 @@ return 0; } -int do_smbus_read_byte(u32 smbus_io_base, u32 device, - u32 address) +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) { u8 byte; @@ -117,8 +116,8 @@ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data R/W cmd, start command */ + byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ + byte |= SMBHST_CTRL_STRT + SMBHST_CTRL_BDT_RW; /* set mode, start */ outb(byte, smbus_io_base + SMBHSTCTRL); /* poll for transaction completion */ @@ -131,8 +130,7 @@ return byte; } -int do_smbus_write_byte(u32 smbus_io_base, u32 device, - u32 address, u8 val) +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) { u8 byte; @@ -149,8 +147,8 @@ outb(val, smbus_io_base + SMBHSTDAT0); byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data R/W cmd, start command */ + byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ + byte |= SMBHST_CTRL_STRT + SMBHST_CTRL_BDT_RW; /* set mode, start */ outb(byte, smbus_io_base + SMBHSTCTRL); /* poll for transaction completion */ @@ -160,8 +158,7 @@ return 0; } -void alink_ab_indx(u32 reg_space, u32 reg_addr, - u32 mask, u32 val) +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) { u32 tmp; @@ -185,8 +182,7 @@ outl(0, AB_INDX); } -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, - u32 mask, u32 val) +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) { u32 tmp; @@ -210,7 +206,8 @@ outl(0, AB_INDX); } -/* space = 0: AX_INDXC, AX_DATAC +/* + * space = 0: AX_INDXC, AX_DATAC * space = 1: AX_INDXP, AX_DATAP */ void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index 167929c..eb04a3e 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2017 Silverback, Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,82 +14,16 @@ * GNU General Public License for more details. */ +#include <io.h> #include <device/pci_def.h> #include <device/device.h> -/* warning: Porting.h includes an open #pragma pack(1) */ #include <Porting.h> #include <AGESA.h> #include <amdlib.h> #include <soc/southbridge.h> #include <soc/smbus.h> #include <dimmSpd.h> - -/* - * readSmbusByteData - read a single SPD byte from any offset - */ -static int readSmbusByteData(int iobase, int address, char *buffer, int offset) -{ - unsigned int status; - UINT64 limit; - - address |= 1; // set read bit - - __outbyte(iobase + SMBHSTSTAT, SMBHST_STAT_CLEAR); - __outbyte(iobase + SMBSLVSTAT, SMBSLV_STAT_CLEAR); - __outbyte(iobase + SMBHSTCMD, offset); // offset in eeprom - __outbyte(iobase + SMBHSTADDR, address); // slave addr & read bit - __outbyte(iobase + SMBHSTCTRL, SMBHST_CTRL_STRT + SMBHST_CTRL_BDT_RW); - - // time limit to avoid hanging for unexpected error status - limit = __rdtsc() + 2000000000 / 10; - for (;;) { - status = __inbyte(iobase + SMBHSTSTAT); - if (__rdtsc() > limit) - break; - if ((status & SMBHST_STAT_INTERRUPT) == 0) - continue; // SMBusInterrupt not set, keep waiting - if ((status & SMBHST_STAT_BUSY) == SMBHST_STAT_BUSY) - continue; // HostBusy set, keep waiting - break; - } - - buffer[0] = __inbyte(iobase + SMBHSTDAT0); - if (status == SMBHST_STAT_NOERROR) - status = 0; // done with no errors - return status; -} - -/* - * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData - */ -static int readSmbusByte(int iobase, int address, char *buffer) -{ - unsigned int status; - UINT64 limit; - - __outbyte(iobase + SMBHSTSTAT, SMBHST_STAT_CLEAR); - __outbyte(iobase + SMBHSTCTRL, SMBHST_CTRL_STRT + SMBHST_CTRL_BTE_RW); - - // time limit to avoid hanging for unexpected error status - limit = __rdtsc() + 2000000000 / 10; - for (;;) { - status = __inbyte(iobase + SMBHSTSTAT); - if (__rdtsc() > limit) - break; - if ((status & SMBHST_STAT_INTERRUPT) == 0) - continue; // SMBusInterrupt not set, keep waiting - if ((status & SMBHST_STAT_BUSY) == SMBHST_STAT_BUSY) - continue; // HostBusy set, keep waiting - break; - } - - buffer[0] = __inbyte(iobase + SMBHSTDAT0); - if (status == SMBHST_STAT_NOERROR) - status = 0; // done with no errors - return status; -} /* * readspd - Read one or more SPD bytes from a DIMM. @@ -99,27 +34,40 @@ */ static int readspd(int iobase, int SmbusSlaveAddress, char *buffer, int count) { + u32 smbus_base, dev_addr; int index, error; + char *pbuf = buffer; printk(BIOS_SPEW, "-------------READING SPD-----------\n"); printk(BIOS_SPEW, "iobase: 0x%08X, SmbusSlave: 0x%08X, count: %d\n", iobase, SmbusSlaveAddress, count); - /* read the first byte using offset zero */ - error = readSmbusByteData(iobase, SmbusSlaveAddress, buffer, 0); + /* + * Convert received parameters to the format accepted by + * do_smbus_read_byte and do_smbus_recv_byte. + */ + dev_addr = (u32)((SmbusSlaveAddress & 0xfe) >> 1); + smbus_base = (u32) iobase; - if (error) { + /* Read the first SPD byte */ + error = do_smbus_read_byte(smbus_base, dev_addr, 0); + if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; + } else { + *pbuf = (char) (error & 0xff); + pbuf++; } - /* read the remaining bytes using auto-increment for speed */ + /* Read the remaining SPD bytes using do_smbus_recv_byte for speed */ for (index = 1 ; index < count ; index++) { - error = readSmbusByte(iobase, SmbusSlaveAddress, - &buffer[index]); - if (error) { + error = do_smbus_recv_byte(smbus_base, dev_addr); + if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; + } else { + *pbuf = (char) (error & 0xff); + pbuf++; } } printk(BIOS_SPEW, "\n"); @@ -130,8 +78,8 @@ static void writePmReg(int reg, int data) { - __outbyte(PM_INDEX, reg); - __outbyte(PM_DATA, data); + outb(reg, PM_INDEX); + outb(data, PM_DATA); } static void setupFch(int ioBase) @@ -141,6 +89,9 @@ writePmReg(0x2c, ioBase | 1); /* set SMBus clock to 400 KHz */ __outbyte(ioBase + SMBTIMING, 66000000 / 400000 / 4); + /* Clear all SMBUS status bits */ + outb(SMBHST_STAT_CLEAR, ioBase + SMBHSTSTAT); + outb(SMBSLV_STAT_CLEAR, ioBase + SMBSLVSTAT); } int sb_readSpd(int spdAddress, char *buf, size_t len) diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 5e36100..895e45a 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -26,11 +26,8 @@ #include <cbmem.h> #include <amd_pci_util.h> #include <soc/southbridge.h> -#include <soc/smbus.h> #include <soc/smi.h> -#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) #include <fchec.h> -#endif int acpi_get_sleep_type(void) @@ -98,12 +95,11 @@ void southbridge_final(void *chip_info) { -#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) - agesawrapper_fchecfancontrolservice(); -#if !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) - enable_imc_thermal_zone(); -#endif -#endif + if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) { + agesawrapper_fchecfancontrolservice(); + if (IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)) + enable_imc_thermal_zone(); + } } /* -- To view, visit https://review.coreboot.org/21887 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibd55560c95b6752652a4f255b04198e7a4e77d05 Gerrit-Change-Number: 21887 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: google/cyan: fix variant memory/silicon init params override
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21704 ) Change subject: google/cyan: fix variant memory/silicon init params override ...................................................................... Patch Set 4: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61580/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16689/ : SUCCESS -- To view, visit https://review.coreboot.org/21704 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b Gerrit-Change-Number: 21704 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 00:51:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Documentation: add thinkpad/codenames.csv
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21364 ) Change subject: Documentation: add thinkpad/codenames.csv ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61579/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16688/ : SUCCESS -- To view, visit https://review.coreboot.org/21364 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iae44ceb29675511ec562c275e750087eca5d2f27 Gerrit-Change-Number: 21364 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Swift Geek <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 00:26:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add support in SKL for PMC common code
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20499 ) Change subject: soc/intel/skylake: Add support in SKL for PMC common code ...................................................................... Patch Set 29: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-checkpatch/16687/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/61578/ : UNSTABLE -- To view, visit https://review.coreboot.org/20499 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Gerrit-Change-Number: 20499 Gerrit-PatchSet: 29 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 00:23:24 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Manage power state variable from common PMC b...
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21851 ) Change subject: soc/intel/common/block: Manage power state variable from common PMC block ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61577/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16686/ : SUCCESS -- To view, visit https://review.coreboot.org/21851 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If65341c1492e3a35a1a927100e0d893f923b9e68 Gerrit-Change-Number: 21851 Gerrit-PatchSet: 8 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 23:57:40 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add support in SKL for PMC common code
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20499 ) Change subject: soc/intel/skylake: Add support in SKL for PMC common code ...................................................................... Patch Set 28: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61576/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16685/ : SUCCESS -- To view, visit https://review.coreboot.org/20499 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Gerrit-Change-Number: 20499 Gerrit-PatchSet: 28 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 23:33:31 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: NOTFORMERGE amd/stoneyridge: Jam sleep states for testing
by Marshall Dawson (Code Review) 05 Oct '17

05 Oct '17

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/21884 ) Change subject: NOTFORMERGE amd/stoneyridge: Jam sleep states for testing ...................................................................... Patch Set 1: Code-Review-2 -- To view, visit https://review.coreboot.org/21884 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6abd1a924d62f218aaa743b538faa7d9bf0dc147 Gerrit-Change-Number: 21884 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 23:14:53 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [DoNotMerge]intel/mainboard/cannonlake: Disable HDA temporary
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21885 ) Change subject: [DoNotMerge]intel/mainboard/cannonlake: Disable HDA temporary ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61574/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16684/ : SUCCESS -- To view, visit https://review.coreboot.org/21885 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icc1ad7db527f419cc32d6714cc94edff44e64200 Gerrit-Change-Number: 21885 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 23:06:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [DoNotMerge]intel/mainboard/cannonlake: Disable HDA temporary
by Lijian Zhao (Code Review) 05 Oct '17

05 Oct '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21885 Change subject: [DoNotMerge]intel/mainboard/cannonlake: Disable HDA temporary ...................................................................... [DoNotMerge]intel/mainboard/cannonlake: Disable HDA temporary Disable HDA by default for now. Change-Id: Icc1ad7db527f419cc32d6714cc94edff44e64200 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/21885/1 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 119af48..c4e85b2 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -81,7 +81,7 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 off end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 6e7c535..8f0fa3f 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -81,7 +81,7 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 off end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE -- To view, visit https://review.coreboot.org/21885 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icc1ad7db527f419cc32d6714cc94edff44e64200 Gerrit-Change-Number: 21885 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: WIP amd/stoneyridge: Add placeholder for SlpTyp handler in SMI
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21751 ) Change subject: WIP amd/stoneyridge: Add placeholder for SlpTyp handler in SMI ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/16677/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/61569/ : SUCCESS -- To view, visit https://review.coreboot.org/21751 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I88d413cdbfc2daf44e8d1142c6532f7034795ead Gerrit-Change-Number: 21751 Gerrit-PatchSet: 4 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Oct 2017 23:00:14 +0000 Gerrit-HasComments: No

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coreboot-gerrit October 2017