coreboot-gerrit October 2017

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Change in coreboot[master]: soc/intel/skylake: Enable bus master for sata
by Kane Chen (Code Review) 05 Oct '17

05 Oct '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21890 to look at the new patch set (#3). Change subject: soc/intel/skylake: Enable bus master for sata ...................................................................... soc/intel/skylake: Enable bus master for sata The bus master needs to be enabled so that the busy bit in ahci PORT_TFDATA will be clear by controller when depthcharge tries to wait for sata to complete spin-up during ahci init. Otherwise, the timeout will happen and cause 5 seconds delay in depthcharge. BUG=b:37639063 BRANCH=none TEST=verify that the sata timeout is gone in depthcharge Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/common/block/sata/sata.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/21890/3 -- To view, visit https://review.coreboot.org/21890 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 Gerrit-Change-Number: 21890 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/docker: Add bc to coreboot-sdk
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21889 ) Change subject: util/docker: Add bc to coreboot-sdk ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61589/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16700/ : SUCCESS -- To view, visit https://review.coreboot.org/21889 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I02f2d5296e7f87876b236af119965d1f4e6a0bc0 Gerrit-Change-Number: 21889 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 03:14:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable bus master for sata
by Kane Chen (Code Review) 05 Oct '17

05 Oct '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21890 to look at the new patch set (#2). Change subject: soc/intel/skylake: Enable bus master for sata ...................................................................... soc/intel/skylake: Enable bus master for sata The bus master needs to be enabled so that the busy bit will be clear by controller when depthcharge tries to wait for sata to complete spin-up during ahci init. Otherwise, the timeout will happen and cause 5 seconds delay in depthcharge BUG=b:37639063 BRANCH=none TEST=verify that the sata timeout is gone in depthcharge Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/common/block/sata/sata.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/21890/2 -- To view, visit https://review.coreboot.org/21890 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 Gerrit-Change-Number: 21890 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Enable bus master for sata
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21890 ) Change subject: soc/intel/skylake: Enable bus master for sata ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61590/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16701/ : SUCCESS -- To view, visit https://review.coreboot.org/21890 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 Gerrit-Change-Number: 21890 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 03:08:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable bus master for sata
by Kane Chen (Code Review) 05 Oct '17

05 Oct '17

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/21890 Change subject: soc/intel/skylake: Enable bus master for sata ...................................................................... soc/intel/skylake: Enable bus master for sata The bus master needs to be enabled so that the busy bit will be clear by controller when depthcharge tries to wait for sata to complete spin-up during ahci init. Otherwise, the timeout will happen and cause 5 seconds delay in depthcharge Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/common/block/sata/sata.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/21890/1 diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 5cacc95..f300656 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -45,6 +45,11 @@ u32 port_impl, temp; dev = PCH_DEV_SATA; + + /* Set Bus Master */ + temp = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER); + /* Read Ports Implemented (GHC_PI) */ port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED) & 0x07; /* Port enable */ -- To view, visit https://review.coreboot.org/21890 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 Gerrit-Change-Number: 21890 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Don't force the AMD firmware outside cbfs
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21867 ) Change subject: soc/amd/stoneyridge: Don't force the AMD firmware outside cbfs ...................................................................... Patch Set 2: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61588/ : UNSTABLE -- To view, visit https://review.coreboot.org/21867 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia8258b5c2ecfaaa42d623e3376ec3233115aed58 Gerrit-Change-Number: 21867 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 02:56:02 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Pass firmware dir location to amdfwtool
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21866 ) Change subject: soc/amd/stoneyridge: Pass firmware dir location to amdfwtool ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61587/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16699/ : SUCCESS -- To view, visit https://review.coreboot.org/21866 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa2e99ea031fc0d9f165ae44ff6b1afef369eb28 Gerrit-Change-Number: 21866 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 02:54:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/docker: Add bc to coreboot-sdk
by Martin Roth (Code Review) 05 Oct '17

05 Oct '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/21889 Change subject: util/docker: Add bc to coreboot-sdk ...................................................................... util/docker: Add bc to coreboot-sdk bc is one of the standard posix utilities. I'm surprised that it's not in the debian docker image by default. Change-Id: I02f2d5296e7f87876b236af119965d1f4e6a0bc0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M util/docker/coreboot-sdk/Dockerfile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/21889/1 diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index 512db06..045963c 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -19,6 +19,7 @@ useradd -p locked -m coreboot && \ apt-get -qq update && \ apt-get -qqy install \ + bc \ bison \ bzip2 \ ccache \ -- To view, visit https://review.coreboot.org/21889 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I02f2d5296e7f87876b236af119965d1f4e6a0bc0 Gerrit-Change-Number: 21889 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/amd/stoneyridge: SMBUS code simplify
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21887 ) Change subject: soc/amd/stoneyridge: SMBUS code simplify ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61582/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16698/ : SUCCESS -- To view, visit https://review.coreboot.org/21887 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibd55560c95b6752652a4f255b04198e7a4e77d05 Gerrit-Change-Number: 21887 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 02:22:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add support in SKL for PMC common code
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20499 ) Change subject: soc/intel/skylake: Add support in SKL for PMC common code ...................................................................... Patch Set 29: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61578/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16697/ : SUCCESS -- To view, visit https://review.coreboot.org/20499 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Gerrit-Change-Number: 20499 Gerrit-PatchSet: 29 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 02:22:18 +0000 Gerrit-HasComments: No

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coreboot-gerrit October 2017