coreboot-gerrit October 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Enabled MRC Cache
by Lijian Zhao (Code Review) 05 Oct '17

05 Oct '17

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/21892 ) Change subject: soc/intel/cannonlake: Enabled MRC Cache ...................................................................... Patch Set 1: What kind of fmap will be using when vboot and chromeos got disabled in config? -- To view, visit https://review.coreboot.org/21892 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e Gerrit-Change-Number: 21892 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 06:51:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Enabled MRC Cache
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21892 ) Change subject: soc/intel/cannonlake: Enabled MRC Cache ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61596/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16705/ : SUCCESS -- To view, visit https://review.coreboot.org/21892 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e Gerrit-Change-Number: 21892 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 06:33:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/cannonlake_rvp: Declare PCIE clock usage
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21879 ) Change subject: intel/cannonlake_rvp: Declare PCIE clock usage ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61595/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16704/ : SUCCESS -- To view, visit https://review.coreboot.org/21879 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7d71d9a87d87ce6a3e3270f67518afdd54a48db4 Gerrit-Change-Number: 21879 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 06:27:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Enabled MRC Cache
by Lijian Zhao (Code Review) 05 Oct '17

05 Oct '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21892 Change subject: soc/intel/cannonlake: Enabled MRC Cache ...................................................................... soc/intel/cannonlake: Enabled MRC Cache Enable MRC cache by default. TEST=Warm reset and check coreboot serial log. Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/21892/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 2d9ffa4..756cdc4 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -15,6 +15,7 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK + select CACHE_MRC_SETTINGS select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select GENERIC_GPIO_LIB @@ -26,6 +27,7 @@ select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP select IOAPIC + select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 -- To view, visit https://review.coreboot.org/21892 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e Gerrit-Change-Number: 21892 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: src/device: Update LTR configuration scheme
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21868 ) Change subject: src/device: Update LTR configuration scheme ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61593/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16702/ : SUCCESS -- To view, visit https://review.coreboot.org/21868 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe Gerrit-Change-Number: 21868 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 05 Oct 2017 06:07:54 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Update PCIE CLKREQ programing
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21878 ) Change subject: soc/intel/cannonlake: Update PCIE CLKREQ programing ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61594/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16703/ : SUCCESS -- To view, visit https://review.coreboot.org/21878 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2261deccfb489c0de577d580997744a484f07a04 Gerrit-Change-Number: 21878 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 06:06:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/cannonlake_rvp: Declare PCIE clock usage
by Lijian Zhao (Code Review) 05 Oct '17

05 Oct '17

Hello Subrata Banik, AndreX Andraos, John Zhao, Bora Guvendik, build bot (Jenkins), Hannah Williams, Shaunak Saha, Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/21879 to look at the new patch set (#4). Change subject: intel/cannonlake_rvp: Declare PCIE clock usage ...................................................................... intel/cannonlake_rvp: Declare PCIE clock usage Define PCI express clock usage for cannonlake u and cannonlake y rvp based on board design. TEST=Bootable into OS. Change-Id: I7d71d9a87d87ce6a3e3270f67518afdd54a48db4 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/21879/4 -- To view, visit https://review.coreboot.org/21879 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7d71d9a87d87ce6a3e3270f67518afdd54a48db4 Gerrit-Change-Number: 21879 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/cannonlake: Update PCIE CLKREQ programing
by Lijian Zhao (Code Review) 05 Oct '17

05 Oct '17

Hello Pratikkumar V Prajapati, Subrata Banik, Ravishankar Sarawadi, Bora Guvendik, build bot (Jenkins), Hannah Williams, Shaunak Saha, Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/21878 to look at the new patch set (#4). Change subject: soc/intel/cannonlake: Update PCIE CLKREQ programing ...................................................................... soc/intel/cannonlake: Update PCIE CLKREQ programing UPD of PCI express clock request had been updated in FSP 7.0.14.11, change that in coreboot accordingly. TEST=NONE Change-Id: I2261deccfb489c0de577d580997744a484f07a04 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/pch.h M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/romstage/romstage.c 5 files changed, 27 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/21878/4 -- To view, visit https://review.coreboot.org/21878 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2261deccfb489c0de577d580997744a484f07a04 Gerrit-Change-Number: 21878 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Enable bus master for sata
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21890 ) Change subject: soc/intel/skylake: Enable bus master for sata ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61592/ : SUCCESS -- To view, visit https://review.coreboot.org/21890 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 Gerrit-Change-Number: 21890 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 03:19:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable bus master for sata
by build bot (Jenkins) (Code Review) 05 Oct '17

05 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21890 ) Change subject: soc/intel/skylake: Enable bus master for sata ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/61591/ : ABORTED -- To view, visit https://review.coreboot.org/21890 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 Gerrit-Change-Number: 21890 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2017 03:14:30 +0000 Gerrit-HasComments: No

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coreboot-gerrit October 2017