coreboot-gerrit January 2017

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Patch set updated for coreboot: amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc
by Timothy Pearson 08 Jan '17

08 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18058 -gerrit commit 86d1a12ffd0e7095c396741119ac7276f0bf7592 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Sun Jan 8 14:00:48 2017 -0600 amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc Several members of DCTStatStruc are designed to persist across resets of all other members. Move the persistent members into a substructure in order to simplify the reset logic and avoid compiler warnings / UB. Change-Id: I1139b7b3b167d33d99619338d42fcd26e2581a5d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 33 ++++----------- src/northbridge/amd/amdmct/mct/mct_d.h | 57 +++++++++++++++----------- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 6 +-- src/northbridge/amd/amdmct/mct/mctsrc.c | 14 +++---- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct/mctsrc2p.c | 6 +-- src/northbridge/amd/amdmct/mct/mcttmrl.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 20 +++------ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 30 ++++++++------ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 20 ++++----- src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 24 +++++------ src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c | 6 +-- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 2 +- 15 files changed, 105 insertions(+), 121 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 73aa20b..909037f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2017 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -35,6 +35,8 @@ #include "mct_d.h" +#include <string.h> + static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void DQSTiming_D(struct MCTStatStruc *pMCTstat, @@ -459,7 +461,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } for (Dir = 0; Dir < 2; Dir++) {//RD/WR - p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][DIMM][Dir]; val = stream_to_int(p); /* CHA Read Data Timing High */ Set_NB32_index_wait(dev, index_reg, index+1, val); val = stream_to_int(p+4); /* CHA Write Data Timing High */ @@ -3598,37 +3600,16 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { u8 Node; - u32 i; struct DCTStatStruc *pDCTstat; - u32 start, stop; - u8 *p; - u16 host_serv1, host_serv2; /* Initialize Data structures by clearing all entries to 0 */ - p = (u8 *) pMCTstat; - for (i = 0; i < sizeof(struct MCTStatStruc); i++) { - p[i] = 0; - } + memset(pMCTstat, 0x00, sizeof(*pMCTstat)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; - host_serv1 = pDCTstat->HostBiosSrvc1; - host_serv2 = pDCTstat->HostBiosSrvc2; - - p = (u8 *) pDCTstat; - start = 0; - stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); - for (i = start; i < stop; i++) { - p[i] = 0; - } - start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); - stop = sizeof(struct DCTStatStruc); - for (i = start; i < stop; i++) { - p[i] = 0; - } - pDCTstat->HostBiosSrvc1 = host_serv1; - pDCTstat->HostBiosSrvc2 = host_serv2; + /* Clear all entries except persistentData */ + memset(pDCTstat, 0x00, sizeof(*pDCTstat) - sizeof(pDCTstat->persistentData)); } } diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 75c4d62..d13143d 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2017 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -296,6 +296,34 @@ struct MCTStatStruc { Local DCT Status structure (a structure for each DCT) ===============================================================================*/ +struct DCTPersistentStatStruc { + u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ + /* CHA DIMM 0 Receiver Enable Delay*/ + /* CHA DIMM 1 Receiver Enable Delay*/ + /* CHA DIMM 2 Receiver Enable Delay*/ + /* CHA DIMM 3 Receiver Enable Delay*/ + + /* CHB DIMM 0 Receiver Enable Delay*/ + /* CHB DIMM 1 Receiver Enable Delay*/ + /* CHB DIMM 2 Receiver Enable Delay*/ + /* CHB DIMM 3 Receiver Enable Delay*/ + u8 CH_D_BC_RCVRDLY[2][4]; + /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ + u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ +} __attribute__((packed)); + + struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller*/ @@ -445,8 +473,6 @@ struct DCTStatStruc { /* A per Node structure*/ /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ uint64_t LogicalCPUID; /* The logical CPUID of the node*/ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ u16 DimmQRPresent; /* QuadRank DIMM present?*/ u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ @@ -462,28 +488,6 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/ /* Max Read Latency (ns) for DCT 1*/ - u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ - /* CHA DIMM 0 Receiver Enable Delay*/ - /* CHA DIMM 1 Receiver Enable Delay*/ - /* CHA DIMM 2 Receiver Enable Delay*/ - /* CHA DIMM 3 Receiver Enable Delay*/ - - /* CHB DIMM 0 Receiver Enable Delay*/ - /* CHB DIMM 1 Receiver Enable Delay*/ - /* CHB DIMM 2 Receiver Enable Delay*/ - /* CHB DIMM 3 Receiver Enable Delay*/ - u8 CH_D_BC_RCVRDLY[2][4]; - /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ - /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ /* DIMM# in DCT1*/ u8 MaxDCTs; /* Max number of DCTs in system*/ @@ -542,6 +546,9 @@ struct DCTStatStruc { /* A per Node structure*/ char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH+1]; uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED]; uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; + + /* NOTE: This must remain the last entry in this structure */ + struct DCTPersistentStatStruc persistentData; } __attribute__((packed)); /*=============================================================================== diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index ec77c49..7140007 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -351,7 +351,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", Channel); for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); - p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); @@ -583,7 +583,7 @@ void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->Status & (1 << SB_Over400MHz)) dn = ChipSel>>1; /* if odd or even logical DIMM */ - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = pDCTstat->DQSDelay; } @@ -606,7 +606,7 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel >> 1; /*if odd or even logical DIMM */ pDCTstat->DQSDelay = - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 3b7cff8..60857f4 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -476,7 +476,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", Channel); for (Receiver = 0; Receiver < 8; Receiver+=2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); @@ -567,7 +567,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } @@ -719,11 +719,11 @@ static u8 mct_SavePassRcvEnDly_D(struct DCTStatStruc *pDCTstat, /* find desired stack offset according to channel/dimm/byte */ if (Pass == SecondPass) { - // FIXME: SecondPass is never used for Barcelona p = pDCTstat->CH_D_B_RCVRDLY_1[Channel][receiver>>1]; + // FIXME: SecondPass is never used for Barcelona p = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][receiver>>1]; p = 0; // Keep the compiler happy. } else { mask_Saved &= mask_Pass; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][receiver>>1]; } for (i = 0; i < 8; i++) { /* cmp per byte lane */ @@ -903,7 +903,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) dev = pDCTstat->dev_dct; index_reg = 0x98 + Channel * 0x100; index = 0x12; - p = pDCTstat->CH_D_BC_RCVRDLY[Channel]; + p = pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel]; print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { val = p[ChipSel>>1]; @@ -929,7 +929,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { u8 *p; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][ChipSel>>1]; /* DQS Delay Value of Data Bytelane * most like ECC byte lane */ @@ -953,7 +953,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, val += val0; } - pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; } } SetEccDQSRcvrEn_D(pDCTstat, Channel); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index 31a3a5d..8ae6025 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -49,7 +49,7 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, u8 val; MaxValue = 0; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index 7454f53..ab278e9 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -57,7 +57,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 max = 0; u8 val; u8 i; - u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + u8 *p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; u8 bn; bn = 8; @@ -91,12 +91,12 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; if (Pass == SecondPass) { /* second pass must average values */ //FIXME: which byte? p_1 = pDCTstat->B_RCVRDLY_1; -// p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; +// p_1 = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 67397fc..4c6d8e6 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -297,7 +297,7 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, for (d = 0; d < 4; d++) { for (Byte = 0; Byte < bn; Byte++) { u8 tmp; - tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; + tmp = pDCTstat->persistentData.CH_D_B_RCVRDLY[ch][d][Byte]; if (tmp > Max) { Max = tmp; Channel_Max = Channel; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index d1d6e8f..eb794bd 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Raptor Engineering, LLC + * Copyright (C) 2015-2017 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -3732,7 +3732,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, 2); /* Pass Second Pass ? */ /* Restore Write levelization training data */ for (ByteLane = 0; ByteLane < 9; ByteLane ++) { - txdqs = pDCTstat->CH_D_B_TxDqs[Channel][Receiver >> 1][ByteLane]; + txdqs = pDCTstat->persistentData.CH_D_B_TxDqs[Channel][Receiver >> 1][ByteLane]; index = Table_DQSRcvEn_Offset[ByteLane >> 1]; index += (Receiver >> 1) * 3 + 0x10 + 0x20; /* Addl_Index */ val = Get_NB32_index_wait_DCT(dev, Channel, 0x98, index); @@ -3775,7 +3775,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } for (Dir = 0; Dir < 2; Dir++) {/* RD/WR */ - p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][DIMM][Dir]; val = stream_to_int(p); /* CHA Read Data Timing High */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, index+1, val); val = stream_to_int(p+4); /* CHA Write Data Timing High */ @@ -7373,23 +7373,13 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, { uint8_t Node; struct DCTStatStruc *pDCTstat; - uint16_t host_serv1, host_serv2; - uint8_t CH_D_B_TxDqs_bkp[2][4][9]; /* Initialize Data structures by clearing all entries to 0 */ - memset(pMCTstat, 0, sizeof(struct MCTStatStruc)); + memset(pMCTstat, 0, sizeof(*pMCTstat)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; - host_serv1 = pDCTstat->HostBiosSrvc1; - host_serv2 = pDCTstat->HostBiosSrvc2; - memcpy(CH_D_B_TxDqs_bkp, pDCTstat->CH_D_B_TxDqs, sizeof(CH_D_B_TxDqs_bkp)); - - memset(pDCTstat, 0, sizeof(struct DCTStatStruc)); - - pDCTstat->HostBiosSrvc1 = host_serv1; - pDCTstat->HostBiosSrvc2 = host_serv2; - memcpy(pDCTstat->CH_D_B_TxDqs, CH_D_B_TxDqs_bkp, sizeof(pDCTstat->CH_D_B_TxDqs)); + memset(pDCTstat, 0, sizeof(*pDCTstat) - sizeof(pDCTstat->persistentData)); } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 575a9d6..d4b3792 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Raptor Engineering, LLC + * Copyright (C) 2015-2017 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -335,6 +335,20 @@ struct amd_spd_node_data { uint8_t nvram_memclk[2]; /* [channel] */ } __attribute__((packed, aligned(4))); +struct DCTPersistentStatStruc { + u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 TxDqs */ + /* CHA DIMM0 Byte 0 - 7 TxDqs */ + /* CHA DIMM1 Byte 0 - 7 TxDqs */ + /* CHA DIMM1 Byte 0 - 7 TxDqs */ + /* CHB DIMM0 Byte 0 - 7 TxDqs */ + /* CHB DIMM0 Byte 0 - 7 TxDqs */ + /* CHB DIMM1 Byte 0 - 7 TxDqs */ + /* CHB DIMM1 Byte 0 - 7 TxDqs */ + u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ + u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ +} __attribute__((packed, aligned(4))); + struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller */ @@ -485,8 +499,6 @@ struct DCTStatStruc { /* A per Node structure*/ /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ uint64_t LogicalCPUID; /* The logical CPUID of the node*/ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ u16 DimmQRPresent; /* QuadRank DIMM present?*/ u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ @@ -513,15 +525,6 @@ struct DCTStatStruc { /* A per Node structure*/ /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ u16 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ /* CHA DIMM 0 Receiver Enable Delay*/ /* CHA DIMM 1 Receiver Enable Delay*/ @@ -635,6 +638,9 @@ struct DCTStatStruc { /* A per Node structure*/ uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; struct amd_spd_node_data spd_data; + + /* NOTE: This must remain the last entry in this structure */ + struct DCTPersistentStatStruc persistentData; } __attribute__((packed, aligned(4))); struct amd_s3_persistent_mct_channel_data { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 69b0104..33c3011 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -738,7 +738,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); /* Save the final Read DQS Timing Control settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; } else { print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 122 Unable to find read passing region for lane ", lane, 2); @@ -781,7 +781,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); /* Save the final Write Data Timing settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; } else { print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 123 Unable to find write passing region for lane ", lane, 2); @@ -814,7 +814,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1467,7 +1467,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); /* Save the final Read DQS Timing Control settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 142 largest read passing region ", best_count, 4); print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest read passing region start ", best_pos, 4); @@ -1520,7 +1520,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg); /* Save the final Write Data Timing settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4); print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 146 largest write passing region start ", best_pos, 4); @@ -1585,7 +1585,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1845,7 +1845,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1922,7 +1922,7 @@ static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel>>1; /* if odd or even logical DIMM */ - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = pDCTstat->DQSDelay; } @@ -1942,7 +1942,7 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel >> 1; /*if odd or even logical DIMM */ pDCTstat->DQSDelay = - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; } /* FindDQSDatDimmVal_D is not required since we use an array */ @@ -2301,7 +2301,7 @@ static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat, val = Get_NB32_index_wait_DCT(dev, pDCTstat->Channel, index_reg, index); if (ByteLane < 8) { if (pDCTstat->Direction == DQS_WRITEDIR) { - dqs_delay += pDCTstat->CH_D_B_TxDqs[pDCTstat->Channel][ChipSel>>1][ByteLane]; + dqs_delay += pDCTstat->persistentData.CH_D_B_TxDqs[pDCTstat->Channel][ChipSel>>1][ByteLane]; } else { dqs_delay <<= 1; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c index 4c6776d..4fe5ad3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c @@ -66,7 +66,7 @@ static void SetEccWrDQS_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pD if (OddByte) val >>= 16; /* Save WrDqs to stack for later usage */ - pDCTstat->CH_D_B_TxDqs[Channel][DimmNum][ByteLane] = val & 0xFF; + pDCTstat->persistentData.CH_D_B_TxDqs[Channel][DimmNum][ByteLane] = val & 0xFF; EccDQSScale = pDCTstat->CH_EccDQSScale[Channel]; word = pDCTstat->CH_EccDQSLike[Channel]; if ((word & 0xFF) == ByteLane) EccRef1 = val & 0xFF; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index fd8a8e7..a2e6ad5 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -949,7 +949,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, */ for (lane = 0; lane < 8; lane++) { if (trained[lane]) { - pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; } else { printk(BIOS_WARNING, "TrainRcvrEn: WARNING: Lane %d of receiver %d on channel %d failed training!\n", lane, Receiver, Channel); @@ -1029,7 +1029,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); - p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); @@ -1433,7 +1433,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, #if DQS_TRAIN_DEBUG > 1 for (lane = 0; lane < 8; lane++) printk(BIOS_DEBUG, "\t\tTrainRcvEn55: Channel: %d dimm: %d nibble: %d lane %d current_total_delay: %04x CH_D_B_RCVRDLY: %04x\n", - Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane]); + Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane]); #endif write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); @@ -1460,9 +1460,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, for (lane = 0; lane < lane_count; lane++) { current_total_delay[lane] = (rank0_current_total_delay[lane] + current_total_delay[lane]) / 2; if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); } @@ -1470,9 +1470,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Save the current delay for later use by other routines */ for (lane = 0; lane < lane_count; lane++) { if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } } } @@ -1531,7 +1531,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); - p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); @@ -1805,7 +1805,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } @@ -2007,7 +2007,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) dev = pDCTstat->dev_dct; index_reg = 0x98; index = 0x12; - p = pDCTstat->CH_D_BC_RCVRDLY[Channel]; + p = pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel]; print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { val = p[ChipSel>>1]; @@ -2033,7 +2033,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { u16 *p; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][ChipSel>>1]; if (pDCTstat->Status & (1 << SB_Registered)) { val0 = p[0x2]; @@ -2067,7 +2067,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, } } - pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; } } SetEccDQSRcvrEn_D(pDCTstat, Channel); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c index 2592eed..f5539fc 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c @@ -68,7 +68,7 @@ static u16 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel u16 val; MaxValue = 0; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c index 7f67824..8eeb93f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c @@ -54,7 +54,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 max = 0; u8 val; u8 i; - u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + u8 *p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; u8 bn; bn = 8; @@ -85,12 +85,12 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; if (Pass == SecondPass) { /* second pass must average values */ /* FIXME: which byte? */ p_1 = pDCTstat->B_RCVRDLY_1; - /* p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ + /* p_1 = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 039a747..dc42456 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -293,7 +293,7 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, for (d = 0; d < 4; d++) { for (Byte = 0; Byte < bn; Byte++) { u8 tmp; - tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; + tmp = pDCTstat->persistentData.CH_D_B_RCVRDLY[ch][d][Byte]; if (tmp > Max) { Max = tmp; Channel_Max = Channel;

1 0

Patch set updated for coreboot: amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc
by Timothy Pearson 08 Jan '17

08 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18058 -gerrit commit 96f77f30c7173ab58db3179b8bf2034abaee5dd6 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Sun Jan 8 14:00:48 2017 -0600 amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc Several members of DCTStatStruc are designed to persist across resets of all other members. Move the persistent members into a substructure in order to simplify the reset logic and avoid compiler warnings / UB. Change-Id: I1139b7b3b167d33d99619338d42fcd26e2581a5d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 33 +++--------- src/northbridge/amd/amdmct/mct/mct_d.h | 57 +++++++++++--------- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 6 +-- src/northbridge/amd/amdmct/mct/mctsrc.c | 14 ++--- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct/mctsrc2p.c | 6 +-- src/northbridge/amd/amdmct/mct/mcttmrl.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 20 ++----- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 74 ++++++++++++++------------ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 20 +++---- src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 24 ++++----- src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c | 6 +-- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 2 +- 15 files changed, 127 insertions(+), 143 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 73aa20b..909037f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2017 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -35,6 +35,8 @@ #include "mct_d.h" +#include <string.h> + static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void DQSTiming_D(struct MCTStatStruc *pMCTstat, @@ -459,7 +461,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } for (Dir = 0; Dir < 2; Dir++) {//RD/WR - p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][DIMM][Dir]; val = stream_to_int(p); /* CHA Read Data Timing High */ Set_NB32_index_wait(dev, index_reg, index+1, val); val = stream_to_int(p+4); /* CHA Write Data Timing High */ @@ -3598,37 +3600,16 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { u8 Node; - u32 i; struct DCTStatStruc *pDCTstat; - u32 start, stop; - u8 *p; - u16 host_serv1, host_serv2; /* Initialize Data structures by clearing all entries to 0 */ - p = (u8 *) pMCTstat; - for (i = 0; i < sizeof(struct MCTStatStruc); i++) { - p[i] = 0; - } + memset(pMCTstat, 0x00, sizeof(*pMCTstat)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; - host_serv1 = pDCTstat->HostBiosSrvc1; - host_serv2 = pDCTstat->HostBiosSrvc2; - - p = (u8 *) pDCTstat; - start = 0; - stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); - for (i = start; i < stop; i++) { - p[i] = 0; - } - start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); - stop = sizeof(struct DCTStatStruc); - for (i = start; i < stop; i++) { - p[i] = 0; - } - pDCTstat->HostBiosSrvc1 = host_serv1; - pDCTstat->HostBiosSrvc2 = host_serv2; + /* Clear all entries except persistentData */ + memset(pDCTstat, 0x00, sizeof(*pDCTstat) - sizeof(pDCTstat->persistentData)); } } diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 75c4d62..d13143d 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2017 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -296,6 +296,34 @@ struct MCTStatStruc { Local DCT Status structure (a structure for each DCT) ===============================================================================*/ +struct DCTPersistentStatStruc { + u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ + /* CHA DIMM 0 Receiver Enable Delay*/ + /* CHA DIMM 1 Receiver Enable Delay*/ + /* CHA DIMM 2 Receiver Enable Delay*/ + /* CHA DIMM 3 Receiver Enable Delay*/ + + /* CHB DIMM 0 Receiver Enable Delay*/ + /* CHB DIMM 1 Receiver Enable Delay*/ + /* CHB DIMM 2 Receiver Enable Delay*/ + /* CHB DIMM 3 Receiver Enable Delay*/ + u8 CH_D_BC_RCVRDLY[2][4]; + /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ + u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ +} __attribute__((packed)); + + struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller*/ @@ -445,8 +473,6 @@ struct DCTStatStruc { /* A per Node structure*/ /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ uint64_t LogicalCPUID; /* The logical CPUID of the node*/ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ u16 DimmQRPresent; /* QuadRank DIMM present?*/ u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ @@ -462,28 +488,6 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/ /* Max Read Latency (ns) for DCT 1*/ - u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ - /* CHA DIMM 0 Receiver Enable Delay*/ - /* CHA DIMM 1 Receiver Enable Delay*/ - /* CHA DIMM 2 Receiver Enable Delay*/ - /* CHA DIMM 3 Receiver Enable Delay*/ - - /* CHB DIMM 0 Receiver Enable Delay*/ - /* CHB DIMM 1 Receiver Enable Delay*/ - /* CHB DIMM 2 Receiver Enable Delay*/ - /* CHB DIMM 3 Receiver Enable Delay*/ - u8 CH_D_BC_RCVRDLY[2][4]; - /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ - /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ /* DIMM# in DCT1*/ u8 MaxDCTs; /* Max number of DCTs in system*/ @@ -542,6 +546,9 @@ struct DCTStatStruc { /* A per Node structure*/ char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH+1]; uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED]; uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; + + /* NOTE: This must remain the last entry in this structure */ + struct DCTPersistentStatStruc persistentData; } __attribute__((packed)); /*=============================================================================== diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index ec77c49..7140007 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -351,7 +351,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", Channel); for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); - p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); @@ -583,7 +583,7 @@ void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->Status & (1 << SB_Over400MHz)) dn = ChipSel>>1; /* if odd or even logical DIMM */ - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = pDCTstat->DQSDelay; } @@ -606,7 +606,7 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel >> 1; /*if odd or even logical DIMM */ pDCTstat->DQSDelay = - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 3b7cff8..60857f4 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -476,7 +476,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", Channel); for (Receiver = 0; Receiver < 8; Receiver+=2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); @@ -567,7 +567,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } @@ -719,11 +719,11 @@ static u8 mct_SavePassRcvEnDly_D(struct DCTStatStruc *pDCTstat, /* find desired stack offset according to channel/dimm/byte */ if (Pass == SecondPass) { - // FIXME: SecondPass is never used for Barcelona p = pDCTstat->CH_D_B_RCVRDLY_1[Channel][receiver>>1]; + // FIXME: SecondPass is never used for Barcelona p = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][receiver>>1]; p = 0; // Keep the compiler happy. } else { mask_Saved &= mask_Pass; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][receiver>>1]; } for (i = 0; i < 8; i++) { /* cmp per byte lane */ @@ -903,7 +903,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) dev = pDCTstat->dev_dct; index_reg = 0x98 + Channel * 0x100; index = 0x12; - p = pDCTstat->CH_D_BC_RCVRDLY[Channel]; + p = pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel]; print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { val = p[ChipSel>>1]; @@ -929,7 +929,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { u8 *p; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][ChipSel>>1]; /* DQS Delay Value of Data Bytelane * most like ECC byte lane */ @@ -953,7 +953,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, val += val0; } - pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; } } SetEccDQSRcvrEn_D(pDCTstat, Channel); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index 31a3a5d..8ae6025 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -49,7 +49,7 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, u8 val; MaxValue = 0; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index 7454f53..ab278e9 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -57,7 +57,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 max = 0; u8 val; u8 i; - u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + u8 *p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; u8 bn; bn = 8; @@ -91,12 +91,12 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; if (Pass == SecondPass) { /* second pass must average values */ //FIXME: which byte? p_1 = pDCTstat->B_RCVRDLY_1; -// p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; +// p_1 = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 67397fc..4c6d8e6 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -297,7 +297,7 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, for (d = 0; d < 4; d++) { for (Byte = 0; Byte < bn; Byte++) { u8 tmp; - tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; + tmp = pDCTstat->persistentData.CH_D_B_RCVRDLY[ch][d][Byte]; if (tmp > Max) { Max = tmp; Channel_Max = Channel; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index d1d6e8f..eb794bd 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Raptor Engineering, LLC + * Copyright (C) 2015-2017 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -3732,7 +3732,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, 2); /* Pass Second Pass ? */ /* Restore Write levelization training data */ for (ByteLane = 0; ByteLane < 9; ByteLane ++) { - txdqs = pDCTstat->CH_D_B_TxDqs[Channel][Receiver >> 1][ByteLane]; + txdqs = pDCTstat->persistentData.CH_D_B_TxDqs[Channel][Receiver >> 1][ByteLane]; index = Table_DQSRcvEn_Offset[ByteLane >> 1]; index += (Receiver >> 1) * 3 + 0x10 + 0x20; /* Addl_Index */ val = Get_NB32_index_wait_DCT(dev, Channel, 0x98, index); @@ -3775,7 +3775,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } for (Dir = 0; Dir < 2; Dir++) {/* RD/WR */ - p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][DIMM][Dir]; val = stream_to_int(p); /* CHA Read Data Timing High */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, index+1, val); val = stream_to_int(p+4); /* CHA Write Data Timing High */ @@ -7373,23 +7373,13 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, { uint8_t Node; struct DCTStatStruc *pDCTstat; - uint16_t host_serv1, host_serv2; - uint8_t CH_D_B_TxDqs_bkp[2][4][9]; /* Initialize Data structures by clearing all entries to 0 */ - memset(pMCTstat, 0, sizeof(struct MCTStatStruc)); + memset(pMCTstat, 0, sizeof(*pMCTstat)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; - host_serv1 = pDCTstat->HostBiosSrvc1; - host_serv2 = pDCTstat->HostBiosSrvc2; - memcpy(CH_D_B_TxDqs_bkp, pDCTstat->CH_D_B_TxDqs, sizeof(CH_D_B_TxDqs_bkp)); - - memset(pDCTstat, 0, sizeof(struct DCTStatStruc)); - - pDCTstat->HostBiosSrvc1 = host_serv1; - pDCTstat->HostBiosSrvc2 = host_serv2; - memcpy(pDCTstat->CH_D_B_TxDqs, CH_D_B_TxDqs_bkp, sizeof(pDCTstat->CH_D_B_TxDqs)); + memset(pDCTstat, 0, sizeof(*pDCTstat) - sizeof(pDCTstat->persistentData)); } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 575a9d6..4992034 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Raptor Engineering, LLC + * Copyright (C) 2015-2017 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -335,6 +335,42 @@ struct amd_spd_node_data { uint8_t nvram_memclk[2]; /* [channel] */ } __attribute__((packed, aligned(4))); +struct DCTPersistentStatStruc { + u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 TxDqs */ + /* CHA DIMM0 Byte 0 - 7 TxDqs */ + /* CHA DIMM1 Byte 0 - 7 TxDqs */ + /* CHA DIMM1 Byte 0 - 7 TxDqs */ + /* CHB DIMM0 Byte 0 - 7 TxDqs */ + /* CHB DIMM0 Byte 0 - 7 TxDqs */ + /* CHB DIMM1 Byte 0 - 7 TxDqs */ + /* CHB DIMM1 Byte 0 - 7 TxDqs */ + u16 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ + /* CHA DIMM 0 Receiver Enable Delay*/ + /* CHA DIMM 1 Receiver Enable Delay*/ + /* CHA DIMM 2 Receiver Enable Delay*/ + /* CHA DIMM 3 Receiver Enable Delay*/ + + /* CHB DIMM 0 Receiver Enable Delay*/ + /* CHB DIMM 1 Receiver Enable Delay*/ + /* CHB DIMM 2 Receiver Enable Delay*/ + /* CHB DIMM 3 Receiver Enable Delay*/ + u16 CH_D_BC_RCVRDLY[2][4]; + /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ + u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ +} __attribute__((packed, aligned(4))); + struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller */ @@ -485,8 +521,6 @@ struct DCTStatStruc { /* A per Node structure*/ /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ uint64_t LogicalCPUID; /* The logical CPUID of the node*/ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ u16 DimmQRPresent; /* QuadRank DIMM present?*/ u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ @@ -504,37 +538,6 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CH_MaxRdLat[2][2]; /* Max Read Latency (nclks) [dct][pstate] */ /* Max Read Latency (ns) for DCT 1*/ - u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ - u16 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ - /* CHA DIMM 0 Receiver Enable Delay*/ - /* CHA DIMM 1 Receiver Enable Delay*/ - /* CHA DIMM 2 Receiver Enable Delay*/ - /* CHA DIMM 3 Receiver Enable Delay*/ - - /* CHB DIMM 0 Receiver Enable Delay*/ - /* CHB DIMM 1 Receiver Enable Delay*/ - /* CHB DIMM 2 Receiver Enable Delay*/ - /* CHB DIMM 3 Receiver Enable Delay*/ - u16 CH_D_BC_RCVRDLY[2][4]; - /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ - /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ /* DIMM# in DCT1*/ u16 CSPresent_DCT[2]; /* DCT# CS mapping */ @@ -635,6 +638,9 @@ struct DCTStatStruc { /* A per Node structure*/ uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; struct amd_spd_node_data spd_data; + + /* NOTE: This must remain the last entry in this structure */ + struct DCTPersistentStatStruc persistentData; } __attribute__((packed, aligned(4))); struct amd_s3_persistent_mct_channel_data { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 69b0104..33c3011 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -738,7 +738,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); /* Save the final Read DQS Timing Control settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; } else { print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 122 Unable to find read passing region for lane ", lane, 2); @@ -781,7 +781,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); /* Save the final Write Data Timing settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; } else { print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 123 Unable to find write passing region for lane ", lane, 2); @@ -814,7 +814,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1467,7 +1467,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); /* Save the final Read DQS Timing Control settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 142 largest read passing region ", best_count, 4); print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest read passing region start ", best_pos, 4); @@ -1520,7 +1520,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg); /* Save the final Write Data Timing settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4); print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 146 largest write passing region start ", best_pos, 4); @@ -1585,7 +1585,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1845,7 +1845,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1922,7 +1922,7 @@ static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel>>1; /* if odd or even logical DIMM */ - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = pDCTstat->DQSDelay; } @@ -1942,7 +1942,7 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel >> 1; /*if odd or even logical DIMM */ pDCTstat->DQSDelay = - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; } /* FindDQSDatDimmVal_D is not required since we use an array */ @@ -2301,7 +2301,7 @@ static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat, val = Get_NB32_index_wait_DCT(dev, pDCTstat->Channel, index_reg, index); if (ByteLane < 8) { if (pDCTstat->Direction == DQS_WRITEDIR) { - dqs_delay += pDCTstat->CH_D_B_TxDqs[pDCTstat->Channel][ChipSel>>1][ByteLane]; + dqs_delay += pDCTstat->persistentData.CH_D_B_TxDqs[pDCTstat->Channel][ChipSel>>1][ByteLane]; } else { dqs_delay <<= 1; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c index 4c6776d..4fe5ad3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c @@ -66,7 +66,7 @@ static void SetEccWrDQS_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pD if (OddByte) val >>= 16; /* Save WrDqs to stack for later usage */ - pDCTstat->CH_D_B_TxDqs[Channel][DimmNum][ByteLane] = val & 0xFF; + pDCTstat->persistentData.CH_D_B_TxDqs[Channel][DimmNum][ByteLane] = val & 0xFF; EccDQSScale = pDCTstat->CH_EccDQSScale[Channel]; word = pDCTstat->CH_EccDQSLike[Channel]; if ((word & 0xFF) == ByteLane) EccRef1 = val & 0xFF; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index fd8a8e7..a2e6ad5 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -949,7 +949,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, */ for (lane = 0; lane < 8; lane++) { if (trained[lane]) { - pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; } else { printk(BIOS_WARNING, "TrainRcvrEn: WARNING: Lane %d of receiver %d on channel %d failed training!\n", lane, Receiver, Channel); @@ -1029,7 +1029,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); - p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); @@ -1433,7 +1433,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, #if DQS_TRAIN_DEBUG > 1 for (lane = 0; lane < 8; lane++) printk(BIOS_DEBUG, "\t\tTrainRcvEn55: Channel: %d dimm: %d nibble: %d lane %d current_total_delay: %04x CH_D_B_RCVRDLY: %04x\n", - Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane]); + Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane]); #endif write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); @@ -1460,9 +1460,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, for (lane = 0; lane < lane_count; lane++) { current_total_delay[lane] = (rank0_current_total_delay[lane] + current_total_delay[lane]) / 2; if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); } @@ -1470,9 +1470,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Save the current delay for later use by other routines */ for (lane = 0; lane < lane_count; lane++) { if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } } } @@ -1531,7 +1531,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); - p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); @@ -1805,7 +1805,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } @@ -2007,7 +2007,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) dev = pDCTstat->dev_dct; index_reg = 0x98; index = 0x12; - p = pDCTstat->CH_D_BC_RCVRDLY[Channel]; + p = pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel]; print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { val = p[ChipSel>>1]; @@ -2033,7 +2033,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { u16 *p; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][ChipSel>>1]; if (pDCTstat->Status & (1 << SB_Registered)) { val0 = p[0x2]; @@ -2067,7 +2067,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, } } - pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; } } SetEccDQSRcvrEn_D(pDCTstat, Channel); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c index 2592eed..f5539fc 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c @@ -68,7 +68,7 @@ static u16 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel u16 val; MaxValue = 0; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c index 7f67824..8eeb93f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c @@ -54,7 +54,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 max = 0; u8 val; u8 i; - u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + u8 *p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; u8 bn; bn = 8; @@ -85,12 +85,12 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; if (Pass == SecondPass) { /* second pass must average values */ /* FIXME: which byte? */ p_1 = pDCTstat->B_RCVRDLY_1; - /* p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ + /* p_1 = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 039a747..dc42456 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -293,7 +293,7 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, for (d = 0; d < 4; d++) { for (Byte = 0; Byte < bn; Byte++) { u8 tmp; - tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; + tmp = pDCTstat->persistentData.CH_D_B_RCVRDLY[ch][d][Byte]; if (tmp > Max) { Max = tmp; Channel_Max = Channel;

1 0

New patch to review for coreboot: mb/lenovo/t400: Increase MAX_CPUS to 4
by Arthur Heymans 08 Jan '17

08 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18059 -gerrit commit ab2003f34c737ac787c73d8b23acd5d56ffae934 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Jan 8 21:55:13 2017 +0100 mb/lenovo/t400: Increase MAX_CPUS to 4 The Lenovo T400 has a CPU socket that can fit quad cores. Change-Id: I585775ac9510cc7d2c2d731531f536c1a56b81e8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/lenovo/t400/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 47e7688..2078a27 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -46,7 +46,7 @@ config USBDEBUG_HCD_INDEX config MAX_CPUS int - default 2 + default 4 config CBFS_SIZE hex

1 0

Patch set updated for coreboot: amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc
by Timothy Pearson 08 Jan '17

08 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18058 -gerrit commit c7f37579a23bd1464da11b117f4451ee0098ae50 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Sun Jan 8 14:00:48 2017 -0600 amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc Several members of DCTStatStruc are designed to persist across resets of all other members. Move the persistent members into a substructure in order to simplify the reset logic and avoid compiler warnings / UB. Change-Id: I1139b7b3b167d33d99619338d42fcd26e2581a5d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 31 ++--------- src/northbridge/amd/amdmct/mct/mct_d.h | 57 +++++++++++--------- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 6 +-- src/northbridge/amd/amdmct/mct/mctsrc.c | 14 ++--- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct/mctsrc2p.c | 6 +-- src/northbridge/amd/amdmct/mct/mcttmrl.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 20 ++----- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 74 ++++++++++++++------------ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 20 +++---- src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 24 ++++----- src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c | 6 +-- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 2 +- 15 files changed, 125 insertions(+), 143 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 73aa20b..9d4d4ff 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2017 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -459,7 +459,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } for (Dir = 0; Dir < 2; Dir++) {//RD/WR - p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][DIMM][Dir]; val = stream_to_int(p); /* CHA Read Data Timing High */ Set_NB32_index_wait(dev, index_reg, index+1, val); val = stream_to_int(p+4); /* CHA Write Data Timing High */ @@ -3598,37 +3598,16 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { u8 Node; - u32 i; struct DCTStatStruc *pDCTstat; - u32 start, stop; - u8 *p; - u16 host_serv1, host_serv2; /* Initialize Data structures by clearing all entries to 0 */ - p = (u8 *) pMCTstat; - for (i = 0; i < sizeof(struct MCTStatStruc); i++) { - p[i] = 0; - } + memset(pMCTstat, 0x00, sizeof(*pMCTstat)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; - host_serv1 = pDCTstat->HostBiosSrvc1; - host_serv2 = pDCTstat->HostBiosSrvc2; - - p = (u8 *) pDCTstat; - start = 0; - stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); - for (i = start; i < stop; i++) { - p[i] = 0; - } - start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); - stop = sizeof(struct DCTStatStruc); - for (i = start; i < stop; i++) { - p[i] = 0; - } - pDCTstat->HostBiosSrvc1 = host_serv1; - pDCTstat->HostBiosSrvc2 = host_serv2; + /* Clear all entries except persistentData */ + memset(pDCTstat, 0x00, sizeof(*pDCTstat) - sizeof(pDCTstat->persistentData)); } } diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 75c4d62..d13143d 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2017 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -296,6 +296,34 @@ struct MCTStatStruc { Local DCT Status structure (a structure for each DCT) ===============================================================================*/ +struct DCTPersistentStatStruc { + u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ + /* CHA DIMM 0 Receiver Enable Delay*/ + /* CHA DIMM 1 Receiver Enable Delay*/ + /* CHA DIMM 2 Receiver Enable Delay*/ + /* CHA DIMM 3 Receiver Enable Delay*/ + + /* CHB DIMM 0 Receiver Enable Delay*/ + /* CHB DIMM 1 Receiver Enable Delay*/ + /* CHB DIMM 2 Receiver Enable Delay*/ + /* CHB DIMM 3 Receiver Enable Delay*/ + u8 CH_D_BC_RCVRDLY[2][4]; + /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ + u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ +} __attribute__((packed)); + + struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller*/ @@ -445,8 +473,6 @@ struct DCTStatStruc { /* A per Node structure*/ /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ uint64_t LogicalCPUID; /* The logical CPUID of the node*/ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ u16 DimmQRPresent; /* QuadRank DIMM present?*/ u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ @@ -462,28 +488,6 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/ /* Max Read Latency (ns) for DCT 1*/ - u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ - /* CHA DIMM 0 Receiver Enable Delay*/ - /* CHA DIMM 1 Receiver Enable Delay*/ - /* CHA DIMM 2 Receiver Enable Delay*/ - /* CHA DIMM 3 Receiver Enable Delay*/ - - /* CHB DIMM 0 Receiver Enable Delay*/ - /* CHB DIMM 1 Receiver Enable Delay*/ - /* CHB DIMM 2 Receiver Enable Delay*/ - /* CHB DIMM 3 Receiver Enable Delay*/ - u8 CH_D_BC_RCVRDLY[2][4]; - /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ - /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ /* DIMM# in DCT1*/ u8 MaxDCTs; /* Max number of DCTs in system*/ @@ -542,6 +546,9 @@ struct DCTStatStruc { /* A per Node structure*/ char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH+1]; uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED]; uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; + + /* NOTE: This must remain the last entry in this structure */ + struct DCTPersistentStatStruc persistentData; } __attribute__((packed)); /*=============================================================================== diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index ec77c49..7140007 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -351,7 +351,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", Channel); for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); - p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); @@ -583,7 +583,7 @@ void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->Status & (1 << SB_Over400MHz)) dn = ChipSel>>1; /* if odd or even logical DIMM */ - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = pDCTstat->DQSDelay; } @@ -606,7 +606,7 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel >> 1; /*if odd or even logical DIMM */ pDCTstat->DQSDelay = - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 3b7cff8..60857f4 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -476,7 +476,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", Channel); for (Receiver = 0; Receiver < 8; Receiver+=2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); @@ -567,7 +567,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } @@ -719,11 +719,11 @@ static u8 mct_SavePassRcvEnDly_D(struct DCTStatStruc *pDCTstat, /* find desired stack offset according to channel/dimm/byte */ if (Pass == SecondPass) { - // FIXME: SecondPass is never used for Barcelona p = pDCTstat->CH_D_B_RCVRDLY_1[Channel][receiver>>1]; + // FIXME: SecondPass is never used for Barcelona p = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][receiver>>1]; p = 0; // Keep the compiler happy. } else { mask_Saved &= mask_Pass; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][receiver>>1]; } for (i = 0; i < 8; i++) { /* cmp per byte lane */ @@ -903,7 +903,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) dev = pDCTstat->dev_dct; index_reg = 0x98 + Channel * 0x100; index = 0x12; - p = pDCTstat->CH_D_BC_RCVRDLY[Channel]; + p = pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel]; print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { val = p[ChipSel>>1]; @@ -929,7 +929,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { u8 *p; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][ChipSel>>1]; /* DQS Delay Value of Data Bytelane * most like ECC byte lane */ @@ -953,7 +953,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, val += val0; } - pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; } } SetEccDQSRcvrEn_D(pDCTstat, Channel); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index 31a3a5d..8ae6025 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -49,7 +49,7 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, u8 val; MaxValue = 0; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index 7454f53..ab278e9 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -57,7 +57,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 max = 0; u8 val; u8 i; - u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + u8 *p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; u8 bn; bn = 8; @@ -91,12 +91,12 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; if (Pass == SecondPass) { /* second pass must average values */ //FIXME: which byte? p_1 = pDCTstat->B_RCVRDLY_1; -// p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; +// p_1 = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 67397fc..4c6d8e6 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -297,7 +297,7 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, for (d = 0; d < 4; d++) { for (Byte = 0; Byte < bn; Byte++) { u8 tmp; - tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; + tmp = pDCTstat->persistentData.CH_D_B_RCVRDLY[ch][d][Byte]; if (tmp > Max) { Max = tmp; Channel_Max = Channel; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index d1d6e8f..eb794bd 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Raptor Engineering, LLC + * Copyright (C) 2015-2017 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -3732,7 +3732,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, 2); /* Pass Second Pass ? */ /* Restore Write levelization training data */ for (ByteLane = 0; ByteLane < 9; ByteLane ++) { - txdqs = pDCTstat->CH_D_B_TxDqs[Channel][Receiver >> 1][ByteLane]; + txdqs = pDCTstat->persistentData.CH_D_B_TxDqs[Channel][Receiver >> 1][ByteLane]; index = Table_DQSRcvEn_Offset[ByteLane >> 1]; index += (Receiver >> 1) * 3 + 0x10 + 0x20; /* Addl_Index */ val = Get_NB32_index_wait_DCT(dev, Channel, 0x98, index); @@ -3775,7 +3775,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } for (Dir = 0; Dir < 2; Dir++) {/* RD/WR */ - p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][DIMM][Dir]; val = stream_to_int(p); /* CHA Read Data Timing High */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, index+1, val); val = stream_to_int(p+4); /* CHA Write Data Timing High */ @@ -7373,23 +7373,13 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, { uint8_t Node; struct DCTStatStruc *pDCTstat; - uint16_t host_serv1, host_serv2; - uint8_t CH_D_B_TxDqs_bkp[2][4][9]; /* Initialize Data structures by clearing all entries to 0 */ - memset(pMCTstat, 0, sizeof(struct MCTStatStruc)); + memset(pMCTstat, 0, sizeof(*pMCTstat)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; - host_serv1 = pDCTstat->HostBiosSrvc1; - host_serv2 = pDCTstat->HostBiosSrvc2; - memcpy(CH_D_B_TxDqs_bkp, pDCTstat->CH_D_B_TxDqs, sizeof(CH_D_B_TxDqs_bkp)); - - memset(pDCTstat, 0, sizeof(struct DCTStatStruc)); - - pDCTstat->HostBiosSrvc1 = host_serv1; - pDCTstat->HostBiosSrvc2 = host_serv2; - memcpy(pDCTstat->CH_D_B_TxDqs, CH_D_B_TxDqs_bkp, sizeof(pDCTstat->CH_D_B_TxDqs)); + memset(pDCTstat, 0, sizeof(*pDCTstat) - sizeof(pDCTstat->persistentData)); } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 575a9d6..4992034 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Raptor Engineering, LLC + * Copyright (C) 2015-2017 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -335,6 +335,42 @@ struct amd_spd_node_data { uint8_t nvram_memclk[2]; /* [channel] */ } __attribute__((packed, aligned(4))); +struct DCTPersistentStatStruc { + u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 TxDqs */ + /* CHA DIMM0 Byte 0 - 7 TxDqs */ + /* CHA DIMM1 Byte 0 - 7 TxDqs */ + /* CHA DIMM1 Byte 0 - 7 TxDqs */ + /* CHB DIMM0 Byte 0 - 7 TxDqs */ + /* CHB DIMM0 Byte 0 - 7 TxDqs */ + /* CHB DIMM1 Byte 0 - 7 TxDqs */ + /* CHB DIMM1 Byte 0 - 7 TxDqs */ + u16 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ + /* CHA DIMM 0 Receiver Enable Delay*/ + /* CHA DIMM 1 Receiver Enable Delay*/ + /* CHA DIMM 2 Receiver Enable Delay*/ + /* CHA DIMM 3 Receiver Enable Delay*/ + + /* CHB DIMM 0 Receiver Enable Delay*/ + /* CHB DIMM 1 Receiver Enable Delay*/ + /* CHB DIMM 2 Receiver Enable Delay*/ + /* CHB DIMM 3 Receiver Enable Delay*/ + u16 CH_D_BC_RCVRDLY[2][4]; + /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ + u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ +} __attribute__((packed, aligned(4))); + struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller */ @@ -485,8 +521,6 @@ struct DCTStatStruc { /* A per Node structure*/ /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ uint64_t LogicalCPUID; /* The logical CPUID of the node*/ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ u16 DimmQRPresent; /* QuadRank DIMM present?*/ u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ @@ -504,37 +538,6 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CH_MaxRdLat[2][2]; /* Max Read Latency (nclks) [dct][pstate] */ /* Max Read Latency (ns) for DCT 1*/ - u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ - u16 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ - /* CHA DIMM 0 Receiver Enable Delay*/ - /* CHA DIMM 1 Receiver Enable Delay*/ - /* CHA DIMM 2 Receiver Enable Delay*/ - /* CHA DIMM 3 Receiver Enable Delay*/ - - /* CHB DIMM 0 Receiver Enable Delay*/ - /* CHB DIMM 1 Receiver Enable Delay*/ - /* CHB DIMM 2 Receiver Enable Delay*/ - /* CHB DIMM 3 Receiver Enable Delay*/ - u16 CH_D_BC_RCVRDLY[2][4]; - /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ - /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ /* DIMM# in DCT1*/ u16 CSPresent_DCT[2]; /* DCT# CS mapping */ @@ -635,6 +638,9 @@ struct DCTStatStruc { /* A per Node structure*/ uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; struct amd_spd_node_data spd_data; + + /* NOTE: This must remain the last entry in this structure */ + struct DCTPersistentStatStruc persistentData; } __attribute__((packed, aligned(4))); struct amd_s3_persistent_mct_channel_data { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 69b0104..33c3011 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -738,7 +738,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); /* Save the final Read DQS Timing Control settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; } else { print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 122 Unable to find read passing region for lane ", lane, 2); @@ -781,7 +781,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); /* Save the final Write Data Timing settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; } else { print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 123 Unable to find write passing region for lane ", lane, 2); @@ -814,7 +814,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1467,7 +1467,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); /* Save the final Read DQS Timing Control settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 142 largest read passing region ", best_count, 4); print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest read passing region start ", best_pos, 4); @@ -1520,7 +1520,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg); /* Save the final Write Data Timing settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4); print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 146 largest write passing region start ", best_pos, 4); @@ -1585,7 +1585,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1845,7 +1845,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1922,7 +1922,7 @@ static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel>>1; /* if odd or even logical DIMM */ - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = pDCTstat->DQSDelay; } @@ -1942,7 +1942,7 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel >> 1; /*if odd or even logical DIMM */ pDCTstat->DQSDelay = - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; } /* FindDQSDatDimmVal_D is not required since we use an array */ @@ -2301,7 +2301,7 @@ static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat, val = Get_NB32_index_wait_DCT(dev, pDCTstat->Channel, index_reg, index); if (ByteLane < 8) { if (pDCTstat->Direction == DQS_WRITEDIR) { - dqs_delay += pDCTstat->CH_D_B_TxDqs[pDCTstat->Channel][ChipSel>>1][ByteLane]; + dqs_delay += pDCTstat->persistentData.CH_D_B_TxDqs[pDCTstat->Channel][ChipSel>>1][ByteLane]; } else { dqs_delay <<= 1; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c index 4c6776d..4fe5ad3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c @@ -66,7 +66,7 @@ static void SetEccWrDQS_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pD if (OddByte) val >>= 16; /* Save WrDqs to stack for later usage */ - pDCTstat->CH_D_B_TxDqs[Channel][DimmNum][ByteLane] = val & 0xFF; + pDCTstat->persistentData.CH_D_B_TxDqs[Channel][DimmNum][ByteLane] = val & 0xFF; EccDQSScale = pDCTstat->CH_EccDQSScale[Channel]; word = pDCTstat->CH_EccDQSLike[Channel]; if ((word & 0xFF) == ByteLane) EccRef1 = val & 0xFF; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index fd8a8e7..a2e6ad5 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -949,7 +949,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, */ for (lane = 0; lane < 8; lane++) { if (trained[lane]) { - pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; } else { printk(BIOS_WARNING, "TrainRcvrEn: WARNING: Lane %d of receiver %d on channel %d failed training!\n", lane, Receiver, Channel); @@ -1029,7 +1029,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); - p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); @@ -1433,7 +1433,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, #if DQS_TRAIN_DEBUG > 1 for (lane = 0; lane < 8; lane++) printk(BIOS_DEBUG, "\t\tTrainRcvEn55: Channel: %d dimm: %d nibble: %d lane %d current_total_delay: %04x CH_D_B_RCVRDLY: %04x\n", - Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane]); + Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane]); #endif write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); @@ -1460,9 +1460,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, for (lane = 0; lane < lane_count; lane++) { current_total_delay[lane] = (rank0_current_total_delay[lane] + current_total_delay[lane]) / 2; if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); } @@ -1470,9 +1470,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Save the current delay for later use by other routines */ for (lane = 0; lane < lane_count; lane++) { if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } } } @@ -1531,7 +1531,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); - p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); @@ -1805,7 +1805,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } @@ -2007,7 +2007,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) dev = pDCTstat->dev_dct; index_reg = 0x98; index = 0x12; - p = pDCTstat->CH_D_BC_RCVRDLY[Channel]; + p = pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel]; print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { val = p[ChipSel>>1]; @@ -2033,7 +2033,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { u16 *p; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][ChipSel>>1]; if (pDCTstat->Status & (1 << SB_Registered)) { val0 = p[0x2]; @@ -2067,7 +2067,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, } } - pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; } } SetEccDQSRcvrEn_D(pDCTstat, Channel); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c index 2592eed..f5539fc 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c @@ -68,7 +68,7 @@ static u16 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel u16 val; MaxValue = 0; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c index 7f67824..8eeb93f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c @@ -54,7 +54,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 max = 0; u8 val; u8 i; - u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + u8 *p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; u8 bn; bn = 8; @@ -85,12 +85,12 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; if (Pass == SecondPass) { /* second pass must average values */ /* FIXME: which byte? */ p_1 = pDCTstat->B_RCVRDLY_1; - /* p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ + /* p_1 = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 039a747..dc42456 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -293,7 +293,7 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, for (d = 0; d < 4; d++) { for (Byte = 0; Byte < bn; Byte++) { u8 tmp; - tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; + tmp = pDCTstat->persistentData.CH_D_B_RCVRDLY[ch][d][Byte]; if (tmp > Max) { Max = tmp; Channel_Max = Channel;

1 0

Patch set updated for coreboot: amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc
by Timothy Pearson 08 Jan '17

08 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18058 -gerrit commit 52738ce1eebba853fff8725c00fc3d79a1b8a50e Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Sun Jan 8 14:00:48 2017 -0600 amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc Several members of DCTStatStruc are designed to persist across resets of all other members. Move the persistent members into a substructure in order to simplify the reset logic and avoid compiler warnings / UB. Change-Id: I1139b7b3b167d33d99619338d42fcd26e2581a5d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 30 ++--------- src/northbridge/amd/amdmct/mct/mct_d.h | 57 +++++++++++--------- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 6 +-- src/northbridge/amd/amdmct/mct/mctsrc.c | 14 ++--- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct/mctsrc2p.c | 6 +-- src/northbridge/amd/amdmct/mct/mcttmrl.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 18 ++----- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 74 ++++++++++++++------------ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 20 +++---- src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 24 ++++----- src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c | 6 +-- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 2 +- 15 files changed, 124 insertions(+), 141 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 73aa20b..5d47453 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2017 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -459,7 +459,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } for (Dir = 0; Dir < 2; Dir++) {//RD/WR - p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][DIMM][Dir]; val = stream_to_int(p); /* CHA Read Data Timing High */ Set_NB32_index_wait(dev, index_reg, index+1, val); val = stream_to_int(p+4); /* CHA Write Data Timing High */ @@ -3598,37 +3598,17 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { u8 Node; - u32 i; struct DCTStatStruc *pDCTstat; - u32 start, stop; u8 *p; - u16 host_serv1, host_serv2; /* Initialize Data structures by clearing all entries to 0 */ - p = (u8 *) pMCTstat; - for (i = 0; i < sizeof(struct MCTStatStruc); i++) { - p[i] = 0; - } + memset(pMCTstat, 0x00, sizeof(*pMCTstat)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; - host_serv1 = pDCTstat->HostBiosSrvc1; - host_serv2 = pDCTstat->HostBiosSrvc2; - - p = (u8 *) pDCTstat; - start = 0; - stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); - for (i = start; i < stop; i++) { - p[i] = 0; - } - start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); - stop = sizeof(struct DCTStatStruc); - for (i = start; i < stop; i++) { - p[i] = 0; - } - pDCTstat->HostBiosSrvc1 = host_serv1; - pDCTstat->HostBiosSrvc2 = host_serv2; + /* Clear all entries except persistentData */ + memset(pDCTstat, 0x00, sizeof(*pDCTstat) - sizeof(*pDCTstat->persistentData)); } } diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 75c4d62..d13143d 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2017 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -296,6 +296,34 @@ struct MCTStatStruc { Local DCT Status structure (a structure for each DCT) ===============================================================================*/ +struct DCTPersistentStatStruc { + u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ + /* CHA DIMM 0 Receiver Enable Delay*/ + /* CHA DIMM 1 Receiver Enable Delay*/ + /* CHA DIMM 2 Receiver Enable Delay*/ + /* CHA DIMM 3 Receiver Enable Delay*/ + + /* CHB DIMM 0 Receiver Enable Delay*/ + /* CHB DIMM 1 Receiver Enable Delay*/ + /* CHB DIMM 2 Receiver Enable Delay*/ + /* CHB DIMM 3 Receiver Enable Delay*/ + u8 CH_D_BC_RCVRDLY[2][4]; + /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ + u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ +} __attribute__((packed)); + + struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller*/ @@ -445,8 +473,6 @@ struct DCTStatStruc { /* A per Node structure*/ /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ uint64_t LogicalCPUID; /* The logical CPUID of the node*/ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ u16 DimmQRPresent; /* QuadRank DIMM present?*/ u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ @@ -462,28 +488,6 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/ /* Max Read Latency (ns) for DCT 1*/ - u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ - /* CHA DIMM 0 Receiver Enable Delay*/ - /* CHA DIMM 1 Receiver Enable Delay*/ - /* CHA DIMM 2 Receiver Enable Delay*/ - /* CHA DIMM 3 Receiver Enable Delay*/ - - /* CHB DIMM 0 Receiver Enable Delay*/ - /* CHB DIMM 1 Receiver Enable Delay*/ - /* CHB DIMM 2 Receiver Enable Delay*/ - /* CHB DIMM 3 Receiver Enable Delay*/ - u8 CH_D_BC_RCVRDLY[2][4]; - /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ - /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ /* DIMM# in DCT1*/ u8 MaxDCTs; /* Max number of DCTs in system*/ @@ -542,6 +546,9 @@ struct DCTStatStruc { /* A per Node structure*/ char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH+1]; uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED]; uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; + + /* NOTE: This must remain the last entry in this structure */ + struct DCTPersistentStatStruc persistentData; } __attribute__((packed)); /*=============================================================================== diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index ec77c49..7140007 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -351,7 +351,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", Channel); for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); - p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); @@ -583,7 +583,7 @@ void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->Status & (1 << SB_Over400MHz)) dn = ChipSel>>1; /* if odd or even logical DIMM */ - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = pDCTstat->DQSDelay; } @@ -606,7 +606,7 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel >> 1; /*if odd or even logical DIMM */ pDCTstat->DQSDelay = - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 3b7cff8..60857f4 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -476,7 +476,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", Channel); for (Receiver = 0; Receiver < 8; Receiver+=2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); @@ -567,7 +567,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } @@ -719,11 +719,11 @@ static u8 mct_SavePassRcvEnDly_D(struct DCTStatStruc *pDCTstat, /* find desired stack offset according to channel/dimm/byte */ if (Pass == SecondPass) { - // FIXME: SecondPass is never used for Barcelona p = pDCTstat->CH_D_B_RCVRDLY_1[Channel][receiver>>1]; + // FIXME: SecondPass is never used for Barcelona p = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][receiver>>1]; p = 0; // Keep the compiler happy. } else { mask_Saved &= mask_Pass; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][receiver>>1]; } for (i = 0; i < 8; i++) { /* cmp per byte lane */ @@ -903,7 +903,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) dev = pDCTstat->dev_dct; index_reg = 0x98 + Channel * 0x100; index = 0x12; - p = pDCTstat->CH_D_BC_RCVRDLY[Channel]; + p = pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel]; print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { val = p[ChipSel>>1]; @@ -929,7 +929,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { u8 *p; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][ChipSel>>1]; /* DQS Delay Value of Data Bytelane * most like ECC byte lane */ @@ -953,7 +953,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, val += val0; } - pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; } } SetEccDQSRcvrEn_D(pDCTstat, Channel); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index 31a3a5d..8ae6025 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -49,7 +49,7 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, u8 val; MaxValue = 0; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index 7454f53..ab278e9 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -57,7 +57,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 max = 0; u8 val; u8 i; - u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + u8 *p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; u8 bn; bn = 8; @@ -91,12 +91,12 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; if (Pass == SecondPass) { /* second pass must average values */ //FIXME: which byte? p_1 = pDCTstat->B_RCVRDLY_1; -// p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; +// p_1 = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 67397fc..4c6d8e6 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -297,7 +297,7 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, for (d = 0; d < 4; d++) { for (Byte = 0; Byte < bn; Byte++) { u8 tmp; - tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; + tmp = pDCTstat->persistentData.CH_D_B_RCVRDLY[ch][d][Byte]; if (tmp > Max) { Max = tmp; Channel_Max = Channel; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index d1d6e8f..2d02eb9 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Raptor Engineering, LLC + * Copyright (C) 2015-2017 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -3732,7 +3732,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, 2); /* Pass Second Pass ? */ /* Restore Write levelization training data */ for (ByteLane = 0; ByteLane < 9; ByteLane ++) { - txdqs = pDCTstat->CH_D_B_TxDqs[Channel][Receiver >> 1][ByteLane]; + txdqs = pDCTstat->persistentData.CH_D_B_TxDqs[Channel][Receiver >> 1][ByteLane]; index = Table_DQSRcvEn_Offset[ByteLane >> 1]; index += (Receiver >> 1) * 3 + 0x10 + 0x20; /* Addl_Index */ val = Get_NB32_index_wait_DCT(dev, Channel, 0x98, index); @@ -3775,7 +3775,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } for (Dir = 0; Dir < 2; Dir++) {/* RD/WR */ - p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][DIMM][Dir]; val = stream_to_int(p); /* CHA Read Data Timing High */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, index+1, val); val = stream_to_int(p+4); /* CHA Write Data Timing High */ @@ -7373,23 +7373,13 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, { uint8_t Node; struct DCTStatStruc *pDCTstat; - uint16_t host_serv1, host_serv2; - uint8_t CH_D_B_TxDqs_bkp[2][4][9]; /* Initialize Data structures by clearing all entries to 0 */ memset(pMCTstat, 0, sizeof(struct MCTStatStruc)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; - host_serv1 = pDCTstat->HostBiosSrvc1; - host_serv2 = pDCTstat->HostBiosSrvc2; - memcpy(CH_D_B_TxDqs_bkp, pDCTstat->CH_D_B_TxDqs, sizeof(CH_D_B_TxDqs_bkp)); - - memset(pDCTstat, 0, sizeof(struct DCTStatStruc)); - - pDCTstat->HostBiosSrvc1 = host_serv1; - pDCTstat->HostBiosSrvc2 = host_serv2; - memcpy(pDCTstat->CH_D_B_TxDqs, CH_D_B_TxDqs_bkp, sizeof(pDCTstat->CH_D_B_TxDqs)); + memset(pDCTstat, 0, sizeof(struct DCTStatStruc) - sizeof(struct DCTPersistentStatStruc)); } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 575a9d6..4992034 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Raptor Engineering, LLC + * Copyright (C) 2015-2017 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -335,6 +335,42 @@ struct amd_spd_node_data { uint8_t nvram_memclk[2]; /* [channel] */ } __attribute__((packed, aligned(4))); +struct DCTPersistentStatStruc { + u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 TxDqs */ + /* CHA DIMM0 Byte 0 - 7 TxDqs */ + /* CHA DIMM1 Byte 0 - 7 TxDqs */ + /* CHA DIMM1 Byte 0 - 7 TxDqs */ + /* CHB DIMM0 Byte 0 - 7 TxDqs */ + /* CHB DIMM0 Byte 0 - 7 TxDqs */ + /* CHB DIMM1 Byte 0 - 7 TxDqs */ + /* CHB DIMM1 Byte 0 - 7 TxDqs */ + u16 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ + /* CHA DIMM 0 Receiver Enable Delay*/ + /* CHA DIMM 1 Receiver Enable Delay*/ + /* CHA DIMM 2 Receiver Enable Delay*/ + /* CHA DIMM 3 Receiver Enable Delay*/ + + /* CHB DIMM 0 Receiver Enable Delay*/ + /* CHB DIMM 1 Receiver Enable Delay*/ + /* CHB DIMM 2 Receiver Enable Delay*/ + /* CHB DIMM 3 Receiver Enable Delay*/ + u16 CH_D_BC_RCVRDLY[2][4]; + /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ + u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ +} __attribute__((packed, aligned(4))); + struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller */ @@ -485,8 +521,6 @@ struct DCTStatStruc { /* A per Node structure*/ /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ uint64_t LogicalCPUID; /* The logical CPUID of the node*/ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ u16 DimmQRPresent; /* QuadRank DIMM present?*/ u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ @@ -504,37 +538,6 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CH_MaxRdLat[2][2]; /* Max Read Latency (nclks) [dct][pstate] */ /* Max Read Latency (ns) for DCT 1*/ - u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ - u16 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ - /* CHA DIMM 0 Receiver Enable Delay*/ - /* CHA DIMM 1 Receiver Enable Delay*/ - /* CHA DIMM 2 Receiver Enable Delay*/ - /* CHA DIMM 3 Receiver Enable Delay*/ - - /* CHB DIMM 0 Receiver Enable Delay*/ - /* CHB DIMM 1 Receiver Enable Delay*/ - /* CHB DIMM 2 Receiver Enable Delay*/ - /* CHB DIMM 3 Receiver Enable Delay*/ - u16 CH_D_BC_RCVRDLY[2][4]; - /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ - /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ /* DIMM# in DCT1*/ u16 CSPresent_DCT[2]; /* DCT# CS mapping */ @@ -635,6 +638,9 @@ struct DCTStatStruc { /* A per Node structure*/ uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; struct amd_spd_node_data spd_data; + + /* NOTE: This must remain the last entry in this structure */ + struct DCTPersistentStatStruc persistentData; } __attribute__((packed, aligned(4))); struct amd_s3_persistent_mct_channel_data { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 69b0104..33c3011 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -738,7 +738,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); /* Save the final Read DQS Timing Control settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; } else { print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 122 Unable to find read passing region for lane ", lane, 2); @@ -781,7 +781,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); /* Save the final Write Data Timing settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; } else { print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 123 Unable to find write passing region for lane ", lane, 2); @@ -814,7 +814,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1467,7 +1467,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); /* Save the final Read DQS Timing Control settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 142 largest read passing region ", best_count, 4); print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest read passing region start ", best_pos, 4); @@ -1520,7 +1520,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg); /* Save the final Write Data Timing settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4); print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 146 largest write passing region start ", best_pos, 4); @@ -1585,7 +1585,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1845,7 +1845,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1922,7 +1922,7 @@ static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel>>1; /* if odd or even logical DIMM */ - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = pDCTstat->DQSDelay; } @@ -1942,7 +1942,7 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel >> 1; /*if odd or even logical DIMM */ pDCTstat->DQSDelay = - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; } /* FindDQSDatDimmVal_D is not required since we use an array */ @@ -2301,7 +2301,7 @@ static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat, val = Get_NB32_index_wait_DCT(dev, pDCTstat->Channel, index_reg, index); if (ByteLane < 8) { if (pDCTstat->Direction == DQS_WRITEDIR) { - dqs_delay += pDCTstat->CH_D_B_TxDqs[pDCTstat->Channel][ChipSel>>1][ByteLane]; + dqs_delay += pDCTstat->persistentData.CH_D_B_TxDqs[pDCTstat->Channel][ChipSel>>1][ByteLane]; } else { dqs_delay <<= 1; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c index 4c6776d..4fe5ad3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c @@ -66,7 +66,7 @@ static void SetEccWrDQS_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pD if (OddByte) val >>= 16; /* Save WrDqs to stack for later usage */ - pDCTstat->CH_D_B_TxDqs[Channel][DimmNum][ByteLane] = val & 0xFF; + pDCTstat->persistentData.CH_D_B_TxDqs[Channel][DimmNum][ByteLane] = val & 0xFF; EccDQSScale = pDCTstat->CH_EccDQSScale[Channel]; word = pDCTstat->CH_EccDQSLike[Channel]; if ((word & 0xFF) == ByteLane) EccRef1 = val & 0xFF; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index fd8a8e7..a2e6ad5 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -949,7 +949,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, */ for (lane = 0; lane < 8; lane++) { if (trained[lane]) { - pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; } else { printk(BIOS_WARNING, "TrainRcvrEn: WARNING: Lane %d of receiver %d on channel %d failed training!\n", lane, Receiver, Channel); @@ -1029,7 +1029,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); - p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); @@ -1433,7 +1433,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, #if DQS_TRAIN_DEBUG > 1 for (lane = 0; lane < 8; lane++) printk(BIOS_DEBUG, "\t\tTrainRcvEn55: Channel: %d dimm: %d nibble: %d lane %d current_total_delay: %04x CH_D_B_RCVRDLY: %04x\n", - Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane]); + Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane]); #endif write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); @@ -1460,9 +1460,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, for (lane = 0; lane < lane_count; lane++) { current_total_delay[lane] = (rank0_current_total_delay[lane] + current_total_delay[lane]) / 2; if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); } @@ -1470,9 +1470,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Save the current delay for later use by other routines */ for (lane = 0; lane < lane_count; lane++) { if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } } } @@ -1531,7 +1531,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); - p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); @@ -1805,7 +1805,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } @@ -2007,7 +2007,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) dev = pDCTstat->dev_dct; index_reg = 0x98; index = 0x12; - p = pDCTstat->CH_D_BC_RCVRDLY[Channel]; + p = pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel]; print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { val = p[ChipSel>>1]; @@ -2033,7 +2033,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { u16 *p; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][ChipSel>>1]; if (pDCTstat->Status & (1 << SB_Registered)) { val0 = p[0x2]; @@ -2067,7 +2067,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, } } - pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; } } SetEccDQSRcvrEn_D(pDCTstat, Channel); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c index 2592eed..f5539fc 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c @@ -68,7 +68,7 @@ static u16 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel u16 val; MaxValue = 0; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c index 7f67824..8eeb93f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c @@ -54,7 +54,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 max = 0; u8 val; u8 i; - u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + u8 *p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; u8 bn; bn = 8; @@ -85,12 +85,12 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; if (Pass == SecondPass) { /* second pass must average values */ /* FIXME: which byte? */ p_1 = pDCTstat->B_RCVRDLY_1; - /* p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ + /* p_1 = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 039a747..dc42456 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -293,7 +293,7 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, for (d = 0; d < 4; d++) { for (Byte = 0; Byte < bn; Byte++) { u8 tmp; - tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; + tmp = pDCTstat->persistentData.CH_D_B_RCVRDLY[ch][d][Byte]; if (tmp > Max) { Max = tmp; Channel_Max = Channel;

1 0

New patch to review for coreboot: amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc
by Timothy Pearson 08 Jan '17

08 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18058 -gerrit commit ed9b566938fe9b4712fca21f9b8907f5777b96ea Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Sun Jan 8 14:00:48 2017 -0600 amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc Several members of DCTStatStruc are designed to persist across resets of all other members. Move the persistent members into a substructure in order to simplify the reset logic and avoid compiler warnings / UB. Change-Id: I1139b7b3b167d33d99619338d42fcd26e2581a5d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 30 +++-------- src/northbridge/amd/amdmct/mct/mct_d.h | 57 +++++++++++--------- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 6 +-- src/northbridge/amd/amdmct/mct/mctsrc.c | 14 ++--- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct/mctsrc2p.c | 6 +-- src/northbridge/amd/amdmct/mct/mcttmrl.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 18 ++----- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 74 ++++++++++++++------------ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 20 +++---- src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 24 ++++----- src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c | 6 +-- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 2 +- 15 files changed, 125 insertions(+), 140 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 73aa20b..4c09784 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2017 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -459,7 +459,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } for (Dir = 0; Dir < 2; Dir++) {//RD/WR - p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][DIMM][Dir]; val = stream_to_int(p); /* CHA Read Data Timing High */ Set_NB32_index_wait(dev, index_reg, index+1, val); val = stream_to_int(p+4); /* CHA Write Data Timing High */ @@ -3600,35 +3600,17 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, u8 Node; u32 i; struct DCTStatStruc *pDCTstat; - u32 start, stop; + size_t start, stop; u8 *p; - u16 host_serv1, host_serv2; /* Initialize Data structures by clearing all entries to 0 */ - p = (u8 *) pMCTstat; - for (i = 0; i < sizeof(struct MCTStatStruc); i++) { - p[i] = 0; - } + memset(pMCTstat, 0x00, sizeof(*pMCTstat)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; - host_serv1 = pDCTstat->HostBiosSrvc1; - host_serv2 = pDCTstat->HostBiosSrvc2; - - p = (u8 *) pDCTstat; - start = 0; - stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); - for (i = start; i < stop; i++) { - p[i] = 0; - } - start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); - stop = sizeof(struct DCTStatStruc); - for (i = start; i < stop; i++) { - p[i] = 0; - } - pDCTstat->HostBiosSrvc1 = host_serv1; - pDCTstat->HostBiosSrvc2 = host_serv2; + /* Clear all entries except persistentData */ + memset(pDCTstat, 0x00, sizeof(*pDCTstat) - sizeof(*pDCTstat->persistentData)); } } diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 75c4d62..d13143d 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2017 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -296,6 +296,34 @@ struct MCTStatStruc { Local DCT Status structure (a structure for each DCT) ===============================================================================*/ +struct DCTPersistentStatStruc { + u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ + /* CHA DIMM 0 Receiver Enable Delay*/ + /* CHA DIMM 1 Receiver Enable Delay*/ + /* CHA DIMM 2 Receiver Enable Delay*/ + /* CHA DIMM 3 Receiver Enable Delay*/ + + /* CHB DIMM 0 Receiver Enable Delay*/ + /* CHB DIMM 1 Receiver Enable Delay*/ + /* CHB DIMM 2 Receiver Enable Delay*/ + /* CHB DIMM 3 Receiver Enable Delay*/ + u8 CH_D_BC_RCVRDLY[2][4]; + /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ + u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ +} __attribute__((packed)); + + struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller*/ @@ -445,8 +473,6 @@ struct DCTStatStruc { /* A per Node structure*/ /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ uint64_t LogicalCPUID; /* The logical CPUID of the node*/ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ u16 DimmQRPresent; /* QuadRank DIMM present?*/ u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ @@ -462,28 +488,6 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/ /* Max Read Latency (ns) for DCT 1*/ - u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ - /* CHA DIMM 0 Receiver Enable Delay*/ - /* CHA DIMM 1 Receiver Enable Delay*/ - /* CHA DIMM 2 Receiver Enable Delay*/ - /* CHA DIMM 3 Receiver Enable Delay*/ - - /* CHB DIMM 0 Receiver Enable Delay*/ - /* CHB DIMM 1 Receiver Enable Delay*/ - /* CHB DIMM 2 Receiver Enable Delay*/ - /* CHB DIMM 3 Receiver Enable Delay*/ - u8 CH_D_BC_RCVRDLY[2][4]; - /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ - /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ /* DIMM# in DCT1*/ u8 MaxDCTs; /* Max number of DCTs in system*/ @@ -542,6 +546,9 @@ struct DCTStatStruc { /* A per Node structure*/ char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH+1]; uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED]; uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; + + /* NOTE: This must remain the last entry in this structure */ + struct DCTPersistentStatStruc persistentData; } __attribute__((packed)); /*=============================================================================== diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index ec77c49..7140007 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -351,7 +351,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", Channel); for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); - p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); @@ -583,7 +583,7 @@ void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->Status & (1 << SB_Over400MHz)) dn = ChipSel>>1; /* if odd or even logical DIMM */ - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = pDCTstat->DQSDelay; } @@ -606,7 +606,7 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel >> 1; /*if odd or even logical DIMM */ pDCTstat->DQSDelay = - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 3b7cff8..60857f4 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -476,7 +476,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", Channel); for (Receiver = 0; Receiver < 8; Receiver+=2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); @@ -567,7 +567,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } @@ -719,11 +719,11 @@ static u8 mct_SavePassRcvEnDly_D(struct DCTStatStruc *pDCTstat, /* find desired stack offset according to channel/dimm/byte */ if (Pass == SecondPass) { - // FIXME: SecondPass is never used for Barcelona p = pDCTstat->CH_D_B_RCVRDLY_1[Channel][receiver>>1]; + // FIXME: SecondPass is never used for Barcelona p = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][receiver>>1]; p = 0; // Keep the compiler happy. } else { mask_Saved &= mask_Pass; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][receiver>>1]; } for (i = 0; i < 8; i++) { /* cmp per byte lane */ @@ -903,7 +903,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) dev = pDCTstat->dev_dct; index_reg = 0x98 + Channel * 0x100; index = 0x12; - p = pDCTstat->CH_D_BC_RCVRDLY[Channel]; + p = pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel]; print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { val = p[ChipSel>>1]; @@ -929,7 +929,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { u8 *p; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][ChipSel>>1]; /* DQS Delay Value of Data Bytelane * most like ECC byte lane */ @@ -953,7 +953,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, val += val0; } - pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; } } SetEccDQSRcvrEn_D(pDCTstat, Channel); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index 31a3a5d..8ae6025 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -49,7 +49,7 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, u8 val; MaxValue = 0; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index 7454f53..ab278e9 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -57,7 +57,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 max = 0; u8 val; u8 i; - u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + u8 *p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; u8 bn; bn = 8; @@ -91,12 +91,12 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; if (Pass == SecondPass) { /* second pass must average values */ //FIXME: which byte? p_1 = pDCTstat->B_RCVRDLY_1; -// p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; +// p_1 = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 67397fc..4c6d8e6 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -297,7 +297,7 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, for (d = 0; d < 4; d++) { for (Byte = 0; Byte < bn; Byte++) { u8 tmp; - tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; + tmp = pDCTstat->persistentData.CH_D_B_RCVRDLY[ch][d][Byte]; if (tmp > Max) { Max = tmp; Channel_Max = Channel; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index d1d6e8f..2d02eb9 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Raptor Engineering, LLC + * Copyright (C) 2015-2017 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -3732,7 +3732,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, 2); /* Pass Second Pass ? */ /* Restore Write levelization training data */ for (ByteLane = 0; ByteLane < 9; ByteLane ++) { - txdqs = pDCTstat->CH_D_B_TxDqs[Channel][Receiver >> 1][ByteLane]; + txdqs = pDCTstat->persistentData.CH_D_B_TxDqs[Channel][Receiver >> 1][ByteLane]; index = Table_DQSRcvEn_Offset[ByteLane >> 1]; index += (Receiver >> 1) * 3 + 0x10 + 0x20; /* Addl_Index */ val = Get_NB32_index_wait_DCT(dev, Channel, 0x98, index); @@ -3775,7 +3775,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } for (Dir = 0; Dir < 2; Dir++) {/* RD/WR */ - p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][DIMM][Dir]; val = stream_to_int(p); /* CHA Read Data Timing High */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, index+1, val); val = stream_to_int(p+4); /* CHA Write Data Timing High */ @@ -7373,23 +7373,13 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, { uint8_t Node; struct DCTStatStruc *pDCTstat; - uint16_t host_serv1, host_serv2; - uint8_t CH_D_B_TxDqs_bkp[2][4][9]; /* Initialize Data structures by clearing all entries to 0 */ memset(pMCTstat, 0, sizeof(struct MCTStatStruc)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; - host_serv1 = pDCTstat->HostBiosSrvc1; - host_serv2 = pDCTstat->HostBiosSrvc2; - memcpy(CH_D_B_TxDqs_bkp, pDCTstat->CH_D_B_TxDqs, sizeof(CH_D_B_TxDqs_bkp)); - - memset(pDCTstat, 0, sizeof(struct DCTStatStruc)); - - pDCTstat->HostBiosSrvc1 = host_serv1; - pDCTstat->HostBiosSrvc2 = host_serv2; - memcpy(pDCTstat->CH_D_B_TxDqs, CH_D_B_TxDqs_bkp, sizeof(pDCTstat->CH_D_B_TxDqs)); + memset(pDCTstat, 0, sizeof(struct DCTStatStruc) - sizeof(struct DCTPersistentStatStruc)); } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 575a9d6..4992034 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Raptor Engineering, LLC + * Copyright (C) 2015-2017 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -335,6 +335,42 @@ struct amd_spd_node_data { uint8_t nvram_memclk[2]; /* [channel] */ } __attribute__((packed, aligned(4))); +struct DCTPersistentStatStruc { + u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ + /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ + u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 TxDqs */ + /* CHA DIMM0 Byte 0 - 7 TxDqs */ + /* CHA DIMM1 Byte 0 - 7 TxDqs */ + /* CHA DIMM1 Byte 0 - 7 TxDqs */ + /* CHB DIMM0 Byte 0 - 7 TxDqs */ + /* CHB DIMM0 Byte 0 - 7 TxDqs */ + /* CHB DIMM1 Byte 0 - 7 TxDqs */ + /* CHB DIMM1 Byte 0 - 7 TxDqs */ + u16 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ + /* CHA DIMM 0 Receiver Enable Delay*/ + /* CHA DIMM 1 Receiver Enable Delay*/ + /* CHA DIMM 2 Receiver Enable Delay*/ + /* CHA DIMM 3 Receiver Enable Delay*/ + + /* CHB DIMM 0 Receiver Enable Delay*/ + /* CHB DIMM 1 Receiver Enable Delay*/ + /* CHB DIMM 2 Receiver Enable Delay*/ + /* CHB DIMM 3 Receiver Enable Delay*/ + u16 CH_D_BC_RCVRDLY[2][4]; + /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ + u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ +} __attribute__((packed, aligned(4))); + struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller */ @@ -485,8 +521,6 @@ struct DCTStatStruc { /* A per Node structure*/ /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ uint64_t LogicalCPUID; /* The logical CPUID of the node*/ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ u16 DimmQRPresent; /* QuadRank DIMM present?*/ u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ @@ -504,37 +538,6 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CH_MaxRdLat[2][2]; /* Max Read Latency (nclks) [dct][pstate] */ /* Max Read Latency (ns) for DCT 1*/ - u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ - u16 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ - /* CHA DIMM 0 Receiver Enable Delay*/ - /* CHA DIMM 1 Receiver Enable Delay*/ - /* CHA DIMM 2 Receiver Enable Delay*/ - /* CHA DIMM 3 Receiver Enable Delay*/ - - /* CHB DIMM 0 Receiver Enable Delay*/ - /* CHB DIMM 1 Receiver Enable Delay*/ - /* CHB DIMM 2 Receiver Enable Delay*/ - /* CHB DIMM 3 Receiver Enable Delay*/ - u16 CH_D_BC_RCVRDLY[2][4]; - /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ - /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ /* DIMM# in DCT1*/ u16 CSPresent_DCT[2]; /* DCT# CS mapping */ @@ -635,6 +638,9 @@ struct DCTStatStruc { /* A per Node structure*/ uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; struct amd_spd_node_data spd_data; + + /* NOTE: This must remain the last entry in this structure */ + struct DCTPersistentStatStruc persistentData; } __attribute__((packed, aligned(4))); struct amd_s3_persistent_mct_channel_data { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 69b0104..33c3011 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -738,7 +738,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); /* Save the final Read DQS Timing Control settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; } else { print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 122 Unable to find read passing region for lane ", lane, 2); @@ -781,7 +781,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); /* Save the final Write Data Timing settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; } else { print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 123 Unable to find write passing region for lane ", lane, 2); @@ -814,7 +814,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1467,7 +1467,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); /* Save the final Read DQS Timing Control settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 142 largest read passing region ", best_count, 4); print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest read passing region start ", best_pos, 4); @@ -1520,7 +1520,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg); /* Save the final Write Data Timing settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4); print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 146 largest write passing region start ", best_pos, 4); @@ -1585,7 +1585,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1845,7 +1845,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; + p = pDCTstat->persistentData.CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); @@ -1922,7 +1922,7 @@ static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel>>1; /* if odd or even logical DIMM */ - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = pDCTstat->DQSDelay; } @@ -1942,7 +1942,7 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, dn = ChipSel >> 1; /*if odd or even logical DIMM */ pDCTstat->DQSDelay = - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; + pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; } /* FindDQSDatDimmVal_D is not required since we use an array */ @@ -2301,7 +2301,7 @@ static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat, val = Get_NB32_index_wait_DCT(dev, pDCTstat->Channel, index_reg, index); if (ByteLane < 8) { if (pDCTstat->Direction == DQS_WRITEDIR) { - dqs_delay += pDCTstat->CH_D_B_TxDqs[pDCTstat->Channel][ChipSel>>1][ByteLane]; + dqs_delay += pDCTstat->persistentData.CH_D_B_TxDqs[pDCTstat->Channel][ChipSel>>1][ByteLane]; } else { dqs_delay <<= 1; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c index 4c6776d..4fe5ad3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c @@ -66,7 +66,7 @@ static void SetEccWrDQS_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pD if (OddByte) val >>= 16; /* Save WrDqs to stack for later usage */ - pDCTstat->CH_D_B_TxDqs[Channel][DimmNum][ByteLane] = val & 0xFF; + pDCTstat->persistentData.CH_D_B_TxDqs[Channel][DimmNum][ByteLane] = val & 0xFF; EccDQSScale = pDCTstat->CH_EccDQSScale[Channel]; word = pDCTstat->CH_EccDQSLike[Channel]; if ((word & 0xFF) == ByteLane) EccRef1 = val & 0xFF; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index fd8a8e7..a2e6ad5 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -949,7 +949,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, */ for (lane = 0; lane < 8; lane++) { if (trained[lane]) { - pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; } else { printk(BIOS_WARNING, "TrainRcvrEn: WARNING: Lane %d of receiver %d on channel %d failed training!\n", lane, Receiver, Channel); @@ -1029,7 +1029,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); - p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); @@ -1433,7 +1433,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, #if DQS_TRAIN_DEBUG > 1 for (lane = 0; lane < 8; lane++) printk(BIOS_DEBUG, "\t\tTrainRcvEn55: Channel: %d dimm: %d nibble: %d lane %d current_total_delay: %04x CH_D_B_RCVRDLY: %04x\n", - Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane]); + Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane]); #endif write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); @@ -1460,9 +1460,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, for (lane = 0; lane < lane_count; lane++) { current_total_delay[lane] = (rank0_current_total_delay[lane] + current_total_delay[lane]) / 2; if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); } @@ -1470,9 +1470,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Save the current delay for later use by other routines */ for (lane = 0; lane < lane_count; lane++) { if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; + pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } } } @@ -1531,7 +1531,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); - p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); @@ -1805,7 +1805,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } @@ -2007,7 +2007,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) dev = pDCTstat->dev_dct; index_reg = 0x98; index = 0x12; - p = pDCTstat->CH_D_BC_RCVRDLY[Channel]; + p = pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel]; print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { val = p[ChipSel>>1]; @@ -2033,7 +2033,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { u16 *p; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][ChipSel>>1]; if (pDCTstat->Status & (1 << SB_Registered)) { val0 = p[0x2]; @@ -2067,7 +2067,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, } } - pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; + pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; } } SetEccDQSRcvrEn_D(pDCTstat, Channel); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c index 2592eed..f5539fc 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c @@ -68,7 +68,7 @@ static u16 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel u16 val; MaxValue = 0; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c index 7f67824..8eeb93f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c @@ -54,7 +54,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 max = 0; u8 val; u8 i; - u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + u8 *p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; u8 bn; bn = 8; @@ -85,12 +85,12 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; + p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; if (Pass == SecondPass) { /* second pass must average values */ /* FIXME: which byte? */ p_1 = pDCTstat->B_RCVRDLY_1; - /* p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ + /* p_1 = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 039a747..dc42456 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -293,7 +293,7 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, for (d = 0; d < 4; d++) { for (Byte = 0; Byte < bn; Byte++) { u8 tmp; - tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; + tmp = pDCTstat->persistentData.CH_D_B_RCVRDLY[ch][d][Byte]; if (tmp > Max) { Max = tmp; Channel_Max = Channel;

1 0

New patch to review for coreboot: Add Concoe-L to model_6fx cpu_device_id list
by Arthur Heymans 08 Jan '17

08 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18057 -gerrit commit 45b058968a264f68cef8c3d0fcd312b71e47a0ab Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Jan 8 21:14:46 2017 +0100 Add Concoe-L to model_6fx cpu_device_id list Tested with Intel® Celeron® Processor 420. Change-Id: I63d308477a22a9e55ceed1b6b36e63a3044c2354 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/cpu/intel/model_6fx/model_6fx_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 91d8d01..d29895b 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -177,6 +177,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x06fa }, /* Intel Core 2 Solo/Core Duo */ { X86_VENDOR_INTEL, 0x06fb }, /* Intel Core 2 Solo/Core Duo */ { X86_VENDOR_INTEL, 0x06fd }, /* Intel Core 2 Solo/Core Duo */ + { X86_VENDOR_INTEL, 0x10661 }, /* Intel Core 2 Celeron Conroe-L */ { X86_VENDOR_INTEL, 0x10676 }, /* Core2 Duo E8200 */ { 0, 0 }, };

1 0

Patch set updated for coreboot: src/cpu/intel/speedstep/acpi.c: Add "FIXME" comment
by HAOUAS Elyes 08 Jan '17

08 Jan '17

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18056 -gerrit commit 3e945a7b2e44985a34ac12f614d8a69fe2214eaa Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Jan 8 11:17:17 2017 +0100 src/cpu/intel/speedstep/acpi.c: Add "FIXME" comment MSR(0x2c) provides information about FSB frequency for Pentium 4. Change-Id: I2ba6c446f77184e6dbabd4194a3dd2fdd665b056 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/cpu/intel/speedstep/acpi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index d85e487..b1125b8 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -49,6 +49,11 @@ static int determine_total_number_of_cores(void) */ static int get_fsb(void) { + + /* FIXME: we probably need to detect the CPU and + * read the right MSR register to have the right FSB. + * Example: for Pentium 4 we should read MSR at 0x2c + */ const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7; switch (fsbcode) { case 0: return 800; /* / 3 == 266 */

1 0

Patch set updated for coreboot: util/autoport: Fix gfx dump of log_maker
by Swift Geek 08 Jan '17

08 Jan '17

Swift Geek (swiftgeek(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18050 -gerrit commit 482a7cde7bf22e5b678be107240bf2375f59ce2a Author: Sebastian 'Swift Geek' Grzywna <swiftgeek(a)gmail.com> Date: Sun Jan 8 03:42:30 2017 +0100 util/autoport: Fix gfx dump of log_maker Variable name of inteltoolArgs was fixed. The way of passing arguments to inteltool was changed from "-a -f" to "-af" which is better as the string seems to be parsed as a single argument. Change-Id: I0c48fb1e912261748ba9e2b91c291bac28b9e856 Signed-off-by: Sebastian 'Swift Geek' Grzywna <swiftgeek(a)gmail.com> --- util/autoport/log_maker.go | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/autoport/log_maker.go b/util/autoport/log_maker.go index 50e0e65..7c8240e 100644 --- a/util/autoport/log_maker.go +++ b/util/autoport/log_maker.go @@ -89,7 +89,7 @@ func MakeLogs(outDir string) { switch opt { case "y", "yes": - opt += " -f" + inteltoolArgs += "f" } RunAndSave(outDir+"/inteltool.log", "../inteltool/inteltool", inteltoolArgs)

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Patch set updated for coreboot: util/ifdtool: Fix ICH Gbe unlock
by Patrick Rudolph 08 Jan '17

08 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18055 -gerrit commit 950a72f0b5d40d5d167e59b702693b8c6b3ba013 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jan 8 09:57:47 2017 +0100 util/ifdtool: Fix ICH Gbe unlock With coreboot 4.4 switched to "Descriptor mode" for Lenovo T500 it automatically unlocks all flash regions. For Gbe region the "Requester ID" was hardcoded resulting in *dead* Gbe. Unlock the Gbe region and keep board specific "Requester ID". Allows Lenovo T500 to boot in "Descriptor mode" with unlocked flash regions. Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Change-Id: Ia4b5d1928e84bee42182fc83020e3a13fadc93c4 --- util/ifdtool/ifdtool.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 45dd97c..0c49e40 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -876,7 +876,8 @@ static void unlock_descriptor(char *filename, char *image, int size) } else { fmba->flmstr1 = 0xffff0000; fmba->flmstr2 = 0xffff0000; - fmba->flmstr3 = 0x08080118; + /* Keep board specific Requester ID */ + fmba->flmstr3 = 0x08080000 | (fmba->flmstr3 & 0xffff); } write_image(filename, image, size);

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coreboot-gerrit January 2017