coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: mainboard/google/poppy: Generate required nhlt table
by Rizwan Qureshi 24 Jan '17

24 Jan '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18214 -gerrit commit 0b74cd25de5cb6d67e34794f5b5cdfed6647195a Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 22:30:01 2017 +0530 mainboard/google/poppy: Generate required nhlt table Select the required NHLT blobs to be packaged in CBFS. Also, generate the required ACPI NHLT table for the current codec and topology supported in poppy. BUG=None BRANCH=None TEST=With the required driver support in kernel verify that the Audio plays on on-board speakers and headset, recording works from on-boards mics and headset mics. Change-Id: I98c65038b35fe99a661807de0766e6eac2c80eed Signed-off-by: M Naveen <naveen.m(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/google/poppy/Kconfig | 6 ++++ src/mainboard/google/poppy/mainboard.c | 55 ++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 742eb64..e889e01 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -41,4 +41,10 @@ config MAX_CPUS int default 8 +config INCLUDE_NHLT_BLOBS + bool "Include blobs for audio." + select NHLT_DMIC_2CH + select NHLT_DMIC_4CH + select NHLT_RT5663 + select NHLT_MAX98927 endif diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index 29559b3..f71ba9e 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -14,19 +14,74 @@ */ #include <arch/acpi.h> +#include <console/console.h> #include <device/device.h> #include <ec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <soc/nhlt.h> + +static const char *oem_id_maxim = "GOOGLE"; +static const char *oem_table_id_maxim = "POPPYMAX"; static void mainboard_init(device_t dev) { mainboard_ec_init(); } + +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + const char *oem_id = NULL; + const char *oem_table_id = NULL; + uint32_t oem_revision = 0; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + + /* 4 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); + /*ToDo as im getting error, i'm reverting to old codecs*/ + /* MAXIM98927 Smart Amps for left and right channel */ + if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0)){ + + printk(BIOS_ERR, "Couldn't add max98927\n"); + oem_id = oem_id_maxim; + oem_table_id = oem_table_id_maxim; + + } + + /* RT5663 Headset codec. */ + if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, + oem_id, oem_table_id, oem_revision); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } struct chip_operations mainboard_ops = {

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New patch to review for coreboot: soc/intel/skylake: Maxim 98927 and Realtek 5663 NHLT blob support
by Rizwan Qureshi 24 Jan '17

24 Jan '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18213 -gerrit commit 87e7f2a01f6e7b306ca84caf56ef11f2e7197a34 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Sat Jan 14 06:08:21 2017 +0530 soc/intel/skylake: Maxim 98927 and Realtek 5663 NHLT blob support Add APIs and required parameters for creating Maxim 98927 and Realtek 5336 SSP endpoints in NHLT table. Change-Id: Ica302aab05c5364faf4923dc5327be8e8eaae8b4 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: M Naveen <naveen.m(a)intel.com> --- src/soc/intel/skylake/Kconfig | 13 ++++++ src/soc/intel/skylake/include/soc/nhlt.h | 12 ++++++ src/soc/intel/skylake/nhlt/Makefile.inc | 14 ++++++- src/soc/intel/skylake/nhlt/max98927.c | 47 +++++++++++++++++++++ src/soc/intel/skylake/nhlt/rt5663.c | 71 ++++++++++++++++++++++++++++++++ 5 files changed, 156 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 24c2e30..8f29b2b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC + select ACPI_NHLT config MAINBOARD_USES_FSP2_0 bool @@ -227,6 +228,18 @@ config NHLT_SSM4567 help Include DSP firmware settings for ssm4567 smart amplifier. +config NHLT_RT5663 + bool + default n + help + Include DSP firmware settings for rt5663 headset codec. + +config NHLT_MAX98927 + bool + default n + help + Include DSP firmware settings for max98927 amplifier. + config SKIP_FSP_CAR bool "Skip cache as RAM setup in FSP" default y diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index 008dd0d..7d23102 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -60,4 +60,16 @@ int nhlt_soc_add_ssm4567(struct nhlt *nhlt, int hwlink); */ int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink); +/* + * Add rt5663 headset codec on provided SSP link. Return 0 on succes, < 0 + * on error. + */ +int nhlt_soc_add_rt5663(struct nhlt *nhlt, int hwlink); + +/* + * Add max98927 amplifier in stereo configuration on provide SSP link. + * Return 0 on success, < 0 on error. + */ +int nhlt_soc_add_max98927(struct nhlt *nhlt, int hwlink); + #endif diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index e022482..da71162 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -2,9 +2,11 @@ ramstage-y += dmic.c ramstage-y += nau88l25.c ramstage-y += max98357.c ramstage-y += ssm4567.c +ramstage-y += rt5663.c +ramstage-y += max98927.c # DSP firmware settings files. -NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/skylake +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/kabylake/nhlt-blobs DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin DMIC_2CH_48KHZ_32B = dmic-2ch-48khz-32b.bin DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin @@ -13,6 +15,8 @@ NAU88L25 = nau88l25-2ch-48khz-24b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin SSM4567_RENDER = ssm4567-render-2ch-48khz-24b.bin SSM4567_CAPTURE = ssm4567-capture-4ch-48khz-32b.bin +RT5663 = rt5663-2ch-48khz-24b.bin +MAX98927_RENDER = max98927-render-2ch-48khz-24b.bin cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) @@ -45,3 +49,11 @@ $(SSM4567_RENDER)-type := raw cbfs-files-$(CONFIG_NHLT_SSM4567) += $(SSM4567_CAPTURE) $(SSM4567_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(SSM4567_CAPTURE) $(SSM4567_CAPTURE)-type := raw + +cbfs-files-$(CONFIG_NHLT_RT5663) += $(RT5663) +$(RT5663)-file := $(NHLT_BLOB_PATH)/$(RT5663) +$(RT5663)-type := raw + +cbfs-files-$(CONFIG_NHLT_MAX98927) += $(MAX98927_RENDER) +$(MAX98927_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98927_RENDER) +$(MAX98927_RENDER)-type := raw diff --git a/src/soc/intel/skylake/nhlt/max98927.c b/src/soc/intel/skylake/nhlt/max98927.c new file mode 100644 index 0000000..7f18657 --- /dev/null +++ b/src/soc/intel/skylake/nhlt/max98927.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation.. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/nhlt.h> + +static const struct nhlt_format_config max98927_render_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, + .settings_file = "max98927-render-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_endp_descriptor max98927_descriptors[] = { + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = max98927_render_formats, + .num_formats = ARRAY_SIZE(max98927_render_formats), + }, +}; + +int nhlt_soc_add_max98927(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, max98927_descriptors, + ARRAY_SIZE(max98927_descriptors)); +} diff --git a/src/soc/intel/skylake/nhlt/rt5663.c b/src/soc/intel/skylake/nhlt/rt5663.c new file mode 100644 index 0000000..603d1dd --- /dev/null +++ b/src/soc/intel/skylake/nhlt/rt5663.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/nhlt.h> + +/* The same DSP firmware settings are used for both the capture and + * render endpoints. */ +static const struct nhlt_format_config rt5663_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, + .settings_file = "rt5663-2ch-48khz-24b.bin", + }, +}; + +/* The rt5663 just has headphones and a mic. Both the capture and render + * endpoints occupy the same virtual slot. */ +static const struct nhlt_tdm_config tdm_config = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_endp_descriptor rt5663_descriptors[] = { + /* Render Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = rt5663_formats, + .num_formats = ARRAY_SIZE(rt5663_formats), + }, + /* Capture Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = rt5663_formats, + .num_formats = ARRAY_SIZE(rt5663_formats), + }, +}; + +int nhlt_soc_add_rt5663(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5663_descriptors, + ARRAY_SIZE(rt5663_descriptors)); +}

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New patch to review for coreboot: drivers/i2c/rt5663: SSDT generator for Realtek 5663 codec
by Rizwan Qureshi 24 Jan '17

24 Jan '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18212 -gerrit commit f1763074d7c596143bc5008c9ad7b6dc2b2b22ee Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Sat Jan 14 16:25:00 2017 +0530 drivers/i2c/rt5663: SSDT generator for Realtek 5663 codec Add a SSDT generator for Realtek 5663 audio codec. Change-Id: Ic5c37b30cd2595579a0e914b67e1d6a646f0b130 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: M Naveen <naveen.m(a)intel.com> --- src/drivers/i2c/rt5663/Kconfig | 2 + src/drivers/i2c/rt5663/Makefile.inc | 1 + src/drivers/i2c/rt5663/chip.h | 96 +++++++++++++++++++++++++++++++++ src/drivers/i2c/rt5663/rt5663.c | 104 ++++++++++++++++++++++++++++++++++++ 4 files changed, 203 insertions(+) diff --git a/src/drivers/i2c/rt5663/Kconfig b/src/drivers/i2c/rt5663/Kconfig new file mode 100644 index 0000000..03b25d1 --- /dev/null +++ b/src/drivers/i2c/rt5663/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_RT5663 + bool diff --git a/src/drivers/i2c/rt5663/Makefile.inc b/src/drivers/i2c/rt5663/Makefile.inc new file mode 100644 index 0000000..35c566b --- /dev/null +++ b/src/drivers/i2c/rt5663/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_RT5663) += rt5663.c diff --git a/src/drivers/i2c/rt5663/chip.h b/src/drivers/i2c/rt5663/chip.h new file mode 100644 index 0000000..f2c1cd4 --- /dev/null +++ b/src/drivers/i2c/rt5663/chip.h @@ -0,0 +1,96 @@ +#include <arch/acpi_device.h> + +#define RT5663_MAX_BUTTONS 8 + +/* + * Realtek RT5663 audio codec devicetree bindings + * linux/Documentation/devicetree/bindings/sound/rt5663.txt + */ +struct drivers_i2c_rt5663_config { + /* Interrupt configuration */ + struct acpi_irq irq; + + /* I2C Bus Frequency in Hertz (default 400kHz) */ + unsigned bus_speed; + + /* Enable jack detection via JKDET pin */ + unsigned jkdet_enable; + + /* Enable JKDET pin pull if set, otherwise high impedance state */ + unsigned jkdet_pull_enable; + + /* Pull-up JKDET pin if set, otherwise pull down */ + unsigned jkdet_pull_up; + + /* JKDET pin polarity, 0 => active high, 1 => active low */ + unsigned jkdet_polarity; + + /* + * VREF Impedance selection + * 0 - Open + * 1 - 25 kOhm + * 2 - 125 kOhm + * 3 - 2.5 kOhm + */ + unsigned vref_impedance; + + /* Button impedance measurement hysteresis */ + unsigned sar_hysteresis; + + /* + * Reference voltage for button impedance measurement and micbias + * 0 - VDDA + * 1 - VDDA + * 2 - VDDA * 1.1 + * 3 - VDDA * 1.2 + * 4 - VDDA * 1.3 + * 5 - VDDA * 1.4 + * 6 - VDDA * 1.53 + * 7 - VDDA * 1.53 + */ + unsigned micbias_voltage; + unsigned sar_voltage; + + /* + * SAR compare time + * 0 - 500 ns + * 1 - 1 us + * 2 - 2 us + * 3 - 4 us + */ + unsigned sar_compare_time; + + /* + * SAR sampling time + * 0 - 2 us + * 1 - 4 us + * 2 - 8 us + * 3 - 16 us + */ + unsigned sar_sampling_time; + + /* + * Button short key press debounce time + * 0 - 30 ms + * 1 - 50 ms + * 2 - 100 ms + * 3 - 30 ms + */ + unsigned short_key_debounce; + + /* Debounce time 2^(n+2) ms (0-7) for jack insert */ + unsigned jack_insert_debounce; + + /* Debounce time 2^(n+2) ms (0-7) for jack eject */ + unsigned jack_eject_debounce; + + /* Number of buttons supported, up to 8 */ + unsigned sar_threshold_num; + + /* + * Impedance threshold for each button, up to 8 + * SAR = 255 * micbias_voltage / sar_voltage * R / (2000 + R) + * R is Button impedance + */ + uint64_t sar_threshold[RT5663_MAX_BUTTONS]; +}; diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c new file mode 100644 index 0000000..842d572 --- /dev/null +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +#define RT5663_ACPI_NAME "RT53" +#define RT5663_ACPI_HID "10EC5663" + +#define RT5663_DP_INT(key, val) \ + acpi_dp_add_integer(dp, "realtek," key, (val)) + + +static void rt5663_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_rt5663_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dp = NULL; + + if (!dev->enabled || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", RT5663_ACPI_HID); + acpigen_write_name_integer("_UID", 1); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_name_integer("_S0W", 4); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpi_device_write_interrupt(&config->irq); + acpigen_write_resourcetemplate_footer(); + + /* Device Properties */ + dp = acpi_dp_new_table("_DSD"); + + acpi_dp_write(dp); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s address 0%xh irq %d\n", + acpi_device_path(dev), dev->chip_ops->name, + dev->path.i2c.device, config->irq.pin); +} + +static const char *rt5663_acpi_name(struct device *dev) +{ + return RT5663_ACPI_NAME; +} +#endif + +static struct device_operations rt5663_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &rt5663_acpi_name, + .acpi_fill_ssdt_generator = &rt5663_fill_ssdt, +#endif +}; + +static void rt5663_enable(struct device *dev) +{ + dev->ops = &rt5663_ops; +} + +struct chip_operations drivers_i2c_rt5663_ops = { + CHIP_NAME("Realtek RT5663 Codec") + .enable_dev = &rt5663_enable +};

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New patch to review for coreboot: driver/i2c/max98927: SSDT generator for Maxim 98927 codec
by Rizwan Qureshi 24 Jan '17

24 Jan '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18211 -gerrit commit 787266b89e72df2a51f3108ab09df210dbd57b70 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 22:17:01 2017 +0530 driver/i2c/max98927: SSDT generator for Maxim 98927 codec Add a SSDT generator for MAXIM 98927 audio codec. BUG=None BRANCH=None TEST=After boot, dump and verify that the generated SSDT ACPI table has the required entries. Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: M Naveen <naveen.m(a)intel.com> Change-Id: Ic2d4d8449288bc00d085852220b2e1e7a208e9ef Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/drivers/i2c/max98927/Kconfig | 2 + src/drivers/i2c/max98927/Makefile.inc | 1 + src/drivers/i2c/max98927/chip.h | 23 +++++++ src/drivers/i2c/max98927/max98927.c | 121 ++++++++++++++++++++++++++++++++++ 4 files changed, 147 insertions(+) diff --git a/src/drivers/i2c/max98927/Kconfig b/src/drivers/i2c/max98927/Kconfig new file mode 100644 index 0000000..1007442 --- /dev/null +++ b/src/drivers/i2c/max98927/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_MAX98927 + bool diff --git a/src/drivers/i2c/max98927/Makefile.inc b/src/drivers/i2c/max98927/Makefile.inc new file mode 100644 index 0000000..3bafee1 --- /dev/null +++ b/src/drivers/i2c/max98927/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_MAX98927) += max98927.c diff --git a/src/drivers/i2c/max98927/chip.h b/src/drivers/i2c/max98927/chip.h new file mode 100644 index 0000000..da190be --- /dev/null +++ b/src/drivers/i2c/max98927/chip.h @@ -0,0 +1,23 @@ +#include <arch/acpi_device.h> + +#define MAXIM_MAX_REG_CFG 42 + +/* + * Maxim MAX98927 audio codec devicetree bindings + */ +struct drivers_i2c_max98927_config { + /* Interrupt configuration */ + struct acpi_irq irq; + /* I2C Bus Frequency in Hertz (default 400kHz) */ + unsigned int bus_speed; + /* Set ‘1’ if I2S channel size is not 32bit. */ + unsigned int interleave_mode; + /*Primary amp – left */ + unsigned int reg; + /*<channel register value>*/ + uint64_t regcfg[MAXIM_MAX_REG_CFG]; + /*Secondary amp – right */ + unsigned int sub_reg; + /* Can skip this if both amp is using same I2C bus. */ + unsigned int sub_bus; +}; diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c new file mode 100644 index 0000000..9e27e52 --- /dev/null +++ b/src/drivers/i2c/max98927/max98927.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +#define MAX98927_ACPI_NAME "MAXI" +#define MAX98927_ACPI_HID "MX98927" + +#define MAX98927_DP_INT(key, val) \ + acpi_dp_add_integer(dp, "maxim," key, (val)) + +static void max98927_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_max98927_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_i2c i2c_right = { + .address = config->sub_reg, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dp = NULL; + + if (!dev->enabled || !scope) + return; + + /* Get regcfg from mainboard */ + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", MAX98927_ACPI_HID); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpi_device_write_i2c(&i2c_right); + acpi_device_write_interrupt(&config->irq); + acpigen_write_resourcetemplate_footer(); + + /* Device Properties */ + dp = acpi_dp_new_table("_DSD"); + + acpi_dp_add_integer(dp, "reg", config->reg); + acpi_dp_add_integer(dp, "interleave_mode", config->interleave_mode); + + MAX98927_DP_INT("sub_reg", config->sub_reg); + MAX98927_DP_INT("sub_bus", config->sub_bus); + + MAX98927_DP_INT("regcfg_sz", ARRAY_SIZE(config->regcfg)); + acpi_dp_add_integer_array(dp, "maxim,regcfg", config->regcfg, + ARRAY_SIZE(config->regcfg)); + + acpi_dp_write(dp); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s address 0%xh irq %d\n", + acpi_device_path(dev), dev->chip_ops->name, + dev->path.i2c.device, config->irq.pin); +} + +static const char *max98927_acpi_name(struct device *dev) +{ + return MAX98927_ACPI_NAME; +} +#endif + +static struct device_operations max98927_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &max98927_acpi_name, + .acpi_fill_ssdt_generator = &max98927_fill_ssdt, +#endif +}; + +static void max98927_enable(struct device *dev) +{ + dev->ops = &max98927_ops; +} + +struct chip_operations drivers_i2c_max98927_ops = { + CHIP_NAME("Maxim MAX98927 Codec") + .enable_dev = &max98927_enable +};

1 0

Patch set updated for coreboot: nb/intel/x4x: Implement resume from S3 suspend
by Arthur Heymans 23 Jan '17

23 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17998 -gerrit commit 2308a43797cbdb12b4579915b8dd40dff6b0b9bc Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Dec 30 21:07:18 2016 +0100 nb/intel/x4x: Implement resume from S3 suspend It rewrites the results of receive enable stored in the upper nvram region, to avoid running receive enable again. Some debug info is also printed about the self-refresh registers. (Not enforcing a reset here, since 0 does not necessarily mean it's not in self-refresh). Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 +++++-- src/northbridge/intel/x4x/pcie.c | 15 ++++++++++++-- src/northbridge/intel/x4x/raminit_ddr2.c | 28 ++++++++++++++++++++------ src/northbridge/intel/x4x/x4x.h | 2 +- 5 files changed, 42 insertions(+), 11 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 3d2a892..ae57e5b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS select REALTEK_8168_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index d76fbb2..0a1470b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -132,6 +132,7 @@ void mainboard_romstage_entry(unsigned long bist) // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; u8 boot_path = 0; + u8 s3_resume; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -151,16 +152,18 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); - cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); - x4x_late_init(); + x4x_late_init(s3_resume); printk(BIOS_DEBUG, "x4x late init complete\n"); diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c index f03869e..648f10d 100644 --- a/src/northbridge/intel/x4x/pcie.c +++ b/src/northbridge/intel/x4x/pcie.c @@ -18,10 +18,11 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> +#include <cbmem.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> - +#include <romstage_handoff.h> #include "iomap.h" #include "x4x.h" @@ -184,8 +185,18 @@ static void init_dmi(void) reg16 = DMIBAR16(0x88); } -void x4x_late_init(void) +static void x4x_prepare_resume(int s3resume) +{ + int cbmem_was_initted; + + cbmem_was_initted = !cbmem_recovery(s3resume); + + romstage_handoff_init(cbmem_was_initted && s3resume); +} + +void x4x_late_init(int s3resume) { init_egress(); init_dmi(); + x4x_prepare_resume(s3resume); } diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index a5e1fc9..0e52dc2 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -262,6 +262,16 @@ static void clkcross_ddr2(struct sysinfo *s) static void checkreset_ddr2(struct sysinfo *s) { u8 pmcon2; + u32 pmsts = MCHBAR32(PMSTS_MCHBAR); + + if (s->boot_path >= 1) { + if (!(pmsts & 1)) + printk(BIOS_DEBUG, + "Channel 0 possibly not in self refresh\n"); + if (!(pmsts & 2)) + printk(BIOS_DEBUG, + "Channel 1 possibly not in self refresh\n"); + } pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); @@ -1476,7 +1486,6 @@ static void rcven_ddr2(struct sysinfo *s) readdelay[ch] = MCHBAR16(0x400*ch + 0x588); } // END EACH POPULATED CHANNEL - /* TODO: Resume support using this */ FOR_EACH_CHANNEL(ch) { for (lane = 0; lane < 8; lane++) { MCHBAR8(0x400*ch + 0x560 + (lane*4)) = @@ -1556,7 +1565,8 @@ static void sdram_program_receive_enable(struct sysinfo *s) RCBA32(0x3400) = (1 << 2); /* Program Receive Enable Timings */ - if (s->boot_path == BOOT_PATH_WARM_RESET) { + if ((s->boot_path == BOOT_PATH_WARM_RESET) + || (s->boot_path == BOOT_PATH_RESUME)) { sdram_recover_receive_enable(); } else { rcven_ddr2(s); @@ -2044,7 +2054,8 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done pre-jedec\n"); // JEDEC reset - jedec_ddr2(s); + if (s->boot_path != BOOT_PATH_RESUME) + jedec_ddr2(s); printk(BIOS_DEBUG, "Done jedec steps\n"); @@ -2095,13 +2106,18 @@ void raminit_ddr2(struct sysinfo *s) volatile u32 data; FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (bank = 0; bank < 4; bank++) { - reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); + reg32 = (ch << 29) | (r*0x8000000) | + (bank << 12); write32((u32 *)reg32, 0xffffffff); data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); + printk(BIOS_DEBUG, "Wrote ones"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); write32((u32 *)reg32, 0x00000000); data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + printk(BIOS_DEBUG, "Wrote zeros"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); } } } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 66d765a..faae775 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -322,7 +322,7 @@ enum ddr2_signals { #ifndef __BOOTBLOCK__ void x4x_early_init(void); -void x4x_late_init(void); +void x4x_late_init(int s3resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len);

1 0

Patch set updated for coreboot: nb/intel/x4x: Fix raminit on reset path
by Arthur Heymans 23 Jan '17

23 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18009 -gerrit commit 7f86333c45fb8f32d49e2d883fb66d033665c85b Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Nov 30 18:40:38 2016 +0100 nb/intel/x4x: Fix raminit on reset path Previously the raminit failed on hot reset and to work around this issue it unconditionally did a cold reset. This has the following issues: * it's slow; * when the OS issues a hot reset some disk drives expect their 5V power supply to remain on, which gets cut off by a cold reset, causing data corruption. To fix this some steps in raminit must be ommited on the reset path. This includes searching for receive enable. To achieve this it stores receive enable results in nvram (which is also needed when implementing S3 suspend/resume from S3). Calling a hot reset after raminit "outb(0x6, 0cf9)" works. Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout | 1 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 +- src/northbridge/intel/x4x/raminit_ddr2.c | 165 ++++++++++++++++++------ src/northbridge/intel/x4x/x4x.h | 7 +- 4 files changed, 139 insertions(+), 41 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index 3138479..fac9d35 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -68,6 +68,7 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum +1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 0f43795..d76fbb2 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -30,6 +30,7 @@ #include <lib.h> #include <arch/stages.h> #include <cbmem.h> +#include <northbridge/intel/x4x/iomap.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) @@ -130,6 +131,7 @@ void mainboard_romstage_entry(unsigned long bist) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -149,8 +151,11 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + printk(BIOS_DEBUG, "Initializing memory\n"); - sdram_initialize(0, spd_addrmap); + sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index b3ee34a..a5e1fc9 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -20,6 +20,11 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <delay.h> +#include <pc80/mc146818rtc.h> +/* This northbridge can also occur with ICH10 */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#include <southbridge/intel/i82801gx/i82801gx.h> +#endif #include "iomap.h" #include "x4x.h" @@ -257,26 +262,25 @@ static void clkcross_ddr2(struct sysinfo *s) static void checkreset_ddr2(struct sysinfo *s) { u8 pmcon2; - u8 reset = 0; pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - if (!(pmcon2 & 0x80)) { - pmcon2 |= 0x80; + + if (pmcon2 & 0x80) { + pmcon2 &= ~0x80; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); - reset = 1; /* do magic 0xf0 thing. */ u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); - } - if (reset) { + printk(BIOS_DEBUG, "Reset...\n"); - outb(0xe, 0xcf9); + outb(0x6, 0xcf9); asm ("hlt"); } - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80); + pmcon2 |= 0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); } static void setioclk_ddr2(struct sysinfo *s) @@ -1486,6 +1490,80 @@ static void rcven_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "End rcven\n"); } +static void sdram_save_receive_enable(void) +{ + int i = 0, uneven; + u16 reg16; + u8 values[18] = { 0 }; + u8 lane, ch; + + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) { + uneven = lane % 2; + values[i] |= (MCHBAR8(0x400*ch + 0x560 + lane * 4) & 0xf) + << uneven * 4; + if (uneven) + i++; + } + values[i++] = (MCHBAR32(0x400*ch + 0x248) >> 16) & 0xf; + reg16 = MCHBAR16(0x400*ch + 0x5fa); + values[i++] = reg16 & 0xff; + values[i++] = (reg16 >> 8) & 0xff; + reg16 = MCHBAR16(0x400*ch + 0x58c); + values[i++] = reg16 & 0xff; + values[i++] = (reg16 >> 8) & 0xff; + } + + for (i = 0; i < ARRAY_SIZE(values); i++) + cmos_write(values[i], 128 + i); +} + +static void sdram_recover_receive_enable(void) +{ + u8 i, uneven; + u32 reg32 = 0; + u16 reg16 = 0; + u8 values[18]; + u8 ch, lane; + + for (i = 0; i < ARRAY_SIZE(values); i++) + values[i] = cmos_read(128 + i); + + i = 0; + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) { + uneven = lane % 2; + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = 0x70 + | ((values[i] >> (4 * uneven)) & 0xf); + if (uneven) + i++; + } + reg32 = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) + | ((values[i++] & 0xf) << 16); + MCHBAR32(0x400*ch + 0x248) = reg32; + reg16 = values[i++]; + reg16 |= values[i++] << 8; + MCHBAR16(0x400*ch + 0x5fa) = reg16; + reg16 = values[i++]; + reg16 |= values[i++] << 8; + MCHBAR16(0x400*ch + 0x58c) = reg16; + } +} + +static void sdram_program_receive_enable(struct sysinfo *s) +{ + /* enable upper CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Program Receive Enable Timings */ + if (s->boot_path == BOOT_PATH_WARM_RESET) { + sdram_recover_receive_enable(); + } else { + rcven_ddr2(s); + sdram_save_receive_enable(); + } +} + static void dradrb_ddr2(struct sysinfo *s) { u8 map, i, ch, r, rankpop0, rankpop1; @@ -1859,23 +1937,25 @@ void raminit_ddr2(struct sysinfo *s) // Reset if required checkreset_ddr2(s); - // Clear self refresh - MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x3; + if (s->boot_path != BOOT_PATH_WARM_RESET) { + // Clear self refresh + MCHBAR32(PMSTS_MCHBAR) = MCHBAR32(PMSTS_MCHBAR) + | PMSTS_BOTH_SELFREFRESH; - // Clear host clk gate reg - MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; + // Clear host clk gate reg + MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; - // Select DDR2 - MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; + // Select DDR2 + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; - // Set freq - MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | - (s->selected_timings.mem_clk << 4) | (1 << 10); + // Set freq + MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | + (s->selected_timings.mem_clk << 4) | (1 << 10); - // Overwrite freq if chipset rejects it - s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; - if (s->selected_timings.mem_clk > (s->max_fsb + 3)) { - die("Error: DDR is faster than FSB, halt\n"); + // Overwrite freq if chipset rejects it + s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; + if (s->selected_timings.mem_clk > (s->max_fsb + 3)) + die("Error: DDR is faster than FSB, halt\n"); } udelay(250000); @@ -1885,8 +1965,10 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done clk crossing\n"); // DDR2 IO - setioclk_ddr2(s); - printk(BIOS_DEBUG, "Done I/O clk\n"); + if (s->boot_path != BOOT_PATH_WARM_RESET) { + setioclk_ddr2(s); + printk(BIOS_DEBUG, "Done I/O clk\n"); + } // Grant to launch launch_ddr2(s); @@ -1900,16 +1982,21 @@ void raminit_ddr2(struct sysinfo *s) dll_ddr2(s); // RCOMP - rcomp_ddr2(s); - printk(BIOS_DEBUG, "RCOMP\n"); + if (s->boot_path != BOOT_PATH_WARM_RESET) { + rcomp_ddr2(s); + printk(BIOS_DEBUG, "RCOMP\n"); + } // ODT odt_ddr2(s); printk(BIOS_DEBUG, "Done ODT\n"); // RCOMP update - while ((MCHBAR8(0x130) & 1) != 0 ); - printk(BIOS_DEBUG, "Done RCOMP update\n"); + if (s->boot_path != BOOT_PATH_WARM_RESET) { + while ((MCHBAR8(0x130) & 1) != 0) + ; + printk(BIOS_DEBUG, "Done RCOMP update\n"); + } // Set defaults MCHBAR32(0x260) = (MCHBAR32(0x260) & ~1) | 0xf00000; @@ -1989,7 +2076,7 @@ void raminit_ddr2(struct sysinfo *s) } // Receive enable - rcven_ddr2(s); + sdram_program_receive_enable(s); printk(BIOS_DEBUG, "Done rcven\n"); // Finish rcven @@ -2004,16 +2091,18 @@ void raminit_ddr2(struct sysinfo *s) MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; // Dummy writes / reads - volatile u32 data; - FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { - for (bank = 0; bank < 4; bank++) { - reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); - write32((u32 *)reg32, 0xffffffff); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); - write32((u32 *)reg32, 0x00000000); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + if (s->boot_path == BOOT_PATH_NORMAL) { + volatile u32 data; + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + for (bank = 0; bank < 4; bank++) { + reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); + write32((u32 *)reg32, 0xffffffff); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); + write32((u32 *)reg32, 0x00000000); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + } } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 7ca634f..66d765a 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -87,8 +87,8 @@ #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) #define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ -#define PMSTS_WARM_RESET (1 << 1) -#define PMSTS_BOTH_SELFREFRESH (1 << 0) +#define PMSTS_WARM_RESET (1 << 8) +#define PMSTS_BOTH_SELFREFRESH (3 << 0) #define CLKCFG_MCHBAR 0x0c00 #define CLKCFG_FSBCLK_SHIFT 0 @@ -290,6 +290,9 @@ struct sysinfo { struct dimminfo dimms[4]; u8 spd_map[4]; }; +#define BOOT_PATH_NORMAL 0 +#define BOOT_PATH_WARM_RESET 1 +#define BOOT_PATH_RESUME 2 enum ddr2_signals { CLKSET0 = 0,

1 0

Patch set updated for coreboot: SeaBIOS Kconfig: Update logging
by Martin Roth 23 Jan '17

23 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18210 -gerrit commit 3c8174291d475bccc44d6984ec9f477acf61785e Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 23 14:56:55 2017 -0700 SeaBIOS Kconfig: Update logging The SeaBIOS VGA ROM outputs interrupts at log level 3, leading to an extreme slowdown in boot speed. - If SeaBIOS VGA is used, limit default log level to 2. - Add help text for what is displayed at various levels. - Get rid of separate type & prompt lines. Change-Id: I5a8b75bd44748cb94a83a77ac3a379c8a9587e7b Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/external/SeaBIOS/Kconfig | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 276f75d..9be7689 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -95,13 +95,32 @@ config PAYLOAD_VGABIOS_FILE default "payloads/external/SeaBIOS/seabios/out/vgabios.bin" config SEABIOS_DEBUG_LEVEL - prompt "SeaBIOS debug level (verbosity)" + int "SeaBIOS debug level (verbosity)" + default 0 if SEABIOS_VGA_COREBOOT && (DEFAULT_CONSOLE_LOGLEVEL_0 || DEFAULT_CONSOLE_LOGLEVEL_1) + default 1 if SEABIOS_VGA_COREBOOT && (DEFAULT_CONSOLE_LOGLEVEL_2 || DEFAULT_CONSOLE_LOGLEVEL_3) + default 2 if SEABIOS_VGA_COREBOOT default DEFAULT_CONSOLE_LOGLEVEL - int help The higher the number, the more verbose SeaBIOS will be. The range is not well defined but the typical values range from 0 to about 9 inclusive where 0 disables all output. Set this value to -1 to use SeaBIOS' default. - The default is to use coreboot's loglevel. + The default is to use coreboot's loglevel unless using the SeaBIOS + VGA rom, where it defaults to 2 or below due to exessive logging + above that level. + + Output at various SeaBIOS log levels: + level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM + level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h + level 3 - SeaBIOS VGA BIOS interrupts, bootsplash, initializations + level 4 - bios tables, more optionrom + level 5 - Extra bootsplash, more XHCI + level 6 - ATA commands, extra optionrom + level 7 - extra ps2 commands, more OHCI & EHCI + level 8 - extra malloc info, more AHCI + level 9 - interrupts 15h, 16h, 1ah, APM, PCI, SMIs, PCIBIOS, + USB-HID commands, SDcard commands, Floppy commands + level 10 - interrupt 13h (Drives other than floppy) + level 20 - interrupt 10h (Display) + endif

1 0

New patch to review for coreboot: SeaBIOS Kconfig: Update logging
by Martin Roth 23 Jan '17

23 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18210 -gerrit commit c2e21ff506b648cadbf11f5665cb710923d60be4 Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 23 14:56:55 2017 -0700 SeaBIOS Kconfig: Update logging The SeaBIOS VGA ROM outputs interrupts at log level 3, leading to an extreme slowdown in boot speed. - If SeaBIOS VGA is used, limit default log level to 2. - Add help text for what is displayed at various levels. - Get rid of separate type & prompt lines. Change-Id: I5a8b75bd44748cb94a83a77ac3a379c8a9587e7b Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/external/SeaBIOS/Kconfig | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 276f75d..51476d8 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -95,13 +95,32 @@ config PAYLOAD_VGABIOS_FILE default "payloads/external/SeaBIOS/seabios/out/vgabios.bin" config SEABIOS_DEBUG_LEVEL - prompt "SeaBIOS debug level (verbosity)" + int "SeaBIOS debug level (verbosity)" + default 0 if SEABIOS_VGA_COREBOOT && (DEFAULT_CONSOLE_LOGLEVEL_0 || DEFAULT_CONSOLE_LOGLEVEL_1) + default 1 if SEABIOS_VGA_COREBOOT && (DEFAULT_CONSOLE_LOGLEVEL_2 || DEFAULT_CONSOLE_LOGLEVEL_3) + default 2 if SEABIOS_VGA_COREBOOT default DEFAULT_CONSOLE_LOGLEVEL - int help The higher the number, the more verbose SeaBIOS will be. The range is not well defined but the typical values range from 0 to about 9 inclusive where 0 disables all output. Set this value to -1 to use SeaBIOS' default. - The default is to use coreboot's loglevel. + The default is to use coreboot's loglevel unless using the SeaBIOS + VGA rom, where it defaults to 2 or below due to exessive logging + above that level. + + Output at various SeaBIOS log levels: + level 1 - Basic output, interrupts 5, 18h, 19h 40h SMP, PNP, PMM + level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h + level 3 - SeaBIOS VGA BIOS interrupts, bootsplash, initializations + level 4 - bios tables, more optionrom + level 5 - Extra bootsplash, more XHCI + level 6 - ATA commands, extra optionrom + level 7 - extra ps2 commands, more OHCI & EHCI + level 8 - extra malloc info, more AHCI + level 9 - interrupts 15h, 16h, 1ah, APM, PCI, SMIs, PCIBIOS, + USB-HID commands, SDcard commands, Floppy commands + level 10 - interrupt 13h (Drives other than floppy) + level 20 - interrupt 10h (Display) + endif

1 0

Patch set updated for coreboot: nb/intel/x4x: Implement resume from S3 suspend
by Arthur Heymans 23 Jan '17

23 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17998 -gerrit commit ab0123537b9e618e51b795bba7e246e4adc62c97 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Dec 30 21:07:18 2016 +0100 nb/intel/x4x: Implement resume from S3 suspend It rewrites the results of receive enable stored in the upper nvram region, to avoid running receive enable again. Some debug info is also printed about the self-refresh registers. (Not enforcing a reset here, since 0 does not necessarily mean it's not in self-refresh). Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 +++++-- src/northbridge/intel/x4x/pcie.c | 15 ++++++++++++-- src/northbridge/intel/x4x/raminit_ddr2.c | 28 ++++++++++++++++++++------ src/northbridge/intel/x4x/x4x.h | 2 +- 5 files changed, 42 insertions(+), 11 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 3d2a892..ae57e5b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS select REALTEK_8168_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index d76fbb2..0a1470b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -132,6 +132,7 @@ void mainboard_romstage_entry(unsigned long bist) // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; u8 boot_path = 0; + u8 s3_resume; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -151,16 +152,18 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); - cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); - x4x_late_init(); + x4x_late_init(s3_resume); printk(BIOS_DEBUG, "x4x late init complete\n"); diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c index f03869e..648f10d 100644 --- a/src/northbridge/intel/x4x/pcie.c +++ b/src/northbridge/intel/x4x/pcie.c @@ -18,10 +18,11 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> +#include <cbmem.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> - +#include <romstage_handoff.h> #include "iomap.h" #include "x4x.h" @@ -184,8 +185,18 @@ static void init_dmi(void) reg16 = DMIBAR16(0x88); } -void x4x_late_init(void) +static void x4x_prepare_resume(int s3resume) +{ + int cbmem_was_initted; + + cbmem_was_initted = !cbmem_recovery(s3resume); + + romstage_handoff_init(cbmem_was_initted && s3resume); +} + +void x4x_late_init(int s3resume) { init_egress(); init_dmi(); + x4x_prepare_resume(s3resume); } diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 48a46fa..6c8a705 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -262,6 +262,16 @@ static void clkcross_ddr2(struct sysinfo *s) static void checkreset_ddr2(struct sysinfo *s) { u8 pmcon2; + u32 pmsts = MCHBAR32(PMSTS_MCHBAR); + + if (s->boot_path >= 1) { + if (!(pmsts & 1)) + printk(BIOS_DEBUG, + "Channel 0 possibly not in self refresh\n"); + if (!(pmsts & 2)) + printk(BIOS_DEBUG, + "Channel 1 possibly not in self refresh\n"); + } pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); @@ -1476,7 +1486,6 @@ static void rcven_ddr2(struct sysinfo *s) readdelay[ch] = MCHBAR16(0x400*ch + 0x588); } // END EACH POPULATED CHANNEL - /* TODO: Resume support using this */ FOR_EACH_CHANNEL(ch) { for (lane = 0; lane < 8; lane++) { MCHBAR8(0x400*ch + 0x560 + (lane*4)) = @@ -1556,7 +1565,8 @@ static void sdram_program_receive_enable(struct sysinfo *s) RCBA32(0x3400) = (1 << 2); /* Program Receive Enable Timings */ - if (s->boot_path == BOOT_PATH_WARM_RESET) { + if ((s->boot_path == BOOT_PATH_WARM_RESET) + || (s->boot_path == BOOT_PATH_RESUME)) { sdram_recover_receive_enable(); } else { rcven_ddr2(s); @@ -2044,7 +2054,8 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done pre-jedec\n"); // JEDEC reset - jedec_ddr2(s); + if (s->boot_path != BOOT_PATH_RESUME) + jedec_ddr2(s); printk(BIOS_DEBUG, "Done jedec steps\n"); @@ -2095,13 +2106,18 @@ void raminit_ddr2(struct sysinfo *s) volatile u32 data; FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (bank = 0; bank < 4; bank++) { - reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); + reg32 = (ch << 29) | (r*0x8000000) | + (bank << 12); write32((u32 *)reg32, 0xffffffff); data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); + printk(BIOS_DEBUG, "Wrote ones"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); write32((u32 *)reg32, 0x00000000); data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + printk(BIOS_DEBUG, "Wrote zeros"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); } } } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 66d765a..faae775 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -322,7 +322,7 @@ enum ddr2_signals { #ifndef __BOOTBLOCK__ void x4x_early_init(void); -void x4x_late_init(void); +void x4x_late_init(int s3resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len);

1 0

Patch set updated for coreboot: nb/intel/x4x: Implement resume from S3 suspend
by Arthur Heymans 23 Jan '17

23 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17998 -gerrit commit 5cfa66fcd058d797f16511817660c2192a2d47dd Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Dec 30 21:07:18 2016 +0100 nb/intel/x4x: Implement resume from S3 suspend It rewrites the results of receive enable stored in the upper nvram region, to avoid running receive enable again. Some debug info is also printed about the self-refresh registers. (Not enforcing a reset here, since 0 does not necessarily mean it's not in self-refresh). Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 +++++-- src/northbridge/intel/x4x/pcie.c | 15 ++++++++++++-- src/northbridge/intel/x4x/raminit_ddr2.c | 28 ++++++++++++++++++++------ src/northbridge/intel/x4x/x4x.h | 2 +- 5 files changed, 42 insertions(+), 11 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 3d2a892..ae57e5b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS select REALTEK_8168_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index d76fbb2..0a1470b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -132,6 +132,7 @@ void mainboard_romstage_entry(unsigned long bist) // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; u8 boot_path = 0; + u8 s3_resume; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -151,16 +152,18 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); - cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); - x4x_late_init(); + x4x_late_init(s3_resume); printk(BIOS_DEBUG, "x4x late init complete\n"); diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c index f03869e..648f10d 100644 --- a/src/northbridge/intel/x4x/pcie.c +++ b/src/northbridge/intel/x4x/pcie.c @@ -18,10 +18,11 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> +#include <cbmem.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> - +#include <romstage_handoff.h> #include "iomap.h" #include "x4x.h" @@ -184,8 +185,18 @@ static void init_dmi(void) reg16 = DMIBAR16(0x88); } -void x4x_late_init(void) +static void x4x_prepare_resume(int s3resume) +{ + int cbmem_was_initted; + + cbmem_was_initted = !cbmem_recovery(s3resume); + + romstage_handoff_init(cbmem_was_initted && s3resume); +} + +void x4x_late_init(int s3resume) { init_egress(); init_dmi(); + x4x_prepare_resume(s3resume); } diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 48a46fa..f1ae3fc 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -262,6 +262,16 @@ static void clkcross_ddr2(struct sysinfo *s) static void checkreset_ddr2(struct sysinfo *s) { u8 pmcon2; + u32 pmsts = MCHBAR32(PMSTS_MCHBAR); + + if (s->boot_path >= 1) { + if (!(pmsts & 1)) + printk(BIOS_DEBUG, + "Channel 0 possibly not in self refresh\n"); + if (!(pmsts & 2)) + printk(BIOS_DEBUG, + "Channel 1 possibly not in self refresh\n"); + } pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); @@ -1476,7 +1486,6 @@ static void rcven_ddr2(struct sysinfo *s) readdelay[ch] = MCHBAR16(0x400*ch + 0x588); } // END EACH POPULATED CHANNEL - /* TODO: Resume support using this */ FOR_EACH_CHANNEL(ch) { for (lane = 0; lane < 8; lane++) { MCHBAR8(0x400*ch + 0x560 + (lane*4)) = @@ -1556,7 +1565,8 @@ static void sdram_program_receive_enable(struct sysinfo *s) RCBA32(0x3400) = (1 << 2); /* Program Receive Enable Timings */ - if (s->boot_path == BOOT_PATH_WARM_RESET) { + if ((s->boot_path == BOOT_PATH_WARM_RESET) + || (s->boot_path == BOOT_PATH_RESUME)) { sdram_recover_receive_enable(); } else { rcven_ddr2(s); @@ -2044,7 +2054,8 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done pre-jedec\n"); // JEDEC reset - jedec_ddr2(s); + if (s->boot_path != BOOT_PATH_SUSPEND) + jedec_ddr2(s); printk(BIOS_DEBUG, "Done jedec steps\n"); @@ -2095,13 +2106,18 @@ void raminit_ddr2(struct sysinfo *s) volatile u32 data; FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (bank = 0; bank < 4; bank++) { - reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); + reg32 = (ch << 29) | (r*0x8000000) | + (bank << 12); write32((u32 *)reg32, 0xffffffff); data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); + printk(BIOS_DEBUG, "Wrote ones"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); write32((u32 *)reg32, 0x00000000); data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + printk(BIOS_DEBUG, "Wrote zeros"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); } } } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 66d765a..faae775 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -322,7 +322,7 @@ enum ddr2_signals { #ifndef __BOOTBLOCK__ void x4x_early_init(void); -void x4x_late_init(void); +void x4x_late_init(int s3resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len);

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coreboot-gerrit January 2017