coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: mainboard/intel/kblrvp: Generate required nhlt tables
by Rizwan Qureshi 24 Jan '17

24 Jan '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18218 -gerrit commit ece3b52162e5d720ad39ed8098ae6b645a2b5c15 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Jan 24 13:52:20 2017 +0530 mainboard/intel/kblrvp: Generate required nhlt tables Change-Id: I0978f3d1d002067ac801291c077fdaa7eda714d7 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/intel/kblrvp/Kconfig | 7 +++++ src/mainboard/intel/kblrvp/mainboard.c | 48 ++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 296b922..f68d8ca 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -53,6 +53,13 @@ config VARIANT_DIR default "rvp3" if BOARD_INTEL_KBLRVP3 default "rvp7" if BOARD_INTEL_KBLRVP7 +config INCLUDE_NHLT_BLOBS + bool "Include blobs for audio." + select NHLT_DMIC_2CH + select NHLT_DMIC_4CH + select NHLT_RT5663 if BOARD_INTEL_KBLRVP3 + select NHLT_MAX98927 if BOARD_INTEL_KBLRVP3 + config MAINBOARD_PART_NUMBER string default "Kblrvp" diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index 652af73..a14b436 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -32,6 +32,53 @@ static void mainboard_init(device_t dev) mainboard_ec_init(); } +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + const char *oem_id = NULL; + const char *oem_table_id = NULL; + uint32_t oem_revision = 0; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + + /* 4 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); + /*ToDo as im getting error, i'm reverting to old codecs*/ + /* MAXIM98927 Smart Amps for left and right channel */ + if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0)){ + + printk(BIOS_ERR, "Couldn't add max98927\n"); + oem_id = oem_id_maxim; + oem_table_id = oem_table_id_maxim; + } + + /* RT5663 Headset codec. */ + if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, + oem_id, oem_table_id, oem_revision); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + /* * mainboard_enable is executed as first thing after * enumerate_buses(). @@ -39,6 +86,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; }

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Patch merged into coreboot/master: cbfs-compression-tool: catch compression failures
by gerrit＠coreboot.org 24 Jan '17

24 Jan '17

the following patch was just integrated into master: commit b46c4ecaba97cc1edbfa2114651fc2bcbf49914b Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jan 23 09:35:44 2017 +0100 cbfs-compression-tool: catch compression failures If compression failed, just store the uncompressed data, which is what cbfstool does as well. Change-Id: I67f51982b332d6ec1bea7c9ba179024fc5344743 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/18201 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18201 for details. -gerrit

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Patch merged into coreboot/master: vboot: vb2ex_printf() ignores null function name
by gerrit＠coreboot.org 24 Jan '17

24 Jan '17

the following patch was just integrated into master: commit e80c6f6d3cd0eb7bde651364cc29d41da94f0082 Author: Randall Spangler <rspangler(a)chromium.org> Date: Fri Jan 20 14:48:53 2017 -0800 vboot: vb2ex_printf() ignores null function name Currently, it will print the function name as a prefix to the debug output. Make it so that a null function name won't get printed, so that it's possible to print little bits of debug output. BUG=chromium:683391 BRANCH=none TEST=build_packages --board=reef chromeos-firmware Change-Id: I046fa766773fc08a29460db1f884d7902692d182 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 853ff7176e97e5e1ab664d094e1914c9c94510aa Original-Change-Id: I1dff38e4d8ab03118e5f8832a16d82c2d2116ec9 Original-Signed-off-by: Randall Spangler <rspangler(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/431111 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/18204 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18204 for details. -gerrit

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Patch merged into coreboot/master: rockchip/rk3399: set edp pclk to 25MHz
by gerrit＠coreboot.org 24 Jan '17

24 Jan '17

the following patch was just integrated into master: commit 4ecccff72f1876c264303aac48cb7143fe36cecc Author: Lin Huang <hl(a)rock-chips.com> Date: Wed Jan 18 09:44:34 2017 +0800 rockchip/rk3399: set edp pclk to 25MHz It may cause an edp aux transfer error if the edp pclk is set too high, so reduce it to 25MHz. BUG=chrome-os-partner:60130 BRANCH=None TEST=Build and Boot Change-Id: Id1063baa5a82637b03c0f1f754181df074ab17cc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8f7ce31a7483e765ae0c86f8e62ef51413ee1596 Original-Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/429410 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/18178 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18178 for details. -gerrit

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Patch merged into coreboot/master: libpayload: drivers/keyboard: report power button events
by gerrit＠coreboot.org 24 Jan '17

24 Jan '17

the following patch was just integrated into master: commit 674e971dc4f7696393a7f7a18cbbc581029d9e0b Author: Shelley Chen <shchen(a)chromium.org> Date: Fri Jan 13 09:40:39 2017 -0800 libpayload: drivers/keyboard: report power button events Power button events are usually dropped because the button is not in the keyboard matrix range. Add condition to forward it like other keys. BUG=chrome-os-partner:61275 BRANCH=None TEST=reboot and make sure power button selection in depthcharge's detachable menus is processed on reef. Change-Id: I86897fa8d73a56533ef62bba05458ac3d339237e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 25654e214f0ab8685d445ced62612a02be851126 Original-Change-Id: I516a0043bd7730789728d5c5498d0a0f30a2acac Original-Signed-off-by: Shelley Chen <shchen(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/428199 Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> Reviewed-on: https://review.coreboot.org/18177 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18177 for details. -gerrit

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New patch to review for coreboot: google/pyro: Modify Wacom touchscreen IRQ type to level-triggered
by Kevin Chiu 24 Jan '17

24 Jan '17

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18217 -gerrit commit d3bb7e36294829c493fcf7c1dc3b329d14ab740c Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Tue Jan 24 16:24:30 2017 +0800 google/pyro: Modify Wacom touchscreen IRQ type to level-triggered Follow i2c-hid spec definition, level trigger interrupt is required for i2c-hid device. BUG=chrome-os-partner:61513 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ia825bd0c898e71e2ee2bf411f117a49a8fb411b6 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index f7551d6..193fdd8 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -170,7 +170,7 @@ chip soc/intel/apollolake .hid = WCOMNTN2_HID, .cid = PNP0C50_CID, .desc = WCOM_TS_DESC, - .irq = IRQ_EDGE_LOW(GPIO_21_IRQ), + .irq = IRQ_LEVEL_LOW(GPIO_21_IRQ), .probed = 1, }" register "hid_desc_reg_offset" = "0x1"

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Patch set updated for coreboot: mb/intel/d510mo: Add cmos.layout and cmos.default
by Arthur Heymans 24 Jan '17

24 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18143 -gerrit commit 456f5dd2db85be9890f64f26a9458a6d2538f5ac Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jan 14 17:40:18 2017 +0100 mb/intel/d510mo: Add cmos.layout and cmos.default Change-Id: I877d4470b697d6a6d4652ed1c60028cdcbe8df98 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/intel/d510mo/Kconfig | 2 + src/mainboard/intel/d510mo/cmos.default | 6 ++ src/mainboard/intel/d510mo/cmos.layout | 98 +++++++++++++++++++++++++++++++++ 3 files changed, 106 insertions(+) diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index 7184665..7131b3a 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -25,6 +25,8 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_1024 select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_INT15 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT config MAX_CPUS int diff --git a/src/mainboard/intel/d510mo/cmos.default b/src/mainboard/intel/d510mo/cmos.default new file mode 100644 index 0000000..488aa37 --- /dev/null +++ b/src/mainboard/intel/d510mo/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable +gfx_uma_size=8M diff --git a/src/mainboard/intel/d510mo/cmos.layout b/src/mainboard/intel/d510mo/cmos.layout new file mode 100644 index 0000000..3e96412 --- /dev/null +++ b/src/mainboard/intel/d510mo/cmos.layout @@ -0,0 +1,98 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: bootloader +416 512 s 0 boot_devices + +# coreboot config options: cpu +944 1 e 2 hyper_threading +#945 7 r 0 unused + +# coreboot config options: northbridge +952 3 e 11 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 8M +11 1 16M +11 2 32M +11 3 48M +11 4 64M +11 5 128M +11 6 256M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984

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Patch set updated for coreboot: nb/intel/pineview: Make preallocated igd memory a cmos parameter
by Arthur Heymans 24 Jan '17

24 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18142 -gerrit commit b9e4498ff3ff97616604398fecfa4cc66f863a23 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jan 14 17:32:20 2017 +0100 nb/intel/pineview: Make preallocated igd memory a cmos parameter Change-Id: Ia7fa2c290e540ff779cf8dc16147db5a248021e2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/pineview/early_init.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 842ffa1..e1cf95f 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -25,6 +25,7 @@ #include <string.h> #include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/chip.h> +#include <pc80/mc146818rtc.h> #define LPC PCI_DEV(0, 0x1f, 0) #define D0F0 PCI_DEV(0, 0, 0) @@ -45,7 +46,16 @@ static void early_graphics_setup(void) const struct northbridge_intel_pineview_config *config = d0f0->chip_info; pci_write_config8(D0F0, DEVEN, BOARD_DEVEN); - pci_write_config16(D0F0, GGC, 0x130); /* 1MB GTT 8MB UMA */ + + /* vram size from cmos option */ + if (get_option(&reg8, "gfx_uma_size") != CB_SUCCESS) + reg8 = 0; /* 0 for 8MB */ + /* make sure no invalid setting is used */ + if (reg8 > 6) + reg8 = 0; + /* Select 1M GTT */ + pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, (1 << 8) + | ((reg8 + 3) << 4)); printk(BIOS_SPEW, "Set GFX clocks..."); reg16 = MCHBAR16(MCH_GCFGC);

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New patch to review for coreboot: mainboard/google/poppy: Enable Realtek 5663 support in poppy
by Rizwan Qureshi 24 Jan '17

24 Jan '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18216 -gerrit commit b95ea6acd973c2359975a018e7d4e48c4e17aaf1 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Mon Jan 16 15:16:50 2017 +0530 mainboard/google/poppy: Enable Realtek 5663 support in poppy Enable Realtek 5663 in poppy BUG=None BRANCH=None TEST=With required driver support in kernel verify audio on headeset Change-Id: I9b9eb1e7edca56870f5be0e4fd603c9b0dc7f9de Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/Kconfig | 3 +++ src/mainboard/google/poppy/devicetree.cb | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 42fdf25..a073bed 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -32,6 +32,9 @@ config MAINBOARD_DIR string default "google/poppy" +config DRIVERS_I2C_RT5663 + default y + config MAINBOARD_PART_NUMBER string default "Poppy" diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 25d63ae..22bf325 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -239,6 +239,10 @@ chip soc/intel/skylake }" device i2c 3A on end end + chip drivers/i2c/rt5663 + register "irq" = "IRQ_LEVEL_LOW(GPP_D9_IRQ)" + device i2c 13 on end + end end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on

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New patch to review for coreboot: mainboard/google/poppy: Enable Maxim 98927 codec
by Rizwan Qureshi 24 Jan '17

24 Jan '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18215 -gerrit commit 3e0a98382022b86c03b8adab1e91ad7e28daf9aa Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 22:22:42 2017 +0530 mainboard/google/poppy: Enable Maxim 98927 codec Enable Maxim 98927 codec i2c device and add required SSDT parameters. BUG=None BRANCH=None TEST=with required driver support in kernel verfy audio on poppy on-board speakers. Change-Id: Id731de42d77204d59f32ac4c33a245837d6e2107 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/Kconfig | 3 +++ src/mainboard/google/poppy/devicetree.cb | 25 ++++++++++++++++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index e889e01..42fdf25 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -20,6 +20,9 @@ config CHROMEOS config DRIVERS_I2C_GENERIC def_bool y +config DRIVERS_I2C_MAX98927 + def_bool y + config GBB_HWID string depends on CHROMEOS diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index a9e0cef..25d63ae 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -216,7 +216,30 @@ chip soc/intel/skylake device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 - device pci 19.1 on end # I2C #5 + device pci 19.1 on + chip drivers/i2c/max98927 + register "interleave_mode" = "1" + register "reg" = "0x3A" + register "sub_reg" = "0x39" + register "regcfg" = "{ + 0, 0x1c, 0xfe, + 0, 0x1e, 0x00, + 0, 0x24, 0x85, + 0, 0x25, 0x85, + 0, 0x36, 0x03, + 0, 0x37, 0x03, + 0, 0x3C, 0x05, + 1, 0x1c, 0xfd, + 1, 0x1e, 0x11, + 1, 0x24, 0x85, + 1, 0x25, 0x40, + 1, 0x36, 0x38, + 1, 0x37, 0x03, + 1, 0x3C, 0x05 + }" + device i2c 3A on end + end + end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on chip drivers/intel/wifi

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coreboot-gerrit January 2017