coreboot-gerrit August 2016

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Patch set updated for coreboot: nb/amd/pi/00730F01: Add initial native IVRS support
by Philipp Deppenwiese 21 Aug '16

21 Aug '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15164 -gerrit commit 5402c41ce353c6f6e1efd758a7580942e8953d67 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jun 13 13:48:58 2016 -0500 nb/amd/pi/00730F01: Add initial native IVRS support Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/mainboard/amd/olivehillplus/acpi_tables.c | 9 ++ src/mainboard/pcengines/apu2/acpi_tables.c | 9 ++ src/northbridge/amd/pi/00730F01/northbridge.c | 208 ++++++++++++++++++++++++-- 3 files changed, 214 insertions(+), 12 deletions(-) diff --git a/src/mainboard/amd/olivehillplus/acpi_tables.c b/src/mainboard/amd/olivehillplus/acpi_tables.c index d5ebad4..a1a5a6b 100644 --- a/src/mainboard/amd/olivehillplus/acpi_tables.c +++ b/src/mainboard/amd/olivehillplus/acpi_tables.c @@ -54,3 +54,12 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } + +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +{ + /* TODO + * Add IVRS entries + */ + + return current; +} diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c index d5ebad4..17995ce 100644 --- a/src/mainboard/pcengines/apu2/acpi_tables.c +++ b/src/mainboard/pcengines/apu2/acpi_tables.c @@ -54,3 +54,12 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } + +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +{ + /* TODO + * Add IVRS entries + */ + + return current; +} diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 9b1c1b1..44b1501 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -478,6 +479,193 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } +static void add_ivrs_device_entries(struct device *parent, struct device *dev, int depth, int linknum, int8_t *root_level, unsigned long *current, uint16_t *length) +{ + uint8_t *p; + struct device *sibling; + struct bus *link; + + if (!root_level) { + root_level = malloc(sizeof(int8_t)); + *root_level = -1; + } + + if (dev->path.type == DEVICE_PATH_PCI) { + if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) + *root_level = depth; + + if (*root_level != -1) { + if (depth >= *root_level) { + if (dev->enabled) { + if (depth == *root_level) { + if (dev->path.pci.devfn == 0x2) { + /* IOMMU */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else if (dev->path.pci.devfn < (0x2 << 3)) { + /* FCH control device */ + } else if ((dev->path.pci.devfn >= (0x2 << 3)) && (dev->path.pci.devfn < (0x3 << 3))) { + /* FCH PCIe bridge device */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else { + if (dev->path.pci.devfn == (0x14 << 3)) { + /* SMBUS controller */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x97; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else { + /* Other southbridge device */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } + } + } else { + if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) { + /* Device behind bridge */ + if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) { + /* Device is PCIe */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else { + /* Device is legacy PCI or PCI-X */ + p = (uint8_t *) *current; + p[0] = 0x42; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Reserved */ + p[5] = parent->path.pci.devfn; /* Device */ + p[6] = parent->bus->secondary; /* Bus */ + p[7] = 0x0; /* Reserved */ + *length += 8; + *current += 8; + } + } else if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { + if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) { + /* Bridge is PCIe */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } + } + } + } + } + } + } + + for (link = dev->link_list; link; link = link->next) + for (sibling = link->children; sibling; sibling = sibling->sibling) + add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length); + + free(root_level); +} + +static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current) +{ + uint8_t *p; + + device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!nb_dev) { + printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate G-series northbridge device! IVRS table not generated...\n"); + return (unsigned long)ivrs; + } + + ivrs->iv_info = 0x0; + ivrs->iv_info |= (0x40 << 15); /* Maximum supported virtual address size */ + ivrs->iv_info |= (0x30 << 8); /* Maximum supported physical address size */ + ivrs->iv_info |= (0x2 << 5); /* Guest virtual address width */ + + ivrs->ivhd.type = 0x10; + ivrs->ivhd.flags = 0x0e; + ivrs->ivhd.flags |= 0x10; /* Enable ATS support */ + ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); + ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */ + ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */ + ivrs->ivhd.iommu_base_low = 0xfeb00000; + ivrs->ivhd.iommu_base_high = 0x0; + ivrs->ivhd.pci_segment_group = 0x0; + ivrs->ivhd.iommu_info = 0x0; + ivrs->ivhd.iommu_info |= (0x13 << 8); + ivrs->ivhd.efr = 0x0; + + /* Describe HPET */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0xd7; /* Data */ + p[4] = 0x0; /* HPET number */ + p[5] = 0x14 << 3; /* HPET device */ + p[6] = nb_dev->bus->secondary; /* HPET bus */ + p[7] = 0x2; /* Variety */ + ivrs->ivhd.length += 8; + current += 8; + + /* Describe PCI devices */ + add_ivrs_device_entries(NULL, all_devices, 0, -1, NULL, &current, &ivrs->ivhd.length); + + /* Describe IOAPICs */ + unsigned long prev_current = current; + current = acpi_fill_ivrs_ioapic(ivrs, current); + ivrs->ivhd.length += (current - prev_current); + + return current; +} + static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; @@ -507,7 +695,7 @@ static unsigned long agesa_write_acpi_tables(device_t device, acpi_slit_t *slit; acpi_header_t *ssdt; acpi_header_t *alib; - acpi_header_t *ivrs; + acpi_ivrs_t *ivrs; acpi_hest_t *hest; /* HEST */ @@ -517,17 +705,13 @@ static unsigned long agesa_write_acpi_tables(device_t device, acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); - ivrs = agesawrapper_getlateinitptr(PICK_IVRS); - if (ivrs != NULL) { - memcpy((void *)current, ivrs, ivrs->length); - ivrs = (acpi_header_t *) current; - current += ivrs->length; - acpi_add_table(rsdp, ivrs); - } else { - printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); - } + /* IVRS */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = (acpi_ivrs_t *) current; + acpi_create_ivrs(ivrs, acpi_fill_ivrs); + current += ivrs->header.length; + acpi_add_table(rsdp, ivrs); /* SRAT */ current = ALIGN(current, 8);

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Patch set updated for coreboot: nb/amd/pi/00730F01: Initialize IOMMU device
by Philipp Deppenwiese 21 Aug '16

21 Aug '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15186 -gerrit commit cbc739a3777ecb77854ecef044b40abc01af205b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 14 14:49:07 2016 -0500 nb/amd/pi/00730F01: Initialize IOMMU device Change-Id: I12d3ed35770ee06626f884db23004652084c88c0 --- src/cpu/amd/pi/heapmanager.c | 4 +- src/include/device/pci_ids.h | 1 + src/northbridge/amd/pi/00730F01/Makefile.inc | 1 + src/northbridge/amd/pi/00730F01/iommu.c | 71 ++++++++++++++++++++++++++++ src/northbridge/amd/pi/agesawrapper.c | 2 + 5 files changed, 77 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c index d4a79b8..31f964f 100644 --- a/src/cpu/amd/pi/heapmanager.c +++ b/src/cpu/amd/pi/heapmanager.c @@ -37,7 +37,7 @@ void EmptyHeap(void) memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE); } -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) && !defined(__PRE_RAM__) +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) && !defined(__PRE_RAM__) #define AGESA_RUNTIME_SIZE 4096 @@ -83,7 +83,7 @@ AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); AllocParams->BufferPointer = NULL; -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) && !defined(__PRE_RAM__) +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) && !defined(__PRE_RAM__) /* if the allocation is for runtime use simple CBMEM data */ if (Data == HEAP_CALLOUT_RUNTIME) return alloc_cbmem(AllocParams); diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 72f1ece..f3e48ee 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -293,6 +293,7 @@ #define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 #define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 +#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 diff --git a/src/northbridge/amd/pi/00730F01/Makefile.inc b/src/northbridge/amd/pi/00730F01/Makefile.inc index 3cf4ed1..39c3ee6 100644 --- a/src/northbridge/amd/pi/00730F01/Makefile.inc +++ b/src/northbridge/amd/pi/00730F01/Makefile.inc @@ -16,3 +16,4 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c +ramstage-y += iommu.c diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c new file mode 100644 index 0000000..00b65a4 --- /dev/null +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <lib.h> + +static void iommu_read_resources(struct device *dev) +{ + struct resource *res; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, 0x44); + res->size = 512 * 1024; + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffff; /* 4G */ + res->flags = IORESOURCE_MEM; +} + +static void iommu_set_resources(struct device *dev) +{ + pci_dev_set_resources(dev); + +#if 0 + struct resource *res; + + res = find_resource(dev, 0x44); + /* Remember this resource has been stored */ + res->flags |= IORESOURCE_STORED; + /* For now, do only 32-bit space allocation */ + pci_write_config32(dev, 0x48, 0x0); + pci_write_config32(dev, 0x44, res->base | (1 << 0)); +#endif +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations iommu_ops = { + .read_resources = iommu_read_resources, + .set_resources = iommu_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver iommu_driver __pci_driver = { + .ops = &iommu_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU, +}; diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index b1e514a..c345f68 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -299,6 +299,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void) /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; + AmdLateParams->GnbLateConfiguration.GnbIoapicId = 0x05; + AmdLateParams->GnbLateConfiguration.FchIoapicId = 0x04; Status = AmdInitLate(AmdLateParams); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus);

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Patch set updated for coreboot: pcengines/apu2: add board support
by Philipp Deppenwiese 21 Aug '16

21 Aug '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14138 -gerrit commit 631f7e7de57d6c46a0d158dfdca37f9d35abd209 Author: Piotr Król <piotr.krol(a)3mdeb.com> Date: Fri May 27 12:04:13 2016 +0200 pcengines/apu2: add board support Initial work based on db-ft3b-ls and code released by Eltan. Board boots with some limitation. Known issues: * AmdInitLate fails Now the AGESA binary is harcoded and board specific until it's fixed by the SoC vendor. Seabios and memtest86+ url hardcoding is removed. memtest86+ from external repo skips looking for SPD on SMBus, which when performed cause memtest86+ to hang. Still didn't tried whole test suit. SeaBIOS from external repo enables input in APU2 serial console and makes devices connected to USB XHCI bootable. Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com> Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/mainboard/pcengines/apu2/BiosCallOuts.c | 158 ++++++++++++ src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex | 264 +++++++++++++++++++++ .../pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex | 261 ++++++++++++++++++++ src/mainboard/pcengines/apu2/Kconfig | 91 +++++++ src/mainboard/pcengines/apu2/Kconfig.name | 2 + src/mainboard/pcengines/apu2/Makefile.inc | 40 ++++ src/mainboard/pcengines/apu2/OemCustomize.c | 121 ++++++++++ src/mainboard/pcengines/apu2/acpi/AmdImc.asl | 109 +++++++++ src/mainboard/pcengines/apu2/acpi/gpe.asl | 67 ++++++ src/mainboard/pcengines/apu2/acpi/ide.asl | 2 + src/mainboard/pcengines/apu2/acpi/mainboard.asl | 37 +++ src/mainboard/pcengines/apu2/acpi/routing.asl | 193 +++++++++++++++ src/mainboard/pcengines/apu2/acpi/si.asl | 23 ++ src/mainboard/pcengines/apu2/acpi/sleep.asl | 95 ++++++++ src/mainboard/pcengines/apu2/acpi/thermal.asl | 2 + src/mainboard/pcengines/apu2/acpi/usb_oc.asl | 36 +++ src/mainboard/pcengines/apu2/acpi_tables.c | 56 +++++ src/mainboard/pcengines/apu2/apu2.h | 54 +++++ src/mainboard/pcengines/apu2/board_info.txt | 6 + src/mainboard/pcengines/apu2/cmos.layout | 74 ++++++ src/mainboard/pcengines/apu2/devicetree.cb | 91 +++++++ src/mainboard/pcengines/apu2/dsdt.asl | 87 +++++++ src/mainboard/pcengines/apu2/irq_tables.c | 103 ++++++++ src/mainboard/pcengines/apu2/mainboard.c | 195 +++++++++++++++ src/mainboard/pcengines/apu2/mptable.c | 166 +++++++++++++ src/mainboard/pcengines/apu2/romstage.c | 110 +++++++++ 26 files changed, 2443 insertions(+) diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c new file mode 100644 index 0000000..2d8fc91 --- /dev/null +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <spd_cache.h> +#include <northbridge/amd/pi/BiosCallOuts.h> +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "cbfs.h" +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include "imc.h" +#endif +#include "hudson.h" +#include <stdlib.h> +#include "apu2.h" + +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); +static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, + {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, + {AGESA_READ_SPD, board_ReadSpd_from_cbfs }, + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +//{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_NoopUnsupported } + + +/* + * Hardware Monitor Fan Control + * Hardware limitation: + * HWM will fail to read the input temperature via I2C if other + * software switches the I2C address. AMD recommends using IMC + * to control fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = FALSE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */ +} + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such Azalia, SATA, IMC etc. + */ +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; + if (StdHeader->Func == AMD_INIT_RESET) { + FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; + FchParams->FchReset.SataEnable = hudson_sata_enable(); + FchParams->FchReset.IdeEnable = hudson_ide_enable(); + FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->FchReset.Xhci1Enable = FALSE; + } else if (StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + + + FchParams->Azalia.AzaliaEnable = AzDisable; + + /* Fan Control */ + oem_fan_control(FchParams); + + /* XHCI configuration */ + FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci1Enable = FALSE; + + /* EHCI configuration */ + FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Ehci1Enable = FALSE; // Disable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci2Enable = TRUE; // Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. + + /* sata configuration */ + FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP + FchParams->Sata.SataDevSlpPort1 = 0; + + FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; + switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams->Sata.SataIdeMode = TRUE; + break; + } + } + printk(BIOS_DEBUG, "Done\n"); + + return AGESA_SUCCESS; +} + + +static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status = AGESA_UNSUPPORTED; +#ifdef __PRE_RAM__ + AGESA_READ_SPD_PARAMS *info = ConfigPtr; + int index = 0; + + if (info->MemChannelId > 0) + return AGESA_UNSUPPORTED; + if (info->SocketId != 0) + return AGESA_UNSUPPORTED; + if (info->DimmId != 0) + return AGESA_UNSUPPORTED; + + /* One SPD file contains all 4 options, determine which index to read here, then call into the standard routines*/ + + u8 *gpio_bank0_ptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE); + if (*(gpio_bank0_ptr + (0x40 << 2) + 2) & BIT0) index |= BIT0; + if (*(gpio_bank0_ptr + (0x41 << 2) + 2) & BIT0) index |= BIT1; + + printk(BIOS_INFO, "Reading SPD index %d\n", index); + + if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0) + die("No SPD data\n"); + + Status = AGESA_SUCCESS; +#endif + return Status; +} diff --git a/src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex b/src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex new file mode 100644 index 0000000..a70db53 --- /dev/null +++ b/src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex @@ -0,0 +1,264 @@ +# PCEngines 2Gb 1333 + +# SPD contents for APU 2GB DDR3 NO ECC (1333MHz PC1333) soldered down +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +01 + +# 1 SPD Revision +# 0x13 = Revision 1.3 +13 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[3:0]: 8 = 72b-SO-DIMM +# bits[7:4]: reserved +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip +# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +03 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[5:3]: 3 = 15 Row Address Bits +# bits[5:3]: 2 = 14 Row Address Bits +# bits[7:6]: reserved +19 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 1 = 8 bits +# bits[2:0]: 2 = 16 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +01 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 0 = 0 bits (no bus width extension) +# bits[4:3]: 1 = 8 bits (for ECC) +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x02 divisor +# bits[7:4]: 0x05 dividend +# 5 / 2 = 2.5ps +52 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) +# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock) +# 0x0c = tCKmin of 1.5 ns = in multiples of MTB +0C + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# Cas Latencies of 11 - 5 are supported +7E 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x6C = 13.5ns - DDR3-1333 +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x6E = 13.5ns - DDR3-1333 +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x30 = 6.0ns +# 0x38 = 7.0ns +# 0x3C = 7.5ns +30 + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x6C = 13.5ns - +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x120 = 36ns - DDR3-1333 (see byte 21) +# 0x120 = 36ns - DDR3 +20 + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x289 = 49.125ns - DDR3-1333 +89 + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x500 = 160ns - for 2 Gigabit chips +# 0x820 = 260ns - for 4 Gigabit chips +00 05 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x00F0 = 30ns - DDR3-1333, 1 KB page size +00 F0 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 1 = DLL Off mode supported +83 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 1 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +01 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 0 = Signal Loading not specified +# bits[3:2]: reserved +# bits[6:4]: 0 = Die count not specified +# bit7 : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +00 + +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +00 + +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +00 + +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +00 + +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 + +# 39 40 (reserved) +00 00 + +# 41 tMAW, MAC +# 8K*tREFI / 200k +86 + +# 42 - 47 (reserved) +00 00 00 00 00 00 + +# 48 - 55 (reserved) +00 00 00 00 00 00 00 00 + +# 56 - 59 (reserved) +00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +00 + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +00 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +# revision B4 +61 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 71 (reserved) +00 00 00 00 00 00 00 00 + +# 72 - 79 (reserved) +00 00 00 00 00 00 00 00 + +# 80 - 87 (reserved) +00 00 00 00 00 00 00 00 + +# 88 - 95 (reserved) +00 00 00 00 00 00 00 00 + +# 96 - 103 (reserved) +00 00 00 00 00 00 00 00 + +# 104 - 111 (reserved) +00 00 00 00 00 00 00 00 + +# 112 - 116 (reserved) +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x0001 = AMD +00 01 + +# 119 Module ID: Module Manufacturing Location - OEM specified +00 + +# 120 Module ID: Module Manufacture Year in BCD +# 0x15 = 2015 +15 + +# 121 Module ID: Module Manufacture week +# 0x44 = 44th week +44 + +# 122 - 125: Module Serial Number +00 00 00 00 + +# 126 - 127: Cyclical Redundancy Code +b6 73 + diff --git a/src/mainboard/pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex b/src/mainboard/pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex new file mode 100644 index 0000000..ac6b4c6 --- /dev/null +++ b/src/mainboard/pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex @@ -0,0 +1,261 @@ +# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix + +# SPD contents for APU 4GB DDR3 ECC (1333MHz PC1333) soldered down +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +01 + +# 1 SPD Revision - +# 0x13 = Revision 1.3 +13 +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[3:0]: 8 = 72b-SO-DIMM +# bits[7:4]: reserved +08 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip +# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[5:3]: 3 = 15 Row Address Bits +# bits[5:3]: 2 = 14 Row Address Bits +# bits[7:6]: reserved +21 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 1 = 8 bits +# bits[2:0]: 2 = 16 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +01 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 0 = 0 bits (no bus width extension) +# bits[4:3]: 1 = 8 bits (for ECC) +# bits[7:5]: reserved +0B + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x02 divisor +# bits[7:4]: 0x05 dividend +# 5 / 2 = 2.5 ps +52 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) +# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock) +# 0x0c = tCKmin of 1.5 ns = in multiples of MTB +0C + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# Cas Latencies of 11 - 5 are supported +7E 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x6C = 13.5ns - DDR3-1333 +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x6E = 13.5ns - DDR3-1333 +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x30 = 6ns +# 0x38 = 7.0ns +# 0x3C = 7.5ns +30 + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x6C = 13.5ns - +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x120 = 36ns - DDR3-1333 (see byte 21) +# 0x120 = 36ns - DDR3 +20 + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x28C = 49.5ns - DDR3-1333 +# 0x289 = 49.125ns - DDR3-1333 +89 + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x500 = 160ns - for 2 Gigabit chips +# 0x820 = 260ns - for 4 Gigabit chips +20 08 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x00F0 = 30ns - DDR3-1333, 1 KB page size +00 F0 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 1 = DLL Off mode supported +83 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 1 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +01 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 0 = Signal Loading not specified +# bits[3:2]: reserved +# bits[6:4]: 0 = Die count not specified +# bit7 : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +00 +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +00 +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +00 +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +00 +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 + +# 39 40 (reserved) +00 00 + +# 41 tMAW, MAC +# 8K*tREFI / 200k +86 + +# 42 - 47 (reserved) +00 00 00 00 00 00 + +# 48 - 55 (reserved) +00 00 00 00 00 00 00 00 + +# 56 - 59 (reserved) +00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +00 + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +00 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +# revision B4 +61 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 71 (reserved) +00 00 00 00 00 00 00 00 + +# 72 - 79 (reserved) +00 00 00 00 00 00 00 00 + +# 80 - 87 (reserved) +00 00 00 00 00 00 00 00 + +# 88 - 95 (reserved) +00 00 00 00 00 00 00 00 + +# 96 - 103 (reserved) +00 00 00 00 00 00 00 00 + +# 104 - 111 (reserved) +00 00 00 00 00 00 00 00 + +# 112 - 116 (reserved) +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x0001 = AMD +00 01 + +# 119 Module ID: Module Manufacturing Location - oem specified +00 + +# 120 Module ID: Module Manufacture Year in BCD +# 0x15 = 2015 +# 121 Module ID: Module Manufacture week +# 0x44 = 44th week +15 44 + +# 122 - 125: Module Serial Number +00 00 00 00 + +# 126 - 127: Cyclical Redundancy Code +67 94 + + + + diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig new file mode 100644 index 0000000..f09a220 --- /dev/null +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -0,0 +1,91 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2015 Kyösti Mälkki <kyosti.malkki(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_PCENGINES_APU2 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_PI_00730F01 + select NORTHBRIDGE_AMD_PI_00730F01 + select SOUTHBRIDGE_AMD_PI_AVALON + select SUPERIO_NUVOTON_NCT5104D + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_8192 + select SPD_CACHE + select HUDSON_DISABLE_IMC + select USE_BLOBS + +config MAINBOARD_DIR + string + default pcengines/apu2 + +config MAINBOARD_PART_NUMBER + string + default "PCEngines apu2" + +config MAX_CPUS + int + default 4 + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config HUDSON_LEGACY_FREE + bool + default y + +config AGESA_BINARY_PI_FILE + string + default "3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin" + +choice + prompt "J19 pins 1-10" + default APU2_PINMUX_OFF_C + +config APU2_PINMUX_OFF_C + bool "disable" + +config APU2_PINMUX_GPIO0 + bool "GPIO" + +config APU2_PINMUX_UART_C + bool "UART 0x3e8" + +endchoice + +choice + prompt "J19 pins 11-20" + default APU2_PINMUX_OFF_D + +config APU2_PINMUX_OFF_D + bool "disable" + +config APU2_PINMUX_GPIO1 + bool "GPIO" + +config APU2_PINMUX_UART_D + bool "UART 0x2e8" + +endchoice + +endif # BOARD_PCENGINES_APU2 diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name new file mode 100644 index 0000000..ab19ee4 --- /dev/null +++ b/src/mainboard/pcengines/apu2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_PCENGINES_APU2 + bool "APU2" diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc new file mode 100644 index 0000000..5fae195 --- /dev/null +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -0,0 +1,40 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c + +## DIMM SPD for on-board memory +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = HYNIX-2G-1333 HYNIX-4G-1333-ECC + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c new file mode 100644 index 0000000..06a8f3d --- /dev/null +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/amd/pi/agesawrapper.h> + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +static const PCIe_PORT_DESCRIPTOR PortList [] = { + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x01, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x05, 0) + } +}; + +static const PCIe_DDI_DESCRIPTOR DdiList [] = { + /* DP0 to HDMI0/DP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + }, + /* DP1 to FCH */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + }, + /* DP2 to HDMI1/DP */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; +} diff --git a/src/mainboard/pcengines/apu2/acpi/AmdImc.asl b/src/mainboard/pcengines/apu2/acpi/AmdImc.asl new file mode 100644 index 0000000..d3bb74e --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/AmdImc.asl @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Store(0, Local0) + While (LNotEqual(Local0, 0xFA)) { + Store(MRG0, Local0) + Sleep(10) + } +} + +//Init +Method (ITZE, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(1, MRG1) + Store(0, MRG2) + Store(0x98, MSTI) + WACK() + + Store(0, MRG0) + Store(0xB4, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() +} + +//Wake +Method (IMWK, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} diff --git a/src/mainboard/pcengines/apu2/acpi/gpe.asl b/src/mainboard/pcengines/apu2/acpi/gpe.asl new file mode 100644 index 0000000..cd366dc --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/gpe.asl @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/pcengines/apu2/acpi/ide.asl b/src/mainboard/pcengines/apu2/acpi/ide.asl new file mode 100644 index 0000000..4a3eac8 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/ide.asl @@ -0,0 +1,2 @@ +/* No license required */ +/* No IDE functionality */ diff --git a/src/mainboard/pcengines/apu2/acpi/mainboard.asl b/src/mainboard/pcengines/apu2/acpi/mainboard.asl new file mode 100644 index 0000000..0141481 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/mainboard.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +/* AcpiGpe0Blk */ +OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, +} diff --git a/src/mainboard/pcengines/apu2/acpi/routing.asl b/src/mainboard/pcengines/apu2/acpi/routing.asl new file mode 100644 index 0000000..7cb7a2f --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/routing.asl @@ -0,0 +1,193 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F16 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 44 }, + Package(){0x0001FFFF, 1, 0, 45 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 24 }, + Package(){0x0002FFFF, 1, 0, 25 }, + Package(){0x0002FFFF, 2, 0, 26 }, + Package(){0x0002FFFF, 3, 0, 27 }, + + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + +}) + +Name(PS2, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS2, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GFX */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, +}) + +/* GPP 0 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 28 }, + Package(){0x0000FFFF, 1, 0, 29 }, + Package(){0x0000FFFF, 2, 0, 30 }, + Package(){0x0000FFFF, 3, 0, 31 }, +}) + +/* GPP 1 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, +}) + +/* GPP 2 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, +}) + +/* GPP 3 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) diff --git a/src/mainboard/pcengines/apu2/acpi/si.asl b/src/mainboard/pcengines/apu2/acpi/si.asl new file mode 100644 index 0000000..2923471 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/si.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ diff --git a/src/mainboard/pcengines/apu2/acpi/sleep.asl b/src/mainboard/pcengines/apu2/acpi/sleep.asl new file mode 100644 index 0000000..0734c8e --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/sleep.asl @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ + +External(\_SB.APTS, MethodObj) +External(\_SB.AWAK, MethodObj) + +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) + \_SB.APTS(Arg0) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* clear USB wake up signal */ + Store(1, USBS) + + \_SB.AWAK(Arg0) + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/pcengines/apu2/acpi/thermal.asl b/src/mainboard/pcengines/apu2/acpi/thermal.asl new file mode 100644 index 0000000..73077ac --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/thermal.asl @@ -0,0 +1,2 @@ +/* No license required */ +/* No thermal zone functionality */ diff --git a/src/mainboard/pcengines/apu2/acpi/usb_oc.asl b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl new file mode 100644 index 0000000..1643fe7 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c new file mode 100644 index 0000000..d5ebad4 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi_tables.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/amd/pi/agesawrapper.h> + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam16.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + /* TODO: Remove the hardcode */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, + 0xFEC20000, 24); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/pcengines/apu2/apu2.h b/src/mainboard/pcengines/apu2/apu2.h new file mode 100644 index 0000000..d2f04e3 --- /dev/null +++ b/src/mainboard/pcengines/apu2/apu2.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + + * + * Copyright (C) 2015 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <agesawrapper.h> + +#define APU2_SPD_STRAP0_GPIO 0x40 // GPIO49 +#define APU2_SPD_STRAP0_FUNC Function2 +#define APU2_SPD_STRAP1_GPIO 0x41 // GPIO50 +#define APU2_SPD_STRAP1_FUNC Function2 +#define APU2_PE3_RST_L_GPIO 0x42 // GPIO51 +#define APU2_PE3_RST_L_FUNC Function2 +#define APU2_PE4_RST_L_GPIO 0x43 // DEVSLP[0]/GPIO59 +#define APU2_PE4_RST_L_FUNC Function3 +#define APU2_LED1_L_GPIO 0x44 // GPIO57 +#define APU2_LED1_L_FUNC Function1 +#define APU2_LED2_L_GPIO 0x45 // GPIO58 +#define APU2_LED2_L_FUNC Function1 +#define APU2_LED3_L_GPIO 0x46 // DEVSLP[1]/GPIO59 +#define APU2_LED3_L_FUNC Function3 +#define APU2_PE3_WDIS_L_GPIO 0x47 // GPIO64 +#define APU2_PE3_WDIS_L_FUNC Function2 +#define APU2_PE4_WDIS_L_GPIO 0x48 // GPIO68 +#define APU2_PE4_WDIS_L_FUNC Function0 +#define APU2_SKR_GPIO 0x5B // SPKR/GPIO66 +#define APU2_SKR_FUNC Function0 +#define APU2_PROCHOT_GPIO 0x4D // GPIO71 +#define APU2_PROCHOT_FUNC Function0 +#define APU2_BIOS_CONSOLE_GPIO 0x59 // GENINT1_L/GPIO32 +#define APU2_BIOS_CONSOLE_FUNC Function0 + + + + + + + + + + + + diff --git a/src/mainboard/pcengines/apu2/board_info.txt b/src/mainboard/pcengines/apu2/board_info.txt new file mode 100644 index 0000000..a69e616 --- /dev/null +++ b/src/mainboard/pcengines/apu2/board_info.txt @@ -0,0 +1,6 @@ +Board name: PC Engines APU2 +Board URL: http://www.pcengines.ch/apu2c2.htm +Category: half +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/pcengines/apu2/cmos.layout b/src/mainboard/pcengines/apu2/cmos.layout new file mode 100644 index 0000000..d83bb14 --- /dev/null +++ b/src/mainboard/pcengines/apu2/cmos.layout @@ -0,0 +1,74 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb new file mode 100644 index 0000000..3c5ec81 --- /dev/null +++ b/src/mainboard/pcengines/apu2/devicetree.cb @@ -0,0 +1,91 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/pi/00730F01/root_complex + device cpu_cluster 0 on + chip cpu/amd/pi/00730F01 + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00730F01 # CPU side of HT root complex + + chip northbridge/amd/pi/00730F01 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU + device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 off end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.2 on end # LAN3 + device pci 2.3 on end # LAN2 + device pci 2.4 on end # LAN1 + device pci 2.5 on end # mPCIe slot 1 + device pci 8.0 on end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 + + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 + device pci 11.0 on end # SATA + device pci 12.0 off end # USB EHCI0 usb[0:3] not connected + device pci 13.0 on end # USB EHCI1 usb[4:7] + device pci 14.0 on end # SM + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d # SIO NCT5104D + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 on + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 on + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 on end + device pnp 2e.107 on end + device pnp 2e.607 off end + device pnp 2e.e off end + end # SIO NCT5104D + end # LPC 0x439d + + device pci 14.7 on end # SD + device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end #chip southbridge/amd/pi/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex + end #domain +end #northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl new file mode 100644 index 0000000..45ae428 --- /dev/null +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/pi/00730F01/acpi/cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c new file mode 100644 index 0000000..eaeed3f --- /dev/null +++ b/src/mainboard/pcengines/apu2/irq_tables.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam16.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdee8, 0x2, 0xdee8, 0x3, 0xdee8, 0x4, 0xdee8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c new file mode 100644 index 0000000..98fe8dd --- /dev/null +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/io.h> +#include <console/console.h> +#include <cpu/amd/pi/s3_resume.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <northbridge/amd/pi/BiosCallOuts.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <southbridge/amd/pi/hudson/pci_devs.h> +#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> +#include <northbridge/amd/pi/00730F01/pci_devs.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> + +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +#define SPD_SIZE 128 +#define PM_RTC_CONTROL 0x56 +#define PM_S_STATE_CONTROL 0xBA + + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { +#if defined(__GNUC__) + [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F, +#endif + /* INTA# - INTH# */ + [0x00] = 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */ + [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, + [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* USB Devs 18/19/22 INTA-C */ + [0x30] = 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F, + [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* SATA */ + [0x40] = 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, + [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x60] = 0x00,0x00,0x1F +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { +#if defined(__GNUC__) + [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F, +#endif + /* INTA# - INTH# */ + [0x00] = 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */ + [0x10] = 0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10, + [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* IMC INT0 - 5 */ + [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, + [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00, + [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* SATA */ + [0x40] = 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00, + [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x60] = 0x00,0x00,0x1F +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ + {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ + {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/* Wrapper to enable GPIO/UART devices under menuconfig. Revisit + * once configuration file format for SPI flash storage is complete. + */ +#define SIO_PORT 0x2e + +static void config_gpio_mux(void) +{ + struct device *uart, *gpio; + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); + gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0); + if (uart) + uart->enabled = CONFIG_APU2_PINMUX_UART_C; + if (gpio) + gpio->enabled = CONFIG_APU2_PINMUX_GPIO0; + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); + gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1); + if (uart) + uart->enabled = CONFIG_APU2_PINMUX_UART_D; + if (gpio) + gpio->enabled = CONFIG_APU2_PINMUX_GPIO1; +} + +/********************************************** + * enable the dedicated function in mainboard. + **********************************************/ + +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + config_gpio_mux(); + + // + // Enable the RTC output + // + pm_write16 ( PM_RTC_CONTROL, pm_read16( PM_RTC_CONTROL ) | (1 << 11)); + + // + // Enable power on from WAKE# + // + pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14)); + + if (acpi_is_wakeup_s3()) + agesawrapper_fchs3earlyrestore(); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + + diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c new file mode 100644 index 0000000..896e637 --- /dev/null +++ b/src/mainboard/pcengines/apu2/mptable.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam15.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/common/amd_pci_util.h> + +#if 0 +u8 picr_data[FCH_INT_TABLE_SIZE] = { + 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/ + 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */ + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* 10 - 17 */ + 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */ + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */ + 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F, /* 30 - 37 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */ + 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */ +// 0x03,0x04,0x05,0x07,0x00,0x00,0x00,0x00, /* 50 - 57 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */ + 0x00,0x00,0x1F /* 60 - 62 */ +}; +u8 intr_data[FCH_INT_TABLE_SIZE] = { + 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/ + 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */ + 0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10, /* 10 - 17 */ + 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */ + 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */ + 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00, /* 30 - 37 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */ + 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */ +// 0x10,0x11,0x12,0x13,0x00,0x00,0x00,0x00, /* 50 - 57 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */ + 0x00,0x00,0x1F /* 60 - 62 */ +}; + +#endif + + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* Intialize the MP_Table */ + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ + smp_write_processors(mc); + + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ + + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* SD card */ + PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + + /* on board NIC & Slot PCIE */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); + + + /* GPP0 */ + PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3 + /* GPP1 */ + PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2 + /* GPP2 */ + PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1 + /* GPP3 */ + PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI + /* GPP4 */ + PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c new file mode 100644 index 0000000..c64fe4e --- /dev/null +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <commonlib/loglevel.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <cpu/amd/pi/s3_resume.h> + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + amd_initmmio(); + + hudson_lpc_port80(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + + post_code(0x31); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x37); + AGESAWRAPPER(amdinitreset); + + post_code(0x38); + printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); + + post_code(0x39); + AGESAWRAPPER(amdinitearly); + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + //PspMboxBiosCmdDramInfo(); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + AGESAWRAPPER(amdinitresume); + + AGESAWRAPPER(amds3laterestore); + + post_code(0x61); + prepare_for_resume(); + } + + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +}

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Patch merged into coreboot/master: mb/asus/[kgpe-d16|kcma-d8]: Fix whitespace errors in devicetree.cb
by gerrit＠coreboot.org 21 Aug '16

21 Aug '16

the following patch was just integrated into master: commit 64444268e2eecf235af9dd77b5f6cee8c0365fc5 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Fri Aug 19 17:26:51 2016 -0500 mb/asus/[kgpe-d16|kcma-d8]: Fix whitespace errors in devicetree.cb Change-Id: I49925040d951dffb9c11425334674d8d498821f0 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> Reviewed-on: https://review.coreboot.org/16268 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker See https://review.coreboot.org/16268 for details. -gerrit

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New patch to review for coreboot: src/southbridge: indent using tabs
by HAOUAS Elyes 21 Aug '16

21 Aug '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16291 -gerrit commit 3aa2ce029223851f1ff6eee73920a238285e003b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 19:14:31 2016 +0200 src/southbridge: indent using tabs Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/amd8111/early_ctrl.c | 40 ++--- src/southbridge/amd/amd8111/ide.c | 4 +- src/southbridge/amd/amd8111/reset.c | 20 +-- src/southbridge/amd/amd8131/bridge.c | 54 +++--- src/southbridge/amd/amd8132/bridge.c | 150 ++++++++-------- src/southbridge/amd/amd8151/agp3.c | 2 +- src/southbridge/amd/cimx/sb800/Amd.h | 2 +- src/southbridge/amd/cimx/sb800/early.c | 4 +- src/southbridge/amd/cimx/sb800/late.c | 54 +++--- src/southbridge/amd/cimx/sb800/smbus.c | 8 +- src/southbridge/amd/cimx/sb900/Amd.h | 2 +- src/southbridge/amd/cimx/sb900/cfg.c | 4 +- src/southbridge/amd/cimx/sb900/late.c | 98 +++++----- src/southbridge/amd/cimx/sb900/smbus.c | 8 +- src/southbridge/amd/cs5535/cs5535.c | 10 +- src/southbridge/amd/rs690/gfx.c | 62 +++---- src/southbridge/amd/rs690/pcie.c | 2 +- src/southbridge/amd/rs780/rs780.h | 2 +- src/southbridge/amd/sb700/sm.c | 4 +- src/southbridge/amd/sr5650/early_setup.c | 32 ++-- src/southbridge/amd/sr5650/sr5650.c | 4 +- src/southbridge/broadcom/bcm21000/pcie.c | 2 +- src/southbridge/broadcom/bcm5780/nic.c | 12 +- src/southbridge/broadcom/bcm5780/pcie.c | 16 +- src/southbridge/broadcom/bcm5780/pcix.c | 20 +-- src/southbridge/broadcom/bcm5785/bcm5785.c | 12 +- src/southbridge/broadcom/bcm5785/chip.h | 8 +- src/southbridge/broadcom/bcm5785/early_setup.c | 236 ++++++++++++------------- src/southbridge/broadcom/bcm5785/early_smbus.c | 8 +- src/southbridge/broadcom/bcm5785/ide.c | 16 +- src/southbridge/broadcom/bcm5785/lpc.c | 20 +-- src/southbridge/broadcom/bcm5785/reset.c | 24 +-- src/southbridge/broadcom/bcm5785/sata.c | 22 +-- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 96 +++++----- src/southbridge/broadcom/bcm5785/smbus.h | 106 +++++------ src/southbridge/broadcom/bcm5785/usb.c | 8 +- src/southbridge/intel/bd82x6x/me.c | 2 +- src/southbridge/intel/bd82x6x/pch.h | 4 +- src/southbridge/intel/bd82x6x/reset.c | 4 +- src/southbridge/intel/bd82x6x/smihandler.c | 62 +++---- src/southbridge/intel/fsp_bd82x6x/me.c | 2 +- src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 4 +- src/southbridge/intel/fsp_bd82x6x/pch.h | 4 +- src/southbridge/intel/fsp_bd82x6x/reset.c | 4 +- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 62 +++---- src/southbridge/intel/fsp_i89xx/me.c | 2 +- src/southbridge/intel/fsp_i89xx/me_8.x.c | 2 +- src/southbridge/intel/fsp_i89xx/pch.h | 2 +- src/southbridge/intel/fsp_i89xx/smihandler.c | 62 +++---- src/southbridge/intel/fsp_rangeley/lpc.c | 2 +- src/southbridge/intel/fsp_rangeley/sata.c | 4 +- src/southbridge/intel/fsp_rangeley/soc.h | 4 +- src/southbridge/intel/i3100/early_smbus.c | 2 +- src/southbridge/intel/i3100/lpc.c | 28 +-- src/southbridge/intel/i82801dx/smihandler.c | 62 +++---- src/southbridge/intel/i82801ex/lpc.c | 6 +- src/southbridge/intel/i82801ex/reset.c | 4 +- src/southbridge/intel/i82801ex/watchdog.c | 34 ++-- src/southbridge/intel/i82801gx/bootblock.c | 16 +- src/southbridge/intel/i82801gx/reset.c | 6 +- src/southbridge/intel/i82801gx/smihandler.c | 62 +++---- src/southbridge/intel/i82801ix/bootblock.c | 16 +- src/southbridge/intel/i82870/ioapic.c | 30 ++-- src/southbridge/intel/i82870/pci_parity.c | 24 +-- src/southbridge/intel/i82870/pcibridge.c | 16 +- src/southbridge/intel/ibexpeak/pch.h | 4 +- src/southbridge/intel/ibexpeak/sata.c | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 62 +++---- src/southbridge/intel/lynxpoint/early_pch.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 2 +- src/southbridge/intel/lynxpoint/me_9.x.c | 4 +- src/southbridge/intel/lynxpoint/pch.h | 4 +- src/southbridge/intel/lynxpoint/reset.c | 4 +- src/southbridge/intel/lynxpoint/smihandler.c | 62 +++---- src/southbridge/nvidia/ck804/early_setup_car.c | 4 +- src/southbridge/sis/sis966/aza.c | 60 +++---- src/southbridge/sis/sis966/early_smbus.c | 90 +++++----- src/southbridge/sis/sis966/ide.c | 32 ++-- src/southbridge/sis/sis966/lpc.c | 54 +++--- src/southbridge/sis/sis966/nic.c | 124 ++++++------- src/southbridge/sis/sis966/sata.c | 36 ++-- src/southbridge/sis/sis966/usb.c | 26 +-- src/southbridge/sis/sis966/usb2.c | 62 +++---- src/southbridge/via/vt8237r/lpc.c | 4 +- 84 files changed, 1171 insertions(+), 1171 deletions(-) diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index ece99ed..d84ef18 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -4,16 +4,16 @@ /* by yhlu 2005.10 */ static unsigned get_sbdn(unsigned bus) { - device_t dev; + device_t dev; - /* Find the device. - * There can only be one 8111 on a hypertransport chain/bus. - */ - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI), - bus); + /* Find the device. + * There can only be one 8111 on a hypertransport chain/bus. + */ + dev = pci_locate_device_on_bus( + PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI), + bus); - return (dev>>15) & 0x1f; + return (dev>>15) & 0x1f; } @@ -40,34 +40,34 @@ static void enable_cf9(void) void hard_reset(void) { - set_bios_reset(); - /* reset */ - enable_cf9(); - outb(0x0e, 0x0cf9); // make sure cf9 is enabled + set_bios_reset(); + /* reset */ + enable_cf9(); + outb(0x0e, 0x0cf9); // make sure cf9 is enabled } void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { - device_t dev; + device_t dev; dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI - pci_write_config8(dev, 0x74, 4); + pci_write_config8(dev, 0x74, 4); - /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ - pci_write_config32(dev, 0x70, 2<<12); + /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ + pci_write_config32(dev, 0x70, 2<<12); } static void soft_reset_x(unsigned sbbusn, unsigned sbdn) { - device_t dev; + device_t dev; dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA - /* Reset */ - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); + /* Reset */ + set_bios_reset(); + pci_write_config8(dev, 0x47, 1); } diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c index ef0cee1..a7eee35 100644 --- a/src/southbridge/amd/amd8111/ide.c +++ b/src/southbridge/amd/amd8111/ide.c @@ -33,8 +33,8 @@ static void ide_init(struct device *dev) pci_write_config16(dev, 0x40, word); - byte = 0x20 ; // Latency: 64-->32 - pci_write_config8(dev, 0xd, byte); + byte = 0x20 ; // Latency: 64-->32 + pci_write_config8(dev, 0xd, byte); word = 0x0f; pci_write_config16(dev, 0x42, word); diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index 8824550..c133c36 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -12,26 +12,26 @@ static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value) { - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); } static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); } static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); } #define PCI_DEV_INVALID (0xffffffffU) diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c index 1587268..6b0a03c 100644 --- a/src/southbridge/amd/amd8131/bridge.c +++ b/src/southbridge/amd/amd8131/bridge.c @@ -280,52 +280,52 @@ static void amd8131_pcix_init(device_t dev) /* Enable memory write and invalidate ??? */ byte = pci_read_config8(dev, 0x04); - byte |= 0x10; - pci_write_config8(dev, 0x04, byte); + byte |= 0x10; + pci_write_config8(dev, 0x04, byte); /* Set drive strength */ word = pci_read_config16(dev, 0xe0); - word = 0x0404; - pci_write_config16(dev, 0xe0, word); + word = 0x0404; + pci_write_config16(dev, 0xe0, word); word = pci_read_config16(dev, 0xe4); - word = 0x0404; - pci_write_config16(dev, 0xe4, word); + word = 0x0404; + pci_write_config16(dev, 0xe4, word); /* Set impedance */ word = pci_read_config16(dev, 0xe8); - word = 0x0404; - pci_write_config16(dev, 0xe8, word); + word = 0x0404; + pci_write_config16(dev, 0xe8, word); /* Set discard unrequested prefetch data */ /* Errata #51 */ word = pci_read_config16(dev, 0x4c); - word |= 1; - pci_write_config16(dev, 0x4c, word); + word |= 1; + pci_write_config16(dev, 0x4c, word); /* Set split transaction limits */ word = pci_read_config16(dev, 0xa8); - pci_write_config16(dev, 0xaa, word); + pci_write_config16(dev, 0xaa, word); word = pci_read_config16(dev, 0xac); - pci_write_config16(dev, 0xae, word); + pci_write_config16(dev, 0xae, word); /* Set up error reporting, enable all */ /* system error enable */ dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); - pci_write_config32(dev, 0x04, dword); + dword |= (1<<8); + pci_write_config32(dev, 0x04, dword); /* system and error parity enable */ dword = pci_read_config32(dev, 0x3c); - dword |= (3<<16); - pci_write_config32(dev, 0x3c, dword); + dword |= (3<<16); + pci_write_config32(dev, 0x3c, dword); /* NMI enable */ nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if(nmi_option) { dword = pci_read_config32(dev, 0x44); - dword |= (1<<0); - pci_write_config32(dev, 0x44, dword); + dword |= (1<<0); + pci_write_config32(dev, 0x44, dword); } /* Set up CRC flood enable */ @@ -377,22 +377,22 @@ static void bridge_set_resources(struct device *dev) static struct device_operations pcix_ops = { #if BRIDGE_40_BIT_SUPPORT - .read_resources = bridge_read_resources, - .set_resources = bridge_set_resources, + .read_resources = bridge_read_resources, + .set_resources = bridge_set_resources, #else - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, #endif .enable_resources = pci_bus_enable_resources, - .init = amd8131_pcix_init, - .scan_bus = amd8131_scan_bridge, + .init = amd8131_pcix_init, + .scan_bus = amd8131_scan_bridge, .reset_bus = pci_bus_reset, }; static const struct pci_driver pcix_driver __pci_driver = { - .ops = &pcix_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7450, + .ops = &pcix_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x7450, }; diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index ee45c65..6a7cab2 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -126,11 +126,11 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr) cmd |= max_tran << 4; } - /* Don't attempt to handle PCI-X errors */ - cmd &= ~PCI_X_CMD_DPERR_E; - if (orig_cmd != cmd) { - pci_write_config16(dev, cap + PCI_X_CMD, cmd); - } + /* Don't attempt to handle PCI-X errors */ + cmd &= ~PCI_X_CMD_DPERR_E; + if (orig_cmd != cmd) { + pci_write_config16(dev, cap + PCI_X_CMD, cmd); + } } @@ -203,13 +203,13 @@ static void amd8132_pcix_init(device_t dev) unsigned chip_rev; /* Find the revision of the 8132 */ - chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); + chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); /* Enable memory write and invalidate ??? */ dword = pci_read_config32(dev, 0x04); - dword |= 0x10; + dword |= 0x10; dword &= ~(1<<6); // PERSP Parity Error Response - pci_write_config32(dev, 0x04, dword); + pci_write_config32(dev, 0x04, dword); if (chip_rev == 0x01) { /* Errata #37 */ @@ -229,54 +229,54 @@ static void amd8132_pcix_init(device_t dev) /* Set up error reporting, enable all */ /* system error enable */ dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); - pci_write_config32(dev, 0x04, dword); + dword |= (1<<8); + pci_write_config32(dev, 0x04, dword); /* system and error parity enable */ dword = pci_read_config32(dev, 0x3c); - dword |= (3<<16); - pci_write_config32(dev, 0x3c, dword); + dword |= (3<<16); + pci_write_config32(dev, 0x3c, dword); - dword = pci_read_config32(dev, 0x40); -// dword &= ~(1<<31); /* WriteChainEnable */ + dword = pci_read_config32(dev, 0x40); +// dword &= ~(1<<31); /* WriteChainEnable */ dword |= (1<<31); dword |= (1<<7);// must set to 1 dword |= (3<<21); //PCIErrorSerrDisable - pci_write_config32(dev, 0x40, dword); + pci_write_config32(dev, 0x40, dword); - /* EXTARB = 1, COMPAT = 0 */ - dword = pci_read_config32(dev, 0x48); - dword |= (1<<3); + /* EXTARB = 1, COMPAT = 0 */ + dword = pci_read_config32(dev, 0x48); + dword |= (1<<3); dword &= ~(1<<0); dword |= (1<<15); //CLEARPCILOG_L dword |= (1<<19); //PERR FATAL Enable dword |= (1<<22); // SERR FATAL Enable dword |= (1<<23); // LPMARBENABLE dword |= (0x61<<24); //LPMARBCOUNT - pci_write_config32(dev, 0x48, dword); + pci_write_config32(dev, 0x48, dword); - dword = pci_read_config32(dev, 0x4c); - dword |= (1<<6); //Initial prefetch for memory read line request + dword = pci_read_config32(dev, 0x4c); + dword |= (1<<6); //Initial prefetch for memory read line request dword |= (1<<9); //continuous prefetch Enable for memory read line request - pci_write_config32(dev, 0x4c, dword); + pci_write_config32(dev, 0x4c, dword); - /* Disable Single-Bit-Error Correction [30] = 0 */ - dword = pci_read_config32(dev, 0x70); - dword &= ~(1<<30); - pci_write_config32(dev, 0x70, dword); + /* Disable Single-Bit-Error Correction [30] = 0 */ + dword = pci_read_config32(dev, 0x70); + dword &= ~(1<<30); + pci_write_config32(dev, 0x70, dword); //link - dword = pci_read_config32(dev, 0xd4); - dword |= (0x5c<<16); - pci_write_config32(dev, 0xd4, dword); + dword = pci_read_config32(dev, 0xd4); + dword |= (0x5c<<16); + pci_write_config32(dev, 0xd4, dword); - /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */ - dword = pci_read_config32(dev, 0xdc); + /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */ + dword = pci_read_config32(dev, 0xdc); dword |= (1<<1) | (1<<4); // stream disable 1 to 0 , DBLINSRATE - dword |= (1<<18)|(1<<26); - dword &= ~((3<<16)|(3<<24)); - pci_write_config32(dev, 0xdc, dword); + dword |= (1<<18)|(1<<26); + dword &= ~((3<<16)|(3<<24)); + pci_write_config32(dev, 0xdc, dword); /* Set up CRC flood enable */ dword = pci_read_config32(dev, 0xc0); @@ -290,12 +290,12 @@ static void amd8132_pcix_init(device_t dev) pci_write_config32(dev, 0xc8, dword); #endif - if (chip_rev == 0x11) { - /* [18] Clock Gate Enable = 1 */ - dword = pci_read_config32(dev, 0xf0); - dword |= 0x00040008; - pci_write_config32(dev, 0xf0, dword); - } + if (chip_rev == 0x11) { + /* [18] Clock Gate Enable = 1 */ + dword = pci_read_config32(dev, 0xf0); + dword |= 0x00040008; + pci_write_config32(dev, 0xf0, dword); + } } return; @@ -337,22 +337,22 @@ static void bridge_set_resources(struct device *dev) static struct device_operations pcix_ops = { #if BRIDGE_40_BIT_SUPPORT - .read_resources = bridge_read_resources, - .set_resources = bridge_set_resources, + .read_resources = bridge_read_resources, + .set_resources = bridge_set_resources, #else - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, #endif .enable_resources = pci_bus_enable_resources, - .init = amd8132_pcix_init, - .scan_bus = amd8132_scan_bridge, + .init = amd8132_pcix_init, + .scan_bus = amd8132_scan_bridge, .reset_bus = pci_bus_reset, }; static const struct pci_driver pcix_driver __pci_driver = { - .ops = &pcix_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7458, + .ops = &pcix_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x7458, }; static void ioapic_enable(device_t dev) @@ -369,39 +369,39 @@ static void ioapic_enable(device_t dev) } static void amd8132_ioapic_init(device_t dev) { - uint32_t dword; - unsigned chip_rev; + uint32_t dword; + unsigned chip_rev; - /* Find the revision of the 8132 */ - chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); + /* Find the revision of the 8132 */ + chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); - if (chip_rev == 0x01) { + if (chip_rev == 0x01) { #if 0 - /* Errata #43 */ - dword = pci_read_config32(dev, 0xc8); + /* Errata #43 */ + dword = pci_read_config32(dev, 0xc8); dword |= (0x3<<23); pci_write_config32(dev, 0xc8, dword); #endif - } - - - if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { - //for b1 b2 - /* Errata #73 */ - dword = pci_read_config32(dev, 0x80); - dword |= (0x1f<<5); - pci_write_config32(dev, 0x80, dword); - dword = pci_read_config32(dev, 0x88); - dword |= (0x1f<<5); - pci_write_config32(dev, 0x88, dword); - - /* Errata #74 */ - dword = pci_read_config32(dev, 0x7c); - dword &= ~(0x3<<30); - dword |= (0x01<<30); - pci_write_config32(dev, 0x7c, dword); - } + } + + + if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { + //for b1 b2 + /* Errata #73 */ + dword = pci_read_config32(dev, 0x80); + dword |= (0x1f<<5); + pci_write_config32(dev, 0x80, dword); + dword = pci_read_config32(dev, 0x88); + dword |= (0x1f<<5); + pci_write_config32(dev, 0x88, dword); + + /* Errata #74 */ + dword = pci_read_config32(dev, 0x7c); + dword &= ~(0x3<<30); + dword |= (0x01<<30); + pci_write_config32(dev, 0x7c, dword); + } } diff --git a/src/southbridge/amd/amd8151/agp3.c b/src/southbridge/amd/amd8151/agp3.c index 57699ff..18dd6d5 100644 --- a/src/southbridge/amd/amd8151/agp3.c +++ b/src/southbridge/amd/amd8151/agp3.c @@ -66,7 +66,7 @@ static void agp3dev_enable(device_t dev) } static struct pci_operations pci_ops_pci_dev = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations agp3dev_ops = { diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h index 42e2b3a..26d2f1e 100644 --- a/src/southbridge/amd/cimx/sb800/Amd.h +++ b/src/southbridge/amd/cimx/sb800/Amd.h @@ -143,7 +143,7 @@ typedef struct _AMD_MODULE_HEADER { #if 0 #define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \ - (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) + (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) #endif #define ILLEGAL_SBDFO 0xFFFFFFFF diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 2a10c0e..866353d 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -66,6 +66,6 @@ void sb800_clk_output_48Mhz(void) /* AcpiMMioDecodeEn */ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0); - *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ + *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ + *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ } diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 693190f..fa47a96 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -151,21 +151,21 @@ unsigned long acpi_fill_mcfg(unsigned long current) } static struct device_operations lpc_ops = { - .read_resources = lpc_read_resources, - .set_resources = lpc_set_resources, - .enable_resources = pci_dev_enable_resources, + .read_resources = lpc_read_resources, + .set_resources = lpc_set_resources, + .enable_resources = pci_dev_enable_resources, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif - .init = lpc_init, - .scan_bus = scan_lpc_bus, - .ops_pci = &lops_pci, + .init = lpc_init, + .scan_bus = scan_lpc_bus, + .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_LPC, + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_LPC, }; static struct device_operations sata_ops = { @@ -226,34 +226,34 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = { static struct device_operations azalia_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver azalia_driver __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_HDA, + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_HDA, }; static struct device_operations gec_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver gec_driver __pci_driver = { - .ops = &gec_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_GEC, + .ops = &gec_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_GEC, }; /** diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index 93ac0aa..80395f1 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -63,7 +63,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n"); return -2; /* not ready */ } @@ -93,7 +93,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n"); return -2; /* not ready */ } @@ -123,7 +123,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n"); return -2; /* not ready */ } @@ -156,7 +156,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n"); return -2; /* not ready */ } diff --git a/src/southbridge/amd/cimx/sb900/Amd.h b/src/southbridge/amd/cimx/sb900/Amd.h index ec81400..1583c6f 100644 --- a/src/southbridge/amd/cimx/sb900/Amd.h +++ b/src/southbridge/amd/cimx/sb900/Amd.h @@ -143,7 +143,7 @@ typedef struct _AMD_MODULE_HEADER { #if 0 #define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \ - (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) + (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) #endif #define ILLEGAL_SBDFO 0xFFFFFFFF diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index be54197..bc7e742 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -28,7 +28,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) { if (!sb_config) { - printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n"); + printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n"); return; } printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n"); @@ -257,7 +257,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) void SbPowerOnInit_Config(AMDSBCFG *sb_config) { if (!sb_config) { - printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n"); + printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n"); return; } printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n"); diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index f078c51..65c2446 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -121,21 +121,21 @@ unsigned long acpi_fill_mcfg(unsigned long current) } static struct device_operations lpc_ops = { - .read_resources = lpc_read_resources, - .set_resources = lpc_set_resources, - .enable_resources = lpc_enable_resources, - .init = lpc_init, + .read_resources = lpc_read_resources, + .set_resources = lpc_set_resources, + .enable_resources = lpc_enable_resources, + .init = lpc_init, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif - .scan_bus = scan_lpc_bus, - .ops_pci = &lops_pci, + .scan_bus = scan_lpc_bus, + .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_LPC, + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_LPC, }; @@ -239,18 +239,18 @@ static void azalia_init(struct device *dev) } static struct device_operations azalia_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = azalia_init, - .scan_bus = 0, - .ops_pci = &lops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = azalia_init, + .scan_bus = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver azalia_driver __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_HDA, + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_HDA, }; @@ -263,18 +263,18 @@ static void gec_init(struct device *dev) } static struct device_operations gec_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = gec_init, - .scan_bus = 0, - .ops_pci = &lops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gec_init, + .scan_bus = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver gec_driver __pci_driver = { - .ops = &gec_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_GEC, + .ops = &gec_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_GEC, }; @@ -286,19 +286,19 @@ static void pcie_init(device_t dev) } static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, }; static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCI, + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCI, }; @@ -315,30 +315,30 @@ struct device_operations bridge_ops = { /* 0:15:0 PCIe PortA */ static const struct pci_driver PORTA_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCIEA, + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEA, }; /* 0:15:1 PCIe PortB */ static const struct pci_driver PORTB_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCIEB, + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEB, }; /* 0:15:2 PCIe PortC */ static const struct pci_driver PORTC_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCIEC, + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEC, }; /* 0:15:3 PCIe PortD */ static const struct pci_driver PORTD_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCIED, + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIED, }; diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c index 358bd48..7d11898 100644 --- a/src/southbridge/amd/cimx/sb900/smbus.c +++ b/src/southbridge/amd/cimx/sb900/smbus.c @@ -63,7 +63,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n"); + printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n"); return -2; /* not ready */ } @@ -93,7 +93,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n"); + printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n"); return -2; /* not ready */ } @@ -123,7 +123,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n"); + printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n"); return -2; /* not ready */ } @@ -156,7 +156,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n"); + printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n"); return -2; /* not ready */ } diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 70b8386..c1f1960 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -103,9 +103,9 @@ static const struct pci_driver cs5535_pci_driver __pci_driver = { }; struct chip_operations southbridge_amd_cs5535_ops = { - CHIP_NAME("AMD Geode CS5535 Southbridge") - /* This is only called when this device is listed in the - * static device tree. - */ - .enable_dev = southbridge_enable, + CHIP_NAME("AMD Geode CS5535 Southbridge") + /* This is only called when this device is listed in the + * static device tree. + */ + .enable_dev = southbridge_enable, }; diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/gfx.c index 57d6628..bcba435 100644 --- a/src/southbridge/amd/rs690/gfx.c +++ b/src/southbridge/amd/rs690/gfx.c @@ -461,48 +461,48 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) /* done by enable_pci_bar3() before */ /* step 6 SBIOS compile flags */ - if (cfg->gfx_tmds) { - /* step 6.2.2 Clock-Muxing Control */ - /* step 6.2.2.1 */ - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16); + if (cfg->gfx_tmds) { + /* step 6.2.2 Clock-Muxing Control */ + /* step 6.2.2.1 */ + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16); - /* step 6.2.2.2 */ - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8); - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10); + /* step 6.2.2.2 */ + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8); + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10); - /* step 6.2.2.3 */ - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26); + /* step 6.2.2.3 */ + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26); - /* step 6.2.3 Lane-Muxing Control */ - /* step 6.2.3.1 */ - set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8); + /* step 6.2.3 Lane-Muxing Control */ + /* step 6.2.3.1 */ + set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8); - /* step 6.2.4 Received Data Control */ - /* step 6.2.4.1 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16); + /* step 6.2.4 Received Data Control */ + /* step 6.2.4.1 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16); - /* step 6.2.4.2 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18); + /* step 6.2.4.2 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18); - /* step 6.2.4.3 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20); + /* step 6.2.4.3 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20); - /* step 6.2.4.4 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22); + /* step 6.2.4.4 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22); - /* step 6.2.5 PLL Power Down Control */ - /* step 6.2.5.1 */ - set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6); + /* step 6.2.5 PLL Power Down Control */ + /* step 6.2.5.1 */ + set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6); - /* step 6.2.6 Driving Strength Control */ - /* step 6.2.6.1 */ - set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24); + /* step 6.2.6 Driving Strength Control */ + /* step 6.2.6.1 */ + set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24); - /* step 6.2.6.2 */ - set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2); - } + /* step 6.2.6.2 */ + set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2); + } - printk(BIOS_INFO, "rs690_gfx_init step6.\n"); + printk(BIOS_INFO, "rs690_gfx_init step6.\n"); /* step 7 compliance state, (only need if CMOS option is enabled) */ /* the compliance state is just for test. refer to 4.2.5.2 of PCIe specification */ diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c index bcf4f4d..043c2ee 100644 --- a/src/southbridge/amd/rs690/pcie.c +++ b/src/southbridge/amd/rs690/pcie.c @@ -84,7 +84,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port) PCIE_GFX_COMPLIANCE))) { } - if (!cfg->gfx_tmds){ + if (!cfg->gfx_tmds){ /* step 3 Power Down Control for Southbridge */ reg = nbpcie_p_read_index(dev, 0xa2); diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index ffd0e15..dbd6651 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -101,7 +101,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 ULONG ulDockingPinCFGInfo; ULONG ulCPUCapInfo; USHORT usNumberOfCyclesInPeriod; //usNumberOfCyclesInPeriod[15] = 0 - invert waveform - // 1 - non inverted waveform + // 1 - non inverted waveform USHORT usMaxNBVoltage; USHORT usMinNBVoltage; USHORT usBootUpNBVoltage; diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 6d93b17..77dd6ca 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -278,7 +278,7 @@ static void sm_init(device_t dev) u16 word; /* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */ - axindxc_reg(0x02, 1 << 9, 1 << 9); + axindxc_reg(0x02, 1 << 9, 1 << 9); abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0); abcfg_reg(0x1009C, 0x00000030, 0x00000030); abcfg_reg(0x10090, 0x00001E00, 0x00001E00); @@ -287,7 +287,7 @@ static void sm_init(device_t dev) abcfg_reg(0x58, 0x0000F800, 0x0000E800); /* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */ - axindxc_reg(0x02, 1 << 10, 1 << 10); + axindxc_reg(0x02, 1 << 10, 1 << 10); /* rpr v2.13 2.38 Unconditional Shutdown */ byte = pci_read_config8(dev, 0x43); diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index a96b127..1c3b9fc 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -30,22 +30,22 @@ */ static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val) { - u32 tmp; - - /* read axindc to tmp */ - outl(space << 30 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(space << 30 | space << 3 | 0x34, AB_INDX); - tmp = inl(AB_DATA); - - tmp &= ~mask; - tmp |= val; - - /* write tmp */ - outl(space << 30 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(space << 30 | space << 3 | 0x34, AB_INDX); - outl(tmp, AB_DATA); + u32 tmp; + + /* read axindc to tmp */ + outl(space << 30 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(space << 30 | space << 3 | 0x34, AB_INDX); + tmp = inl(AB_DATA); + + tmp &= ~mask; + tmp |= val; + + /* write tmp */ + outl(space << 30 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(space << 30 | space << 3 | 0x34, AB_INDX); + outl(tmp, AB_DATA); } diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index d28adfc..87845c6 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -817,8 +817,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { - res = sr5650_retrieve_cpu_mmio_resource(); - if (res) + res = sr5650_retrieve_cpu_mmio_resource(); + if (res) mmconf_base = res->base; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); diff --git a/src/southbridge/broadcom/bcm21000/pcie.c b/src/southbridge/broadcom/bcm21000/pcie.c index ca9a225..ab52029 100644 --- a/src/southbridge/broadcom/bcm21000/pcie.c +++ b/src/southbridge/broadcom/bcm21000/pcie.c @@ -43,7 +43,7 @@ static void pcie_init(struct device *dev) } static struct pci_operations lops_pci = { - .set_subsystem = 0, + .set_subsystem = 0, }; static struct device_operations pcie_ops = { diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c index be23d68..d0ff9ca 100644 --- a/src/southbridge/broadcom/bcm5780/nic.c +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -23,12 +23,12 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations nic_ops = { @@ -47,7 +47,7 @@ static const struct pci_driver nic_driver __pci_driver = { }; static const struct pci_driver nic1_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_BROADCOM, - .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1, + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_BROADCOM, + .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1, }; diff --git a/src/southbridge/broadcom/bcm5780/pcie.c b/src/southbridge/broadcom/bcm5780/pcie.c index 6f8493e..2ed6102 100644 --- a/src/southbridge/broadcom/bcm5780/pcie.c +++ b/src/southbridge/broadcom/bcm5780/pcie.c @@ -35,17 +35,17 @@ static void pcie_init(struct device *dev) } static struct pci_operations lops_pci = { - .set_subsystem = 0, + .set_subsystem = 0, }; static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, }; diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c index 22dc771..8aa37a6 100644 --- a/src/southbridge/broadcom/bcm5780/pcix.c +++ b/src/southbridge/broadcom/bcm5780/pcix.c @@ -22,22 +22,22 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations ht_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = 0 , - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = 0 , + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, }; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 7e8d8c3..5fc97c3 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -36,13 +36,13 @@ void bcm5785_enable(device_t dev) sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn); // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; } else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && - (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X ) - { - unsigned devfn; - devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3); - sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn); + (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X ) + { + unsigned devfn; + devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3); + sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn); // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; - } + } else { // same bus unsigned devfn; devfn = (dev->path.pci.devfn) & ~7; diff --git a/src/southbridge/broadcom/bcm5785/chip.h b/src/southbridge/broadcom/bcm5785/chip.h index ac39fd1..2c65734 100644 --- a/src/southbridge/broadcom/bcm5785/chip.h +++ b/src/southbridge/broadcom/bcm5785/chip.h @@ -19,10 +19,10 @@ struct southbridge_broadcom_bcm5785_config { - unsigned int ide0_enable : 1; - unsigned int ide1_enable : 1; - unsigned int sata0_enable : 1; - unsigned int sata1_enable : 1; + unsigned int ide0_enable : 1; + unsigned int ide1_enable : 1; + unsigned int sata0_enable : 1; + unsigned int sata1_enable : 1; }; #endif /* BCM5785_CHIP_H */ diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index e29fab4..e8895fb 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -19,62 +19,62 @@ static void bcm5785_enable_lpc(void) { - uint8_t byte; - device_t dev; - - dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); - - /* LPC Control 0 */ - byte = pci_read_config8(dev, 0x44); - /* Serial 0 */ - byte |= (1<<6); - pci_write_config8(dev, 0x44, byte); - - /* LPC Control 4 */ - byte = pci_read_config8(dev, 0x48); - /* superio port 0x2e/4e enable */ - byte |=(1<<1)|(1<<0); - pci_write_config8(dev, 0x48, byte); + uint8_t byte; + device_t dev; + + dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); + + /* LPC Control 0 */ + byte = pci_read_config8(dev, 0x44); + /* Serial 0 */ + byte |= (1<<6); + pci_write_config8(dev, 0x44, byte); + + /* LPC Control 4 */ + byte = pci_read_config8(dev, 0x48); + /* superio port 0x2e/4e enable */ + byte |=(1<<1)|(1<<0); + pci_write_config8(dev, 0x48, byte); } static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; - uint32_t dword; - uint32_t dword_old; + device_t dev; + uint32_t dword; + uint32_t dword_old; - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); + dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - dword_old = pci_read_config32(dev, 0x4c); - dword = dword_old | (1<<4); //enable Timer Func - if(dword != dword_old ) { - pci_write_config32(dev, 0x4c, dword); - } + dword_old = pci_read_config32(dev, 0x4c); + dword = dword_old | (1<<4); //enable Timer Func + if(dword != dword_old ) { + pci_write_config32(dev, 0x4c, dword); + } - dword_old = pci_read_config32(dev, 0x6c); - dword = dword_old | (1<<9); //unhide Timer Func in pci space - if(dword != dword_old ) { - pci_write_config32(dev, 0x6c, dword); - } + dword_old = pci_read_config32(dev, 0x6c); + dword = dword_old | (1<<9); //unhide Timer Func in pci space + if(dword != dword_old ) { + pci_write_config32(dev, 0x6c, dword); + } - dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0); + dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0); - /* enable cf9 */ - pci_write_config8(dev, 0x40, (1<<2)); + /* enable cf9 */ + pci_write_config8(dev, 0x40, (1<<2)); } unsigned get_sbdn(unsigned bus) { - device_t dev; + device_t dev; - /* Find the device. - * There can only be one bcm5785 on a hypertransport chain/bus. - */ - dev = pci_locate_device_on_bus( - PCI_ID(0x1166, 0x0036), - bus); + /* Find the device. + * There can only be one bcm5785 on a hypertransport chain/bus. + */ + dev = pci_locate_device_on_bus( + PCI_ID(0x1166, 0x0036), + bus); - return (dev>>15) & 0x1f; + return (dev>>15) & 0x1f; } @@ -89,8 +89,8 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) // set port to 0x2060 outb(0x67, 0xcd6); outb(0x60, 0xcd7); - outb(0x68, 0xcd6); - outb(0x20, 0xcd7); + outb(0x68, 0xcd6); + outb(0x20, 0xcd7); outb(0x69, 0xcd6); outb(7, 0xcd7); @@ -107,113 +107,113 @@ void ldtstop_sb(void) void hard_reset(void) { - bcm5785_enable_wdt_port_cf9(); + bcm5785_enable_wdt_port_cf9(); - set_bios_reset(); + set_bios_reset(); - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); + /* full reset */ + outb(0x0a, 0x0cf9); + outb(0x0e, 0x0cf9); } void soft_reset(void) { - bcm5785_enable_wdt_port_cf9(); + bcm5785_enable_wdt_port_cf9(); - set_bios_reset(); + set_bios_reset(); #if 1 - /* link reset */ -// outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); + /* link reset */ +// outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); #endif } static void bcm5785_enable_msg(void) { - device_t dev; - uint32_t dword; - uint32_t dword_old; - uint8_t byte; - - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - - byte = pci_read_config8(dev, 0x42); - byte = (1<<1); //enable a20 - pci_write_config8(dev, 0x42, byte); - - dword_old = pci_read_config32(dev, 0x6c); - // bit 5: enable A20 Message - // bit 4: enable interrupt messages - // bit 3: enable reset init message - // bit 2: enable keyboard init message - // bit 1: enable upsteam messages - // bit 0: enable shutdowm message to init generation - dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor - if(dword != dword_old ) { - pci_write_config32(dev, 0x6c, dword); - } + device_t dev; + uint32_t dword; + uint32_t dword_old; + uint8_t byte; + + dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); + + byte = pci_read_config8(dev, 0x42); + byte = (1<<1); //enable a20 + pci_write_config8(dev, 0x42, byte); + + dword_old = pci_read_config32(dev, 0x6c); + // bit 5: enable A20 Message + // bit 4: enable interrupt messages + // bit 3: enable reset init message + // bit 2: enable keyboard init message + // bit 1: enable upsteam messages + // bit 0: enable shutdowm message to init generation + dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor + if(dword != dword_old ) { + pci_write_config32(dev, 0x6c, dword); + } } static void bcm5785_early_setup(void) { - uint8_t byte; - uint32_t dword; - device_t dev; + uint8_t byte; + uint32_t dword; + device_t dev; //F0 - // enable device on bcm5785 at first - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - dword = pci_read_config32(dev, 0x64); - dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable - dword |= (1<<8); // USB enable - dword |= /* (1<<27)|*/(1<<14); // IDE enable - pci_write_config32(dev, 0x64, dword); - - byte = pci_read_config8(dev, 0x84); - byte |= (1<<0); // SATA enable - pci_write_config8(dev, 0x84, byte); + // enable device on bcm5785 at first + dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); + dword = pci_read_config32(dev, 0x64); + dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable + dword |= (1<<8); // USB enable + dword |= /* (1<<27)|*/(1<<14); // IDE enable + pci_write_config32(dev, 0x64, dword); + + byte = pci_read_config8(dev, 0x84); + byte |= (1<<0); // SATA enable + pci_write_config8(dev, 0x84, byte); // WDT and cf9 for later in ramstage to call hard_reset - bcm5785_enable_wdt_port_cf9(); + bcm5785_enable_wdt_port_cf9(); - bcm5785_enable_msg(); + bcm5785_enable_msg(); // IDE related //F0 - byte = pci_read_config8(dev, 0x4e); - byte |= (1<<4); //enable IDE ext regs - pci_write_config8(dev, 0x4e, byte); + byte = pci_read_config8(dev, 0x4e); + byte |= (1<<4); //enable IDE ext regs + pci_write_config8(dev, 0x4e, byte); //F1 - dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0); - byte = pci_read_config8(dev, 0x48); - byte &= ~1; // disable pri channel - pci_write_config8(dev, 0x48, byte); - pci_write_config8(dev, 0xb0, 0x01); - pci_write_config8(dev, 0xb2, 0x02); - byte = pci_read_config8(dev, 0x06); - byte |= (1<<4); // so b0, b2 can not be changed from now - pci_write_config8(dev, 0x06, byte); - byte = pci_read_config8(dev, 0x49); - byte |= 1; // enable second channel - pci_write_config8(dev, 0x49, byte); + dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0); + byte = pci_read_config8(dev, 0x48); + byte &= ~1; // disable pri channel + pci_write_config8(dev, 0x48, byte); + pci_write_config8(dev, 0xb0, 0x01); + pci_write_config8(dev, 0xb2, 0x02); + byte = pci_read_config8(dev, 0x06); + byte |= (1<<4); // so b0, b2 can not be changed from now + pci_write_config8(dev, 0x06, byte); + byte = pci_read_config8(dev, 0x49); + byte |= 1; // enable second channel + pci_write_config8(dev, 0x49, byte); //F2 - dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); + dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); - byte = pci_read_config8(dev, 0x40); - byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable - pci_write_config8(dev, 0x40, byte); + byte = pci_read_config8(dev, 0x40); + byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable + pci_write_config8(dev, 0x40, byte); - pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end + pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end // USB related - pci_write_config8(dev, 0x90, 0x40); - pci_write_config8(dev, 0x92, 0x06); - pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register - pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func - pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func - pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func - pci_write_config8(dev, 0xb4, 0x40); + pci_write_config8(dev, 0x90, 0x40); + pci_write_config8(dev, 0x92, 0x06); + pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register + pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func + pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func + pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func + pci_write_config8(dev, 0xb4, 0x40); } diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 9d3d3e8..f37aed9 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -38,20 +38,20 @@ static void enable_smbus(void) static inline int smbus_recv_byte(unsigned device) { - return do_smbus_recv_byte(SMBUS_IO_BASE, device); + return do_smbus_recv_byte(SMBUS_IO_BASE, device); } static inline int smbus_send_byte(unsigned device, unsigned char val) { - return do_smbus_send_byte(SMBUS_IO_BASE, device, val); + return do_smbus_send_byte(SMBUS_IO_BASE, device, val); } static inline int smbus_read_byte(unsigned device, unsigned address) { - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val) { - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); + return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); } diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 868586c..a6bb204 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -23,13 +23,13 @@ static void bcm5785_ide_read_resources(device_t dev) { - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); - /* BAR */ - pci_get_resource(dev, 0x64); + /* BAR */ + pci_get_resource(dev, 0x64); - compact_resources(dev); + compact_resources(dev); } static void ide_init(struct device *dev) @@ -38,12 +38,12 @@ static void ide_init(struct device *dev) static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations ide_ops = { diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index f0d7416..6ac4c95 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -74,15 +74,15 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config8(dev, 0x44); for (link = dev->link_list; link; link = link->next) { - device_t child; - for (child = link->children; child; child = child->sibling) { + device_t child; + for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; for(res = child->resource_list; res; res = res->next) { unsigned long base, end; // don't need long long if(!(res->flags & IORESOURCE_IO)) continue; base = res->base; - end = resource_end(res); + end = resource_end(res); printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); switch(base) { case 0x60: //KBC @@ -103,8 +103,8 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) } } } - } - } + } + } pci_write_config32(dev, 0x44, reg); @@ -112,18 +112,18 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) static void bcm5785_lpc_enable_resources(device_t dev) { - pci_dev_enable_resources(dev); - bcm5785_lpc_enable_childrens_resources(dev); + pci_dev_enable_resources(dev); + bcm5785_lpc_enable_childrens_resources(dev); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations lpc_ops = { diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 7064b19..8140e01 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -18,24 +18,24 @@ #include <reset.h> #define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) + (((BUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x7) << 12)) static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); } static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); } #include "../../../northbridge/amd/amdk8/reset_test.c" @@ -43,7 +43,7 @@ static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) void hard_reset(void) { set_bios_reset(); - /* Try rebooting through port 0xcf9 */ + /* Try rebooting through port 0xcf9 */ /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c index 75f2d46..571c444 100644 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -28,27 +28,27 @@ static void sata_init(struct device *dev) uint8_t byte; u8 *mmio; - struct resource *res; - u8 *mmio_base; + struct resource *res; + u8 *mmio_base; int i; if(!(dev->path.pci.devfn & 7)) { // only set it in Func0 byte = pci_read_config8(dev, 0x78); byte |= (1<<7); - pci_write_config8(dev, 0x78, byte); + pci_write_config8(dev, 0x78, byte); res = find_resource(dev, 0x24); - mmio_base = res2mmio(res, 0, 3); + mmio_base = res2mmio(res, 0, 3); write32(mmio_base + 0x10f0, 0x40000001); write32(mmio_base + 0x8c, 0x00ff2007); - mdelay( 10 ); + mdelay( 10 ); write32(mmio_base + 0x8c, 0x78592009); - mdelay( 10 ); + mdelay( 10 ); write32(mmio_base + 0x8c, 0x00082004); - mdelay( 10 ); + mdelay( 10 ); write32(mmio_base + 0x8c, 0x00002004); - mdelay( 10 ); + mdelay( 10 ); //init PHY @@ -70,12 +70,12 @@ static void sata_init(struct device *dev) static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 1898ca6..6950f06 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -63,101 +63,101 @@ static void bcm5785_sb_read_resources(device_t dev) compact_resources(dev); - /* Add an extra subtractive resource for both memory and I/O */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* Add an extra subtractive resource for both memory and I/O */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } static int lsmbus_recv_byte(device_t dev) { - unsigned device; - struct resource *res; + unsigned device; + struct resource *res; struct bus *pbus; - device = dev->path.i2c.device; + device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); + res = find_resource(pbus->dev, 0x90); - return do_smbus_recv_byte(res->base, device); + return do_smbus_recv_byte(res->base, device); } static int lsmbus_send_byte(device_t dev, uint8_t val) { - unsigned device; - struct resource *res; - struct bus *pbus; + unsigned device; + struct resource *res; + struct bus *pbus; - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); + res = find_resource(pbus->dev, 0x90); - return do_smbus_send_byte(res->base, device, val); + return do_smbus_send_byte(res->base, device, val); } static int lsmbus_read_byte(device_t dev, uint8_t address) { - unsigned device; - struct resource *res; - struct bus *pbus; + unsigned device; + struct resource *res; + struct bus *pbus; - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); + res = find_resource(pbus->dev, 0x90); - return do_smbus_read_byte(res->base, device, address); + return do_smbus_read_byte(res->base, device, address); } static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) { - unsigned device; - struct resource *res; - struct bus *pbus; + unsigned device; + struct resource *res; + struct bus *pbus; - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); + res = find_resource(pbus->dev, 0x90); - return do_smbus_write_byte(res->base, device, address, val); + return do_smbus_write_byte(res->base, device, address, val); } static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, + .recv_byte = lsmbus_recv_byte, + .send_byte = lsmbus_send_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, }; static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x2c, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x2c, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations sb_ops = { - .read_resources = bcm5785_sb_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sb_init, - .scan_bus = scan_smbus, + .read_resources = bcm5785_sb_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sb_init, + .scan_bus = scan_smbus, // .enable = bcm5785_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, }; static const struct pci_driver sb_driver __pci_driver = { - .ops = &sb_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN, + .ops = &sb_ops, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN, }; diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h index bb43269..22545d2 100644 --- a/src/southbridge/broadcom/bcm5785/smbus.h +++ b/src/southbridge/broadcom/bcm5785/smbus.h @@ -81,54 +81,54 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { uint8_t byte; - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; // not ready + } - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; // Clear [4:2] + byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command + outb(byte, smbus_io_base + SMBHSTCTRL); - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; // timeout or error + } - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD); return byte; } static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) { - uint8_t byte; + uint8_t byte; - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; // not ready + } - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; // Clear [4:2] + byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command + outb(byte, smbus_io_base + SMBHSTCTRL); - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; // timeout or error + } - return 0; + return 0; } static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) @@ -142,8 +142,8 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); byte = inb(smbus_io_base + SMBHSTCTRL); byte &= 0xe3; // Clear [4:2] @@ -163,30 +163,30 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) { - uint8_t byte; + uint8_t byte; - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; // not ready + } - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); - /* output value */ - outb(val, smbus_io_base + SMBHSTDAT0); + /* output value */ + outb(val, smbus_io_base + SMBHSTDAT0); - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; // Clear [4:2] + byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command + outb(byte, smbus_io_base + SMBHSTCTRL); - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; // timeout or error + } - return 0; + return 0; } diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c index fa73b2f..9aa64df 100644 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -23,7 +23,7 @@ static void usb_init(struct device *dev) { - uint32_t dword; + uint32_t dword; dword = pci_read_config32(dev, 0x04); dword |= (1<<2)|(1<<1)|(1<<0); @@ -35,12 +35,12 @@ static void usb_init(struct device *dev) static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations usb_ops = { diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 83c99e0..23915c3 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -445,7 +445,7 @@ static int mkhi_get_fwcaps(void) print_cap("IntelR Power Sharing Technology (MPC)", cap.caps_sku.intel_mpc); print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); + print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); print_cap("IPV6", cap.caps_sku.ipv6); print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index f22fed5..a4866e7 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -289,7 +289,7 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) #define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) + RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) @@ -426,7 +426,7 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) + ((b) << DIR_IBR) | ((a) << DIR_IAR)) #define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */ diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c index daabbbc..804fb81 100644 --- a/src/southbridge/intel/bd82x6x/reset.c +++ b/src/southbridge/intel/bd82x6x/reset.c @@ -19,10 +19,10 @@ void soft_reset(void) { - outb(0x04, 0xcf9); + outb(0x04, 0xcf9); } void hard_reset(void) { - outb(0x06, 0xcf9); + outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index e4e5b81..4a0149f 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -271,37 +271,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } static void southbridge_gate_memory_reset_real(int offset, diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index 68a9ee5..a951f9f 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -444,7 +444,7 @@ static int mkhi_get_fwcaps(void) print_cap("IntelR Power Sharing Technology (MPC)", cap.caps_sku.intel_mpc); print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); + print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); print_cap("IPV6", cap.caps_sku.ipv6); print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index e29d86b..b7edd77 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -389,7 +389,7 @@ static int mkhi_get_fwcaps(mefwcaps_sku *cap) < 0) { printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); return -1; - } + } *cap = cap_msg.caps_sku; return 0; } @@ -413,7 +413,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); print_cap("IPV6", cap->ipv6); print_cap("KVM Remote Control (KVM)", cap->kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap->och); diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index 7fe40f7..0c34449 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -271,7 +271,7 @@ void display_fd_settings(void); #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) #define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) + RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) @@ -408,7 +408,7 @@ void display_fd_settings(void); #define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) + ((b) << DIR_IBR) | ((a) << DIR_IAR)) #define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */ diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c index c2e76d5..a2e8236 100644 --- a/src/southbridge/intel/fsp_bd82x6x/reset.c +++ b/src/southbridge/intel/fsp_bd82x6x/reset.c @@ -20,10 +20,10 @@ void soft_reset(void) { - outb(0x04, 0xcf9); + outb(0x04, 0xcf9); } void hard_reset(void) { - outb(0x06, 0xcf9); + outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 987d6d1..2eec026 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -235,37 +235,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } /* diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c index caf24e3..7ea42d4 100644 --- a/src/southbridge/intel/fsp_i89xx/me.c +++ b/src/southbridge/intel/fsp_i89xx/me.c @@ -444,7 +444,7 @@ static int mkhi_get_fwcaps(void) print_cap("IntelR Power Sharing Technology (MPC)", cap.caps_sku.intel_mpc); print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); + print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); print_cap("IPV6", cap.caps_sku.ipv6); print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c index 090d8d0..fc14020 100644 --- a/src/southbridge/intel/fsp_i89xx/me_8.x.c +++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c @@ -413,7 +413,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); print_cap("IPV6", cap->ipv6); print_cap("KVM Remote Control (KVM)", cap->kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap->och); diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h index 6d8b873..ed9a3b3 100644 --- a/src/southbridge/intel/fsp_i89xx/pch.h +++ b/src/southbridge/intel/fsp_i89xx/pch.h @@ -204,7 +204,7 @@ void early_pch_init(void); #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) #define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) + RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index e0d19d6..d8cbed2 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -235,37 +235,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } /* diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 3a144ea..8201a1d 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -465,7 +465,7 @@ static struct device_operations device_ops = { /* IDs for LPC device of Intel 89xx Series Chipset */ static const unsigned short pci_device_ids[] = { 0x1F38, 0x1F39, 0x1F3A, 0x1F3B, - 0 }; + 0 }; static const struct pci_driver soc_lpc __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index 4861f83..72a2a55 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -121,8 +121,8 @@ static struct device_operations sata_ops = { }; static const unsigned short pci_device_ids[] = { 0x1f20, 0x1f21, 0x1f22, 0x1f23, - 0x1f30, 0x1f31, 0x1f32, 0x1f33, - 0 }; + 0x1f30, 0x1f31, 0x1f32, 0x1f33, + 0 }; static const struct pci_driver soc_sata __pci_driver = { .ops = &sata_ops, diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 0674dca..388209a 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -200,7 +200,7 @@ void rangeley_sb_early_initialization(void); #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) #define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) + RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) @@ -248,7 +248,7 @@ void rangeley_sb_early_initialization(void); #define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) + ((b) << DIR_IBR) | ((a) << DIR_IAR)) /* PBASE Registers */ #define PMC_CFG 0x08 diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c index 12a9202..2cb241a 100644 --- a/src/southbridge/intel/i3100/early_smbus.c +++ b/src/southbridge/intel/i3100/early_smbus.c @@ -27,7 +27,7 @@ static void enable_smbus(void) pci_write_config8(dev, 0x40, 1); pci_write_config8(dev, 0x4, 1); /* SMBALERT_DIS */ - outb(4, SMBUS_IO_BASE + SMBSLVCMD); + outb(4, SMBUS_IO_BASE + SMBSLVCMD); /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index 4d529ca..355b0d4 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -206,19 +206,19 @@ static void i3100_pirq_init(device_t dev) if(config->pirq_e_h) pci_write_config32(dev, 0x68, config->pirq_e_h); - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; + for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + u8 int_pin=0, int_line=0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; + if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + continue; - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - switch (int_pin) { - case 1: /* INTA# */ + int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + switch (int_pin) { + case 1: /* INTA# */ int_line = config->pirq_a_d & 0xff; break; - case 2: /* INTB# */ + case 2: /* INTB# */ int_line = (config->pirq_a_d >> 8) & 0xff; break; @@ -226,17 +226,17 @@ static void i3100_pirq_init(device_t dev) int_line = (config->pirq_a_d >> 16) & 0xff; break; - case 4: /* INTD# */ + case 4: /* INTD# */ int_line = (config->pirq_a_d >> 24) & 0xff; break; - } + } - if (!int_line) - continue; + if (!int_line) + continue; printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n", dev_path(irq_dev), int_pin, int_line); - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } } diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 326a9e5..1eae32d 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -233,37 +233,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 630484a..4ff3fb5 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -78,8 +78,8 @@ static void i82801ex_pci_dma_cfg(device_t dev) #define LPC_EN 0xe6 static void i82801ex_enable_lpc(device_t dev) { - /* lpc i/f enable */ - pci_write_config8(dev, LPC_EN, 0x0d); + /* lpc i/f enable */ + pci_write_config8(dev, LPC_EN, 0x0d); } typedef struct southbridge_intel_i82801ex_config config_t; @@ -292,7 +292,7 @@ static void lpc_init(struct device *dev) /* Clear SATA to non raid */ pci_write_config8(dev, 0xae, 0x00); - get_option(&pwr_on, "power_on_after_fail"); + get_option(&pwr_on, "power_on_after_fail"); byte = pci_read_config8(dev, 0xa4); byte &= 0xfe; if (!pwr_on) { diff --git a/src/southbridge/intel/i82801ex/reset.c b/src/southbridge/intel/i82801ex/reset.c index 9936892..8036ffd 100644 --- a/src/southbridge/intel/i82801ex/reset.c +++ b/src/southbridge/intel/i82801ex/reset.c @@ -3,6 +3,6 @@ void hard_reset(void) { - /* Try rebooting through port 0xcf9 */ - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); + /* Try rebooting through port 0xcf9 */ + outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); } diff --git a/src/southbridge/intel/i82801ex/watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c index 28e1f5e..6aba270 100644 --- a/src/southbridge/intel/i82801ex/watchdog.c +++ b/src/southbridge/intel/i82801ex/watchdog.c @@ -6,23 +6,23 @@ void watchdog_off(void) { - device_t dev; - unsigned long value,base; + device_t dev; + unsigned long value,base; /* turn off the ICH5 watchdog */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); - /* Enable I/O space */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - /* Get TCO base */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; - /* Disable the watchdog timer */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - /* Clear TCO timeout status */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n"); + dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + /* Get TCO base */ + base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + /* Disable the watchdog timer */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); + printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n"); } diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 50268b6..c9c19a3 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -30,22 +30,22 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { - u8 reg8; - pci_devfn_t dev; + u8 reg8; + pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 0); + dev = PCI_DEV(0, 0x1f, 0); - reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); } static void bootblock_southbridge_init(void) { store_initial_timestamp(); - enable_spi_prefetch(); + enable_spi_prefetch(); /* Enable RCBA */ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/i82801gx/reset.c b/src/southbridge/intel/i82801gx/reset.c index 39c4f31..97b8225 100644 --- a/src/southbridge/intel/i82801gx/reset.c +++ b/src/southbridge/intel/i82801gx/reset.c @@ -19,7 +19,7 @@ void soft_reset(void) { - outb(0x04, 0xcf9); + outb(0x04, 0xcf9); } #if 0 @@ -32,6 +32,6 @@ void hard_reset(void) void hard_reset(void) { - outb(0x02, 0xcf9); - outb(0x06, 0xcf9); + outb(0x02, 0xcf9); + outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index b128280..609355c 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -269,37 +269,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index e222368..6252712 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -17,18 +17,18 @@ static void enable_spi_prefetch(void) { - u8 reg8; - pci_devfn_t dev; + u8 reg8; + pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 0); + dev = PCI_DEV(0, 0x1f, 0); - reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); } static void bootblock_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetch(); } diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 6a0f0d2..e6a21ad 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -49,9 +49,9 @@ static void p64h2_ioapic_init(device_t dev) // IDs 3, 4, 5, and 8+ are available (see above note) if (apic_index < 3) - apic_id = apic_index + 3; + apic_id = apic_index + 3; else - apic_id = apic_index + 5; + apic_id = apic_index + 5; ASSERT(apic_id < 16); // ID is only 4 bits @@ -63,8 +63,8 @@ static void p64h2_ioapic_init(device_t dev) pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10); printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n", - apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister); + apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister); apic_id <<= 24; // Convert ID to bitmask @@ -72,27 +72,27 @@ static void p64h2_ioapic_init(device_t dev) *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id; // Set the ID if ((*pWindowRegister & (0xF<<24)) != apic_id) - die("p64h2_ioapic_init failed"); + die("p64h2_ioapic_init failed"); *pIndexRegister = 3; // Select Boot Configuration register *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts if (!(*pWindowRegister & 1)) - die("p64h2_ioapic_init failed"); + die("p64h2_ioapic_init failed"); } static struct device_operations ioapic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = p64h2_ioapic_init, - .scan_bus = 0, - .enable = p64h2_ioapic_enable, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = p64h2_ioapic_init, + .scan_bus = 0, + .enable = p64h2_ioapic_enable, }; static const struct pci_driver ioapic_driver __pci_driver = { - .ops = &ioapic_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82870_1E0, + .ops = &ioapic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82870_1E0, }; diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c index 71d2c53..b886c52 100644 --- a/src/southbridge/intel/i82870/pci_parity.c +++ b/src/southbridge/intel/i82870/pci_parity.c @@ -5,19 +5,19 @@ void p64h2_pci_parity_enable(void) { - uint8_t reg; + uint8_t reg; - /* 2SERREN - SERR enable for PCI bridge secondary device */ - /* 2PEREN - Parity error for PCI bridge secondary device */ - pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg); - reg |= ((1 << 1) + (1 << 0)); - pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg); + /* 2SERREN - SERR enable for PCI bridge secondary device */ + /* 2PEREN - Parity error for PCI bridge secondary device */ + pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg); + reg |= ((1 << 1) + (1 << 0)); + pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg); - /* 2SERREN - SERR enable for PCI bridge secondary device */ - /* 2PEREN - Parity error for PCI bridge secondary device */ - pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg); - reg |= ((1 << 1) + (1 << 0)); - pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg); + /* 2SERREN - SERR enable for PCI bridge secondary device */ + /* 2PEREN - Parity error for PCI bridge secondary device */ + pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg); + reg |= ((1 << 1) + (1 << 0)); + pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg); - return; + return; } diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c index b46b338..e8d890a 100644 --- a/src/southbridge/intel/i82870/pcibridge.c +++ b/src/southbridge/intel/i82870/pcibridge.c @@ -23,16 +23,16 @@ static void p64h2_pcix_init(device_t dev) } static struct device_operations pcix_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = p64h2_pcix_init, - .scan_bus = pci_scan_bridge, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = p64h2_pcix_init, + .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, }; static const struct pci_driver pcix_driver __pci_driver = { - .ops = &pcix_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82870_1F0, + .ops = &pcix_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82870_1F0, }; diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 6c694fd..62341ff 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -263,7 +263,7 @@ void southbridge_configure_default_intmap(void); #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) #define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) + RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) @@ -401,7 +401,7 @@ void southbridge_configure_default_intmap(void); #define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) + ((b) << DIR_IBR) | ((a) << DIR_IAR)) #define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */ diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index e7681fb..19ef098 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -126,7 +126,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0x28, reg32); } else { - /* IDE */ + /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index d4fbed4..b5450a0 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -273,37 +273,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } static void southbridge_gate_memory_reset_real(int offset, diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 0e4fa3d..8e2d42f 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -125,7 +125,7 @@ void pch_enable_lpc(void) } int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config) + const struct rcba_config_instruction *rcba_config) { int wake_from_s3; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 1d20bbb..5af6bf5 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -194,7 +194,7 @@ static void pch_power_options(device_t dev) * If the option is not existent (Laptops), use Kconfig setting. */ get_option(&pwr_on, "power_on_after_fail"); - pwr_on = MAINBOARD_POWER_KEEP; + pwr_on = MAINBOARD_POWER_KEEP; reg16 = pci_read_config16(dev, GEN_PMCON_3); reg16 &= 0xfffe; diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 43e5289..355db4b 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -485,7 +485,7 @@ static int mkhi_get_fwcaps(mbp_mefwcaps *cap) &cap_msg, sizeof(cap_msg)) < 0) { printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); return -1; - } + } *cap = cap_msg.caps_sku; return 0; } @@ -650,7 +650,7 @@ static int me_icc_set_clock_enables(u32 mask) if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) { printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n"); return -1; - } else { + } else { printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask); } diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 8cae50a..b170755 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -201,7 +201,7 @@ void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config); + const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); #endif /* !__PRE_RAM__ && !__SMM__ */ #endif /* __ASSEMBLER__ */ @@ -503,7 +503,7 @@ void pch_enable_lpc(void); #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) #define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) + RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) diff --git a/src/southbridge/intel/lynxpoint/reset.c b/src/southbridge/intel/lynxpoint/reset.c index daabbbc..804fb81 100644 --- a/src/southbridge/intel/lynxpoint/reset.c +++ b/src/southbridge/intel/lynxpoint/reset.c @@ -19,10 +19,10 @@ void soft_reset(void) { - outb(0x04, 0xcf9); + outb(0x04, 0xcf9); } void hard_reset(void) { - outb(0x06, 0xcf9); + outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 4f0db1b..4a156ea 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -68,37 +68,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index ae8b6a0..6b21a3f 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -377,6 +377,6 @@ void soft_reset(void) void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { - /* The default value for CK804 is good. */ - /* Set VFSMAF (VID/FID System Management Action Field) to 2. */ + /* The default value for CK804 is good. */ + /* Set VFSMAF (VID/FID System Management Action Field) to 2. */ } diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c index a7c3319..4cb9215 100644 --- a/src/southbridge/sis/sis966/aza.c +++ b/src/southbridge/sis/sis966/aza.c @@ -184,7 +184,7 @@ static u32 verb_data[] = { static unsigned find_verb(u32 viddid, u32 **verb) { - if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; + if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; *verb = (u32 *)verb_data; return sizeof(verb_data)/sizeof(u32); } @@ -236,45 +236,45 @@ static void codecs_init(u8 *base, u32 codec_mask) static void aza_init(struct device *dev) { - u8 *base; - struct resource *res; - u32 codec_mask; + u8 *base; + struct resource *res; + u32 codec_mask; - printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n"); + printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n"); //-------------- enable AZA (SiS7502) ------------------------- { - u8 temp8; - int i=0; - while(SiS_SiS7502_init[i][0] != 0) - { - temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]); - temp8 &= SiS_SiS7502_init[i][1]; - temp8 |= SiS_SiS7502_init[i][2]; - pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8); - i++; - }; + u8 temp8; + int i=0; + while(SiS_SiS7502_init[i][0] != 0) + { + temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]); + temp8 &= SiS_SiS7502_init[i][1]; + temp8 |= SiS_SiS7502_init[i][2]; + pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8); + i++; + }; } //----------------------------------------------------------- - // put audio to D0 state - pci_write_config8(dev, 0x54,0x00); + // put audio to D0 state + pci_write_config8(dev, 0x54,0x00); #if DEBUG_AZA { - int i; - - printk(BIOS_DEBUG, "****** Azalia PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for(i=0;i<0xff;i+=4){ - if((i%16)==0){ - printk(BIOS_DEBUG, "\n%02x: ", i); - } - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); + int i; + + printk(BIOS_DEBUG, "****** Azalia PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + printk(BIOS_DEBUG, "\n%02x: ", i); + } + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); + } + printk(BIOS_DEBUG, "\n"); } #endif @@ -292,7 +292,7 @@ static void aza_init(struct device *dev) codecs_init(base, codec_mask); } - printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n"); + printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n"); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c index 15d4f4c..d29c405 100644 --- a/src/southbridge/sis/sis966/early_smbus.c +++ b/src/southbridge/sis/sis966/early_smbus.c @@ -502,11 +502,11 @@ static const uint8_t SiS_SiS1183_init[44][3]={ }; /* In => Share Memory size - => 00h : 0MBytes - => 02h : 32MBytes - => 03h : 64MBytes - => 04h : 128MBytes - => Others: Reserved + => 00h : 0MBytes + => 02h : 32MBytes + => 03h : 64MBytes + => 04h : 128MBytes + => Others: Reserved */ static void Init_Share_Memory(uint8_t ShareSize) { @@ -517,31 +517,31 @@ static void Init_Share_Memory(uint8_t ShareSize) } /* In: => Aperture size - => 00h : 32MBytes - => 01h : 64MBytes - => 02h : 128MBytes - => 03h : 256MBytes - => 04h : 512MBytes - => Others: Reserved + => 00h : 32MBytes + => 01h : 64MBytes + => 02h : 128MBytes + => 03h : 256MBytes + => 04h : 512MBytes + => Others: Reserved */ static void Init_Aper_Size(uint8_t AperSize) { - device_t dev; - uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00}; + device_t dev; + uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00}; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0); - pci_write_config8(dev, 0x90, AperSize << 1); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0); + pci_write_config8(dev, 0x90, AperSize << 1); - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); - pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); + pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]); } static void sis_init_stage1(void) { - device_t dev; - uint8_t temp8; - int i; - uint8_t GUI_En; + device_t dev; + uint8_t temp8; + int i; + uint8_t GUI_En; // SiS_Chipset_Initialization // ========================== NB ============================= @@ -608,20 +608,20 @@ static void sis_init_stage2(void) // ========================== NB_AGP ============================= - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Enable Internal GUI enable bit - pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Enable Internal GUI enable bit + pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10); - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0); - i=0; + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0); + i=0; - while(SiS_NBAGP_init[i][0] != 0) - { - temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]); - temp8 &= SiS_NBAGP_init[i][1]; - temp8 |= SiS_NBAGP_init[i][2]; - pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8); - i++; - }; + while(SiS_NBAGP_init[i][0] != 0) + { + temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]); + temp8 &= SiS_NBAGP_init[i][1]; + temp8 |= SiS_NBAGP_init[i][2]; + pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8); + i++; + }; /** * Share Memory size @@ -640,24 +640,24 @@ static void sis_init_stage2(void) * => Others: Reserved */ - Init_Share_Memory(0x02); //0x02 : 32M - Init_Aper_Size(0x01); //0x1 : 64M + Init_Share_Memory(0x02); //0x02 : 32M + Init_Aper_Size(0x01); //0x1 : 64M // ========================== NB ============================= - printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n"); - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); - msr = rdmsr(0xC001001A); + printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n"); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); + msr = rdmsr(0xC001001A); printk(BIOS_DEBUG, "Memory Top Bound %x\n",msr.lo ); - temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5; - temp16=0x0001<<(temp16-1); - temp16<<=8; + temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5; + temp16=0x0001<<(temp16-1); + temp16<<=8; - printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4); - pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1); - pci_write_config8(dev, 0x7F, 0x08); // ACPI Base - outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function + printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4); + pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1); + pci_write_config8(dev, 0x7F, 0x08); // ACPI Base + outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function // ========================== ACPI ============================= i=0; diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index f3fa079..faee0a0 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -101,15 +101,15 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n"); //-------------- enable IDE (SiS5513) ------------------------- { - uint8_t temp8; - int i=0; + uint8_t temp8; + int i=0; while(SiS_SiS5513_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]); - temp8 &= SiS_SiS5513_init[i][1]; - temp8 |= SiS_SiS5513_init[i][2]; - pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8); - i++; + temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]); + temp8 &= SiS_SiS5513_init[i][1]; + temp8 |= SiS_SiS5513_init[i][2]; + pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8); + i++; }; } //----------------------------------------------------------- @@ -143,17 +143,17 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n"); #if DEBUG_IDE { - int i; + int i; - printk(BIOS_DEBUG, "****** IDE PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** IDE PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); + for(i=0;i<0xff;i+=4){ + if((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); + } + printk(BIOS_DEBUG, "\n"); } #endif printk(BIOS_DEBUG, "IDE_INIT:<----------\n"); diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 0a5adf0..35691a8 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -123,33 +123,33 @@ static void lpc_init(device_t dev) (on*12)+(on>>1),(on&1)*5); } - /* Enable Error reporting */ - /* Set up sync flood detected */ - byte = pci_read_config8(dev, 0x47); - byte |= (1 << 1); - pci_write_config8(dev, 0x47, byte); - - /* Set up NMI on errors */ - byte = inb(0x70); // RTC70 - byte_old = byte; - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ - } else { - byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW - } - if( byte != byte_old) { - outb(byte, 0x70); - } - - /* Initialize the real time clock */ - cmos_init(0); - - /* Initialize isa dma */ - isa_dma_init(); - - printk(BIOS_DEBUG, "LPC_INIT <--------\n"); + /* Enable Error reporting */ + /* Set up sync flood detected */ + byte = pci_read_config8(dev, 0x47); + byte |= (1 << 1); + pci_write_config8(dev, 0x47, byte); + + /* Set up NMI on errors */ + byte = inb(0x70); // RTC70 + byte_old = byte; + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte &= ~(1 << 7); /* set NMI */ + } else { + byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW + } + if( byte != byte_old) { + outb(byte, 0x70); + } + + /* Initialize the real time clock */ + cmos_init(0); + + /* Initialize isa dma */ + isa_dma_init(); + + printk(BIOS_DEBUG, "LPC_INIT <--------\n"); } static void sis966_lpc_read_resources(device_t dev) diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c index cd376ab..f9ec7ff 100644 --- a/src/southbridge/sis/sis966/nic.c +++ b/src/southbridge/sis/sis966/nic.c @@ -75,7 +75,7 @@ static void readApcMacAddr(void) printk(BIOS_DEBUG, "MAC addr in APC = "); for(i = 0x9 ; i <=0xe ; i++) { - printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); + printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); } printk(BIOS_DEBUG, "\n"); @@ -103,7 +103,7 @@ static void set_apc(struct device *dev) addr=0x9+2*i; writeApcByte(addr,(u8)(MacAddr[i]&0xFF)); writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF)); - // printf("%x - ",readMacAddrByte(0x59+i)); + // printf("%x - ",readMacAddrByte(0x59+i)); } /* Set APC Reload */ @@ -146,10 +146,10 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg) { ulValue=read32(base + 0x3c); - if(!(ulValue & 0x0080)) //BIT_7 - break; + if(!(ulValue & 0x0080)) //BIT_7 + break; - mdelay(100); + mdelay(100); } mdelay(50); @@ -172,22 +172,22 @@ static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg) Read_Cmd = ((phy_reg << 11) | - (phy_addr << 6) | + (phy_addr << 6) | SMI_READ | SMI_REQUEST); - // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC + // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC write32(base + 0x44, Read_Cmd); - // Polling SMI_REQ bit to be deasserted indicated read command completed - do - { + // Polling SMI_REQ bit to be deasserted indicated read command completed + do + { // Wait 20 usec before checking status mdelay(20); ulValue = read32(base + 0x44); - } while((ulValue & SMI_REQUEST) != 0); - //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue); - usData=(ulValue>>16); + } while((ulValue & SMI_REQUEST) != 0); + //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue); + usData=(ulValue>>16); @@ -204,19 +204,19 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect() int PhyAddress = 0; - // Scan all PHY address(0 ~ 31) to find a valid PHY - for(PhyAddress = 0; PhyAddress < 32; PhyAddress++) - { + // Scan all PHY address(0 ~ 31) to find a valid PHY + for(PhyAddress = 0; PhyAddress < 32; PhyAddress++) + { usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h) - // Found a valid PHY + // Found a valid PHY - if((usData != 0x0) && (usData != 0xffff)) - { - bFoundPhy = TRUE; - break; - } - } + if((usData != 0x0) && (usData != 0xffff)) + { + bFoundPhy = TRUE; + break; + } + } if(!bFoundPhy) @@ -232,31 +232,31 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect() static void nic_init(struct device *dev) { - int val; - u16 PhyAddr; - u8 *base; - struct resource *res; + int val; + u16 PhyAddr; + u8 *base; + struct resource *res; - printk(BIOS_DEBUG, "NIC_INIT:---------->\n"); + printk(BIOS_DEBUG, "NIC_INIT:---------->\n"); //-------------- enable NIC (SiS19x) ------------------------- { - u8 temp8; - int i=0; - while(SiS_SiS191_init[i][0] != 0) + u8 temp8; + int i=0; + while(SiS_SiS191_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]); - temp8 &= SiS_SiS191_init[i][1]; - temp8 |= SiS_SiS191_init[i][2]; - pci_write_config8(dev, SiS_SiS191_init[i][0], temp8); - i++; + temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]); + temp8 &= SiS_SiS191_init[i][1]; + temp8 |= SiS_SiS191_init[i][2]; + pci_write_config8(dev, SiS_SiS191_init[i][0], temp8); + i++; }; } //----------------------------------------------------------- { - unsigned long i; - unsigned long ulValue; + unsigned long i; + unsigned long ulValue; res = find_resource(dev, 0x10); @@ -266,7 +266,7 @@ static void nic_init(struct device *dev) return; } base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "NIC base address %p\n",base); + printk(BIOS_DEBUG, "NIC base address %p\n",base); if(!(val=phy_detect(base,&PhyAddr))) { @@ -274,14 +274,14 @@ static void nic_init(struct device *dev) return; } - ulValue=read32(base + 0x38L); // check EEPROM existing + ulValue=read32(base + 0x38L); // check EEPROM existing - if((ulValue & 0x0002)) - { + if((ulValue & 0x0002)) + { - // read MAC address from EEPROM at first + // read MAC address from EEPROM at first - // if that is valid we will use that + // if that is valid we will use that printk(BIOS_DEBUG, "EEPROM contents %lx \n",ReadEEprom( dev, base, 0LL)); for(i=0;i<3;i++) { @@ -292,31 +292,31 @@ static void nic_init(struct device *dev) MacAddr[i] =ulValue & 0xFFFF; } - }else{ - // read MAC address from firmware - printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue); - MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here - MacAddr[1]=read16((u16 *)0xffffffc2); - MacAddr[2]=read16((u16 *)0xffffffc4); - } + }else{ + // read MAC address from firmware + printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue); + MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here + MacAddr[1]=read16((u16 *)0xffffffc2); + MacAddr[2]=read16((u16 *)0xffffffc4); + } - set_apc(dev); + set_apc(dev); - readApcMacAddr(); + readApcMacAddr(); #if DEBUG_NIC { - int i; + int i; - printk(BIOS_DEBUG, "****** NIC PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** NIC PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); + for(i=0;i<0xff;i+=4){ + if((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); + } + printk(BIOS_DEBUG, "\n"); } diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c index 197f4d2..92737bf 100644 --- a/src/southbridge/sis/sis966/sata.c +++ b/src/southbridge/sis/sis966/sata.c @@ -112,19 +112,19 @@ static void sata_init(struct device *dev) conf = dev->chip_info; - printk(BIOS_DEBUG, "SATA_INIT:---------->\n"); + printk(BIOS_DEBUG, "SATA_INIT:---------->\n"); //-------------- enable IDE (SiS1183) ------------------------- { - uint8_t temp8; - int i=0; + uint8_t temp8; + int i=0; while(SiS_SiS1183_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]); - temp8 &= SiS_SiS1183_init[i][1]; - temp8 |= SiS_SiS1183_init[i][2]; - pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8); - i++; + temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]); + temp8 &= SiS_SiS1183_init[i][1]; + temp8 |= SiS_SiS1183_init[i][2]; + pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8); + i++; }; } //----------------------------------------------------------- @@ -145,21 +145,21 @@ for (i=0;i<10;i++){ #if DEBUG_SATA { - int i; + int i; - printk(BIOS_DEBUG, "****** SATA PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** SATA PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); + for(i=0;i<0xff;i+=4){ + if((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); + } + printk(BIOS_DEBUG, "\n"); } #endif - printk(BIOS_DEBUG, "SATA_INIT:<----------\n"); + printk(BIOS_DEBUG, "SATA_INIT:<----------\n"); } diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c index 95f01d1..d616a7d 100644 --- a/src/southbridge/sis/sis966/usb.c +++ b/src/southbridge/sis/sis966/usb.c @@ -51,12 +51,12 @@ uint8_t SiS_SiS7001_init[16][3]={ static void usb_init(struct device *dev) { - printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n"); + printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n"); //-------------- enable USB1.1 (SiS7001) ------------------------- { - uint8_t temp8; - int i=0; + uint8_t temp8; + int i=0; while(SiS_SiS7001_init[i][0] != 0) { temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]); @@ -70,20 +70,20 @@ static void usb_init(struct device *dev) #if DEBUG_USB { - int i; + int i; - printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); + for(i=0;i<0xff;i+=4){ + if((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); + } + printk(BIOS_DEBUG, "\n"); } #endif - printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n"); + printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n"); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c index 5bad6b3..ad0bd6c 100644 --- a/src/southbridge/sis/sis966/usb2.c +++ b/src/southbridge/sis/sis966/usb2.c @@ -62,46 +62,46 @@ static const u8 SiS_SiS7002_init[22][3]={ static void usb2_init(struct device *dev) { - u8 *base; - struct resource *res; - int i; - u8 temp8; + u8 *base; + struct resource *res; + int i; + u8 temp8; - printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n"); + printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n"); //-------------- enable USB2.0 (SiS7002) ---------------------- i = 0; - while(SiS_SiS7002_init[i][0] != 0) - { - temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); - temp8 &= SiS_SiS7002_init[i][1]; - temp8 |= SiS_SiS7002_init[i][2]; - pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8); - i++; - }; - - res = find_resource(dev, 0x10); - if(!res) - return; - - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "base = 0x%p\n", base); - write32(base + 0x20, 0x2); + while(SiS_SiS7002_init[i][0] != 0) + { + temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); + temp8 &= SiS_SiS7002_init[i][1]; + temp8 |= SiS_SiS7002_init[i][2]; + pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8); + i++; + }; + + res = find_resource(dev, 0x10); + if(!res) + return; + + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "base = 0x%p\n", base); + write32(base + 0x20, 0x2); //------------------------------------------------------------- #if DEBUG_USB2 - printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for(i=0;i<0xff;i+=4){ - if((i%16)==0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); + printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); + } + printk(BIOS_DEBUG, "\n"); #endif - printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n"); + printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n"); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index dd3bcae..478a9ee 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -35,10 +35,10 @@ static void southbridge_init_common(struct device *dev); #if CONFIG_EPIA_VT8237R_INIT - /* Interrupts for INT# A B C D */ + /* Interrupts for INT# A B C D */ static const unsigned char pciIrqs[4] = { 10, 11, 12, 0}; - /* Interrupt Assignments for Pins 1 2 3 4 */ + /* Interrupt Assignments for Pins 1 2 3 4 */ static const unsigned char sataPins[4] = { 'A','B','C','D'}; static const unsigned char vgaPins[4] = { 'A','B','C','D'}; static const unsigned char usbPins[4] = { 'A','B','C','D'};

1 0

Patch merged into coreboot/master: 3rdparty/blobs: Update to get AGESA binary for pcengines/apu2
by gerrit＠coreboot.org 21 Aug '16

21 Aug '16

the following patch was just integrated into master: commit 5a859517e26ef7aff68e8a0c18a838d0816f6e86 Author: Martin Roth <martinroth(a)google.com> Date: Thu Aug 18 17:16:34 2016 -0600 3rdparty/blobs: Update to get AGESA binary for pcengines/apu2 The AGESA binary for PC Engines' APU2 board was just added to the blobs directory. Update the submodule pointer to allow access. Change-Id: Ic2995f253d12d17e229526cb71dea5bf65fa36f9 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/16253 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com> See https://review.coreboot.org/16253 for details. -gerrit

1 0

New patch to review for coreboot: src/southbridge: space required before the open parenthesis '('
by HAOUAS Elyes 21 Aug '16

21 Aug '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16290 -gerrit commit e97a50ad89b3bedff18a01caf462eb4fe83a3d4a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 18:36:06 2016 +0200 src/southbridge: space required before the open parenthesis '(' Change-Id: I43b9b86fd51dbdc50108026099c60238f3012cbe Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/amd8132/bridge.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 6 +++--- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/fsp_bd82x6x/sata.c | 2 +- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 2 +- src/southbridge/intel/fsp_i89xx/sata.c | 2 +- src/southbridge/intel/fsp_i89xx/smihandler.c | 2 +- src/southbridge/intel/fsp_rangeley/sata.c | 2 +- src/southbridge/intel/i3100/lpc.c | 2 +- src/southbridge/intel/i82801dx/smihandler.c | 2 +- src/southbridge/intel/i82801ex/i82801ex.c | 2 +- src/southbridge/intel/i82801gx/sata.c | 2 +- src/southbridge/intel/i82801gx/smihandler.c | 2 +- src/southbridge/intel/i82801ix/smihandler.c | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- src/southbridge/intel/lynxpoint/sata.c | 2 +- src/southbridge/sis/sis966/aza.c | 8 ++++---- src/southbridge/sis/sis966/ide.c | 4 ++-- src/southbridge/sis/sis966/lpc.c | 2 +- src/southbridge/sis/sis966/nic.c | 20 ++++++++++---------- src/southbridge/sis/sis966/sata.c | 4 ++-- src/southbridge/sis/sis966/usb.c | 4 ++-- src/southbridge/sis/sis966/usb2.c | 6 +++--- 24 files changed, 43 insertions(+), 43 deletions(-) diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index ee45c65..4df33da 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -386,7 +386,7 @@ static void amd8132_ioapic_init(device_t dev) } - if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { + if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { //for b1 b2 /* Errata #73 */ dword = pci_read_config32(dev, 0x80); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 7e8d8c3..26e3b5f 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -49,7 +49,7 @@ void bcm5785_enable(device_t dev) if( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) { if(dev->device == 0x0036) //PCI-X Bridge { devfn += (1<<3); } - else if(dev->device == 0x0223) // USB + else if (dev->device == 0x0223) // USB { devfn -= (1<<3); } } sb_pci_main_dev = dev_find_slot(dev->bus->secondary, devfn); diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index e29fab4..3ddc9ca 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -47,13 +47,13 @@ static void bcm5785_enable_wdt_port_cf9(void) dword_old = pci_read_config32(dev, 0x4c); dword = dword_old | (1<<4); //enable Timer Func - if(dword != dword_old ) { + if (dword != dword_old ) { pci_write_config32(dev, 0x4c, dword); } dword_old = pci_read_config32(dev, 0x6c); dword = dword_old | (1<<9); //unhide Timer Func in pci space - if(dword != dword_old ) { + if (dword != dword_old ) { pci_write_config32(dev, 0x6c, dword); } @@ -149,7 +149,7 @@ static void bcm5785_enable_msg(void) // bit 1: enable upsteam messages // bit 0: enable shutdowm message to init generation dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor - if(dword != dword_old ) { + if (dword != dword_old ) { pci_write_config32(dev, 0x6c, dword); } } diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index e4e5b81..bc19b78 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -782,7 +782,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c index 81a5d7d..6130646 100644 --- a/src/southbridge/intel/fsp_bd82x6x/sata.c +++ b/src/southbridge/intel/fsp_bd82x6x/sata.c @@ -52,7 +52,7 @@ static void sata_init(struct device *dev) reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { u32 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 987d6d1..77ada10 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/fsp_i89xx/sata.c b/src/southbridge/intel/fsp_i89xx/sata.c index 87d5431..810847a 100644 --- a/src/southbridge/intel/fsp_i89xx/sata.c +++ b/src/southbridge/intel/fsp_i89xx/sata.c @@ -52,7 +52,7 @@ static void sata_init(struct device *dev) reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { u32 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index e0d19d6..27b8166 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index 4861f83..624af23 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -60,7 +60,7 @@ static void sata_init(struct device *dev) reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set the controller mode */ diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index 4d529ca..a58cb6a 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -206,7 +206,7 @@ static void i3100_pirq_init(device_t dev) if(config->pirq_e_h) pci_write_config32(dev, 0x68, config->pirq_e_h); - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0, int_line=0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 326a9e5..f4ab2f6 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -549,7 +549,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c index fc41645..3d37ce8 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.c +++ b/src/southbridge/intel/i82801ex/i82801ex.c @@ -15,7 +15,7 @@ void i82801ex_enable(device_t dev) if((dev->path.pci.devfn &0xf8)== 0xf8) { index = dev->path.pci.devfn & 7; } - else if((dev->path.pci.devfn &0xf8)== 0xe8) { + else if ((dev->path.pci.devfn &0xf8)== 0xe8) { index = (dev->path.pci.devfn & 7) +8; } if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) { diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 9cb6f39..2fcb83d 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -118,7 +118,7 @@ static void sata_init(struct device *dev) /* Restrict ports - 0 and 2 only available */ ports &= 0x5; - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); /* Allow both Legacy and Native mode */ pci_write_config8(dev, 0x09, 0x8f); diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index b128280..e76087c 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -586,7 +586,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st /* IOTRAP(0) SMIC: currently unused */ printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 4f30865..5f1a44f 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -409,7 +409,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index d4fbed4..d11d531 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -768,7 +768,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index ffeb8a2..98cd0bc 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -91,7 +91,7 @@ static void sata_init(struct device *dev) /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { u32 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c index a7c3319..462670e 100644 --- a/src/southbridge/sis/sis966/aza.c +++ b/src/southbridge/sis/sis966/aza.c @@ -105,7 +105,7 @@ static int codec_detect(u8 *base) dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId - if(dword==0) { + if (dword==0) { printk(BIOS_DEBUG, "No codec!\n"); return 0; } @@ -184,7 +184,7 @@ static u32 verb_data[] = { static unsigned find_verb(u32 viddid, u32 **verb) { - if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; + if ((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; *verb = (u32 *)verb_data; return sizeof(verb_data)/sizeof(u32); } @@ -268,8 +268,8 @@ static void aza_init(struct device *dev) printk(BIOS_DEBUG, "****** Azalia PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0){ + for (i=0;i<0xff;i+=4){ + if ((i%16)==0){ printk(BIOS_DEBUG, "\n%02x: ", i); } printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index f3fa079..6b939e7 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -148,8 +148,8 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n"); printk(BIOS_DEBUG, "****** IDE PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 0a5adf0..ef26745 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -139,7 +139,7 @@ static void lpc_init(device_t dev) } else { byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW } - if( byte != byte_old) { + if ( byte != byte_old) { outb(byte, 0x70); } diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c index cd376ab..e60eeb8 100644 --- a/src/southbridge/sis/sis966/nic.c +++ b/src/southbridge/sis/sis966/nic.c @@ -73,7 +73,7 @@ static void readApcMacAddr(void) outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data printk(BIOS_DEBUG, "MAC addr in APC = "); - for(i = 0x9 ; i <=0xe ; i++) + for (i = 0x9 ; i <=0xe ; i++) { printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); } @@ -98,7 +98,7 @@ static void set_apc(struct device *dev) outl(0x80001048,0xcf8); outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data - for(i = 0 ; i <3; i++) + for (i = 0 ; i <3; i++) { addr=0x9+2*i; writeApcByte(addr,(u8)(MacAddr[i]&0xFF)); @@ -142,11 +142,11 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg) mdelay(10); - for(i=0 ; i <= LoopNum; i++) + for (i=0 ; i <= LoopNum; i++) { ulValue=read32(base + 0x3c); - if(!(ulValue & 0x0080)) //BIT_7 + if (!(ulValue & 0x0080)) //BIT_7 break; mdelay(100); @@ -154,7 +154,7 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg) mdelay(50); - if(i==LoopNum) data=0x10000; + if (i==LoopNum) data=0x10000; else{ ulValue=read32(base + 0x3c); data = ((ulValue & 0xffff0000) >> 16); @@ -205,13 +205,13 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect() // Scan all PHY address(0 ~ 31) to find a valid PHY - for(PhyAddress = 0; PhyAddress < 32; PhyAddress++) + for (PhyAddress = 0; PhyAddress < 32; PhyAddress++) { usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h) // Found a valid PHY - if((usData != 0x0) && (usData != 0xffff)) + if ((usData != 0x0) && (usData != 0xffff)) { bFoundPhy = TRUE; break; @@ -276,7 +276,7 @@ static void nic_init(struct device *dev) ulValue=read32(base + 0x38L); // check EEPROM existing - if((ulValue & 0x0002)) + if ((ulValue & 0x0002)) { // read MAC address from EEPROM at first @@ -311,8 +311,8 @@ static void nic_init(struct device *dev) printk(BIOS_DEBUG, "****** NIC PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c index 197f4d2..eb69ab0 100644 --- a/src/southbridge/sis/sis966/sata.c +++ b/src/southbridge/sis/sis966/sata.c @@ -150,8 +150,8 @@ for (i=0;i<10;i++){ printk(BIOS_DEBUG, "****** SATA PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c index 95f01d1..64398e2 100644 --- a/src/southbridge/sis/sis966/usb.c +++ b/src/southbridge/sis/sis966/usb.c @@ -75,8 +75,8 @@ static void usb_init(struct device *dev) printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c index 5bad6b3..e93e4c9 100644 --- a/src/southbridge/sis/sis966/usb2.c +++ b/src/southbridge/sis/sis966/usb2.c @@ -82,7 +82,7 @@ static void usb2_init(struct device *dev) }; res = find_resource(dev, 0x10); - if(!res) + if (!res) return; base = res2mmio(res, 0, 0); @@ -94,8 +94,8 @@ static void usb2_init(struct device *dev) printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); }

1 0

New patch to review for coreboot: src/device: space required before the open parenthesis '('
by HAOUAS Elyes 21 Aug '16

21 Aug '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16289 -gerrit commit bad34599983a396348bc080e37b08313c1042dff Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 18:28:17 2016 +0200 src/device: space required before the open parenthesis '(' Change-Id: I48477c2917ab1be14d3cedf25e8b97dae1c1d309 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/device/oprom/x86emu/decode.c | 4 ++-- src/device/oprom/x86emu/ops.c | 4 ++-- src/device/oprom/x86emu/ops2.c | 16 ++++++++-------- src/device/oprom/x86emu/prim_ops.c | 4 ++-- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/device/oprom/x86emu/decode.c b/src/device/oprom/x86emu/decode.c index d59583c..b7a6f35 100644 --- a/src/device/oprom/x86emu/decode.c +++ b/src/device/oprom/x86emu/decode.c @@ -1138,9 +1138,9 @@ Return the offset given by "mod" addressing. unsigned decode_rmXX_address(int mod, int rm) { - if(mod == 0) + if (mod == 0) return decode_rm00_address(rm); - if(mod == 1) + if (mod == 1) return decode_rm01_address(rm); return decode_rm10_address(rm); } diff --git a/src/device/oprom/x86emu/ops.c b/src/device/oprom/x86emu/ops.c index c805b58..68658b1 100644 --- a/src/device/oprom/x86emu/ops.c +++ b/src/device/oprom/x86emu/ops.c @@ -211,7 +211,7 @@ static void x86emuOp_genop_byte_RM_R(u8 op1) DECODE_PRINTF(x86emu_GenOpName[op1]); DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); - if(mod<3) + if (mod<3) { destoffset = decode_rmXX_address(mod,rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); @@ -251,7 +251,7 @@ static void x86emuOp_genop_word_RM_R(u8 op1) DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); - if(mod<3) { + if (mod<3) { destoffset = decode_rmXX_address(mod,rl); if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; diff --git a/src/device/oprom/x86emu/ops2.c b/src/device/oprom/x86emu/ops2.c index 95ec09a..6089b1f 100644 --- a/src/device/oprom/x86emu/ops2.c +++ b/src/device/oprom/x86emu/ops2.c @@ -1507,7 +1507,7 @@ static void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) TRACE_AND_STEP(); srcval = fetch_data_long(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + for (*dstreg = 0; *dstreg < 32; (*dstreg)++) if ((srcval >> *dstreg) & 1) break; } else { u16 srcval, *dstreg; @@ -1516,7 +1516,7 @@ static void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) TRACE_AND_STEP(); srcval = fetch_data_word(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + for (*dstreg = 0; *dstreg < 16; (*dstreg)++) if ((srcval >> *dstreg) & 1) break; } } else { /* register to register */ @@ -1528,7 +1528,7 @@ static void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) dstreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + for (*dstreg = 0; *dstreg < 32; (*dstreg)++) if ((srcval >> *dstreg) & 1) break; } else { u16 srcval, *dstreg; @@ -1538,7 +1538,7 @@ static void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) dstreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + for (*dstreg = 0; *dstreg < 16; (*dstreg)++) if ((srcval >> *dstreg) & 1) break; } } @@ -1568,7 +1568,7 @@ static void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) TRACE_AND_STEP(); srcval = fetch_data_long(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + for (*dstreg = 31; *dstreg > 0; (*dstreg)--) if ((srcval >> *dstreg) & 1) break; } else { u16 srcval, *dstreg; @@ -1577,7 +1577,7 @@ static void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) TRACE_AND_STEP(); srcval = fetch_data_word(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + for (*dstreg = 15; *dstreg > 0; (*dstreg)--) if ((srcval >> *dstreg) & 1) break; } } else { /* register to register */ @@ -1589,7 +1589,7 @@ static void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) dstreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + for (*dstreg = 31; *dstreg > 0; (*dstreg)--) if ((srcval >> *dstreg) & 1) break; } else { u16 srcval, *dstreg; @@ -1599,7 +1599,7 @@ static void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) dstreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + for (*dstreg = 15; *dstreg > 0; (*dstreg)--) if ((srcval >> *dstreg) & 1) break; } } diff --git a/src/device/oprom/x86emu/prim_ops.c b/src/device/oprom/x86emu/prim_ops.c index 08a22bd..8b2c38a 100644 --- a/src/device/oprom/x86emu/prim_ops.c +++ b/src/device/oprom/x86emu/prim_ops.c @@ -2295,7 +2295,7 @@ Implements the IN string instruction and side effects. static void single_in(int size) { - if(size == 1) + if (size == 1) store_data_byte_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inb)(M.x86.R_DX)); else if (size == 2) store_data_word_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inw)(M.x86.R_DX)); @@ -2337,7 +2337,7 @@ Implements the OUT string instruction and side effects. static void single_out(int size) { - if(size == 1) + if (size == 1) (*sys_outb)(M.x86.R_DX,fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); else if (size == 2) (*sys_outw)(M.x86.R_DX,fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI));

1 0

New patch to review for coreboot: src/device: Unnecessary whitespace before "\n" removed
by HAOUAS Elyes 21 Aug '16

21 Aug '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16288 -gerrit commit 9306b95b6d6647622b33bee672952d7bd0d5a912 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 18:21:59 2016 +0200 src/device: Unnecessary whitespace before "\n" removed Change-Id: I3536a99a1a6fd2bc7b10777654c1937b92e8eacd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/device/oprom/x86emu/debug.c | 2 +- src/device/oprom/x86emu/ops.c | 6 +++--- src/device/oprom/x86emu/sys.c | 12 ++++++------ src/device/oprom/yabel/device.c | 6 +++--- src/device/oprom/yabel/interrupt.c | 2 +- src/device/oprom/yabel/vbe.c | 2 +- 6 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/device/oprom/x86emu/debug.c b/src/device/oprom/x86emu/debug.c index bc249a9..9e216e9 100644 --- a/src/device/oprom/x86emu/debug.c +++ b/src/device/oprom/x86emu/debug.c @@ -400,7 +400,7 @@ void x86emu_dump_xregs (void) printf("\tEAX=%08x ", M.x86.R_EAX ); printf("EBX=%08x ", M.x86.R_EBX ); printf("ECX=%08x ", M.x86.R_ECX ); - printf("EDX=%08x \n", M.x86.R_EDX ); + printf("EDX=%08x\n", M.x86.R_EDX ); printf("\tESP=%08x ", M.x86.R_ESP ); printf("EBP=%08x ", M.x86.R_EBP ); printf("ESI=%08x ", M.x86.R_ESI ); diff --git a/src/device/oprom/x86emu/ops.c b/src/device/oprom/x86emu/ops.c index c805b58..803e0c6 100644 --- a/src/device/oprom/x86emu/ops.c +++ b/src/device/oprom/x86emu/ops.c @@ -4986,7 +4986,7 @@ static void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) case 5: case 6: case 7: - DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); + DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x\n", mod); HALT_SYS(); break; } @@ -5183,7 +5183,7 @@ static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) M.x86.R_IP = *destreg; break; case 3: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + DECODE_PRINTF("OPERATION UNDEFINED 0XFF\n"); TRACE_AND_STEP(); HALT_SYS(); break; @@ -5195,7 +5195,7 @@ static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) M.x86.R_IP = (u16) (*destreg); break; case 5: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + DECODE_PRINTF("OPERATION UNDEFINED 0XFF\n"); TRACE_AND_STEP(); HALT_SYS(); break; diff --git a/src/device/oprom/x86emu/sys.c b/src/device/oprom/x86emu/sys.c index e550c45..afb7efb 100644 --- a/src/device/oprom/x86emu/sys.c +++ b/src/device/oprom/x86emu/sys.c @@ -215,7 +215,7 @@ Default PIO byte read function. Doesn't perform real inb. static u8 X86API p_inb(X86EMU_pioAddr addr) { DB(if (DEBUG_IO_TRACE()) - printf("inb %#04x \n", addr);) + printf("inb %#04x\n", addr);) return inb(addr); } @@ -230,7 +230,7 @@ Default PIO word read function. Doesn't perform real inw. static u16 X86API p_inw(X86EMU_pioAddr addr) { DB(if (DEBUG_IO_TRACE()) - printf("inw %#04x \n", addr);) + printf("inw %#04x\n", addr);) return inw(addr); } @@ -245,7 +245,7 @@ Default PIO long read function. Doesn't perform real inl. static u32 X86API p_inl(X86EMU_pioAddr addr) { DB(if (DEBUG_IO_TRACE()) - printf("inl %#04x \n", addr);) + printf("inl %#04x\n", addr);) return inl(addr); } @@ -259,7 +259,7 @@ Default PIO byte write function. Doesn't perform real outb. static void X86API p_outb(X86EMU_pioAddr addr, u8 val) { DB(if (DEBUG_IO_TRACE()) - printf("outb %#02x -> %#04x \n", val, addr);) + printf("outb %#02x -> %#04x\n", val, addr);) outb(val, addr); return; } @@ -274,7 +274,7 @@ Default PIO word write function. Doesn't perform real outw. static void X86API p_outw(X86EMU_pioAddr addr, u16 val) { DB(if (DEBUG_IO_TRACE()) - printf("outw %#04x -> %#04x \n", val, addr);) + printf("outw %#04x -> %#04x\n", val, addr);) outw(val, addr); return; } @@ -289,7 +289,7 @@ Default PIO ;ong write function. Doesn't perform real outl. static void X86API p_outl(X86EMU_pioAddr addr, u32 val) { DB(if (DEBUG_IO_TRACE()) - printf("outl %#08x -> %#04x \n", val, addr);) + printf("outl %#08x -> %#04x\n", val, addr);) outl(val, addr); return; diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index a1961bb..ee920d5 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -97,7 +97,7 @@ biosemu_dev_get_addr_info(void) taa_index++; /* legacy ranges if its a VGA card... */ if ((bios_device.dev->class & 0xFF0000) == 0x030000) { - DEBUG_PRINTF("%s: VGA device found, adding legacy resources... \n", __func__); + DEBUG_PRINTF("%s: VGA device found, adding legacy resources...\n", __func__); /* I/O 0x3B0-0x3BB */ translate_address_array[taa_index].info = IORESOURCE_FIXED | IORESOURCE_IO; translate_address_array[taa_index].bus = bus; @@ -133,7 +133,7 @@ biosemu_dev_get_addr_info(void) taa_last_entry = taa_index - 1; #if CONFIG_X86EMU_DEBUG //dump translate_address_array - printf("translate_address_array: \n"); + printf("translate_address_array:\n"); translate_address_t ta; int i; for (i = 0; i <= taa_last_entry; i++) { @@ -217,7 +217,7 @@ biosemu_dev_get_addr_info(void) taa_last_entry = taa_index - 1; #if CONFIG_X86EMU_DEBUG //dump translate_address_array - printf("translate_address_array: \n"); + printf("translate_address_array:\n"); translate_address_t ta; for (i = 0; i <= taa_last_entry; i++) { ta = translate_address_array[i]; diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index 8748319..e826fbf 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -386,7 +386,7 @@ handleInt1a(void) #endif } else { DEBUG_PRINTF_INTR - ("%s(): function %x: invalid device/vendor/device index! (%04x/%04x/%02x expected: %04x/%04x/00) \n", + ("%s(): function %x: invalid device/vendor/device index! (%04x/%04x/%02x expected: %04x/%04x/00)\n", __func__, M.x86.R_AX, M.x86.R_CX, M.x86.R_DX, M.x86.R_SI, bios_device.pci_device_id, bios_device.pci_vendor_id); diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 9a5b45a..219ef91 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -505,7 +505,7 @@ vbe_get_info(void) DEBUG_PRINTF_VBE("DDC: edid_tranfer_time: %d\n", ddc_info.edid_transfer_time); DEBUG_PRINTF_VBE("DDC: ddc_level: %x\n", ddc_info.ddc_level); - DEBUG_PRINTF_VBE("DDC: EDID: \n"); + DEBUG_PRINTF_VBE("DDC: EDID:\n"); CHECK_DBG(DEBUG_VBE) { dump(ddc_info.edid_block_zero, sizeof(ddc_info.edid_block_zero));

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Patch set updated for coreboot: src/arch: space required before the open parenthesis '('
by HAOUAS Elyes 21 Aug '16

21 Aug '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16287 -gerrit commit 41a60483cd861d5047c84e90a2c54c16492c48e1 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 17:37:15 2016 +0200 src/arch: space required before the open parenthesis '(' Change-Id: I8a44a58506d7cf5ebc9fe7ac4f2b46f9544ba61a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/arch/arm/armv7/thread.c | 2 +- src/arch/x86/acpi.c | 2 +- src/arch/x86/acpigen.c | 2 +- src/arch/x86/cpu.c | 6 +++--- src/arch/x86/exception.c | 4 ++-- src/arch/x86/include/arch/io.h | 6 +++--- src/arch/x86/mpspec.c | 12 ++++++------ src/arch/x86/pirq_routing.c | 6 +++--- src/arch/x86/smbios.c | 8 ++++---- 9 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c index 6ed7e96..53ca2b3 100644 --- a/src/arch/arm/armv7/thread.c +++ b/src/arch/arm/armv7/thread.c @@ -55,7 +55,7 @@ void arch_prepare_thread(struct thread *t, * hunting for (e.g.) misaligned stacks or other such * weirdness. The -1 is because we already pushed lr. */ - for(i = 0; i < sizeof(struct pushed_regs)/sizeof(u32)-1; i++) + for (i = 0; i < sizeof(struct pushed_regs)/sizeof(u32)-1; i++) stack = push_stack(stack, poison++); t->stack_current = stack; diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 4ebdcbe..50526a5 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -814,7 +814,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt) fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; - if(IS_ENABLED(CONFIG_SYSTEM_TYPE_LAPTOP)) { + if (IS_ENABLED(CONFIG_SYSTEM_TYPE_LAPTOP)) { fadt->preferred_pm_profile = PM_MOBILE; } else { fadt->preferred_pm_profile = PM_DESKTOP; diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index f35fe02..f8e3ae9 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -298,7 +298,7 @@ void acpigen_emit_namestring(const char *namepath) { /* If we have only \\ or only ^...^. Then we need to put a null name (0x00). */ - if(namepath[0] == '\0') { + if (namepath[0] == '\0') { acpigen_emit_byte(0x00); return; } diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 0fdc11c..fbd48b0 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -196,7 +196,7 @@ static void identify_cpu(struct device *cpu) } } cpu->vendor = X86_VENDOR_UNKNOWN; - for(i = 0; i < ARRAY_SIZE(x86_vendors); i++) { + for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { cpu->vendor = x86_vendors[i].vendor; break; @@ -267,12 +267,12 @@ void cpu_initialize(unsigned int index) /* Lookup the cpu's operations */ set_cpu_ops(cpu); - if(!cpu->ops) { + if (!cpu->ops) { /* mask out the stepping and try again */ cpu->device -= c.x86_mask; set_cpu_ops(cpu); cpu->device += c.x86_mask; - if(!cpu->ops) die("Unknown cpu"); + if (!cpu->ops) die("Unknown cpu"); printk(BIOS_DEBUG, "Using generic CPU ops (good)\n"); } diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index cbf0358..84328be 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -513,9 +513,9 @@ void x86_exception(struct eregs *info) * evident from the looking at the dump */ code = (u8*)((uintptr_t)code & ~0x7); int i; - for(i = 0; i < MDUMP_SIZE; i++) + for (i = 0; i < MDUMP_SIZE; i++) { - if( (i & 0x07) == 0 ) + if ( (i & 0x07) == 0 ) printk(BIOS_EMERG, "\n%p:\t", code + i); printk(BIOS_EMERG, "%.2x ", code[i]); } diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index a71e1a4..69922e2 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -267,7 +267,7 @@ void pci_or_config32(pci_devfn_t dev, unsigned where, uint32_t value) #define PCI_DEV_INVALID (0xffffffffU) static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev) { - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_io_read_config32(dev, 0); if (id == pci_id) { @@ -279,7 +279,7 @@ static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev) static inline pci_devfn_t pci_locate_device(unsigned pci_id, pci_devfn_t dev) { - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_read_config32(dev, 0); if (id == pci_id) { @@ -296,7 +296,7 @@ static inline pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); - for(; dev <=last; dev += PCI_DEV(0,0,1)) { + for (; dev <=last; dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_read_config32(dev, 0); if (id == pci_id) { diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index d91adf8..5f251e3 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -63,7 +63,7 @@ static unsigned char smp_compute_checksum(void *v, int len) int i; bytes = v; checksum = 0; - for(i = 0; i < len; i++) { + for (i = 0; i < len; i++) { checksum -= bytes[i]; } return checksum; @@ -170,8 +170,8 @@ void smp_write_processors(struct mp_config_table *mc) cpu_features = result.eax; cpu_feature_flags = result.edx; /* order the output of the cpus to fix a bug in kernel 2.6.11 */ - for(order_id = 0;order_id <256; order_id++) { - for(cpu = all_devices; cpu; cpu = cpu->next) { + for (order_id = 0;order_id <256; order_id++) { + for (cpu = all_devices; cpu; cpu = cpu->next) { unsigned long cpu_flag; if ((cpu->path.type != DEVICE_PATH_APIC) || (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) @@ -185,7 +185,7 @@ void smp_write_processors(struct mp_config_table *mc) if (boot_apic_id == cpu->path.apic.apic_id) cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR; - if(cpu->path.apic.apic_id == order_id) { + if (cpu->path.apic.apic_id == order_id) { smp_write_processor(mc, cpu->path.apic.apic_id, apic_version, cpu_flag, cpu_features, cpu_feature_flags @@ -504,7 +504,7 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) mptable_write_buses(mc, NULL, &isa_bus); - for(dev = all_devices; dev; dev = dev->next) { + for (dev = all_devices; dev; dev = dev->next) { if (dev->path.type != DEVICE_PATH_IOAPIC) continue; @@ -530,7 +530,7 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) mptable_add_isa_interrupts(mc, isa_bus, isaioapic, 0); } - for(dev = all_devices; dev; dev = dev->next) { + for (dev = all_devices; dev; dev = dev->next) { if (dev->path.type != DEVICE_PATH_PCI || !dev->enabled) continue; diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 4d93114..f758dbb 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -110,14 +110,14 @@ static u8 pirq_get_next_free_irq(u8* pirq, u16 bitmap) /* And assume we have not yet routed it */ int already_routed = 0; /* Have we already routed it ? */ - for(link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) { + for (link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) { if (pirq[link] == irq) { already_routed = 1; break; } } /* If it's not yet routed, use it */ - if(!already_routed) + if (!already_routed) break; /* But if it was already routed, try the next one */ continue; @@ -179,7 +179,7 @@ static void pirq_route_irqs(unsigned long addr) pirq_tbl->slots[i].devfn >> 3, irq_slot); } - for(i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) + for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) printk(BIOS_DEBUG, "PIRQ%c: %d\n", i + 'A', pirq[i]); pirq_assign_irqs(pirq); diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 9df95e9..0c7f3ac 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -60,7 +60,7 @@ int smbios_add_string(char *start, const char *str) if (*str == '\0') return 0; - for(;;) { + for (;;) { if (!*p) { strcpy(p, str); p += strlen(str); @@ -419,7 +419,7 @@ static int smbios_write_type3(unsigned long *current, int handle) t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; t->thermal_state = SMBIOS_STATE_SAFE; - if(IS_ENABLED(CONFIG_SYSTEM_TYPE_LAPTOP)) { + if (IS_ENABLED(CONFIG_SYSTEM_TYPE_LAPTOP)) { t->_type = SMBIOS_ENCLOSURE_NOTEBOOK; } else { t->_type = SMBIOS_ENCLOSURE_DESKTOP; @@ -476,7 +476,7 @@ static int smbios_write_type11(unsigned long *current, int *handle) t->handle = *handle; t->length = len = sizeof *t - 2; - for(dev = all_devices; dev; dev = dev->next) { + for (dev = all_devices; dev; dev = dev->next) { if (dev->ops && dev->ops->get_smbios_strings) dev->ops->get_smbios_strings(dev, t); } @@ -572,7 +572,7 @@ static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned lo struct device *dev; int len = 0; - for(dev = tree; dev; dev = dev->next) { + for (dev = tree; dev; dev = dev->next) { printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), dev_name(dev)); if (dev->ops && dev->ops->get_smbios_data)

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coreboot-gerrit August 2016