coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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1820 discussions

Patch merged into coreboot/master: google/urara: Provide dummy implementations of rec/dev functions
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit c66a02634c1d4b0f7929cb9f4c510fff56db0ca6 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 25 16:59:00 2016 -0700 google/urara: Provide dummy implementations of rec/dev functions This is required to enable elog support in ChromeOS by default. BUG=chrome-os-partner:55639 Change-Id: I9c97143d794de4bf220ddf67c0ca2eac2f7a326d Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15896 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/15896 for details. -gerrit

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Patch merged into coreboot/master: qualcomm/gale: Add required files to enable elog in ramstage
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit faf07a8fabb142c8862bfe85ddd1e677e195e023 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 25 16:58:15 2016 -0700 qualcomm/gale: Add required files to enable elog in ramstage BUG=chrome-os-partner:55639 Change-Id: Idbad4f8763be18002907a62be755b2fdf7e479ec Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15895 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/15895 for details. -gerrit

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Patch merged into coreboot/master: qualcomm/storm: Add required files to enable elog in ramstage
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit a7f11b8ecf94d8ddb09f5dbfeff14dfee66e372d Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 25 16:57:46 2016 -0700 qualcomm/storm: Add required files to enable elog in ramstage BUG=chrome-os-partner:55639 Change-Id: Ie859ec3ff682e91a4d7d38d3c3cd6badf7385431 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15894 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/15894 for details. -gerrit

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Patch merged into coreboot/master: i2c/ww_ring: Add ww_ring files to ramstage
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit 01ac811b08b6e4dbae4aa979cc23910a261e6310 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 25 16:56:44 2016 -0700 i2c/ww_ring: Add ww_ring files to ramstage These files are required by storm and gale boards for enabling elog support in ramstage. BUG=chrome-os-partner:55639 Change-Id: I2bbfee2acf2bfe2f896a8619b1276dcea1b87f16 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15893 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/15893 for details. -gerrit

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Patch merged into coreboot/master: google/chromeos: Use vboot bootmode functions for elog add boot reason
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit 18b02c5630ce0c1edfa2b87168043d92fc473ab8 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 25 13:26:32 2016 -0700 google/chromeos: Use vboot bootmode functions for elog add boot reason BUG=chrome-os-partner:55639 Change-Id: I3ac2b256862758bb5c9e6c2f1311972af474e8f6 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15870 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15870 for details. -gerrit

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Patch merged into coreboot/master: bootmode: Get rid of CONFIG_BOOTMODE_STRAPS
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit 0325dc6f7cbdad4fd29315bfcb7f4e54fb678f3e Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 25 13:02:36 2016 -0700 bootmode: Get rid of CONFIG_BOOTMODE_STRAPS With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and developer mode check functions to vboot. Thus, get rid of the BOOTMODE_STRAPS option which controlled these functions under src/lib. BUG=chrome-os-partner:55639 Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15868 for details. -gerrit

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Patch merged into coreboot/master: vboot: Separate vboot from chromeos
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit 2a12e2e8da2477d97b8774babd1a74dda65d11a0 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 25 11:48:03 2016 -0700 vboot: Separate vboot from chromeos VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use of verified boot library without having to stick to CHROMEOS. BUG=chrome-os-partner:55639 Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15867 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/15867 for details. -gerrit

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Patch set updated for coreboot: google/reef: Enable DPTF in mainboard
by Shaunak Saha 28 Jul '16

28 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15640 -gerrit commit f9611cba009623670e5efd7e9acf07c5571186a6 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jul 12 16:03:29 2016 -0700 google/reef: Enable DPTF in mainboard This patch enables DPTF support for Google Reef platform, adds the ASL settings specific to Reef boards. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal in Reef boards. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: Ib43e4e9dd0d92fffc1b2c8459c552acd04ca0150 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/google/reef/acpi/dptf.asl | 130 ++++++++++++++++++++++++++++++++ src/mainboard/google/reef/devicetree.cb | 3 + src/mainboard/google/reef/dsdt.asl | 5 ++ 3 files changed, 138 insertions(+) diff --git a/src/mainboard/google/reef/acpi/dptf.asl b/src/mainboard/google/reef/acpi/dptf.asl new file mode 100644 index 0000000..eec108f --- /dev/null +++ b/src/mainboard/google/reef/acpi/dptf.asl @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +#ifdef DPTF_ENABLE_FAN_CONTROL +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO: Need to update this table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {100, 0xFFFFFFFF, 4986, 220, 2200}, + Package () {90, 0xFFFFFFFF, 4804, 180, 1800}, + Package () {80, 0xFFFFFFFF, 4512, 145, 1450}, + Package () {70, 0xFFFFFFFF, 4204, 115, 1150}, + Package () {60, 0xFFFFFFFF, 3838, 90, 900}, + Package () {50, 0xFFFFFFFF, 3402, 65, 650}, + Package () {40, 0xFFFFFFFF, 2904, 45, 450}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 100, 90, 80, 70, 60, 0, 0, + 0, 0, 0 + } +}) +#endif + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 6000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include soc specific DPTF changes */ +#include <soc/intel/apollolake/acpi/dptf.asl> +/* Include common dptf ASL files */ +#include <soc/intel/common/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index a04a3cd..0763a6d 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -31,6 +31,9 @@ chip soc/intel/apollolake # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 register "emmc_rx_cmd_data_cntl2" = "0x1001C" + # Enable DPTF + register "dptf_enable" = "1" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route, i.e., if this route changes then the affected GPE diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 7a88fb6..c035371 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -46,4 +46,9 @@ DefinitionBlock( /* Mainboard Specific devices */ #include "acpi/mainboard.asl" + + Scope (\_SB) { + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } }

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Patch set updated for coreboot: intel/apollolake: Update gnvs for dptf
by Shaunak Saha 28 Jul '16

28 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15620 -gerrit commit 2ba45bb9e99fd44c888fd1acff3c6234d88d0dc1 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jul 12 01:22:33 2016 -0700 intel/apollolake: Update gnvs for dptf This patch updates dptf variable in gnvs based on device configuration by reading the device tree structure. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal in Amenia and Reef board. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: I8ab34cdc94d8cdc840b02347569a9f07688e92cd Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 14 ++++++++++++++ src/soc/intel/apollolake/chip.h | 3 +++ 2 files changed, 17 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a38c377..262e140 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -27,6 +27,8 @@ #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> +#include <soc/pci_devs.h> +#include "chip.h" #define CSTATE_RES(address_space, width, offset, address) \ { \ @@ -146,6 +148,15 @@ unsigned long southbridge_write_acpi_tables(device_t device, static void acpi_create_gnvs(struct global_nvs_t *gnvs) { + struct soc_intel_apollolake_config *cfg; + struct device *dev = NB_DEV_ROOT; + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + cfg = dev->chip_info; + if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); @@ -154,6 +165,9 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) chromeos_init_vboot(&gnvs->chromeos); gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } + + /* Enable DPTF based on mainboard configuration */ + gnvs->dpte = cfg->dptf_enable; } void southbridge_inject_dsdt(device_t device) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index a1df481..37b1cc0 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -102,6 +102,9 @@ struct soc_intel_apollolake_config { /* Configure LPSS S0ix Enable */ uint8_t lpss_s0ix_enable; + + /* Enable DPTF support */ + int dptf_enable; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */

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Patch set updated for coreboot: intel/common: Add ASL code for DPTF
by Shaunak Saha 28 Jul '16

28 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15093 -gerrit commit 76bd2432d402916f6f45bd9445685f1e8cfecf88 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jun 7 00:05:00 2016 -0700 intel/common: Add ASL code for DPTF This patch adds the common ASL code for Intel platforms. This is the basic ASL needed to add support for DPTF controlled devices. We are moving these commmon ASL files to src/soc/intel/common/acpi as these are same codes used in all Intel platforms and hence no need to duplicate. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: I01078382a9008263c6ad99f6bf07558885af6a63 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/common/acpi/dptf/charger.asl | 75 ++++++++ src/soc/intel/common/acpi/dptf/cpu.asl | 196 ++++++++++++++++++++ src/soc/intel/common/acpi/dptf/dptf.asl | 116 ++++++++++++ src/soc/intel/common/acpi/dptf/fan.asl | 68 +++++++ src/soc/intel/common/acpi/dptf/thermal.asl | 283 +++++++++++++++++++++++++++++ 5 files changed, 738 insertions(+) diff --git a/src/soc/intel/common/acpi/dptf/charger.asl b/src/soc/intel/common/acpi/dptf/charger.asl new file mode 100644 index 0000000..fa54a5f --- /dev/null +++ b/src/soc/intel/common/acpi/dptf/charger.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (TCHG) +{ + Name (_HID, "INT3403") + Name (_UID, 0) + Name (PTYP, 0x0B) + Name (_STR, Unicode("Battery Charger")) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Return charger performance states defined by mainboard */ + Method (PPSS) + { + Return (\_SB.CHPS) + } + + /* Return maximum charger current limit */ + Method (PPPC) + { + /* Convert size of PPSS table to index */ + Store (SizeOf (\_SB.CHPS), Local0) + Decrement (Local0) + + /* Check if charging is disabled (AC removed) */ + If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) { + /* Return last power state */ + Return (Local0) + } Else { + /* Return highest power state */ + Return (0) + } + + Return (0) + } + + /* Set charger current limit */ + Method (SPPC, 1) + { + /* Retrieve Control (index 4) for specified PPSS level */ + Store (DeRefOf (Index (DeRefOf (Index + (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0) + + /* Pass Control value to EC to limit charging */ + \_SB.PCI0.LPCB.EC0.CHGS (Local0) + } + + /* Initialize charger participant */ + Method (INIT) + { + /* Disable charge limit */ + \_SB.PCI0.LPCB.EC0.CHGD () + } +} diff --git a/src/soc/intel/common/acpi/dptf/cpu.asl b/src/soc/intel/common/acpi/dptf/cpu.asl new file mode 100644 index 0000000..c28c0cc --- /dev/null +++ b/src/soc/intel/common/acpi/dptf/cpu.asl @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +External (\_PR.CP00._PSS, PkgObj) +External (\_PR.CP00._TSS, PkgObj) +External (\_PR.CP00._TPC, MethodObj) +External (\_PR.CP00._PTC, PkgObj) +External (\_PR.CP00._TSD, PkgObj) +External (\_SB.MPDL, IntObj) + +Device (DPTF_CPU_DEVICE) +{ + Name(_ADR, 0x00000001) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* + * Processor Throttling Controls + */ + + Method (_TSS) + { + If (CondRefOf (\_PR.CP00._TSS)) { + Return (\_PR.CP00._TSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0 } + }) + } + } + + Method (_TPC) + { + If (CondRefOf (\_PR.CP00._TPC)) { + Return (\_PR.CP00._TPC) + } Else { + Return (0) + } + } + + Method (_PTC) + { + If (CondRefOf (\_PR.CP00._PTC)) { + Return (\_PR.CP00._PTC) + } Else { + Return (Package () + { + Buffer () { 0 }, + Buffer () { 0 } + }) + } + } + + Method (_TSD) + { + If (CondRefOf (\_PR.CP00._TSD)) { + Return (\_PR.CP00._TSD) + } Else { + Return (Package () + { + Package () { 5, 0, 0, 0, 0 } + }) + } + } + + Method (_TDL) + { + If (CondRefOf (\_PR.CP00._TSS)) { + Store (SizeOf (\_PR.CP00._TSS), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* + * Processor Performance Control + */ + + Method (_PPC) + { + Return (0) + } + + Method (SPPC, 1) + { + Store (Arg0, \PPCM) + + /* Notify OS to re-read _PPC limit on each CPU */ + \PPCN () + } + + Method (_PSS) + { + If (CondRefOf (\_PR.CP00._PSS)) { + Return (\_PR.CP00._PSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0, 0 } + }) + } + } + + + Method (_PDL) + { + /* Check for mainboard specific _PDL override */ + If (CondRefOf (\_SB.MPDL)) { + Return (\_SB.MPDL) + } ElseIf (CondRefOf (\_PR.CP00._PSS)) { + Store (SizeOf (\_PR.CP00._PSS), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* Return PPCC table defined by mainboard */ + Method (PPCC) + { + Return (\_SB.MPPC) + } + +#ifdef DPTF_CPU_CRITICAL + Method (_CRT) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_CRITICAL)) + } +#endif + +#ifdef DPTF_CPU_PASSIVE + Method (_PSV) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_PASSIVE)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC0)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC1)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC2)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC3)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC4)) + } +#endif +} diff --git a/src/soc/intel/common/acpi/dptf/dptf.asl b/src/soc/intel/common/acpi/dptf/dptf.asl new file mode 100644 index 0000000..beb41e2 --- /dev/null +++ b/src/soc/intel/common/acpi/dptf/dptf.asl @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (DPTF) +{ + Name (_HID, EISAID ("INT3400")) + Name (_UID, 0) + + Name (IDSP, Package() + { + /* DPPM Passive Policy 1.0 */ + ToUUID ("42A441D6-AE6A-462B-A84B-4A8CE79027D3"), + + /* DPPM Critical Policy */ + ToUUID ("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"), + + /* DPPM Cooling Policy */ + ToUUID ("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"), + +#ifdef DPTF_ENABLE_FAN_CONTROL + /* DPPM Active Policy */ + ToUUID ("3A95C389-E4B8-4629-A526-C52C88626BAE"), +#endif + }) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* + * Arg0: Buffer containing UUID + * Arg1: Integer containing Revision ID of buffer format + * Arg2: Integer containing count of entries in Arg3 + * Arg3: Buffer containing list of DWORD capabilities + * Return: Buffer containing list of DWORD capabilities + */ + Method (_OSC, 4, Serialized) + { + /* Check for Passive Policy UUID */ + If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) { + /* Initialize Thermal Devices */ + ^TINI () + +#ifdef DPTF_ENABLE_CHARGER + /* Initialize Charger Device */ + ^TCHG.INIT () +#endif + } + + Return (Arg3) + } + + /* Priority based _TRT */ + Name (TRTR, 1) + + Method (_TRT) + { + Return (\_SB.DTRT) + } + +#ifdef DPTF_ENABLE_FAN_CONTROL + /* _ART : Active Cooling Relationship Table */ + Method (_ART) + { + Return (\_SB.DART) + } +#endif + + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ + Method (CTOK, 1) { + /* 10th of Degrees C */ + Multiply (Arg0, 10, Local0) + + /* Convert to Kelvin */ + Add (Local0, 2732, Local0) + + Return (Local0) + } + + /* Include Thermal Participants */ + #include "thermal.asl" + +#ifdef DPTF_ENABLE_CHARGER + /* Include Charger Participant */ + #include "charger.asl" +#endif + +#ifdef DPTF_ENABLE_FAN_CONTROL + /* Include Fan Participant */ + #include "fan.asl" +#endif + +} + +Scope (\_SB.PCI0) +{ + #include "cpu.asl" +} diff --git a/src/soc/intel/common/acpi/dptf/fan.asl b/src/soc/intel/common/acpi/dptf/fan.asl new file mode 100644 index 0000000..a748088 --- /dev/null +++ b/src/soc/intel/common/acpi/dptf/fan.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (TFN1) +{ + Name (_HID, "INT3404") + Name (_UID, 0) + Name (_STR, Unicode("Fan Control")) + + /* _FIF: Fan Information */ + Name (_FIF, Package () + { + 0, // Revision + 1, // Fine Grained Control + 2, // Step Size + 0 // No Low Speed Notification + }) + + /* Return Fan Performance States defined by mainboard */ + Method (_FPS) + { + Return (\_SB.DFPS) + } + + Name (TFST, Package () + { + 0, // Revision + 0x00, // Control + 0x00 // Speed + }) + + /* _FST: Fan current Status */ + Method (_FST, 0, Serialized,,PkgObj) + { + /* Fill in TFST with current control. */ + Store (\_SB.PCI0.LPCB.EC0.FAND, Index (TFST, 1)) + Return (TFST) + } + + /* _FSL: Fan Speed Level */ + Method (_FSL, 1, Serialized) + { + Store (Arg0, \_SB.PCI0.LPCB.EC0.FAND) + Notify (DPTF, 0x83) // Reevaluate _ART + } + + Method (_STA) + { + If (LEqual (\DPTE, One)) + { + Return (0xF) + } Else { + Return (0x0) + } + } +} diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl new file mode 100644 index 0000000..ce220c4 --- /dev/null +++ b/src/soc/intel/common/acpi/dptf/thermal.asl @@ -0,0 +1,283 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Thermal Threshold Event Handler */ +Method (TEVT, 1, NotSerialized) +{ + Store (ToInteger (Arg0), Local0) + +#ifdef DPTF_TSR0_SENSOR_ID + If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) { + Notify (^TSR0, 0x90) + } +#endif +#ifdef DPTF_TSR1_SENSOR_ID + If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) { + Notify (^TSR1, 0x90) + } +#endif +#ifdef DPTF_TSR2_SENSOR_ID + If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) { + Notify (^TSR2, 0x90) + } +#endif +#ifdef DPTF_TSR3_SENSOR_ID + If (LEqual (Local0, DPTF_TSR3_SENSOR_ID)) { + Notify (^TSR3, 0x90) + } +#endif +} + +/* Thermal device initialization - Disable Aux Trip Points */ +Method (TINI) +{ +#ifdef DPTF_TSR0_SENSOR_ID + ^TSR0.PATD () +#endif +#ifdef DPTF_TSR1_SENSOR_ID + ^TSR1.PATD () +#endif +#ifdef DPTF_TSR2_SENSOR_ID + ^TSR2.PATD () +#endif +#ifdef DPTF_TSR3_SENSOR_ID + ^TSR3.PATD () +#endif +} + +#ifdef DPTF_TSR0_SENSOR_ID +Device (TSR0) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 1) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR0_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (CTOK (DPTF_TSR0_PASSIVE)) + } + + Method (_CRT) + { + Return (CTOK (DPTF_TSR0_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } +} +#endif + +#ifdef DPTF_TSR1_SENSOR_ID +Device (TSR1) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 2) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR1_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (CTOK (DPTF_TSR1_PASSIVE)) + } + + Method (_CRT) + { + Return (CTOK (DPTF_TSR1_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } +} +#endif + +#ifdef DPTF_TSR2_SENSOR_ID +Device (TSR2) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 3) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR2_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (CTOK (DPTF_TSR2_PASSIVE)) + } + + Method (_CRT) + { + Return (CTOK (DPTF_TSR2_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } +} +#endif + +#ifdef DPTF_TSR3_SENSOR_ID +Device (TSR3) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 4) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR3_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR3_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (CTOK (DPTF_TSR3_PASSIVE)) + } + + Method (_CRT) + { + Return (CTOK (DPTF_TSR3_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } +} +#endif

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coreboot-gerrit July 2016