coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: skylake/devicetree: Add LPC EC decode range
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit 89f6d6079ef88ff20c7da3422d1298d614ed6b5a Author: Subrata Banik <subrata.banik(a)intel.com> Date: Tue Jul 26 15:37:11 2016 +0530 skylake/devicetree: Add LPC EC decode range Define LPC decode ranges for EC communication. BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu to ensure no EC timeout error Change-Id: Idefdd79e67e89a794195c6821fee16550d1eda53 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/15898 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15898 for details. -gerrit

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Patch merged into coreboot/master: skylake/mainboard: Define mainboard hook in bootblock
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit 50b9258a0bbe6cf99606c87a5b9b835ff0689a7d Author: Subrata Banik <subrata.banik(a)intel.com> Date: Thu Jul 21 23:47:38 2016 +0530 skylake/mainboard: Define mainboard hook in bootblock Move mainboard post console init functionality (google_chrome_ec_init & early_gpio programming) from verstage to bootblock. Add chromeos-ec support in bootblock BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu till POST code 0x34 Change-Id: I1b912985a0234d103dcf025b1a88094e639d197d Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/15786 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15786 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/skylake: Add C entry bootblock support
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit e4a8537ce20d801a5985ba6268ae83593063a4bf Author: Subrata Banik <subrata.banik(a)intel.com> Date: Sun Jul 24 00:36:12 2016 +0530 soc/intel/skylake: Add C entry bootblock support List of activity performing in this patch - early PCH programming - early SA programming - early CPU programming - mainborad early gpio programming for UART and SPI - car setup - move chipset programming from verstage to post console BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and booted kunimitsu till POST code 0x34 Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/15785 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15785 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/skylake: Do cache as ram and prepare for C entry
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit 68d5d8b28ab399b8dfb8ef6477d25311a319f2d5 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Jul 18 14:13:52 2016 +0530 soc/intel/skylake: Do cache as ram and prepare for C entry Enable cache-as-ram and prepare for c entry in bootblock. BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and booted kunimitsu till POST code 0x2A Credits-to: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I3412216cdf8ef7e952145943d33c3f07949da3c1 Reviewed-on: https://review.coreboot.org/15784 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15784 for details. -gerrit

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Patch set updated for coreboot: chromeos mainboards: remove chromeos.asl
by Aaron Durbin 28 Jul '16

28 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15909 -gerrit commit 3127e2ce1778242889812162f88bb02beb4ba850 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 25 21:31:41 2016 -0500 chromeos mainboards: remove chromeos.asl Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/auron/acpi/chromeos.asl | 19 ------ src/mainboard/google/auron/chromeos.c | 10 +++ src/mainboard/google/auron/dsdt.asl | 1 - src/mainboard/google/auron/mainboard.c | 2 + src/mainboard/google/auron_paine/acpi/chromeos.asl | 19 ------ src/mainboard/google/auron_paine/chromeos.c | 10 +++ src/mainboard/google/auron_paine/dsdt.asl | 1 - src/mainboard/google/auron_paine/mainboard.c | 2 + src/mainboard/google/butterfly/acpi/chromeos.asl | 20 ------ src/mainboard/google/butterfly/chromeos.c | 12 ++++ src/mainboard/google/butterfly/dsdt.asl | 1 - src/mainboard/google/butterfly/mainboard.c | 2 + src/mainboard/google/chell/acpi/chromeos.asl | 23 ------- src/mainboard/google/chell/chromeos.c | 10 +++ src/mainboard/google/chell/dsdt.asl | 1 - src/mainboard/google/chell/mainboard.c | 2 + src/mainboard/google/cyan/acpi/chromeos.asl | 33 ---------- src/mainboard/google/cyan/chromeos.c | 10 +++ src/mainboard/google/cyan/dsdt.asl | 1 - src/mainboard/google/cyan/mainboard.c | 2 + src/mainboard/google/falco/acpi/chromeos.asl | 19 ------ src/mainboard/google/falco/chromeos.c | 11 ++++ src/mainboard/google/falco/dsdt.asl | 1 - src/mainboard/google/falco/mainboard.c | 2 + src/mainboard/google/glados/acpi/chromeos.asl | 23 ------- src/mainboard/google/glados/chromeos.c | 10 +++ src/mainboard/google/glados/dsdt.asl | 1 - src/mainboard/google/glados/mainboard.c | 2 + src/mainboard/google/guado/acpi/chromeos.asl | 19 ------ src/mainboard/google/guado/chromeos.c | 10 +++ src/mainboard/google/guado/dsdt.asl | 1 - src/mainboard/google/guado/mainboard.c | 2 + src/mainboard/google/jecht/acpi/chromeos.asl | 19 ------ src/mainboard/google/jecht/chromeos.c | 10 +++ src/mainboard/google/jecht/dsdt.asl | 1 - src/mainboard/google/jecht/mainboard.c | 2 + src/mainboard/google/lars/acpi/chromeos.asl | 24 -------- src/mainboard/google/lars/chromeos.c | 10 +++ src/mainboard/google/lars/dsdt.asl | 1 - src/mainboard/google/lars/mainboard.c | 2 + src/mainboard/google/link/acpi/chromeos.asl | 19 ------ src/mainboard/google/link/chromeos.c | 11 ++++ src/mainboard/google/link/dsdt.asl | 1 - src/mainboard/google/link/mainboard.c | 2 + src/mainboard/google/ninja/acpi/chromeos.asl | 31 ---------- src/mainboard/google/ninja/chromeos.c | 12 +++- src/mainboard/google/ninja/dsdt.asl | 1 - src/mainboard/google/ninja/mainboard.c | 2 + src/mainboard/google/panther/acpi/chromeos.asl | 19 ------ src/mainboard/google/panther/chromeos.c | 10 +++ src/mainboard/google/panther/dsdt.asl | 1 - src/mainboard/google/panther/mainboard.c | 2 + src/mainboard/google/parrot/acpi/chromeos.asl | 20 ------ src/mainboard/google/parrot/chromeos.c | 12 ++++ src/mainboard/google/parrot/dsdt.asl | 1 - src/mainboard/google/parrot/mainboard.c | 2 + src/mainboard/google/peppy/acpi/chromeos.asl | 19 ------ src/mainboard/google/peppy/chromeos.c | 11 ++++ src/mainboard/google/peppy/dsdt.asl | 1 - src/mainboard/google/peppy/mainboard.c | 2 + src/mainboard/google/rambi/acpi/chromeos.asl | 32 ---------- src/mainboard/google/rambi/chromeos.c | 11 ++++ src/mainboard/google/rambi/dsdt.asl | 1 - src/mainboard/google/rambi/mainboard.c | 2 + src/mainboard/google/reef/acpi/chromeos.asl | 23 ------- src/mainboard/google/reef/chromeos.c | 11 ++++ src/mainboard/google/reef/dsdt.asl | 1 - src/mainboard/google/reef/mainboard.c | 2 + src/mainboard/google/rikku/acpi/chromeos.asl | 19 ------ src/mainboard/google/rikku/chromeos.c | 10 +++ src/mainboard/google/rikku/dsdt.asl | 1 - src/mainboard/google/rikku/mainboard.c | 2 + src/mainboard/google/samus/acpi/chromeos.asl | 19 ------ src/mainboard/google/samus/chromeos.c | 10 +++ src/mainboard/google/samus/dsdt.asl | 1 - src/mainboard/google/samus/mainboard.c | 2 + src/mainboard/google/stout/acpi/chromeos.asl | 22 ------- src/mainboard/google/stout/chromeos.c | 12 ++++ src/mainboard/google/stout/dsdt.asl | 1 - src/mainboard/google/stout/mainboard.c | 2 + src/mainboard/google/tidus/acpi/chromeos.asl | 19 ------ src/mainboard/google/tidus/chromeos.c | 10 +++ src/mainboard/google/tidus/dsdt.asl | 1 - src/mainboard/google/tidus/mainboard.c | 2 + src/mainboard/intel/amenia/acpi/chromeos.asl | 24 -------- src/mainboard/intel/amenia/chromeos.c | 11 ++++ src/mainboard/intel/amenia/dsdt.asl | 3 - src/mainboard/intel/baskingridge/acpi/chromeos.asl | 20 ------ src/mainboard/intel/baskingridge/chromeos.c | 12 ++++ src/mainboard/intel/baskingridge/dsdt.asl | 1 - src/mainboard/intel/baskingridge/mainboard.c | 4 +- src/mainboard/intel/emeraldlake2/acpi/chromeos.asl | 20 ------ src/mainboard/intel/emeraldlake2/chromeos.c | 12 ++++ src/mainboard/intel/emeraldlake2/dsdt.asl | 1 - src/mainboard/intel/emeraldlake2/mainboard.c | 2 + src/mainboard/intel/kunimitsu/acpi/chromeos.asl | 24 -------- src/mainboard/intel/kunimitsu/chromeos.c | 10 +++ src/mainboard/intel/kunimitsu/dsdt.asl | 1 - src/mainboard/intel/kunimitsu/mainboard.c | 2 + src/mainboard/intel/strago/acpi/chromeos.asl | 33 ---------- src/mainboard/intel/strago/chromeos.c | 10 +++ src/mainboard/intel/strago/dsdt.asl | 1 - src/mainboard/intel/strago/mainboard.c | 2 + src/mainboard/intel/wtm2/acpi/chromeos.asl | 20 ------ src/mainboard/intel/wtm2/chromeos.c | 12 ++++ src/mainboard/intel/wtm2/dsdt.asl | 1 - src/mainboard/intel/wtm2/mainboard.c | 2 + src/mainboard/samsung/lumpy/acpi/chromeos.asl | 20 ------ src/mainboard/samsung/lumpy/chromeos.c | 12 ++++ src/mainboard/samsung/lumpy/dsdt.asl | 1 - src/mainboard/samsung/lumpy/mainboard.c | 2 + src/mainboard/samsung/stumpy/acpi/chromeos.asl | 20 ------ src/mainboard/samsung/stumpy/chromeos.c | 12 ++++ src/mainboard/samsung/stumpy/dsdt.asl | 1 - src/mainboard/samsung/stumpy/mainboard.c | 2 + src/soc/intel/apollolake/include/soc/gpio_defs.h | 6 ++ src/soc/intel/baytrail/include/soc/gpio.h | 2 + src/soc/intel/braswell/include/soc/gpio.h | 2 + src/soc/intel/broadwell/include/soc/gpio.h | 3 + src/soc/intel/skylake/include/soc/gpio.h | 2 + src/southbridge/intel/bd82x6x/pch.h | 6 ++ src/southbridge/intel/lynxpoint/pch.h | 2 + src/vendorcode/google/chromeos/Makefile.inc | 1 + src/vendorcode/google/chromeos/acpi.c | 43 +++++++++++++ src/vendorcode/google/chromeos/acpi/chromeos.asl | 6 ++ src/vendorcode/google/chromeos/chromeos.h | 72 ++++++++++++++++++++++ 126 files changed, 514 insertions(+), 675 deletions(-) diff --git a/src/mainboard/google/auron/acpi/chromeos.asl b/src/mainboard/google/auron/acpi/chromeos.asl deleted file mode 100644 index 85b4415..0000000 --- a/src/mainboard/google/auron/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // no recovery button - Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 4447ddc..20685c6 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -82,3 +82,13 @@ int get_write_protect_state(void) { return get_gpio(CROS_WP_GPIO); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 58c3481..531d6a7 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -47,7 +47,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c index 7b67cc0..188c16d 100644 --- a/src/mainboard/google/auron/mainboard.c +++ b/src/mainboard/google/auron/mainboard.c @@ -28,6 +28,7 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "onboard.h" @@ -88,6 +89,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/auron_paine/acpi/chromeos.asl b/src/mainboard/google/auron_paine/acpi/chromeos.asl deleted file mode 100644 index 85b4415..0000000 --- a/src/mainboard/google/auron_paine/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // no recovery button - Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/google/auron_paine/chromeos.c b/src/mainboard/google/auron_paine/chromeos.c index 4447ddc..20685c6 100644 --- a/src/mainboard/google/auron_paine/chromeos.c +++ b/src/mainboard/google/auron_paine/chromeos.c @@ -82,3 +82,13 @@ int get_write_protect_state(void) { return get_gpio(CROS_WP_GPIO); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/auron_paine/dsdt.asl b/src/mainboard/google/auron_paine/dsdt.asl index 58c3481..531d6a7 100644 --- a/src/mainboard/google/auron_paine/dsdt.asl +++ b/src/mainboard/google/auron_paine/dsdt.asl @@ -47,7 +47,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/auron_paine/mainboard.c b/src/mainboard/google/auron_paine/mainboard.c index a73a4bd..81ca9cf 100644 --- a/src/mainboard/google/auron_paine/mainboard.c +++ b/src/mainboard/google/auron_paine/mainboard.c @@ -28,6 +28,7 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "onboard.h" @@ -61,6 +62,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/google/butterfly/acpi/chromeos.asl b/src/mainboard/google/butterfly/acpi/chromeos.asl deleted file mode 100644 index a6cf28e..0000000 --- a/src/mainboard/google/butterfly/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button - Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button - Package() { 0x003, 0, 6, "PantherPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 69887f5..b25d78e 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -23,6 +23,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <ec/quanta/ene_kb3940q/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #define WP_GPIO 6 @@ -136,3 +137,14 @@ int get_recovery_mode_switch(void) return ec_rec_mode; } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index 4b0e730..3e13a41 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -50,7 +50,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index ac005d8..2c5170d 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -34,6 +34,7 @@ #include <smbios.h> #include <device/pci.h> #include <ec/quanta/ene_kb3940q/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> static unsigned int search(char *p, char *a, unsigned int lengthp, unsigned int lengtha) @@ -276,6 +277,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = butterfly_onboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/chell/acpi/chromeos.asl b/src/mainboard/google/chell/acpi/chromeos.asl deleted file mode 100644 index 90b1a4f..0000000 --- a/src/mainboard/google/chell/acpi/chromeos.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../gpio.h" - -Name (OIPG, Package () { - /* No physical recovery GPIO. */ - Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" }, - /* Firmware write protect GPIO. */ - Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" }, -}) diff --git a/src/mainboard/google/chell/chromeos.c b/src/mainboard/google/chell/chromeos.c index f0b3613..3ca1872 100644 --- a/src/mainboard/google/chell/chromeos.c +++ b/src/mainboard/google/chell/chromeos.c @@ -82,3 +82,13 @@ int get_write_protect_state(void) /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/chell/dsdt.asl b/src/mainboard/google/chell/dsdt.asl index c9e13e7..b5a37c6 100644 --- a/src/mainboard/google/chell/dsdt.asl +++ b/src/mainboard/google/chell/dsdt.asl @@ -45,7 +45,6 @@ DefinitionBlock( } // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/chell/mainboard.c b/src/mainboard/google/chell/mainboard.c index 6033e21..bfa79b4 100644 --- a/src/mainboard/google/chell/mainboard.c +++ b/src/mainboard/google/chell/mainboard.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <stdlib.h> #include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(device_t dev) @@ -69,6 +70,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/cyan/acpi/chromeos.asl b/src/mainboard/google/cyan/acpi/chromeos.asl deleted file mode 100644 index 0bb7985..0000000 --- a/src/mainboard/google/cyan/acpi/chromeos.asl +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Fields are in the following order. - * - Type: recovery = 1 developer mode = 2 write protect = 3 - * - Active Level - if -1 not a valid gpio - * - GPIO number encoding - if -1 not a valid gpio - * - Chipset Name - * - * Note: We need to encode gpios within the 4 separate banks - * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded - * as 0x10016 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. - */ - -Name(OIPG, Package() { - /* No physical recovery button */ - Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, - Package () { 0x0003, 1, 0x10013, "Braswell" }, -}) diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index a038d1f..5d277aa 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -123,3 +123,13 @@ int get_write_protect_state(void) return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0)) & PAD_VAL_HIGH); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index b3c970d..cb6d91a 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -53,7 +53,6 @@ DefinitionBlock( #include <soc/intel/common/acpi/wifi.asl> } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c index 0566c8e..71ba62b 100644 --- a/src/mainboard/google/cyan/mainboard.c +++ b/src/mainboard/google/cyan/mainboard.c @@ -18,6 +18,7 @@ #include <bootstate.h> #include <device/device.h> #include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(device_t dev) @@ -32,6 +33,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } diff --git a/src/mainboard/google/falco/acpi/chromeos.asl b/src/mainboard/google/falco/acpi/chromeos.asl deleted file mode 100644 index 673985f..0000000 --- a/src/mainboard/google/falco/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button - Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/falco/chromeos.c b/src/mainboard/google/falco/chromeos.c index 1659d9c..a8cef32 100644 --- a/src/mainboard/google/falco/chromeos.c +++ b/src/mainboard/google/falco/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #if CONFIG_EC_GOOGLE_CHROMEEC #include "ec.h" @@ -86,3 +87,13 @@ int get_write_protect_state(void) { return get_gpio(58); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/falco/dsdt.asl b/src/mainboard/google/falco/dsdt.asl index 1020ae7..f4a4627 100644 --- a/src/mainboard/google/falco/dsdt.asl +++ b/src/mainboard/google/falco/dsdt.asl @@ -54,7 +54,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/falco/mainboard.c b/src/mainboard/google/falco/mainboard.c index b9ce50e..10252d8 100644 --- a/src/mainboard/google/falco/mainboard.c +++ b/src/mainboard/google/falco/mainboard.c @@ -29,6 +29,7 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "onboard.h" @@ -87,6 +88,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/glados/acpi/chromeos.asl b/src/mainboard/google/glados/acpi/chromeos.asl deleted file mode 100644 index 90b1a4f..0000000 --- a/src/mainboard/google/glados/acpi/chromeos.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../gpio.h" - -Name (OIPG, Package () { - /* No physical recovery GPIO. */ - Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" }, - /* Firmware write protect GPIO. */ - Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" }, -}) diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index f0b3613..3ca1872 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -82,3 +82,13 @@ int get_write_protect_state(void) /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index c9e13e7..b5a37c6 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -45,7 +45,6 @@ DefinitionBlock( } // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index d387fef..855d69d 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <stdlib.h> #include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(device_t dev) @@ -73,6 +74,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/guado/acpi/chromeos.asl b/src/mainboard/google/guado/acpi/chromeos.asl deleted file mode 100644 index 492ee6b..0000000 --- a/src/mainboard/google/guado/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button - Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/google/guado/chromeos.c b/src/mainboard/google/guado/chromeos.c index 13fbfc3..710ab48 100644 --- a/src/mainboard/google/guado/chromeos.c +++ b/src/mainboard/google/guado/chromeos.c @@ -93,3 +93,13 @@ void save_chromeos_gpios(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); } #endif + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/guado/dsdt.asl b/src/mainboard/google/guado/dsdt.asl index e078694..c3d1fc9 100644 --- a/src/mainboard/google/guado/dsdt.asl +++ b/src/mainboard/google/guado/dsdt.asl @@ -46,7 +46,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/guado/mainboard.c b/src/mainboard/google/guado/mainboard.c index 3287a7e..1d65829 100644 --- a/src/mainboard/google/guado/mainboard.c +++ b/src/mainboard/google/guado/mainboard.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <arch/io.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" void mainboard_suspend_resume(void) @@ -35,6 +36,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/jecht/acpi/chromeos.asl b/src/mainboard/google/jecht/acpi/chromeos.asl deleted file mode 100644 index 492ee6b..0000000 --- a/src/mainboard/google/jecht/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button - Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index cc19666..c22f942 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -94,3 +94,13 @@ void save_chromeos_gpios(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); } #endif + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index b434727..3132aab 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -47,7 +47,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c index 58c0190..cb17797 100644 --- a/src/mainboard/google/jecht/mainboard.c +++ b/src/mainboard/google/jecht/mainboard.c @@ -30,6 +30,7 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" void mainboard_suspend_resume(void) @@ -135,6 +136,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/lars/acpi/chromeos.asl b/src/mainboard/google/lars/acpi/chromeos.asl deleted file mode 100644 index 4fc5f22..0000000 --- a/src/mainboard/google/lars/acpi/chromeos.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../gpio.h" - -Name (OIPG, Package () { - /* No physical recovery GPIO. */ - Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" }, - /* Firmware write protect GPIO. */ - Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" }, -}) diff --git a/src/mainboard/google/lars/chromeos.c b/src/mainboard/google/lars/chromeos.c index 1e0bd3c..daa85c6 100644 --- a/src/mainboard/google/lars/chromeos.c +++ b/src/mainboard/google/lars/chromeos.c @@ -82,3 +82,13 @@ int get_write_protect_state(void) /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/lars/dsdt.asl b/src/mainboard/google/lars/dsdt.asl index c9e13e7..b5a37c6 100644 --- a/src/mainboard/google/lars/dsdt.asl +++ b/src/mainboard/google/lars/dsdt.asl @@ -45,7 +45,6 @@ DefinitionBlock( } // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/lars/mainboard.c b/src/mainboard/google/lars/mainboard.c index 6725f13..e044405 100644 --- a/src/mainboard/google/lars/mainboard.c +++ b/src/mainboard/google/lars/mainboard.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <stdlib.h> #include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(device_t dev) @@ -69,6 +70,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/link/acpi/chromeos.asl b/src/mainboard/google/link/acpi/chromeos.asl deleted file mode 100644 index eec650a..0000000 --- a/src/mainboard/google/link/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package() { 0x001, 0, 9, "PantherPoint" }, // recovery button - Package() { 0x003, 1, 57, "PantherPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index d07e851..4be31d9 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -22,6 +22,7 @@ #include <southbridge/intel/common/gpio.h> #include "ec.h" #include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -107,3 +108,13 @@ int get_recovery_mode_switch(void) return !!(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(9, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(57, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index be6a412..da4587d 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -50,7 +50,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 922061f..53915d2 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -36,6 +36,7 @@ #include <smbios.h> #include <device/pci.h> #include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> /* placeholder for evenual link post. Not sure what we'll * do but it will look nice @@ -199,6 +200,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = link_onboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/ninja/acpi/chromeos.asl b/src/mainboard/google/ninja/acpi/chromeos.asl deleted file mode 100644 index 814380c..0000000 --- a/src/mainboard/google/ninja/acpi/chromeos.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Fields are in the following order. - * - Type: recovery = 1 developer mode = 2 write protect = 3 - * - Active Level - if -1 not a valid gpio - * - GPIO number encoding - if -1 not a valid gpio - * - Chipset Name - * - * Note: On Bay Trail we need to encode gpios within the 3 separate banks - * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded - * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 0x2008, "BayTrail" }, // recovery - Package () { 0x0003, 1, 0x2006, "BayTrail" }, // firmware write protect -}) diff --git a/src/mainboard/google/ninja/chromeos.c b/src/mainboard/google/ninja/chromeos.c index baafb6f..1213266 100644 --- a/src/mainboard/google/ninja/chromeos.c +++ b/src/mainboard/google/ninja/chromeos.c @@ -100,4 +100,14 @@ int get_write_protect_state(void) /* WP is enabled when the pin is reading high. */ return ssus_get_gpio(WP_STATUS_PAD); -} \ No newline at end of file +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(0x2008, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/ninja/dsdt.asl b/src/mainboard/google/ninja/dsdt.asl index 6475e1c..a37756f 100644 --- a/src/mainboard/google/ninja/dsdt.asl +++ b/src/mainboard/google/ninja/dsdt.asl @@ -44,7 +44,6 @@ DefinitionBlock( #include "acpi/dptf.asl" } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/ninja/mainboard.c b/src/mainboard/google/ninja/mainboard.c index a5d171e..df9ecfa 100644 --- a/src/mainboard/google/ninja/mainboard.c +++ b/src/mainboard/google/ninja/mainboard.c @@ -34,6 +34,7 @@ #include "onboard.h" #include <soc/gpio.h> #include <bootstate.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -144,6 +145,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/panther/acpi/chromeos.asl b/src/mainboard/google/panther/acpi/chromeos.asl deleted file mode 100644 index d77a79e..0000000 --- a/src/mainboard/google/panther/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 12, "LynxPoint" }, // recovery button - Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c index 014bb7e..4ee6810 100644 --- a/src/mainboard/google/panther/chromeos.c +++ b/src/mainboard/google/panther/chromeos.c @@ -92,3 +92,13 @@ void init_bootmode_straps(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); } #endif + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/panther/dsdt.asl b/src/mainboard/google/panther/dsdt.asl index 6fdb48b..66cc041 100644 --- a/src/mainboard/google/panther/dsdt.asl +++ b/src/mainboard/google/panther/dsdt.asl @@ -54,7 +54,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/panther/mainboard.c b/src/mainboard/google/panther/mainboard.c index 68932cf..661e507 100644 --- a/src/mainboard/google/panther/mainboard.c +++ b/src/mainboard/google/panther/mainboard.c @@ -29,6 +29,7 @@ #include <pc80/mc146818rtc.h> #include <southbridge/intel/lynxpoint/pch.h> #include <drivers/intel/gma/int15.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" @@ -51,6 +52,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/parrot/acpi/chromeos.asl b/src/mainboard/google/parrot/acpi/chromeos.asl deleted file mode 100644 index b754183..0000000 --- a/src/mainboard/google/parrot/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button - Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button - Package() { 0x003, 0, 70, "PantherPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index c898f0e..4dcbfa5 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -23,6 +23,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <ec/compal/ene932/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" @@ -122,3 +123,14 @@ int parrot_ec_running_ro(void) { return !get_gpio(68); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(70, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index 4b0e730..3e13a41 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -50,7 +50,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index a2b7169..4d357f8 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -32,6 +32,7 @@ #include <smbios.h> #include <device/pci.h> #include <ec/compal/ene932/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -81,6 +82,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = parrot_onboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/peppy/acpi/chromeos.asl b/src/mainboard/google/peppy/acpi/chromeos.asl deleted file mode 100644 index 673985f..0000000 --- a/src/mainboard/google/peppy/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button - Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/peppy/chromeos.c b/src/mainboard/google/peppy/chromeos.c index 1659d9c..a8cef32 100644 --- a/src/mainboard/google/peppy/chromeos.c +++ b/src/mainboard/google/peppy/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #if CONFIG_EC_GOOGLE_CHROMEEC #include "ec.h" @@ -86,3 +87,13 @@ int get_write_protect_state(void) { return get_gpio(58); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/peppy/dsdt.asl b/src/mainboard/google/peppy/dsdt.asl index 9e5a114..83305ab 100644 --- a/src/mainboard/google/peppy/dsdt.asl +++ b/src/mainboard/google/peppy/dsdt.asl @@ -52,7 +52,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/peppy/mainboard.c b/src/mainboard/google/peppy/mainboard.c index b9ce50e..10252d8 100644 --- a/src/mainboard/google/peppy/mainboard.c +++ b/src/mainboard/google/peppy/mainboard.c @@ -29,6 +29,7 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "onboard.h" @@ -87,6 +88,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/rambi/acpi/chromeos.asl b/src/mainboard/google/rambi/acpi/chromeos.asl deleted file mode 100644 index 3072eca..0000000 --- a/src/mainboard/google/rambi/acpi/chromeos.asl +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Fields are in the following order. - * - Type: recovery = 1 developer mode = 2 write protect = 3 - * - Active Level - if -1 not a valid gpio - * - GPIO number encoding - if -1 not a valid gpio - * - Chipset Name - * - * Note: On Bay Trail we need to encode gpios within the 3 separate banks - * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded - * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000. - */ - -Name(OIPG, Package() { - // No physical recovery button - Package () { 0x0001, 0, 0xFFFFFFFF, "BayTrail" }, - Package () { 0x0003, 1, 0x2006, "BayTrail" }, -}) diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index f2a2ab7..a7753c9 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #if CONFIG_EC_GOOGLE_CHROMEEC #include "ec.h" @@ -110,3 +111,13 @@ int get_write_protect_state(void) /* WP is enabled when the pin is reading high. */ return ssus_get_gpio(WP_STATUS_PAD); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 6475e1c..a37756f 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -44,7 +44,6 @@ DefinitionBlock( #include "acpi/dptf.asl" } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 29cebb1..adbfd96 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -34,6 +34,7 @@ #include "onboard.h" #include <soc/gpio.h> #include <bootstate.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -163,6 +164,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/reef/acpi/chromeos.asl b/src/mainboard/google/reef/acpi/chromeos.asl deleted file mode 100644 index d6a0080..0000000 --- a/src/mainboard/google/reef/acpi/chromeos.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/gpio_defs.h> - -Name (OIPG, Package () { - /* No physical recovery GPIO. */ - Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:00" }, - /* Firmware write protect GPIO. */ - Package () { 0x0003, 1, GPIO_75, "INT3452:00" }, -}) diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 4de6a70..5c526dc 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -19,6 +19,7 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include "ec.h" +#include "gpio.h" #define GPIO_PCH_WP GPIO_75 #define GPIO_EC_IN_RW GPIO_41 @@ -69,3 +70,13 @@ int get_write_protect_state(void) /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), + CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 7a88fb6..6243c72 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -38,7 +38,6 @@ DefinitionBlock( } /* Chrome OS specific */ - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index def6900..0c4ba8d 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -20,6 +20,7 @@ #include <nhlt.h> #include <soc/gpio.h> #include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "gpio.h" @@ -83,6 +84,7 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(device_t dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/rikku/acpi/chromeos.asl b/src/mainboard/google/rikku/acpi/chromeos.asl deleted file mode 100644 index bad5f47..0000000 --- a/src/mainboard/google/rikku/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button - Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/google/rikku/chromeos.c b/src/mainboard/google/rikku/chromeos.c index d440968..b007484 100644 --- a/src/mainboard/google/rikku/chromeos.c +++ b/src/mainboard/google/rikku/chromeos.c @@ -93,3 +93,13 @@ void save_chromeos_gpios(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); } #endif + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/rikku/dsdt.asl b/src/mainboard/google/rikku/dsdt.asl index 663b3c5..edb04f0 100644 --- a/src/mainboard/google/rikku/dsdt.asl +++ b/src/mainboard/google/rikku/dsdt.asl @@ -46,7 +46,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/rikku/mainboard.c b/src/mainboard/google/rikku/mainboard.c index 16fe630..e3eaf4e 100644 --- a/src/mainboard/google/rikku/mainboard.c +++ b/src/mainboard/google/rikku/mainboard.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <arch/io.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" void mainboard_suspend_resume(void) @@ -35,6 +36,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/samus/acpi/chromeos.asl b/src/mainboard/google/samus/acpi/chromeos.asl deleted file mode 100644 index 604cd7d..0000000 --- a/src/mainboard/google/samus/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "INT3437:00" }, // no recovery button - Package () { 0x0003, 1, 16, "INT3437:00" }, // firmware write protect -}) diff --git a/src/mainboard/google/samus/chromeos.c b/src/mainboard/google/samus/chromeos.c index 51f2f2e..7010ac9 100644 --- a/src/mainboard/google/samus/chromeos.c +++ b/src/mainboard/google/samus/chromeos.c @@ -93,3 +93,13 @@ int get_write_protect_state(void) { return get_gpio(CROS_WP_GPIO); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_ACPI_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_ACPI_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/samus/dsdt.asl b/src/mainboard/google/samus/dsdt.asl index 34071b1..02e6363 100644 --- a/src/mainboard/google/samus/dsdt.asl +++ b/src/mainboard/google/samus/dsdt.asl @@ -47,7 +47,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c index 54c6283..9fa9c57 100644 --- a/src/mainboard/google/samus/mainboard.c +++ b/src/mainboard/google/samus/mainboard.c @@ -28,6 +28,7 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "board_version.h" #include "ec.h" @@ -51,6 +52,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/stout/acpi/chromeos.asl b/src/mainboard/google/stout/acpi/chromeos.asl deleted file mode 100644 index ddabdc8..0000000 --- a/src/mainboard/google/stout/acpi/chromeos.asl +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - // No GPIO for recovery mode, developer mode, or firmware write protect - // on stout - note: all virtual pins are active HIGH polarity on stout. - Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button - Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button - Package() { 0x003, 0, 7, "PantherPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 4c7a9f5..cbb9574 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -22,6 +22,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include <ec/quanta/it8518/ec.h> @@ -133,3 +134,14 @@ int get_recovery_mode_switch(void) return ec_in_rec_mode; #endif } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(7, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 723cc71..3a822ed 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -50,7 +50,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 2581310..4e3839f 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -32,6 +32,7 @@ #include <smbios.h> #include <device/pci.h> #include <ec/quanta/it8518/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -66,6 +67,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/tidus/acpi/chromeos.asl b/src/mainboard/google/tidus/acpi/chromeos.asl deleted file mode 100644 index 492ee6b..0000000 --- a/src/mainboard/google/tidus/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button - Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/google/tidus/chromeos.c b/src/mainboard/google/tidus/chromeos.c index 13fbfc3..710ab48 100644 --- a/src/mainboard/google/tidus/chromeos.c +++ b/src/mainboard/google/tidus/chromeos.c @@ -93,3 +93,13 @@ void save_chromeos_gpios(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); } #endif + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/tidus/dsdt.asl b/src/mainboard/google/tidus/dsdt.asl index e078694..c3d1fc9 100644 --- a/src/mainboard/google/tidus/dsdt.asl +++ b/src/mainboard/google/tidus/dsdt.asl @@ -46,7 +46,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/tidus/mainboard.c b/src/mainboard/google/tidus/mainboard.c index 3287a7e..1d65829 100644 --- a/src/mainboard/google/tidus/mainboard.c +++ b/src/mainboard/google/tidus/mainboard.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <arch/io.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" void mainboard_suspend_resume(void) @@ -35,6 +36,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/amenia/acpi/chromeos.asl b/src/mainboard/intel/amenia/acpi/chromeos.asl deleted file mode 100644 index 31d0afc..0000000 --- a/src/mainboard/intel/amenia/acpi/chromeos.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/gpio_defs.h> - -Name (OIPG, Package () { - /* No physical recovery GPIO. */ - Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:01" }, - /* Firmware write protect GPIO. */ - Package () { 0x0003, 1, PAD_NW(GPIO_75), "INT3452:01" }, -}) diff --git a/src/mainboard/intel/amenia/chromeos.c b/src/mainboard/intel/amenia/chromeos.c index b6669bf..4cfc2a6 100644 --- a/src/mainboard/intel/amenia/chromeos.c +++ b/src/mainboard/intel/amenia/chromeos.c @@ -18,6 +18,7 @@ #include "ec.h" #include <ec/google/chromeec/ec.h> +#include <soc/gpio_defs.h> #include <vendorcode/google/chromeos/chromeos.h> int get_lid_switch(void) @@ -48,3 +49,13 @@ int get_write_protect_state(void) { return 0; } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), + CROS_GPIO_WP_AH(PAD_NW(GPIO_75), GPIO_COMM_NW_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 7602b1e..9314469 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -39,10 +39,7 @@ DefinitionBlock( } } - #if IS_ENABLED(CONFIG_CHROMEOS) - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> - #endif /* Mainboard Specific devices */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/baskingridge/acpi/chromeos.asl b/src/mainboard/intel/baskingridge/acpi/chromeos.asl deleted file mode 100644 index 9c49265..0000000 --- a/src/mainboard/intel/baskingridge/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 1, 69, "LynxPoint" }, // recovery - Package () { 0x0002, 0, 48, "LynxPoint" }, // developer - Package () { 0x0003, 0, 22, "LynxPoint" }, // firmware write protect -}) diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 94e8d89..1666fc5 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -102,3 +103,14 @@ int get_write_protect_state(void) { return 0; } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AL(48, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index 5cd0ffb..e4b489c 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -48,7 +48,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 4c7baca..dbf3574 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -28,6 +28,7 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -35,13 +36,12 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } - - // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl deleted file mode 100644 index 9f2e54a..0000000 --- a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch - Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect -}) diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index bb4ebe9..896f876 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -91,3 +92,14 @@ int get_recovery_mode_switch(void) /* Recovery: GPIO22, active low */ return !get_gpio(22); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AH(57, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index 8d9e281..a31c415 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -49,7 +49,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index a0fd9e8..654b1de 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -28,12 +28,14 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/kunimitsu/acpi/chromeos.asl b/src/mainboard/intel/kunimitsu/acpi/chromeos.asl deleted file mode 100644 index 4fc5f22..0000000 --- a/src/mainboard/intel/kunimitsu/acpi/chromeos.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../gpio.h" - -Name (OIPG, Package () { - /* No physical recovery GPIO. */ - Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" }, - /* Firmware write protect GPIO. */ - Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" }, -}) diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 1e0bd3c..daa85c6 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -82,3 +82,13 @@ int get_write_protect_state(void) /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index c9e13e7..b5a37c6 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -45,7 +45,6 @@ DefinitionBlock( } // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index d634fac..9f79db6 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -22,6 +22,7 @@ #include <stdlib.h> #include <string.h> #include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "gpio.h" @@ -99,6 +100,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/strago/acpi/chromeos.asl b/src/mainboard/intel/strago/acpi/chromeos.asl deleted file mode 100644 index c470ca3..0000000 --- a/src/mainboard/intel/strago/acpi/chromeos.asl +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Fields are in the following order. - * - Type: recovery = 1 developer mode = 2 write protect = 3 - * - Active Level - if -1 not a valid gpio - * - GPIO number encoding - if -1 not a valid gpio - * - Chipset Name - * - * Note: We need to encode gpios within the 4 separate banks - * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded - * as 0x10013 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. - */ - -Name(OIPG, Package() { - /* No physical recovery button */ - Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, - Package () { 0x0003, 1, 0x10013, "Braswell" }, -}) diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 2cc092d..e3efaf1 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -118,3 +118,13 @@ int get_write_protect_state(void) /* WP is enabled when the pin is reading high. */ return !!gpio_get(WP_GPIO); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index f1248d8..59af6dd 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -54,7 +54,6 @@ DefinitionBlock( #include <soc/intel/common/acpi/wifi.asl> } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index 0566c8e..71ba62b 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -18,6 +18,7 @@ #include <bootstate.h> #include <device/device.h> #include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(device_t dev) @@ -32,6 +33,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } diff --git a/src/mainboard/intel/wtm2/acpi/chromeos.asl b/src/mainboard/intel/wtm2/acpi/chromeos.asl deleted file mode 100644 index 4257e7d..0000000 --- a/src/mainboard/intel/wtm2/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // recovery - Package () { 0x0002, 0, 0xFFFFFFFF, "PCH-LP" }, // developer - Package () { 0x0003, 0, 0xFFFFFFFF, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index feee0cb..862f4a4 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> /* Compile-time settings for developer and recovery mode. */ #define DEV_MODE_SETTING 1 @@ -55,3 +56,14 @@ int get_write_protect_state(void) { return 0; } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index 1601483..410f6d2 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -49,7 +49,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 253e8ff..ffb5b86 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -39,6 +40,7 @@ void mainboard_suspend_resume(void) static void mainboard_enable(device_t dev) { + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/samsung/lumpy/acpi/chromeos.asl b/src/mainboard/samsung/lumpy/acpi/chromeos.asl deleted file mode 100644 index f3bb40b..0000000 --- a/src/mainboard/samsung/lumpy/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch - Package() { 0x003, 1, 24, "CougarPoint" }, // firmware write protect -}) diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 9ee32bb..71d82b5 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -21,6 +21,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #define GPIO_SPI_WP 24 #define GPIO_REC_MODE 42 @@ -135,3 +136,14 @@ void init_bootmode_straps(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); #endif } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index ed3a84a..28b0c1b 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -52,7 +52,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 95a7531..3de067e 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -31,6 +31,7 @@ #include "onboard.h" #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -98,6 +99,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = lumpy_onboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/samsung/stumpy/acpi/chromeos.asl b/src/mainboard/samsung/stumpy/acpi/chromeos.asl deleted file mode 100644 index 5d69251..0000000 --- a/src/mainboard/samsung/stumpy/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch - Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect -}) diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 5f2a062..96d2b12 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #define GPIO_SPI_WP 68 #define GPIO_REC_MODE 42 @@ -132,3 +133,14 @@ void init_bootmode_straps(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); #endif } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index 4b0e730..3e13a41 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -50,7 +50,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index a0fd9e8..654b1de 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -28,12 +28,14 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 48e08e7..aa1ce8c 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -362,6 +362,12 @@ #define PAD_W(pad) (pad - W_OFFSET) #define PAD_SW(pad) (pad - SW_OFFSET) +/* Linux names of the GPIO devices. */ +#define GPIO_COMM_N_NAME "INT3452:00" +#define GPIO_COMM_NW_NAME "INT3452:01" +#define GPIO_COMM_W_NAME "INT3452:02" +#define GPIO_COMM_SW_NAME "INT3452:03" + /* Default configurations */ #define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP | PAD_CFG0_MODE_FUNC(x)) #define PAD_CFG0_DEFAULT_NATIVE PAD_CFG0_DEFAULT_FUNC(1) diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 79c19b4..3757eb0 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -22,6 +22,8 @@ /* #define GPIO_DEBUG */ +#define CROS_GPIO_DEVICE_NAME "BayTrail" + /* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */ #define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) #define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE) diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index c7bfb65..3c56f6a 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -22,6 +22,8 @@ #include <soc/gpio_defs.h> #include <soc/iomap.h> +#define CROS_GPIO_DEVICE_NAME "Braswell" + #define COMMUNITY_SIZE 0x20000 #define COMMUNITY_GPSOUTHWEST_BASE \ diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index 7345df5..ff51283 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -18,6 +18,9 @@ #include <stdint.h> +#define CROS_GPIO_DEVICE_NAME "PCH-LP" +#define CROS_GPIO_ACPI_DEVICE_NAME "INT3437:00" + /* PCH-LP GPIOBASE Registers */ #define GPIO_OWNER(set) (0x00 + ((set) * 4)) #define GPIO_PIRQ_APIC_EN 0x10 diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 6733889..d86af0f 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -19,6 +19,8 @@ #include <soc/gpio_defs.h> +#define CROS_GPIO_DEVICE_NAME "INT344B:00" + #ifndef __ACPI__ #include <stdint.h> #include <stddef.h> diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 28323ac..f22fed5 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -51,6 +51,12 @@ #define DEFAULT_RCBA 0xfed1c000 #endif +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) +#define CROS_GPIO_DEVICE_NAME "CougarPoint" +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216) +#define CROS_GPIO_DEVICE_NAME "PantherPoint" +#endif + #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index a3cd811..8cae50a 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -19,6 +19,8 @@ #include <arch/acpi.h> +#define CROS_GPIO_DEVICE_NAME "LynxPoint" + /* * Lynx Point PCH PCI Devices: * diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 18ce13e..a7c765c 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -45,6 +45,7 @@ ramstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c romstage-y += vpd_decode.c ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_serialno.c vpd_calibration.c diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c new file mode 100644 index 0000000..6605809 --- /dev/null +++ b/src/vendorcode/google/chromeos/acpi.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include "chromeos.h" + +void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num) +{ + size_t i; + + acpigen_write_scope("\\"); + acpigen_write_name("OIPG"); + + acpigen_write_package(num); + for (i = 0; i < num; i++) { + acpigen_write_package(4); + acpigen_write_integer(gpios[i].type); + acpigen_write_integer(gpios[i].polarity); + acpigen_write_integer(gpios[i].gpio_num); + acpigen_write_string(gpios[i].device); + acpigen_pop_len(); + } + acpigen_pop_len(); + + acpigen_pop_len(); +} + +void chromeos_dsdt_generator(struct device *dev) +{ + mainboard_chromeos_acpi_generate(); +} diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 66ebbc1..4a41c15 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -15,6 +15,11 @@ #include <vendorcode/google/chromeos/vbnv_layout.h> +#if IS_ENABLED(CONFIG_CHROMEOS) + +/* GPIO package generated at run time. */ +External (OIPG) + Device (CRHW) { Name(_HID, EISAID("GGL0001")) @@ -107,3 +112,4 @@ Device (CRHW) } #include "ramoops.asl" +#endif diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index ad9ef2f..375b407 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -19,6 +19,7 @@ #include <stddef.h> #include <stdint.h> #include <bootmode.h> +#include <device/device.h> #include <rules.h> #include "vbnv.h" #include "vboot_common.h" @@ -60,4 +61,75 @@ static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} void cbmem_add_vpd_calibration_data(void); +/* + * Create the OIPG package containing the Chrome OS gpios described by + * the chromeos_gpio array. + */ +struct cros_gpio; +void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num); + +/* + * Common helper function and delcarations for mainboards to use to generate + * ACPI-specific Chrome OS needs. + */ +void mainboard_chromeos_acpi_generate(void); +#if IS_ENABLED(CONFIG_CHROMEOS) +void chromeos_dsdt_generator(struct device *dev); +#else +#define chromeos_dsdt_generator DEVICE_NOOP +#endif + +enum { + CROS_GPIO_REC = 1, /* Recovery */ + CROS_GPIO_DEV = 2, /* Developer */ + CROS_GPIO_WP = 3, /* Write Protect */ + + CROS_GPIO_ACTIVE_LOW = 0, + CROS_GPIO_ACTIVE_HIGH = 1, + + CROS_GPIO_VIRTUAL = -1, +}; + +struct cros_gpio { + int type; + int polarity; + int gpio_num; + const char *device; +}; + +#define CROS_GPIO_INITIALIZER(typ, pol, num, dev) \ + { \ + .type = (typ), \ + .polarity = (pol), \ + .gpio_num = (num), \ + .device = (dev), \ + } + +#define CROS_GPIO_REC_INITIALIZER(pol, num, dev) \ + CROS_GPIO_INITIALIZER(CROS_GPIO_REC, pol, num, dev) + +#define CROS_GPIO_REC_AL(num, dev) \ + CROS_GPIO_REC_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev) + +#define CROS_GPIO_REC_AH(num, dev) \ + CROS_GPIO_REC_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) + +#define CROS_GPIO_DEV_INITIALIZER(pol, num, dev) \ + CROS_GPIO_INITIALIZER(CROS_GPIO_DEV, pol, num, dev) + +#define CROS_GPIO_DEV_AL(num, dev) \ + CROS_GPIO_DEV_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev) + +#define CROS_GPIO_DEV_AH(num, dev) \ + CROS_GPIO_DEV_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) + +#define CROS_GPIO_WP_INITIALIZER(pol, num, dev) \ + CROS_GPIO_INITIALIZER(CROS_GPIO_WP, pol, num, dev) + +#define CROS_GPIO_WP_AL(num, dev) \ + CROS_GPIO_WP_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev) + +#define CROS_GPIO_WP_AH(num, dev) \ + CROS_GPIO_WP_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) + #endif /* __CHROMEOS_H__ */

1 0

Patch set updated for coreboot: skylake: fix VSDIO is at 0.8V when SDCard is not inserted
by Zhuo-hao Lee 28 Jul '16

28 Jul '16

Zhuo-hao Lee (zhuo-hao.lee(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15910 -gerrit commit d999712ad955e9f1a2af8d113b0cec3e7559b5f1 Author: Zhuo-hao.Lee <zhuo-hao.lee(a)intel.com> Date: Wed Jul 27 13:18:22 2016 +0800 skylake: fix VSDIO is at 0.8V when SDCard is not inserted 1. Enable SoC SD_CMD/D* signals pull-down of 20k when SD-card is removed. When SD-card is disconnected, the pull-down is disabled. 2. Provide path for weak leakage from buffers of SD_CMD/D* signal to be grounded. Thus dropping voltage on the SD_CMD/D* signals to ~0V. BUG=chrome-os-partner:54421 TEST=no power leakage when SDCard isn't inserted on skylake platform Change-Id: I567199b172841125f8916a61a76005cfdaa62eb8 Signed-off-by: Zhuo-hao.Lee <zhuo-hao.lee(a)intel.com> --- src/soc/intel/skylake/acpi/scs.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index 56f27a9..69bc82a 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -88,6 +88,14 @@ Device (SDXC) Method (_PS0, 0, Serialized) { + /* Disable 20K pull-down on CLK, CMD and DAT lines */ + ^^PCRA (PID_GPIOCOM3, 0x4c4, 0xFFFFEFFF) + ^^PCRA (PID_GPIOCOM3, 0x4cc, 0xFFFFEFFF) + ^^PCRA (PID_GPIOCOM3, 0x4d4, 0xFFFFEFFF) + ^^PCRA (PID_GPIOCOM3, 0x4dc, 0xFFFFEFFF) + ^^PCRA (PID_GPIOCOM3, 0x4e4, 0xFFFFEFFF) + ^^PCRA (PID_GPIOCOM3, 0x4f4, 0xFFFFEFFF) + /* Disable Power Gate */ Store (0, ^PGEN) @@ -113,6 +121,14 @@ Device (SDXC) Store (3, Local0) Store (Local0, ^D0D3) Store (^D0D3, Local0) + + /* Enable 20K pull-down on CLK, CMD and DAT lines */ + ^^PCRO (PID_GPIOCOM3, 0x4c4, 0x00001000) + ^^PCRO (PID_GPIOCOM3, 0x4cc, 0x00001000) + ^^PCRO (PID_GPIOCOM3, 0x4d4, 0x00001000) + ^^PCRO (PID_GPIOCOM3, 0x4dc, 0x00001000) + ^^PCRO (PID_GPIOCOM3, 0x4e4, 0x00001000) + ^^PCRO (PID_GPIOCOM3, 0x4f4, 0x00001000) } Device (CARD)

1 0

Patch set updated for coreboot: skylake: fix VSDIO is at 0.8V when SDCard is not inserted
by Zhuo-hao Lee 28 Jul '16

28 Jul '16

Zhuo-hao Lee (zhuo-hao.lee(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15910 -gerrit commit 024e1ddc86b33a611a47561074879a57c9cc2d8f Author: Zhuo-hao Lee <zhuo-hao.lee(a)intel.com> Date: Wed Jul 27 13:18:22 2016 +0800 skylake: fix VSDIO is at 0.8V when SDCard is not inserted 1. Enable SoC SD_CMD/D* signals pull-down of 20k when SD-card is removed. When SD-card is disconnected, the pull-down is disabled. 2. Provide path for weak leakage from buffers of SD_CMD/D* signal to be grounded. Thus dropping voltage on the SD_CMD/D* signals to ~0V. BUG=chrome-os-partner:54421 TEST=no power leakage when SDCard isn't inserted on skylake platform Change-Id: I567199b172841125f8916a61a76005cfdaa62eb8 Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee(a)intel.com> --- src/soc/intel/skylake/acpi/scs.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index 56f27a9..69bc82a 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -88,6 +88,14 @@ Device (SDXC) Method (_PS0, 0, Serialized) { + /* Disable 20K pull-down on CLK, CMD and DAT lines */ + ^^PCRA (PID_GPIOCOM3, 0x4c4, 0xFFFFEFFF) + ^^PCRA (PID_GPIOCOM3, 0x4cc, 0xFFFFEFFF) + ^^PCRA (PID_GPIOCOM3, 0x4d4, 0xFFFFEFFF) + ^^PCRA (PID_GPIOCOM3, 0x4dc, 0xFFFFEFFF) + ^^PCRA (PID_GPIOCOM3, 0x4e4, 0xFFFFEFFF) + ^^PCRA (PID_GPIOCOM3, 0x4f4, 0xFFFFEFFF) + /* Disable Power Gate */ Store (0, ^PGEN) @@ -113,6 +121,14 @@ Device (SDXC) Store (3, Local0) Store (Local0, ^D0D3) Store (^D0D3, Local0) + + /* Enable 20K pull-down on CLK, CMD and DAT lines */ + ^^PCRO (PID_GPIOCOM3, 0x4c4, 0x00001000) + ^^PCRO (PID_GPIOCOM3, 0x4cc, 0x00001000) + ^^PCRO (PID_GPIOCOM3, 0x4d4, 0x00001000) + ^^PCRO (PID_GPIOCOM3, 0x4dc, 0x00001000) + ^^PCRO (PID_GPIOCOM3, 0x4e4, 0x00001000) + ^^PCRO (PID_GPIOCOM3, 0x4f4, 0x00001000) } Device (CARD)

1 0

Patch set updated for coreboot: libpayload: Replace majority of timer drivers with a generic one
by Stefan Reinauer 28 Jul '16

28 Jul '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15035 -gerrit commit 05fb9f3e420a351031b710fbf1e862152e7ec590 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon May 16 15:39:12 2016 -0700 libpayload: Replace majority of timer drivers with a generic one Currently every non-x86 platform supported by libpayload needs to provide its own timer driver. Most of the ones we have accumulated there look almost identical: For the frequency, return a preset constant. For the value, read a 32-bit register, possibly read another 32-bit register and shift+OR it with the previous one, then return that. Let's replace this with a single .c file that can easily handle all of those cases. Menuconfig convenience can still be maintained by providing several presets that select different defaults for the driver's configuration options (register address(es) and frequency). Removes an "enabled" check from Samsung MCT driver since coreboot always unconditionally enables that timer anyway. CQ-DEPEND=CL:344809 BRANCH=None BUG=None TEST=Booted Oak and Veyron, observed how dev-mode delay was still ~30s Change-Id: I61cb7d2ffd4902aa841c57f9afa9cd991f770ace Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: a036af6 Original-Change-Id: I9784e7c6aa5abd6d92478ea7ec1cf42c9a437546 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347749 --- payloads/libpayload/Kconfig | 101 ++++++++++------------ payloads/libpayload/drivers/Makefile.inc | 11 +-- payloads/libpayload/drivers/timer/bg4cd.c | 26 ------ payloads/libpayload/drivers/timer/cygnus.c | 52 ------------ payloads/libpayload/drivers/timer/generic.c | 45 ++++++++++ payloads/libpayload/drivers/timer/ipq40xx.c | 52 ------------ payloads/libpayload/drivers/timer/ipq806x.c | 58 ------------- payloads/libpayload/drivers/timer/mct.c | 115 -------------------------- payloads/libpayload/drivers/timer/mtk_timer.c | 30 ------- payloads/libpayload/drivers/timer/rktimer.c | 42 ---------- payloads/libpayload/drivers/timer/tegra_1us.c | 41 --------- 11 files changed, 92 insertions(+), 481 deletions(-) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 276eb30..20f10ee 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -438,11 +438,11 @@ config TIMER_IPQ40XX This is the timer driver for QCA IPQ40xx based platforms. -config TIMER_RK - bool "Timer for Rockchip" +config TIMER_RK3288 + bool "Timer for Rockchip RK3288" -config TIMER_BG4CD - bool "Marvell BG4CD" +config TIMER_RK3399 + bool "Timer for Rockchip RK3399" config TIMER_CYGNUS bool "Timer for Cygnus" @@ -455,41 +455,6 @@ config TIMER_MTK endchoice -config TIMER_MCT_HZ - int "Exynos MCT frequency" - depends on TIMER_MCT - default 24000000 - -config TIMER_MCT_ADDRESS - hex "Exynos MCT base address" - depends on TIMER_MCT - default 0x101c0000 - -config TIMER_RK_ADDRESS - hex "Rockchip timer base address" - depends on TIMER_RK - default 0xff810020 - -config TIMER_TEGRA_1US_ADDRESS - hex "Tegra u1s timer base address" - depends on TIMER_TEGRA_1US - default 0x60005010 - -config IPQ806X_TIMER_FREQ - int "Hardware timer frequency" - default 32000 - depends on TIMER_IPQ806X - help - IPQ hardware presently provides a single timer running at 32KHz, a - finer granulariry timer is available but is not yet enabled. - -config IPQ806X_TIMER_REG - hex "Timer register address" - default 0x0200A008 - depends on TIMER_IPQ806X - help - Address of the register to read a free running timer value. - config ARMADA38X_TIMER_FREQ int "Hardware timer frequency" depends on TIMER_ARMADA38X @@ -500,24 +465,46 @@ config ARMADA38X_TIMER_REG default 0xF1020314 depends on TIMER_ARMADA38X -config IPROC_PERIPH_GLB_TIM_REG_BASE - hex "Cygnus timer base address" - depends on TIMER_CYGNUS - default 0x19020200 - -config TIMER_MTK_HZ - int "MediaTek GPT frequency" - depends on TIMER_MTK - default 13000000 - help - Clock frequency of MediaTek General Purpose Timer. - -config TIMER_MTK_ADDRESS - hex "MTK GPT register address" - depends on TIMER_MTK - default 0x10008048 - help - Address of GPT4's counter register to read the FREERUN-mode timer value. +config TIMER_GENERIC_HZ + int "Generic Timer Frequency" + default 500000000 if TIMER_CYGNUS + default 48000000 if TIMER_IPQ40XX + default 6250000 if TIMER_IPQ806X + default 24000000 if TIMER_MCT + default 13000000 if TIMER_MTK + default 24000000 if TIMER_RK3288 + default 24000000 if TIMER_RK3399 + default 1000000 if TIMER_TEGRA_1US + default 0 + help + Clock frequency of generic time counter in Hertz. Leave at 0 to + disable when using a non-generic timer driver. + +config TIMER_GENERIC_REG + hex "Generic Timer Register Address" + default 0x19020200 if TIMER_CYGNUS + default 0x004A2000 if TIMER_IPQ40XX + default 0x0200A028 if TIMER_IPQ806X + default 0x101C0100 if TIMER_MCT + default 0x10008048 if TIMER_MTK + default 0xff810028 if TIMER_RK3288 + default 0xff850008 if TIMER_RK3399 + default 0x60005010 if TIMER_TEGRA_1US + default 0x0 + help + Register address to read generic time counter from. + +config TIMER_GENERIC_HIGH_REG + hex "Generic Timer High Register Address" + default 0x19020204 if TIMER_CYGNUS + default 0x004A2004 if TIMER_IPQ40XX + default 0x101C0104 if TIMER_MCT + default 0xff81002C if TIMER_RK3288 + default 0xff85000C if TIMER_RK3399 + default 0x0 + help + Register address to read high 32 bits of generic time counter from. + Leave at 0x0 for 32-bit counters. config USB bool "USB Support" diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 75f08f2..3c6b12b 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -46,16 +46,11 @@ libc-$(CONFIG_LP_NVRAM) += nvram.c libc-$(CONFIG_LP_NVRAM) += options.c # Timer drivers -libc-$(CONFIG_LP_TIMER_MTK) += timer/mtk_timer.c -libc-$(CONFIG_LP_TIMER_MCT) += timer/mct.c +ifneq ($(CONFIG_LP_TIMER_GENERIC_HZ),0) +libc-y += timer/generic.c +endif libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c -libc-$(CONFIG_LP_TIMER_TEGRA_1US) += timer/tegra_1us.c -libc-$(CONFIG_LP_TIMER_IPQ806X) += timer/ipq806x.c -libc-$(CONFIG_LP_TIMER_IPQ40XX) += timer/ipq40xx.c -libc-$(CONFIG_LP_TIMER_RK) += timer/rktimer.c -libc-$(CONFIG_LP_TIMER_BG4CD) += timer/bg4cd.c libc-$(CONFIG_LP_TIMER_IMG_PISTACHIO) += timer/img_pistachio.c -libc-$(CONFIG_LP_TIMER_CYGNUS) += timer/cygnus.c libc-$(CONFIG_LP_TIMER_ARMADA38X) += timer/armada38x.c # Video console drivers diff --git a/payloads/libpayload/drivers/timer/bg4cd.c b/payloads/libpayload/drivers/timer/bg4cd.c deleted file mode 100644 index 649622b..0000000 --- a/payloads/libpayload/drivers/timer/bg4cd.c +++ /dev/null @@ -1,26 +0,0 @@ - -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Electronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <libpayload.h> - -uint64_t timer_hz(void) -{ - return 0; -} - -uint64_t timer_raw_value(void) -{ - return 0; -} diff --git a/payloads/libpayload/drivers/timer/cygnus.c b/payloads/libpayload/drivers/timer/cygnus.c deleted file mode 100644 index c8f2098..0000000 --- a/payloads/libpayload/drivers/timer/cygnus.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Electronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <libpayload.h> - -struct cygnus_timer { - u32 gtim_glob_low; - u32 gtim_glob_hi; - u32 gtim_glob_ctrl; -}; - -static struct cygnus_timer * const timer_ptr = - (void *)CONFIG_LP_IPROC_PERIPH_GLB_TIM_REG_BASE; - -uint64_t timer_hz(void) -{ - /* - * this is set up by coreboot as follows: - * - * PERIPH_CLOCK / - * (((TIMER_GLB_TIM_CTRL_PRESC & TIMER_GLB_TIM_CTRL_PRESC_MASK)>>8) + 1) - * - * where PERIPH_CLOCK is typically 500000000. - */ - return 500000000; -} - -uint64_t timer_raw_value(void) -{ - uint64_t cur_tick; - uint32_t count_h; - uint32_t count_l; - - do { - count_h = readl(&timer_ptr->gtim_glob_hi); - count_l = readl(&timer_ptr->gtim_glob_low); - cur_tick = readl(&timer_ptr->gtim_glob_hi); - } while (cur_tick != count_h); - - return (cur_tick << 32) + count_l; -} diff --git a/payloads/libpayload/drivers/timer/generic.c b/payloads/libpayload/drivers/timer/generic.c new file mode 100644 index 0000000..5d0d977 --- /dev/null +++ b/payloads/libpayload/drivers/timer/generic.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <libpayload.h> + +static uint32_t *const low_reg = phys_to_virt(CONFIG_LP_TIMER_GENERIC_REG); +static uint32_t *const high_reg = phys_to_virt(CONFIG_LP_TIMER_GENERIC_HIGH_REG); + +uint64_t timer_hz(void) +{ + /* libc/time.c currently requires all timers to be at least 1MHz. */ + assert(CONFIG_LP_TIMER_GENERIC_HZ >= 1000000); + return CONFIG_LP_TIMER_GENERIC_HZ; +} + +uint64_t timer_raw_value(void) +{ + uint64_t cur_tick; + uint32_t count_h; + uint32_t count_l; + + if (!high_reg) + return readl(low_reg); + + do { + count_h = readl(high_reg); + count_l = readl(low_reg); + cur_tick = readl(high_reg); + } while (cur_tick != count_h); + + return (cur_tick << 32) + count_l; +} diff --git a/payloads/libpayload/drivers/timer/ipq40xx.c b/payloads/libpayload/drivers/timer/ipq40xx.c deleted file mode 100644 index 0ca2600..0000000 --- a/payloads/libpayload/drivers/timer/ipq40xx.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2015, 2016, The Linux Foundation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of The Linux Foundation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include <libpayload.h> - -#define GCNT_FREQ_MHZ 48 - -#define MSM_TMR_BASE ((void *)0x004a1000u) -#define GCNT_CNTCV_LO (MSM_TMR_BASE + 0x1000) -#define GCNT_CNTCV_HI (MSM_TMR_BASE + 0x1004) - -uint64_t timer_hz(void) -{ - return GCNT_FREQ_MHZ * 1000 * 1000; -} - -uint64_t timer_raw_value(void) -{ - uint32_t hi, lo; - - do { - hi = read32(GCNT_CNTCV_HI); - lo = read32(GCNT_CNTCV_LO); - } while (hi != read32(GCNT_CNTCV_HI)); - - return ((((uint64_t)hi) << 32) | lo); -} diff --git a/payloads/libpayload/drivers/timer/ipq806x.c b/payloads/libpayload/drivers/timer/ipq806x.c deleted file mode 100644 index f39f23d..0000000 --- a/payloads/libpayload/drivers/timer/ipq806x.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the depthcharge project. - * - * Copyright (C) 2014 The Linux Foundation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <libpayload.h> - -/* - * TODO(vbendeb): reverted this hack once proper timer code is in place (see - * http://crosbug.com/p/28880 for details. - */ -#define MIN_TIMER_FREQ 1000000 - -uint64_t timer_hz(void) -{ - return (CONFIG_LP_IPQ806X_TIMER_FREQ >= MIN_TIMER_FREQ) ? - CONFIG_LP_IPQ806X_TIMER_FREQ : MIN_TIMER_FREQ; -} - -uint64_t timer_raw_value(void) -{ - uint64_t rawv = readl((void *)CONFIG_LP_IPQ806X_TIMER_REG); - - /* - * This is extremely crude, but it kicks in only for the case when the - * timer clock frequency is below 1MHz, which should never be the case - * on a properly configured system. The compiler will eliminate the - * check as long as config value exceeds 1MHz. - */ - if (CONFIG_LP_IPQ806X_TIMER_FREQ < MIN_TIMER_FREQ) - rawv *= (MIN_TIMER_FREQ / CONFIG_LP_IPQ806X_TIMER_FREQ); - - return rawv; -} diff --git a/payloads/libpayload/drivers/timer/mct.c b/payloads/libpayload/drivers/timer/mct.c deleted file mode 100644 index 992643d..0000000 --- a/payloads/libpayload/drivers/timer/mct.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <arch/io.h> -#include <libpayload.h> -#include <libpayload-config.h> -#include <stdint.h> - -#include "config.h" - -struct __attribute__((packed)) mct_regs -{ - uint32_t mct_cfg; - uint8_t reserved0[0xfc]; - uint32_t g_cnt_l; - uint32_t g_cnt_u; - uint8_t reserved1[0x8]; - uint32_t g_cnt_wstat; - uint8_t reserved2[0xec]; - uint32_t g_comp0_l; - uint32_t g_comp0_u; - uint32_t g_comp0_addr_incr; - uint8_t reserved3[0x4]; - uint32_t g_comp1_l; - uint32_t g_comp1_u; - uint32_t g_comp1_addr_incr; - uint8_t reserved4[0x4]; - uint32_t g_comp2_l; - uint32_t g_comp2_u; - uint32_t g_comp2_addr_incr; - uint8_t reserved5[0x4]; - uint32_t g_comp3_l; - uint32_t g_comp3_u; - uint32_t g_comp3_addr_incr; - uint8_t reserved6[0x4]; - uint32_t g_tcon; - uint32_t g_int_cstat; - uint32_t g_int_enb; - uint32_t g_wstat; - uint8_t reserved7[0xb0]; - uint32_t l0_tcntb; - uint32_t l0_tcnto; - uint32_t l0_icntb; - uint32_t l0_icnto; - uint32_t l0_frcntb; - uint32_t l0_frcnto; - uint8_t reserved8[0x8]; - uint32_t l0_tcon; - uint8_t reserved9[0xc]; - uint32_t l0_int_cstat; - uint32_t l0_int_enb; - uint8_t reserved10[0x8]; - uint32_t l0_wstat; - uint8_t reserved11[0xbc]; - uint32_t l1_tcntb; - uint32_t l1_tcnto; - uint32_t l1_icntb; - uint32_t l1_icnto; - uint32_t l1_frcntb; - uint32_t l1_frcnto; - uint8_t reserved12[0x8]; - uint32_t l1_tcon; - uint8_t reserved13[0xc]; - uint32_t l1_int_cstat; - uint32_t l1_int_enb; - uint8_t reserved14[0x8]; - uint32_t l1_wstat; -}; - -uint64_t timer_hz(void) -{ - return CONFIG_LP_TIMER_MCT_HZ; -} - -uint64_t timer_raw_value(void) -{ - static int enabled = 0; - - struct mct_regs * const mct = - (struct mct_regs *)(uintptr_t)CONFIG_LP_TIMER_MCT_ADDRESS; - - if (!enabled) { - writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); - enabled = 1; - } - - uint64_t upper = readl(&mct->g_cnt_u); - uint64_t lower = readl(&mct->g_cnt_l); - - return (upper << 32) | lower; -} diff --git a/payloads/libpayload/drivers/timer/mtk_timer.c b/payloads/libpayload/drivers/timer/mtk_timer.c deleted file mode 100644 index 706ef48..0000000 --- a/payloads/libpayload/drivers/timer/mtk_timer.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 MediaTek Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <arch/io.h> -#include <libpayload.h> -#include <libpayload-config.h> -#include <stdint.h> - -static uint32_t *const mtk_tmrus = (void*)CONFIG_LP_TIMER_MTK_ADDRESS; - -uint64_t timer_hz(void) -{ - return CONFIG_LP_TIMER_MTK_HZ; -} - -uint64_t timer_raw_value(void) -{ - return (uint64_t)readl(mtk_tmrus); -} diff --git a/payloads/libpayload/drivers/timer/rktimer.c b/payloads/libpayload/drivers/timer/rktimer.c deleted file mode 100644 index 5b4ce6b..0000000 --- a/payloads/libpayload/drivers/timer/rktimer.c +++ /dev/null @@ -1,42 +0,0 @@ - -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Rockchip Electronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <arch/io.h> -#include <libpayload.h> -#include <stdint.h> -struct rk_timer { - u32 timer_load_count0; - u32 timer_load_count1; - u32 timer_curr_value0; - u32 timer_curr_value1; - u32 timer_ctrl_reg; - u32 timer_int_status; -}; - -uint64_t timer_hz(void) -{ - return 24000000; -} - -uint64_t timer_raw_value(void) -{ - uint64_t upper; - uint64_t lower; - struct rk_timer *rk_timer; - rk_timer = (struct rk_timer *) CONFIG_LP_TIMER_RK_ADDRESS; - lower = (uint64_t) rk_timer->timer_curr_value0; - upper = (uint64_t) rk_timer->timer_curr_value1; - return (upper << 32) | lower; -} diff --git a/payloads/libpayload/drivers/timer/tegra_1us.c b/payloads/libpayload/drivers/timer/tegra_1us.c deleted file mode 100644 index f227ad0..0000000 --- a/payloads/libpayload/drivers/timer/tegra_1us.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <libpayload.h> -#include <libpayload-config.h> - -static uint32_t * const tegra_tmrus = (void *)CONFIG_LP_TIMER_TEGRA_1US_ADDRESS; - -uint64_t timer_hz(void) -{ - return 1000 * 1000; -} - -uint64_t timer_raw_value(void) -{ - return readl(tegra_tmrus); -}

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Patch set updated for coreboot: libpayload: split "Drivers" config section in Kconfig
by Stefan Reinauer 28 Jul '16

28 Jul '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15914 -gerrit commit 8e89fd62dcf8846262918f9ec9b50e015277843f Author: Antonello Dettori <dev(a)dettori.io> Date: Wed Jul 27 12:41:04 2016 +0200 libpayload: split "Drivers" config section in Kconfig Move the configuration of the timer, storage and USB drivers from the main Kconfig to three separate ones stored in the respective directories. This reduces the LOC of Kconfig and makes it more manageable. Change-Id: I0786dbc1d5d8317c8ccb600f5de9ef4a8243d035 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- payloads/libpayload/Kconfig | 283 +--------------------------- payloads/libpayload/drivers/storage/Kconfig | 59 ++++++ payloads/libpayload/drivers/timer/Kconfig | 129 +++++++++++++ payloads/libpayload/drivers/usb/Kconfig | 129 +++++++++++++ 4 files changed, 320 insertions(+), 280 deletions(-) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 276eb30..51826ea 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -354,286 +354,9 @@ config SPEAKER depends on ARCH_X86 default y -config STORAGE - bool "Support for storage devices" - default y - help - Select this option if you want support for storage devices (like - hard drives, memory sticks or optical drives). - -config STORAGE_64BIT_LBA - bool "Use 64-bit integers to address sectors" - depends on STORAGE - default n - help - If this is selected, sectors will be addressed by an 64-bit integer. - Select this to support LBA-48 for ATA drives. - -config STORAGE_ATA - bool "Support ATA drives (i.e. hard drives)" - depends on STORAGE - default y - help - Select this option if you want support for ATA storage devices - (i.e. hard drives). - -config STORAGE_ATAPI - bool "Support ATAPI drives (i.e. optical drives)" - depends on STORAGE - default y - select STORAGE_ATA - help - Select this option if you want support for ATAPI storage devices - (i.e. optical drives like CD or DVD drives). - -config STORAGE_AHCI - bool "Support for AHCI host controllers" - depends on STORAGE && (STORAGE_ATA || STORAGE_ATAPI) && PCI - default y - help - Select this option if you want support for SATA controllers in - AHCI mode. - -config STORAGE_AHCI_ONLY_TESTED - bool "Only enable tested controllers" - depends on STORAGE_AHCI - default y - help - If this option is selected only AHCI controllers which are known - to work will be used. - -config TIMER_RDTSC - bool - default y - depends on ARCH_X86 - -choice - prompt "Timer driver" - default TIMER_NONE - depends on !ARCH_X86 - -config TIMER_NONE - bool "None" - help - The timer driver is provided by the payload itself. - -config TIMER_MCT - bool "Exynos MCT" - -config TIMER_TEGRA_1US - bool "Tegra 1us" - -config TIMER_IPQ806X - bool "Timer for ipq806x platforms" - -config TIMER_ARMADA38X - bool "Timer for armada38x platforms" - help - This is the timer driver for marvell armada38x - platforms. - -config TIMER_IPQ40XX - bool "Timer for ipq40xx platforms" - help - This is the timer driver for QCA IPQ40xx based - platforms. - -config TIMER_RK - bool "Timer for Rockchip" - -config TIMER_BG4CD - bool "Marvell BG4CD" - -config TIMER_CYGNUS - bool "Timer for Cygnus" - -config TIMER_IMG_PISTACHIO - bool "Timer for IMG Pistachio" - -config TIMER_MTK - bool "Timer for MediaTek MT8173" - -endchoice - -config TIMER_MCT_HZ - int "Exynos MCT frequency" - depends on TIMER_MCT - default 24000000 - -config TIMER_MCT_ADDRESS - hex "Exynos MCT base address" - depends on TIMER_MCT - default 0x101c0000 - -config TIMER_RK_ADDRESS - hex "Rockchip timer base address" - depends on TIMER_RK - default 0xff810020 - -config TIMER_TEGRA_1US_ADDRESS - hex "Tegra u1s timer base address" - depends on TIMER_TEGRA_1US - default 0x60005010 - -config IPQ806X_TIMER_FREQ - int "Hardware timer frequency" - default 32000 - depends on TIMER_IPQ806X - help - IPQ hardware presently provides a single timer running at 32KHz, a - finer granulariry timer is available but is not yet enabled. - -config IPQ806X_TIMER_REG - hex "Timer register address" - default 0x0200A008 - depends on TIMER_IPQ806X - help - Address of the register to read a free running timer value. - -config ARMADA38X_TIMER_FREQ - int "Hardware timer frequency" - depends on TIMER_ARMADA38X - default 25000000 - -config ARMADA38X_TIMER_REG - hex "Timer register address" - default 0xF1020314 - depends on TIMER_ARMADA38X - -config IPROC_PERIPH_GLB_TIM_REG_BASE - hex "Cygnus timer base address" - depends on TIMER_CYGNUS - default 0x19020200 - -config TIMER_MTK_HZ - int "MediaTek GPT frequency" - depends on TIMER_MTK - default 13000000 - help - Clock frequency of MediaTek General Purpose Timer. - -config TIMER_MTK_ADDRESS - hex "MTK GPT register address" - depends on TIMER_MTK - default 0x10008048 - help - Address of GPT4's counter register to read the FREERUN-mode timer value. - -config USB - bool "USB Support" - default y - -config USB_UHCI - bool "Support for USB UHCI controllers" - depends on USB && ARCH_X86 - default y - help - Select this option if you are going to use USB 1.1 on an Intel based - system. - -config USB_OHCI - bool "Support for USB OHCI controllers" - depends on USB - default y - help - Select this option if you are going to use USB 1.1 on a non-Intel based - system. - -config USB_EHCI - bool "Support for USB EHCI controllers" - depends on USB - default y - help - Select this option if you want to use USB 2.0 - -config USB_XHCI - bool "Support for USB xHCI controllers" - depends on USB - default y - help - Select this option if you want to use USB 3.0 - -config USB_XHCI_MTK_QUIRK - bool "Support for USB xHCI controllers on MTK SoC" - depends on USB_XHCI - help - Select this option if you want to use USB 3.0 on MTK platform. - -config USB_DWC2 - bool "Support for USB DesignWare HCD controllers" - depends on USB - help - Select this option if you want to use DesignWare USB 2.0 host controller - -config USB_HID - bool "Support for USB keyboards" - depends on USB - default y - help - Select this option if you want to use devices complying to the - USB HID (Human Interface Device) standard. Such devices are for - example keyboards and mice. Currently only keyboards are supported. - Say Y here unless you know exactly what you are doing. - -config USB_HUB - bool "Support for USB hubs" - depends on USB - default y - help - Select this option if you want to compile in support for USB hubs. - Say Y here unless you know exactly what you are doing. - -config USB_EHCI_HOSTPC_ROOT_HUB_TT - bool "Support for USB EHCI ROOT HUB that has TT" - depends on USB_EHCI - default n - help - Select this option if USB EHCI root hub supports TT (Transaction - Translator). - To support this TT feature we read port-speed from non-standard - register HOSTPC (offset 84h of Operational Register base). - -config USB_MSC - bool "Support for USB storage" - depends on USB - default y - help - Select this option if you want to compile in support for USB mass - storage devices (USB memory sticks, hard drives, CDROM/DVD drives) - Say Y here unless you know exactly what you are doing. - -config USB_GEN_HUB - bool - default n if (!USB_HUB && !USB_XHCI) - default y if (USB_HUB || USB_XHCI) -config USB_PCI - bool "Auto-scan PCI bus for USB host controllers" - depends on USB - default y if ARCH_X86 - default n - -config UDC - bool "USB device mode support" - default n - help - Select this option to add support for running as - a USB device. - -config UDC_CI - bool "ChipIdea driver for USB device mode" - depends on UDC - default n - help - Select this option to add the driver for ChipIdea - USB device controller. - -config UDC_DWC2 - bool "Designware driver for USB device mode" - depends on UDC - default n - help - Select this option to add the driver for Designware - USB device controller. +source "drivers/timer/Kconfig" +source "drivers/storage/Kconfig" +source "drivers/usb/Kconfig" endmenu diff --git a/payloads/libpayload/drivers/storage/Kconfig b/payloads/libpayload/drivers/storage/Kconfig new file mode 100644 index 0000000..961144e --- /dev/null +++ b/payloads/libpayload/drivers/storage/Kconfig @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +config STORAGE + bool "Support for storage devices" + default y + help + Select this option if you want support for storage devices (like + hard drives, memory sticks or optical drives). + +config STORAGE_64BIT_LBA + bool "Use 64-bit integers to address sectors" + depends on STORAGE + default n + help + If this is selected, sectors will be addressed by an 64-bit integer. + Select this to support LBA-48 for ATA drives. + +config STORAGE_ATA + bool "Support ATA drives (i.e. hard drives)" + depends on STORAGE + default y + help + Select this option if you want support for ATA storage devices + (i.e. hard drives). + +config STORAGE_ATAPI + bool "Support ATAPI drives (i.e. optical drives)" + depends on STORAGE + default y + select STORAGE_ATA + help + Select this option if you want support for ATAPI storage devices + (i.e. optical drives like CD or DVD drives). + +config STORAGE_AHCI + bool "Support for AHCI host controllers" + depends on STORAGE && (STORAGE_ATA || STORAGE_ATAPI) && PCI + default y + help + Select this option if you want support for SATA controllers in + AHCI mode. + +config STORAGE_AHCI_ONLY_TESTED + bool "Only enable tested controllers" + depends on STORAGE_AHCI + default y + help + If this option is selected only AHCI controllers which are known + to work will be used. diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig new file mode 100644 index 0000000..8f047fa --- /dev/null +++ b/payloads/libpayload/drivers/timer/Kconfig @@ -0,0 +1,129 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +config TIMER_RDTSC + bool + default y + depends on ARCH_X86 + +choice + prompt "Timer driver" + default TIMER_NONE + depends on !ARCH_X86 + +config TIMER_NONE + bool "None" + help + The timer driver is provided by the payload itself. + +config TIMER_MCT + bool "Exynos MCT" + +config TIMER_TEGRA_1US + bool "Tegra 1us" + +config TIMER_IPQ806X + bool "Timer for ipq806x platforms" + +config TIMER_ARMADA38X + bool "Timer for armada38x platforms" + help + This is the timer driver for marvell armada38x + platforms. + +config TIMER_IPQ40XX + bool "Timer for ipq40xx platforms" + help + This is the timer driver for QCA IPQ40xx based + platforms. + +config TIMER_RK + bool "Timer for Rockchip" + +config TIMER_BG4CD + bool "Marvell BG4CD" + +config TIMER_CYGNUS + bool "Timer for Cygnus" + +config TIMER_IMG_PISTACHIO + bool "Timer for IMG Pistachio" + +config TIMER_MTK + bool "Timer for MediaTek MT8173" + +endchoice + +config TIMER_MCT_HZ + int "Exynos MCT frequency" + depends on TIMER_MCT + default 24000000 + +config TIMER_MCT_ADDRESS + hex "Exynos MCT base address" + depends on TIMER_MCT + default 0x101c0000 + +config TIMER_RK_ADDRESS + hex "Rockchip timer base address" + depends on TIMER_RK + default 0xff810020 + +config TIMER_TEGRA_1US_ADDRESS + hex "Tegra u1s timer base address" + depends on TIMER_TEGRA_1US + default 0x60005010 + +config IPQ806X_TIMER_FREQ + int "Hardware timer frequency" + default 32000 + depends on TIMER_IPQ806X + help + IPQ hardware presently provides a single timer running at 32KHz, a + finer granulariry timer is available but is not yet enabled. + +config IPQ806X_TIMER_REG + hex "Timer register address" + default 0x0200A008 + depends on TIMER_IPQ806X + help + Address of the register to read a free running timer value. + +config ARMADA38X_TIMER_FREQ + int "Hardware timer frequency" + depends on TIMER_ARMADA38X + default 25000000 + +config ARMADA38X_TIMER_REG + hex "Timer register address" + default 0xF1020314 + depends on TIMER_ARMADA38X + +config IPROC_PERIPH_GLB_TIM_REG_BASE + hex "Cygnus timer base address" + depends on TIMER_CYGNUS + default 0x19020200 + +config TIMER_MTK_HZ + int "MediaTek GPT frequency" + depends on TIMER_MTK + default 13000000 + help + Clock frequency of MediaTek General Purpose Timer. + +config TIMER_MTK_ADDRESS + hex "MTK GPT register address" + depends on TIMER_MTK + default 0x10008048 + help + Address of GPT4's counter register to read the FREERUN-mode timer value. + diff --git a/payloads/libpayload/drivers/usb/Kconfig b/payloads/libpayload/drivers/usb/Kconfig new file mode 100644 index 0000000..e1b68f7 --- /dev/null +++ b/payloads/libpayload/drivers/usb/Kconfig @@ -0,0 +1,129 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config USB + bool "USB Support" + default y + +config USB_UHCI + bool "Support for USB UHCI controllers" + depends on USB && ARCH_X86 + default y + help + Select this option if you are going to use USB 1.1 on an Intel based + system. + +config USB_OHCI + bool "Support for USB OHCI controllers" + depends on USB + default y + help + Select this option if you are going to use USB 1.1 on a non-Intel based + system. + +config USB_EHCI + bool "Support for USB EHCI controllers" + depends on USB + default y + help + Select this option if you want to use USB 2.0 + +config USB_XHCI + bool "Support for USB xHCI controllers" + depends on USB + default y + help + Select this option if you want to use USB 3.0 + +config USB_XHCI_MTK_QUIRK + bool "Support for USB xHCI controllers on MTK SoC" + depends on USB_XHCI + help + Select this option if you want to use USB 3.0 on MTK platform. + +config USB_DWC2 + bool "Support for USB DesignWare HCD controllers" + depends on USB + help + Select this option if you want to use DesignWare USB 2.0 host controller + +config USB_HID + bool "Support for USB keyboards" + depends on USB + default y + help + Select this option if you want to use devices complying to the + USB HID (Human Interface Device) standard. Such devices are for + example keyboards and mice. Currently only keyboards are supported. + Say Y here unless you know exactly what you are doing. + +config USB_HUB + bool "Support for USB hubs" + depends on USB + default y + help + Select this option if you want to compile in support for USB hubs. + Say Y here unless you know exactly what you are doing. + +config USB_EHCI_HOSTPC_ROOT_HUB_TT + bool "Support for USB EHCI ROOT HUB that has TT" + depends on USB_EHCI + default n + help + Select this option if USB EHCI root hub supports TT (Transaction + Translator). + To support this TT feature we read port-speed from non-standard + register HOSTPC (offset 84h of Operational Register base). + +config USB_MSC + bool "Support for USB storage" + depends on USB + default y + help + Select this option if you want to compile in support for USB mass + storage devices (USB memory sticks, hard drives, CDROM/DVD drives) + Say Y here unless you know exactly what you are doing. + +config USB_GEN_HUB + bool + default n if (!USB_HUB && !USB_XHCI) + default y if (USB_HUB || USB_XHCI) +config USB_PCI + bool "Auto-scan PCI bus for USB host controllers" + depends on USB + default y if ARCH_X86 + default n + +config UDC + bool "USB device mode support" + default n + help + Select this option to add support for running as + a USB device. + +config UDC_CI + bool "ChipIdea driver for USB device mode" + depends on UDC + default n + help + Select this option to add the driver for ChipIdea + USB device controller. + +config UDC_DWC2 + bool "Designware driver for USB device mode" + depends on UDC + default n + help + Select this option to add the driver for Designware + USB device controller. +

1 0

Patch merged into coreboot/master: util: Correct typo in MSR_EBC_SOFT_POWERON
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit e3e2bb0a892bc185a52f210bcae15db268c1d034 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 26 18:34:14 2016 +0200 util: Correct typo in MSR_EBC_SOFT_POWERON Change-Id: Iba5fc92d8740d0bb7d41f8a83513ba7fb97be592 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/15900 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/15900 for details. -gerrit

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