coreboot-gerrit July 2016

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New patch to review for coreboot: elmex/pcm20540x: Copy of amd/persimmon
by Kyösti Mälkki 28 Jul '16

28 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15928 -gerrit commit fc82c6c8acbbee2bc2221c9cf5458cbc438b21c0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 28 16:12:12 2016 +0300 elmex/pcm20540x: Copy of amd/persimmon Change-Id: Ic172fc57ad0aa2b6a9be3f493664127a37861468 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/elmex/pcm205400/BiosCallOuts.c | 93 ++++++ src/mainboard/elmex/pcm205400/Kconfig | 77 +++++ src/mainboard/elmex/pcm205400/Kconfig.name | 2 + src/mainboard/elmex/pcm205400/Makefile.inc | 29 ++ src/mainboard/elmex/pcm205400/OemCustomize.c | 157 ++++++++++ src/mainboard/elmex/pcm205400/OptionsIds.h | 56 ++++ .../elmex/pcm205400/PlatformGnbPcieComplex.h | 65 ++++ src/mainboard/elmex/pcm205400/acpi/gpe.asl | 78 +++++ src/mainboard/elmex/pcm205400/acpi/ide.asl | 240 +++++++++++++++ src/mainboard/elmex/pcm205400/acpi/mainboard.asl | 63 ++++ src/mainboard/elmex/pcm205400/acpi/routing.asl | 336 +++++++++++++++++++++ src/mainboard/elmex/pcm205400/acpi/sata.asl | 145 +++++++++ src/mainboard/elmex/pcm205400/acpi/sleep.asl | 117 +++++++ src/mainboard/elmex/pcm205400/acpi/superio.asl | 14 + src/mainboard/elmex/pcm205400/acpi/usb_oc.asl | 170 +++++++++++ src/mainboard/elmex/pcm205400/acpi_tables.c | 53 ++++ src/mainboard/elmex/pcm205400/board_info.txt | 5 + src/mainboard/elmex/pcm205400/buildOpts.c | 297 ++++++++++++++++++ src/mainboard/elmex/pcm205400/cmos.layout | 76 +++++ src/mainboard/elmex/pcm205400/devicetree.cb | 157 ++++++++++ src/mainboard/elmex/pcm205400/dsdt.asl | 63 ++++ src/mainboard/elmex/pcm205400/irq_tables.c | 111 +++++++ src/mainboard/elmex/pcm205400/mainboard.c | 178 +++++++++++ src/mainboard/elmex/pcm205400/mptable.c | 148 +++++++++ src/mainboard/elmex/pcm205400/platform_cfg.h | 254 ++++++++++++++++ src/mainboard/elmex/pcm205400/romstage.c | 111 +++++++ src/mainboard/elmex/pcm205401/BiosCallOuts.c | 93 ++++++ src/mainboard/elmex/pcm205401/Kconfig | 77 +++++ src/mainboard/elmex/pcm205401/Kconfig.name | 2 + src/mainboard/elmex/pcm205401/Makefile.inc | 29 ++ src/mainboard/elmex/pcm205401/OemCustomize.c | 157 ++++++++++ src/mainboard/elmex/pcm205401/OptionsIds.h | 56 ++++ .../elmex/pcm205401/PlatformGnbPcieComplex.h | 65 ++++ src/mainboard/elmex/pcm205401/acpi/gpe.asl | 78 +++++ src/mainboard/elmex/pcm205401/acpi/ide.asl | 240 +++++++++++++++ src/mainboard/elmex/pcm205401/acpi/mainboard.asl | 63 ++++ src/mainboard/elmex/pcm205401/acpi/routing.asl | 336 +++++++++++++++++++++ src/mainboard/elmex/pcm205401/acpi/sata.asl | 145 +++++++++ src/mainboard/elmex/pcm205401/acpi/sleep.asl | 117 +++++++ src/mainboard/elmex/pcm205401/acpi/superio.asl | 14 + src/mainboard/elmex/pcm205401/acpi/usb_oc.asl | 170 +++++++++++ src/mainboard/elmex/pcm205401/acpi_tables.c | 53 ++++ src/mainboard/elmex/pcm205401/board_info.txt | 5 + src/mainboard/elmex/pcm205401/buildOpts.c | 297 ++++++++++++++++++ src/mainboard/elmex/pcm205401/cmos.layout | 76 +++++ src/mainboard/elmex/pcm205401/devicetree.cb | 157 ++++++++++ src/mainboard/elmex/pcm205401/dsdt.asl | 63 ++++ src/mainboard/elmex/pcm205401/irq_tables.c | 111 +++++++ src/mainboard/elmex/pcm205401/mainboard.c | 178 +++++++++++ src/mainboard/elmex/pcm205401/mptable.c | 148 +++++++++ src/mainboard/elmex/pcm205401/platform_cfg.h | 254 ++++++++++++++++ src/mainboard/elmex/pcm205401/romstage.c | 111 +++++++ 52 files changed, 6190 insertions(+) diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c new file mode 100644 index 0000000..9a2a9bb --- /dev/null +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "heapManager.h" +#include "SB800.h" +#include <stdlib.h> + +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/* Call the host environment interface to provide a user hook opportunity. */ +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. + // Make sure the right speed settings are selected. + ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + return AGESA_SUCCESS; +} + +/* PCIE slot reset control */ +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + PCIe_SLOT_RESET_INFO *ResetInfo; + + UINT32 GpioMmioAddr; + UINT32 AcpiMmioAddr; + UINT8 Data8; + UINT16 Data16; + + FcnData = Data; + ResetInfo = ConfigPtr; + // Get SB800 MMIO Base (AcpiMmioAddr) + WriteIo8(0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16=Data8<<8; + WriteIo8(0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16|=Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + Status = AGESA_UNSUPPORTED; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + switch (ResetInfo->ResetId) + { + case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); + Status = AGESA_SUCCESS; + break; + } + break; + } + return Status; +} diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig new file mode 100644 index 0000000..e279aea --- /dev/null +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -0,0 +1,77 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ELMEX_PCM205400 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_AGESA_FAMILY14 + select NORTHBRIDGE_AMD_AGESA_FAMILY14 + select SOUTHBRIDGE_AMD_CIMX_SB800 + select SUPERIO_FINTEK_F81865F + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select GFXUMA + +config MAINBOARD_DIR + string + default elmex/pcm205400 + +config MAINBOARD_PART_NUMBER + string + default "pcm205400" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 2 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +#config VGA_BIOS_FILE +# string "VGA BIOS path and filename" +# depends on VGA_BIOS +# default "rom/video/OntarioGenericVbios.bin" + +config VGA_BIOS_ID + string + default "1002,9802" + +config SB800_AHCI_ROM + bool + default n + +endif # BOARD_ELMEX_PCM205400 diff --git a/src/mainboard/elmex/pcm205400/Kconfig.name b/src/mainboard/elmex/pcm205400/Kconfig.name new file mode 100644 index 0000000..445b588 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ELMEX_PCM205400 + bool "pcm205400" diff --git a/src/mainboard/elmex/pcm205400/Makefile.inc b/src/mainboard/elmex/pcm205400/Makefile.inc new file mode 100644 index 0000000..ba56286 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/Makefile.inc @@ -0,0 +1,29 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ifeq ($(CONFIG_AHCI_BIOS),y) +stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID)) +cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom +pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE)) +pci$(stripped_ahcibios_id).rom-type := optionrom +endif + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c new file mode 100644 index 0000000..825364e --- /dev/null +++ b/src/mainboard/elmex/pcm205400/OemCustomize.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "PlatformGnbPcieComplex.h" + +#include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> +#include <PlatformMemoryConfiguration.h> + +#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE + +/** + * OemCustomizeInitEarly + * + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] *InitEarly + * + * @retval VOID + * + **/ + +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +{ + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + +PCIe_PORT_DESCRIPTOR PortList [] = { + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeLvds, Aux1, Hdp1} + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} + } +}; + +PCIe_COMPLEX_DESCRIPTOR Brazos = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + ASSERT(Status == AGESA_SUCCESS); + + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(Brazos); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(PortList); + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); + memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); + memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); + + + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + PSO_END +}; + +const struct OEM_HOOK OemCustomize = { + .InitEarly = OemInitEarly, +}; diff --git a/src/mainboard/elmex/pcm205400/OptionsIds.h b/src/mainboard/elmex/pcm205400/OptionsIds.h new file mode 100644 index 0000000..2d8381b --- /dev/null +++ b/src/mainboard/elmex/pcm205400/OptionsIds.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..4132c7c --- /dev/null +++ b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/elmex/pcm205400/acpi/gpe.asl b/src/mainboard/elmex/pcm205400/acpi/gpe.asl new file mode 100644 index 0000000..2f22758 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/gpe.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ + +/* Contains the GPEs for USB overcurrent */ +#include "usb_oc.asl" diff --git a/src/mainboard/elmex/pcm205400/acpi/ide.asl b/src/mainboard/elmex/pcm205400/acpi/ide.asl new file mode 100644 index 0000000..59ea078 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/ide.asl @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0, Serialized) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, Serialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF, 0, Serialized) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF, 0, Serialized) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/elmex/pcm205400/acpi/mainboard.asl b/src/mainboard/elmex/pcm205400/acpi/mainboard.asl new file mode 100644 index 0000000..b666a4f --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/mainboard.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Data to be patched by the BIOS during POST */ +/* FIXME the patching is not done yet! */ +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +Scope(\_SB) { + Method(OSFL, 0){ + + if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + + if(CondRefOf(\_OSI)) + { + Store(1, OSVR) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSVR) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSVR) /* Linux */ + } Else { + Store(4, OSVR) /* Gotta be WinCE */ + } + } + Return(OSVR) + } +} + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ diff --git a/src/mainboard/elmex/pcm205400/acpi/routing.asl b/src/mainboard/elmex/pcm205400/acpi/routing.asl new file mode 100644 index 0000000..6f94b45 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/routing.asl @@ -0,0 +1,336 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */ + Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */ + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 19 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + + /* TODO: pcie */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */ + Package(){0x0003FFFF, 0, 0, 0x14 }, + Package(){0x0003FFFF, 1, 0, 0x15 }, + Package(){0x0003FFFF, 2, 0, 0x16 }, + Package(){0x0003FFFF, 3, 0, 0x17 }, + Package(){0x0004FFFF, 0, 0, 0x15 }, + Package(){0x0004FFFF, 1, 0, 0x16 }, + Package(){0x0004FFFF, 2, 0, 0x17 }, + Package(){0x0004FFFF, 3, 0, 0x14 }, + Package(){0x0005FFFF, 0, 0, 0x16 }, + Package(){0x0005FFFF, 1, 0, 0x17 }, + Package(){0x0005FFFF, 2, 0, 0x14 }, + Package(){0x0005FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/elmex/pcm205400/acpi/sata.asl b/src/mainboard/elmex/pcm205400/acpi/sata.asl new file mode 100644 index 0000000..9e0e535 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/sata.asl @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/elmex/pcm205400/acpi/sleep.asl b/src/mainboard/elmex/pcm205400/acpi/sleep.asl new file mode 100644 index 0000000..b3fd07e --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/sleep.asl @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, Local1) + Store(Local1, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/elmex/pcm205400/acpi/superio.asl b/src/mainboard/elmex/pcm205400/acpi/superio.asl new file mode 100644 index 0000000..daf6e91 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/superio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl new file mode 100644 index 0000000..6e9c701 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/elmex/pcm205400/acpi_tables.c b/src/mainboard/elmex/pcm205400/acpi_tables.c new file mode 100644 index 0000000..9b92c05 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi_tables.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam14.h> + + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/elmex/pcm205400/board_info.txt b/src/mainboard/elmex/pcm205400/board_info.txt new file mode 100644 index 0000000..85cb19a --- /dev/null +++ b/src/mainboard/elmex/pcm205400/board_info.txt @@ -0,0 +1,5 @@ +Board name: DBFT1-00-EVAL-KT (Persimmon) +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c new file mode 100644 index 0000000..fe4e779 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -0,0 +1,297 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + */ + +#include <stdlib.h> +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT TRUE +#define INSTALL_FAMILY_15_SUPPORT FALSE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + +#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE +#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE + + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE TRUE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 + +/* + * Agesa configuration values selection. + * Uncomment and specify the value for the configuration options + * needed by the system. + */ +#include "AGESA.h" + +/* The fixed MTRR values to be set after memory initialization. */ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, + { CPU_LIST_TERMINAL } +}; + +/* Include the files that instantiate the configuration definitions. */ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ +// This is the delivery package title, "BrazosPI" +// This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + +// This is the release version number of the AGESA component +// This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + diff --git a/src/mainboard/elmex/pcm205400/cmos.layout b/src/mainboard/elmex/pcm205400/cmos.layout new file mode 100644 index 0000000..f47185f --- /dev/null +++ b/src/mainboard/elmex/pcm205400/cmos.layout @@ -0,0 +1,76 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/elmex/pcm205400/devicetree.cb b/src/mainboard/elmex/pcm205400/devicetree.cb new file mode 100644 index 0000000..afab841 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/devicetree.cb @@ -0,0 +1,157 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/agesa/family14/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge PCIe slot + device pci 7.0 off end # PCIE P2P bridge + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge + + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB 10-13 + device pci 16.2 off end # EHCI USB 10-13 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + + #set up SB800 Fan control registers and IMC fan controls + register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common + register "fan0_enabled" = "1" + register "fan1_enabled" = "1" + register "imc_fan_zone0_enabled" = "1" + register "imc_fan_zone1_enabled" = "1" + + register "fan0_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan1_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + + register "imc_zone0_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" + register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone0_temp_offset" = "0x00" # No temp offset + register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + register "imc_zone1_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" + register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone1_temp_offset" = "0x00" # No temp offset + register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + # T56N has a Maximum operating temperature of 90C + # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C + # ZONEX_FANSPEEDS - Fan speeds as a "percentage" + register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" + register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" + register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" + register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" + + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 +# These seem unnecessary + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #domain +end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl new file mode 100644 index 0000000..0cf657f --- /dev/null +++ b/src/mainboard/elmex/pcm205400/dsdt.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + #include "acpi/mainboard.asl" + + #include <cpu/amd/agesa/family14/acpi/cpu.asl> + + #include "acpi/routing.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + Device(PCI0) { + + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/cimx/sb800/acpi/fch.asl> + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + } + } /* End Scope(_SB) */ + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c new file mode 100644 index 0000000..0c53417 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam14.h> + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c new file mode 100644 index 0000000..e0440f2 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -0,0 +1,178 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <device/pci_def.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <southbridge/amd/cimx/cimx_util.h> +#include <arch/acpi.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/amd/mtrr.h> +#include "SBPLATFORM.h" +#include <southbridge/amd/cimx/sb800/pci_devs.h> +#include <northbridge/amd/agesa/family14/pci_devs.h> + +void set_pcie_reset(void); +void set_pcie_dereset(void); + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + * + * The Persimmon PCI INTA/B/C/D pins are connected to + * FCH pins INTE/F/G/H on the schematic so these need + * to be routed as well. + */ +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ + [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + /* IDE, SATA */ + [0x40] = 0x0B,0x0B, + /* GPPInt0 - 3 */ + [0x50] = 0x0A,0x0B,0x0A,0x0B +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22/20 INTA-C */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + /* IDE, SATA */ + [0x40] = 0x11,0x13, + /* GPPInt0 - 3 */ + [0x50] = 0x10,0x11,0x12,0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +/* + * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H + * but because PCI INT_PIN swizzling isnt implemented to match + * the IDSEL (dev 3) of the slot, the table is adjusted for the + * swizzle and INTA is connected to PIRQH so PINA/B/C/D on + * off-chip devices should get mapped to PIRQH/E/F/G. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void) +{ +} + +/** + * TODO + * mainboard specific SB CIMx callback + */ +void set_pcie_dereset(void) +{ +} + + +/********************************************** + * Enable the dedicated functions of the board. + **********************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* enable GPP CLK0 thru CLK1 */ + /* disable GPP CLK2 thru SLT_GFX_CLK */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + write8(misc_mem_clk_cntrl + 0, 0xFF); + write8(misc_mem_clk_cntrl + 1, 0x00); + write8(misc_mem_clk_cntrl + 2, 0x00); + write8(misc_mem_clk_cntrl + 3, 0x00); + write8(misc_mem_clk_cntrl + 4, 0x00); + + /* + * Initialize ASF registers to an arbitrary address because someone + * long ago set things up this way inside the SPD read code. The + * SPD read code has been made generic and moved out of the board + * directory, so the ASF init is being done here. + */ + pm_iowrite(0x29, 0x80); + pm_iowrite(0x28, 0x61); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c new file mode 100644 index 0000000..8e954cd --- /dev/null +++ b/src/mainboard/elmex/pcm205400/mptable.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam14.h> +#include <SBPLATFORM.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <drivers/generic/ioapic/chip.h> +#include <arch/ioapic.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + /* Intialize the MP_Table */ + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ + smp_write_processors(mc); + + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); + + /* IDE */ + PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + + /* on board NIC & Slot PCIE */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + + /* PCI slots */ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0 */ + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + } + + /* PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + /* PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + /* PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + /* PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/elmex/pcm205400/platform_cfg.h b/src/mainboard/elmex/pcm205400/platform_cfg.h new file mode 100644 index 0000000..660be41 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/platform_cfg.h @@ -0,0 +1,254 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + +/** + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M + * + * In SB800, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) +#endif /* BIOS_SIZE */ + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @brief + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CONFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @brief bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x07 + +/** + * @def SATA_CONTROLLER + * @brief INCHIP Sata Controller + */ +#define SATA_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def SATA_MODE + * @brief INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_MODE CONFIG_SB800_SATA_MODE + +/** + * @brief INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @brief INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_IDE_MODE IDE_LEGACY_MODE + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +/* NOTE: inagua have to using internal clock, + * otherwise can not detect sata drive + */ +#define SATA_CLOCK_SOURCE INTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @brief INCHIP HDA controller + */ +#define AZALIA_CONTROLLER AZALIA_AUTO + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#define AZALIA_PIN_CONFIG 1 + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A + +/** + * @def GPP_CONTROLLER + */ +#define GPP_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#define GPP_CFGMODE GPP_CFGMODE_X1111 + +/** + * @def NB_SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define NB_SB_GEN2 TRUE + +/** + * @def SB_GPP_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define SB_GPP_GEN2 TRUE + +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visible always, even port empty + * FALSE - ports invisible if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE + +/** + * @def GEC_CONFIG + * 0 - Enable + * 1 - Disable + */ +#define GEC_CONFIG 0 + +static const CODECENTRY persimmon_codec_alc269[] = +{ + /* NID, PinConfig */ + {0x12, 0x411111F0}, + {0x14, 0x99130110}, + {0x21, 0x0121401F}, + {0x17, 0x411111F0}, + {0x18, 0x01A19820}, + {0x19, 0x411111F0}, + {0x1A, 0x0181302F}, + {0x1B, 0x411111F0}, + {0x1D, 0x40069E05}, + {0x1E, 0x411111F0}, + {0x20, 0x0001FFFF}, + {0xff, 0xffffffff} /* end of table */ +}; + +static const CODECTBLLIST codec_tablelist[] = +{ + {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, + {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} +}; + +/** + * @def AZALIA_OEM_VERB_TABLE + * Mainboard specific codec verb table list + */ +#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) + +/* set up an ACPI preferred power management profile */ +/* from acpi.h + * PM_UNSPECIFIED = 0, + * PM_DESKTOP = 1, + * PM_MOBILE = 2, + * PM_WORKSTATION = 3, + * PM_ENTERPRISE_SERVER = 4, + * PM_SOHO_SERVER = 5, + * PM_APPLIANCE_PC = 6, + * PM_PERFORMANCE_SERVER = 7, + * PM_TABLET = 8 + */ +#define FADT_PM_PROFILE 1 + +#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c new file mode 100644 index 0000000..0aad4f5 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <commonlib/loglevel.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/x86/bist.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81865f/f81865f.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <sb_cimx.h> +#include "SBPLATFORM.h" +#include "cbmem.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> + + +#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + /* + * All cores: allow caching of flash chip code and data + * (there are no cache-as-ram reliability concerns with family 14h) + */ + __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ + __writemsr (0xc0010062, 0); + + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + sb_Poweron_Init(); + + post_code(0x31); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + agesawrapper_amdinitreset(); + + post_code(0x39); + agesawrapper_amdinitearly(); + + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + + post_code(0x42); + agesawrapper_amdinitenv(); + amd_initenv(); + + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); + printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); + + post_code(0x54); /* Should never see this post code. */ +} diff --git a/src/mainboard/elmex/pcm205401/BiosCallOuts.c b/src/mainboard/elmex/pcm205401/BiosCallOuts.c new file mode 100644 index 0000000..9a2a9bb --- /dev/null +++ b/src/mainboard/elmex/pcm205401/BiosCallOuts.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "heapManager.h" +#include "SB800.h" +#include <stdlib.h> + +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/* Call the host environment interface to provide a user hook opportunity. */ +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. + // Make sure the right speed settings are selected. + ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + return AGESA_SUCCESS; +} + +/* PCIE slot reset control */ +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + PCIe_SLOT_RESET_INFO *ResetInfo; + + UINT32 GpioMmioAddr; + UINT32 AcpiMmioAddr; + UINT8 Data8; + UINT16 Data16; + + FcnData = Data; + ResetInfo = ConfigPtr; + // Get SB800 MMIO Base (AcpiMmioAddr) + WriteIo8(0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16=Data8<<8; + WriteIo8(0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16|=Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + Status = AGESA_UNSUPPORTED; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + switch (ResetInfo->ResetId) + { + case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); + Status = AGESA_SUCCESS; + break; + } + break; + } + return Status; +} diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig new file mode 100644 index 0000000..e80e68b --- /dev/null +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -0,0 +1,77 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ELMEX_PCM205401 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_AGESA_FAMILY14 + select NORTHBRIDGE_AMD_AGESA_FAMILY14 + select SOUTHBRIDGE_AMD_CIMX_SB800 + select SUPERIO_FINTEK_F81865F + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select GFXUMA + +config MAINBOARD_DIR + string + default elmex/pcm205401 + +config MAINBOARD_PART_NUMBER + string + default "pcm205401" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 2 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +#config VGA_BIOS_FILE +# string "VGA BIOS path and filename" +# depends on VGA_BIOS +# default "rom/video/OntarioGenericVbios.bin" + +config VGA_BIOS_ID + string + default "1002,9802" + +config SB800_AHCI_ROM + bool + default n + +endif # BOARD_ELMEX_PCM205401 diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name new file mode 100644 index 0000000..f70b215 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ELMEX_PCM205401 + bool "pcm205401" diff --git a/src/mainboard/elmex/pcm205401/Makefile.inc b/src/mainboard/elmex/pcm205401/Makefile.inc new file mode 100644 index 0000000..ba56286 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/Makefile.inc @@ -0,0 +1,29 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ifeq ($(CONFIG_AHCI_BIOS),y) +stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID)) +cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom +pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE)) +pci$(stripped_ahcibios_id).rom-type := optionrom +endif + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/elmex/pcm205401/OemCustomize.c b/src/mainboard/elmex/pcm205401/OemCustomize.c new file mode 100644 index 0000000..825364e --- /dev/null +++ b/src/mainboard/elmex/pcm205401/OemCustomize.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "PlatformGnbPcieComplex.h" + +#include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> +#include <PlatformMemoryConfiguration.h> + +#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE + +/** + * OemCustomizeInitEarly + * + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] *InitEarly + * + * @retval VOID + * + **/ + +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +{ + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + +PCIe_PORT_DESCRIPTOR PortList [] = { + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeLvds, Aux1, Hdp1} + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} + } +}; + +PCIe_COMPLEX_DESCRIPTOR Brazos = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + ASSERT(Status == AGESA_SUCCESS); + + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(Brazos); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(PortList); + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); + memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); + memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); + + + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + PSO_END +}; + +const struct OEM_HOOK OemCustomize = { + .InitEarly = OemInitEarly, +}; diff --git a/src/mainboard/elmex/pcm205401/OptionsIds.h b/src/mainboard/elmex/pcm205401/OptionsIds.h new file mode 100644 index 0000000..2d8381b --- /dev/null +++ b/src/mainboard/elmex/pcm205401/OptionsIds.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..4132c7c --- /dev/null +++ b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/elmex/pcm205401/acpi/gpe.asl b/src/mainboard/elmex/pcm205401/acpi/gpe.asl new file mode 100644 index 0000000..2f22758 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/gpe.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ + +/* Contains the GPEs for USB overcurrent */ +#include "usb_oc.asl" diff --git a/src/mainboard/elmex/pcm205401/acpi/ide.asl b/src/mainboard/elmex/pcm205401/acpi/ide.asl new file mode 100644 index 0000000..59ea078 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/ide.asl @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0, Serialized) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, Serialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF, 0, Serialized) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF, 0, Serialized) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/elmex/pcm205401/acpi/mainboard.asl b/src/mainboard/elmex/pcm205401/acpi/mainboard.asl new file mode 100644 index 0000000..b666a4f --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/mainboard.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Data to be patched by the BIOS during POST */ +/* FIXME the patching is not done yet! */ +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +Scope(\_SB) { + Method(OSFL, 0){ + + if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + + if(CondRefOf(\_OSI)) + { + Store(1, OSVR) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSVR) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSVR) /* Linux */ + } Else { + Store(4, OSVR) /* Gotta be WinCE */ + } + } + Return(OSVR) + } +} + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ diff --git a/src/mainboard/elmex/pcm205401/acpi/routing.asl b/src/mainboard/elmex/pcm205401/acpi/routing.asl new file mode 100644 index 0000000..6f94b45 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/routing.asl @@ -0,0 +1,336 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */ + Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */ + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 19 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + + /* TODO: pcie */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */ + Package(){0x0003FFFF, 0, 0, 0x14 }, + Package(){0x0003FFFF, 1, 0, 0x15 }, + Package(){0x0003FFFF, 2, 0, 0x16 }, + Package(){0x0003FFFF, 3, 0, 0x17 }, + Package(){0x0004FFFF, 0, 0, 0x15 }, + Package(){0x0004FFFF, 1, 0, 0x16 }, + Package(){0x0004FFFF, 2, 0, 0x17 }, + Package(){0x0004FFFF, 3, 0, 0x14 }, + Package(){0x0005FFFF, 0, 0, 0x16 }, + Package(){0x0005FFFF, 1, 0, 0x17 }, + Package(){0x0005FFFF, 2, 0, 0x14 }, + Package(){0x0005FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/elmex/pcm205401/acpi/sata.asl b/src/mainboard/elmex/pcm205401/acpi/sata.asl new file mode 100644 index 0000000..9e0e535 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/sata.asl @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/elmex/pcm205401/acpi/sleep.asl b/src/mainboard/elmex/pcm205401/acpi/sleep.asl new file mode 100644 index 0000000..b3fd07e --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/sleep.asl @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, Local1) + Store(Local1, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/elmex/pcm205401/acpi/superio.asl b/src/mainboard/elmex/pcm205401/acpi/superio.asl new file mode 100644 index 0000000..daf6e91 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/superio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/elmex/pcm205401/acpi/usb_oc.asl b/src/mainboard/elmex/pcm205401/acpi/usb_oc.asl new file mode 100644 index 0000000..6e9c701 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/usb_oc.asl @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/elmex/pcm205401/acpi_tables.c b/src/mainboard/elmex/pcm205401/acpi_tables.c new file mode 100644 index 0000000..9b92c05 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi_tables.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam14.h> + + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/elmex/pcm205401/board_info.txt b/src/mainboard/elmex/pcm205401/board_info.txt new file mode 100644 index 0000000..85cb19a --- /dev/null +++ b/src/mainboard/elmex/pcm205401/board_info.txt @@ -0,0 +1,5 @@ +Board name: DBFT1-00-EVAL-KT (Persimmon) +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/elmex/pcm205401/buildOpts.c b/src/mainboard/elmex/pcm205401/buildOpts.c new file mode 100644 index 0000000..fe4e779 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/buildOpts.c @@ -0,0 +1,297 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + */ + +#include <stdlib.h> +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT TRUE +#define INSTALL_FAMILY_15_SUPPORT FALSE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + +#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE +#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE + + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE TRUE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 + +/* + * Agesa configuration values selection. + * Uncomment and specify the value for the configuration options + * needed by the system. + */ +#include "AGESA.h" + +/* The fixed MTRR values to be set after memory initialization. */ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, + { CPU_LIST_TERMINAL } +}; + +/* Include the files that instantiate the configuration definitions. */ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ +// This is the delivery package title, "BrazosPI" +// This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + +// This is the release version number of the AGESA component +// This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + diff --git a/src/mainboard/elmex/pcm205401/cmos.layout b/src/mainboard/elmex/pcm205401/cmos.layout new file mode 100644 index 0000000..f47185f --- /dev/null +++ b/src/mainboard/elmex/pcm205401/cmos.layout @@ -0,0 +1,76 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/elmex/pcm205401/devicetree.cb b/src/mainboard/elmex/pcm205401/devicetree.cb new file mode 100644 index 0000000..afab841 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/devicetree.cb @@ -0,0 +1,157 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/agesa/family14/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge PCIe slot + device pci 7.0 off end # PCIE P2P bridge + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge + + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB 10-13 + device pci 16.2 off end # EHCI USB 10-13 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + + #set up SB800 Fan control registers and IMC fan controls + register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common + register "fan0_enabled" = "1" + register "fan1_enabled" = "1" + register "imc_fan_zone0_enabled" = "1" + register "imc_fan_zone1_enabled" = "1" + + register "fan0_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan1_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + + register "imc_zone0_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" + register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone0_temp_offset" = "0x00" # No temp offset + register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + register "imc_zone1_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" + register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone1_temp_offset" = "0x00" # No temp offset + register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + # T56N has a Maximum operating temperature of 90C + # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C + # ZONEX_FANSPEEDS - Fan speeds as a "percentage" + register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" + register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" + register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" + register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" + + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 +# These seem unnecessary + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #domain +end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/elmex/pcm205401/dsdt.asl b/src/mainboard/elmex/pcm205401/dsdt.asl new file mode 100644 index 0000000..0cf657f --- /dev/null +++ b/src/mainboard/elmex/pcm205401/dsdt.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + #include "acpi/mainboard.asl" + + #include <cpu/amd/agesa/family14/acpi/cpu.asl> + + #include "acpi/routing.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + Device(PCI0) { + + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/cimx/sb800/acpi/fch.asl> + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + } + } /* End Scope(_SB) */ + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/elmex/pcm205401/irq_tables.c b/src/mainboard/elmex/pcm205401/irq_tables.c new file mode 100644 index 0000000..0c53417 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/irq_tables.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam14.h> + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/elmex/pcm205401/mainboard.c b/src/mainboard/elmex/pcm205401/mainboard.c new file mode 100644 index 0000000..e0440f2 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/mainboard.c @@ -0,0 +1,178 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <device/pci_def.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <southbridge/amd/cimx/cimx_util.h> +#include <arch/acpi.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/amd/mtrr.h> +#include "SBPLATFORM.h" +#include <southbridge/amd/cimx/sb800/pci_devs.h> +#include <northbridge/amd/agesa/family14/pci_devs.h> + +void set_pcie_reset(void); +void set_pcie_dereset(void); + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + * + * The Persimmon PCI INTA/B/C/D pins are connected to + * FCH pins INTE/F/G/H on the schematic so these need + * to be routed as well. + */ +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ + [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + /* IDE, SATA */ + [0x40] = 0x0B,0x0B, + /* GPPInt0 - 3 */ + [0x50] = 0x0A,0x0B,0x0A,0x0B +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22/20 INTA-C */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + /* IDE, SATA */ + [0x40] = 0x11,0x13, + /* GPPInt0 - 3 */ + [0x50] = 0x10,0x11,0x12,0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +/* + * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H + * but because PCI INT_PIN swizzling isnt implemented to match + * the IDSEL (dev 3) of the slot, the table is adjusted for the + * swizzle and INTA is connected to PIRQH so PINA/B/C/D on + * off-chip devices should get mapped to PIRQH/E/F/G. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void) +{ +} + +/** + * TODO + * mainboard specific SB CIMx callback + */ +void set_pcie_dereset(void) +{ +} + + +/********************************************** + * Enable the dedicated functions of the board. + **********************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* enable GPP CLK0 thru CLK1 */ + /* disable GPP CLK2 thru SLT_GFX_CLK */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + write8(misc_mem_clk_cntrl + 0, 0xFF); + write8(misc_mem_clk_cntrl + 1, 0x00); + write8(misc_mem_clk_cntrl + 2, 0x00); + write8(misc_mem_clk_cntrl + 3, 0x00); + write8(misc_mem_clk_cntrl + 4, 0x00); + + /* + * Initialize ASF registers to an arbitrary address because someone + * long ago set things up this way inside the SPD read code. The + * SPD read code has been made generic and moved out of the board + * directory, so the ASF init is being done here. + */ + pm_iowrite(0x29, 0x80); + pm_iowrite(0x28, 0x61); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/elmex/pcm205401/mptable.c b/src/mainboard/elmex/pcm205401/mptable.c new file mode 100644 index 0000000..8e954cd --- /dev/null +++ b/src/mainboard/elmex/pcm205401/mptable.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam14.h> +#include <SBPLATFORM.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <drivers/generic/ioapic/chip.h> +#include <arch/ioapic.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + /* Intialize the MP_Table */ + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ + smp_write_processors(mc); + + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); + + /* IDE */ + PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + + /* on board NIC & Slot PCIE */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + + /* PCI slots */ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0 */ + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + } + + /* PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + /* PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + /* PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + /* PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/elmex/pcm205401/platform_cfg.h b/src/mainboard/elmex/pcm205401/platform_cfg.h new file mode 100644 index 0000000..660be41 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/platform_cfg.h @@ -0,0 +1,254 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + +/** + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M + * + * In SB800, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) +#endif /* BIOS_SIZE */ + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @brief + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CONFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @brief bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x07 + +/** + * @def SATA_CONTROLLER + * @brief INCHIP Sata Controller + */ +#define SATA_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def SATA_MODE + * @brief INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_MODE CONFIG_SB800_SATA_MODE + +/** + * @brief INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @brief INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_IDE_MODE IDE_LEGACY_MODE + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +/* NOTE: inagua have to using internal clock, + * otherwise can not detect sata drive + */ +#define SATA_CLOCK_SOURCE INTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @brief INCHIP HDA controller + */ +#define AZALIA_CONTROLLER AZALIA_AUTO + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#define AZALIA_PIN_CONFIG 1 + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A + +/** + * @def GPP_CONTROLLER + */ +#define GPP_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#define GPP_CFGMODE GPP_CFGMODE_X1111 + +/** + * @def NB_SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define NB_SB_GEN2 TRUE + +/** + * @def SB_GPP_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define SB_GPP_GEN2 TRUE + +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visible always, even port empty + * FALSE - ports invisible if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE + +/** + * @def GEC_CONFIG + * 0 - Enable + * 1 - Disable + */ +#define GEC_CONFIG 0 + +static const CODECENTRY persimmon_codec_alc269[] = +{ + /* NID, PinConfig */ + {0x12, 0x411111F0}, + {0x14, 0x99130110}, + {0x21, 0x0121401F}, + {0x17, 0x411111F0}, + {0x18, 0x01A19820}, + {0x19, 0x411111F0}, + {0x1A, 0x0181302F}, + {0x1B, 0x411111F0}, + {0x1D, 0x40069E05}, + {0x1E, 0x411111F0}, + {0x20, 0x0001FFFF}, + {0xff, 0xffffffff} /* end of table */ +}; + +static const CODECTBLLIST codec_tablelist[] = +{ + {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, + {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} +}; + +/** + * @def AZALIA_OEM_VERB_TABLE + * Mainboard specific codec verb table list + */ +#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) + +/* set up an ACPI preferred power management profile */ +/* from acpi.h + * PM_UNSPECIFIED = 0, + * PM_DESKTOP = 1, + * PM_MOBILE = 2, + * PM_WORKSTATION = 3, + * PM_ENTERPRISE_SERVER = 4, + * PM_SOHO_SERVER = 5, + * PM_APPLIANCE_PC = 6, + * PM_PERFORMANCE_SERVER = 7, + * PM_TABLET = 8 + */ +#define FADT_PM_PROFILE 1 + +#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/elmex/pcm205401/romstage.c b/src/mainboard/elmex/pcm205401/romstage.c new file mode 100644 index 0000000..0aad4f5 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/romstage.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <commonlib/loglevel.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/x86/bist.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81865f/f81865f.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <sb_cimx.h> +#include "SBPLATFORM.h" +#include "cbmem.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> + + +#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + /* + * All cores: allow caching of flash chip code and data + * (there are no cache-as-ram reliability concerns with family 14h) + */ + __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ + __writemsr (0xc0010062, 0); + + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + sb_Poweron_Init(); + + post_code(0x31); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + agesawrapper_amdinitreset(); + + post_code(0x39); + agesawrapper_amdinitearly(); + + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + + post_code(0x42); + agesawrapper_amdinitenv(); + amd_initenv(); + + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); + printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); + + post_code(0x54); /* Should never see this post code. */ +}

1 0

Patch set updated for coreboot: src/mainboard: Add vendor ELMEX
by Kyösti Mälkki 28 Jul '16

28 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15926 -gerrit commit 60ca98e76f51064660b3ccbf2c8f14826de687e6 Author: Yuichi Ito <yui.corebt(a)gmail.com> Date: Thu Jul 28 13:34:18 2016 +0900 src/mainboard: Add vendor ELMEX Change-Id: I263b54e0f49b6f1ba730c7f87de41f990ba8fe67 Signed-off-by: Yuichi Ito <yui.corebt(a)gmail.com> --- src/mainboard/elmex/Kconfig | 16 ++++++++++++++++ src/mainboard/elmex/Kconfig.name | 2 ++ 2 files changed, 18 insertions(+) diff --git a/src/mainboard/elmex/Kconfig b/src/mainboard/elmex/Kconfig new file mode 100644 index 0000000..d1fc9ad --- /dev/null +++ b/src/mainboard/elmex/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_ELMEX + +choice + prompt "Mainboard model" + +source "src/mainboard/elmex/*/Kconfig.name" + +endchoice + +source "src/mainboard/elmex/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "ELMEX" + +endif # VENDOR_ELMEX diff --git a/src/mainboard/elmex/Kconfig.name b/src/mainboard/elmex/Kconfig.name new file mode 100644 index 0000000..b2dcf2e --- /dev/null +++ b/src/mainboard/elmex/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ELMEX + bool "ELMEX"

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Update the copyrights
by Lee Leahy 28 Jul '16

28 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15852 -gerrit commit 2a90e84fabe33124d293257c235bf52310aab76f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 18:12:16 2016 -0700 drivers/intel/fsp2_0: Update the copyrights Update the copyright dates in the FSP 2.0 files. Add a copyright to Kconfig. TEST=Build and run on Galileo Gen2 Change-Id: I0ad0c5650bde0e31d01a04bcc7d22a19273fe29b Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 15 +++++++++++++++ src/drivers/intel/fsp2_0/Makefile.inc | 2 ++ src/drivers/intel/fsp2_0/hand_off_block.c | 2 +- src/drivers/intel/fsp2_0/include/fsp/api.h | 2 +- src/drivers/intel/fsp2_0/include/fsp/info_header.h | 2 +- src/drivers/intel/fsp2_0/include/fsp/util.h | 2 +- src/drivers/intel/fsp2_0/memory_init.c | 2 +- src/drivers/intel/fsp2_0/notify.c | 2 +- src/drivers/intel/fsp2_0/silicon_init.c | 2 +- src/drivers/intel/fsp2_0/util.c | 2 +- 10 files changed, 25 insertions(+), 8 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index a669870..01ce75d 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -1,3 +1,18 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2016 Intel Corp. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + config PLATFORM_USES_FSP2_0 bool select UEFI_2_4_BINDING diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index ff82390..4f36664 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -1,6 +1,8 @@ # # This file is part of the coreboot project. # +# Copyright (C) 2015-2016 Intel Corp. +# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index c9d5b8e..b7cb981 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 48cc54f..bc55c50 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 2d30614..f5db37d 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 9f4d67a..01186f7 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 8afa6d7..5b93a30 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index bd489d4..4e7e9c5 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index cc8c408..c069ff1 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 1d3c744..108457d 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) *

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Patch set updated for coreboot: superiotool: Add Nuvoton NCT6791D
by Omar Pakker 28 Jul '16

28 Jul '16

Omar Pakker just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15252 -gerrit commit 47e3dfadf8b7e071819ef57b954847cd1e82b45f Author: Omar Pakker <omarpakker+coreboot(a)gmail.com> Date: Sat Jun 18 15:33:43 2016 +0200 superiotool: Add Nuvoton NCT6791D This adds support for the Nuvoton NCT6791D Super I/O chip to the superiotool. The implementation is based on the Datasheet supplied by Nuvoton: Datasheet Version: January 8th, 2016 Revision 1.11 Datasheet deviation: - Defaults for control registers 0x20 and 0x21 are invalid. Datasheet: 0xc562. Actual: 0xc803. Change-Id: I8ced9738cd41960cbab7b5ea38ff19192d210672 Signed-off-by: Omar Pakker <omarpakker+coreboot(a)gmail.com> --- util/superiotool/nuvoton.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index fd161bb..82772e7 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -532,6 +532,56 @@ static const struct superio_registers reg_table[] = { {0x30,0xe0,0xe1,0xe2,EOT}, {0x20,0x20,0x04,0x05,EOT}}, {EOT}}}, + {0xc803, "NCT6791D", { + {NOLDN, NULL, + {0x07,0x10,0x11,0x13,0x14,0x1a,0x1b,0x1c,0x1d,0x20,0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b,0x2c,0x2d,0x2f,EOT}, + {0x00,0xff,0xff,0x00,0x00,0x30,0x70,0x10,0x00,0xc8,0x03,0xff,0x04,0x00,MISC,0x00,0x00,0xc0,0x00,0x01,0x00,MISC,EOT}}, + {0x01, "Parallel Port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,0xf2,EOT}, + {0x01,0x03,0xf8,0x04,0x00,0x00,EOT}}, + {0x03, "UART B, IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "Consumer IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, + {0x07, "GPIO 6, GPIO 7, GPIO 8", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xec,0xed,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x7f,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, WDT_MEM, GPIO 0, GPIO 1", + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfe,0xff,EOT}, + {0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO 2, GPIO 3, GPIO 4, GPIO 5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4,0xf5,0xf6,0xf7,0xfe,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x7f,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9,0xec,0xed,0xee,0xf0,0xf2,0xf3,0xf4,0xf6,0xf7,0xfc,0xfe,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x02,0x1a,0x00,0x00,0x00,0x00,0x00,0x10,0x5c,0x00,0x00,0x00,0xc0,0x00,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe6,0xe7,0xf0,0xf1,0xf2,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff,0xff,0xff,0x08,0xff,0x00,0x00,0x00,0x10,0x00,0x87,0x47,0x00,0x00,0x00,EOT}}, + {0x0d, "BCLK, WDT2, WDT_MEM", + {0xe0,0xe1,0xe7,0xe8,0xeb,0xed,0xf0,0xf3,EOT}, + {0x00,MISC,0x00,0x32,0x14,0x00,0x00,0x00,EOT}}, + {0x0e, "CIR Wake-Up", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-Drain selection", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9,0xf0,0xf1,0xf2,EOT}, + {0xff,0xff,0x7f,0xff,0xff,0xff,0x0f,0xff,0xff,0x9d,0x00,0x00,EOT}}, + {0x14, "Port 80 UART", + {0xe0,0xe1,0xe2,0xe3,0xe4,EOT}, + {0x80,0x00,0x00,0x10,0x00,EOT}}, + {0x16, "Deep Sleep", + {0x30,0xe0,0xe1,0xe2,0xe3,EOT}, + {0x20,0x20,0x04,0x05,0x01,EOT}}, + {EOT}}}, {EOT} };

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Patch set updated for coreboot: Documentation: Capitalize RAM, ROM and ACPI
by HAOUAS Elyes 28 Jul '16

28 Jul '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15927 -gerrit commit dbc978f89fb54af2b39e1415c27b539eef4e8382 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 28 13:08:24 2016 +0200 Documentation: Capitalize RAM, ROM and ACPI Change-Id: I06c1d0fe0e3d429e54d3777de679f9fc641f4eed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- Documentation/CorebootBuildingGuide.tex | 2 +- Documentation/Kconfig.tex | 6 +++--- Documentation/RFC/config.tex | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/CorebootBuildingGuide.tex b/Documentation/CorebootBuildingGuide.tex index dac031a..eb4dfd2 100644 --- a/Documentation/CorebootBuildingGuide.tex +++ b/Documentation/CorebootBuildingGuide.tex @@ -70,7 +70,7 @@ base on the AMD platform. \item 2013/12/20 Add Git, Gerrit, toolchains building. \item 2009/04/19 replace LinuxBIOS with coreboot \item 2004/06/02 url and language fixes from Ken Fuchs $<$kfuchs(a)winternet.com$>$ - \item 2004/02/10 acpi and option rom updates + \item 2004/02/10 ACPI and option ROM updates \item 2003/11/18 initial release \end{itemize} diff --git a/Documentation/Kconfig.tex b/Documentation/Kconfig.tex index 2b2bf7f..bac8f2b 100644 --- a/Documentation/Kconfig.tex +++ b/Documentation/Kconfig.tex @@ -13,7 +13,7 @@ Most Kconfig files set variables, which can be set as part of the Kconfig dialog For variables set by the user, see src/console/Kconfig. -For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as ram base. These are highly mainboard dependent. +For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as RAM base. These are highly mainboard dependent. Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally. @@ -28,8 +28,8 @@ We define the common rules for which variation to use below. \subsection{object file specification} There are several different types of objects specified in the tree. They are: \begin{description} -\item[obj]objects for the ram part of the code -\item[driver]drivers for the ram part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section. +\item[obj]objects for the RAM part of the code +\item[driver]drivers for the RAM part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section. \item[initobj]seperately-compiled code for the ROM section of coreboot \end{description} These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax. diff --git a/Documentation/RFC/config.tex b/Documentation/RFC/config.tex index 696ab7a..97fec9d 100644 --- a/Documentation/RFC/config.tex +++ b/Documentation/RFC/config.tex @@ -172,7 +172,7 @@ A sample file: \begin{verbatim} target x -# over-ride the default rom size in the mainboard file +# over-ride the default ROM size in the mainboard file option CONFIG_ROM_SIZE=1024*1024 mainboard amd/solo end

1 0

Patch set updated for coreboot: libpayload: replace cbfs_media api with region_device api
by Antonello Dettori 28 Jul '16

28 Jul '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15774 -gerrit commit 53314a152d7bdc2ec0e97913762e7504c84d2dec Author: Antonello Dettori <dev(a)dettori.io> Date: Thu Jul 21 15:30:46 2016 +0200 libpayload: replace cbfs_media api with region_device api Replace all the functionality provided by the cbfs_image api with the more recent region_device api used throughout the rest of the coreboot project. Change-Id: Ia79f532a9f8701f6c586609d38f6a88bfdf116e9 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- payloads/libpayload/arch/arm/dummy_media.c | 5 +- payloads/libpayload/arch/arm64/dummy_media.c | 5 +- payloads/libpayload/arch/mips/dummy_media.c | 5 +- payloads/libpayload/arch/x86/rom_media.c | 85 +----- payloads/libpayload/drivers/video/graphics.c | 1 - payloads/libpayload/include/cbfs.h | 13 +- payloads/libpayload/include/cbfs_core.h | 40 +-- payloads/libpayload/include/cbfs_ram.h | 57 ---- payloads/libpayload/include/mem_pool.h | 69 +++++ payloads/libpayload/include/region_device.h | 248 +++++++++++++++ payloads/libpayload/include/stddef.h | 2 + payloads/libpayload/include/stdlib.h | 19 ++ payloads/libpayload/libc/fmap.c | 16 +- payloads/libpayload/libcbfs/Makefile.inc | 3 +- payloads/libpayload/libcbfs/cbfs.c | 36 ++- payloads/libpayload/libcbfs/cbfs_core.c | 106 +++---- payloads/libpayload/libcbfs/mem_pool.c | 48 +++ payloads/libpayload/libcbfs/ram_media.c | 118 -------- payloads/libpayload/libcbfs/region_device.c | 434 +++++++++++++++++++++++++++ 19 files changed, 930 insertions(+), 380 deletions(-) diff --git a/payloads/libpayload/arch/arm/dummy_media.c b/payloads/libpayload/arch/arm/dummy_media.c index c67344f..e74d4c7 100644 --- a/payloads/libpayload/arch/arm/dummy_media.c +++ b/payloads/libpayload/arch/arm/dummy_media.c @@ -34,10 +34,7 @@ /* The generic cbfs code relies on the libpayload_init_default_cbfs_media * symbol. Therefore, provide an implementation that just throws an error. */ -int libpayload_init_default_cbfs_media(struct cbfs_media *media); - -__attribute__((weak)) int libpayload_init_default_cbfs_media( - struct cbfs_media *media) +__attribute__((weak)) int libpayload_init_default_cbfs_media(void) { return -1; } diff --git a/payloads/libpayload/arch/arm64/dummy_media.c b/payloads/libpayload/arch/arm64/dummy_media.c index c67344f..e74d4c7 100644 --- a/payloads/libpayload/arch/arm64/dummy_media.c +++ b/payloads/libpayload/arch/arm64/dummy_media.c @@ -34,10 +34,7 @@ /* The generic cbfs code relies on the libpayload_init_default_cbfs_media * symbol. Therefore, provide an implementation that just throws an error. */ -int libpayload_init_default_cbfs_media(struct cbfs_media *media); - -__attribute__((weak)) int libpayload_init_default_cbfs_media( - struct cbfs_media *media) +__attribute__((weak)) int libpayload_init_default_cbfs_media(void) { return -1; } diff --git a/payloads/libpayload/arch/mips/dummy_media.c b/payloads/libpayload/arch/mips/dummy_media.c index 112d7fe..1732b75 100644 --- a/payloads/libpayload/arch/mips/dummy_media.c +++ b/payloads/libpayload/arch/mips/dummy_media.c @@ -33,10 +33,7 @@ /* The generic cbfs code relies on the libpayload_init_default_cbfs_media * symbol. Therefore, provide an implementation that just throws an error. */ -int libpayload_init_default_cbfs_media(struct cbfs_media *media); - -__attribute__((weak)) int libpayload_init_default_cbfs_media( - struct cbfs_media *media) +__attribute__((weak)) int libpayload_init_default_cbfs_media(void) { return -1; } diff --git a/payloads/libpayload/arch/x86/rom_media.c b/payloads/libpayload/arch/x86/rom_media.c index 0c6f521..48c1669 100644 --- a/payloads/libpayload/arch/x86/rom_media.c +++ b/payloads/libpayload/arch/x86/rom_media.c @@ -26,86 +26,31 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ -#define LIBPAYLOAD #include <cbfs.h> #include <string.h> +#include <sysinfo.h> -#ifdef LIBPAYLOAD -# define printk(x...) -# define init_default_cbfs_media libpayload_init_default_cbfs_media - extern int libpayload_init_default_cbfs_media(struct cbfs_media *media); -#else -# include <console/console.h> -#endif +static struct mem_region_device boot_dev; -// Implementation of memory-mapped ROM media source on X86. - -static int x86_rom_open(struct cbfs_media *media) { - return 0; -} - -static void *x86_rom_map(struct cbfs_media *media, size_t offset, size_t count) { - void *ptr; - // Some address (ex, pointer to master header) may be given in memory - // mapped location. To workaround that, we handle >0xf0000000 as real - // memory pointer. - - if ((uint32_t)offset > (uint32_t)0xf0000000) - ptr = (void*)offset; - else - ptr = (void*)(0 - (uint32_t)media->context + offset); - return ptr; +struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; } -static void *x86_rom_unmap(struct cbfs_media *media, const void *address) { - return NULL; -} - -static size_t x86_rom_read(struct cbfs_media *media, void *dest, size_t offset, - size_t count) { - void *ptr = x86_rom_map(media, offset, count); - memcpy(dest, ptr, count); - x86_rom_unmap(media, ptr); - return count; -} +static int init_x86rom_cbfs_media(void) +{ + /* The ROM is memory mapped just below 4GiB. + * Form a pointer for the base. */ + size_t romsize = lib_sysinfo.boot_media_size; + void *rombase = (void *)(uintptr_t)(0x100000000ULL - romsize); -static int x86_rom_close(struct cbfs_media *media) { - return 0; -} + mem_region_device_ro_init(&boot_dev, rombase, romsize); -int init_x86rom_cbfs_media(struct cbfs_media *media); -int init_x86rom_cbfs_media(struct cbfs_media *media) { - // On X86, we always keep a reference of pointer to CBFS header in - // 0xfffffffc, and the pointer is still a memory-mapped address. - // Since the CBFS core always use ROM offset, we need to figure out - // header->romsize even before media is initialized. - struct cbfs_header *header = (struct cbfs_header*) - *(uint32_t*)(0xfffffffc); - if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { -#if IS_ENABLED(CONFIG_LP_ROM_SIZE) - printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header); - media->context = (void*)CONFIG_LP_ROM_SIZE; -#else - return -1; -#endif - } else { - uint32_t romsize = ntohl(header->romsize); - media->context = (void*)romsize; -#if IS_ENABLED(CONFIG_LP_ROM_SIZE) - if (CONFIG_LP_ROM_SIZE != romsize) - printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n", - CONFIG_LP_ROM_SIZE, romsize); -#endif - } - media->open = x86_rom_open; - media->close = x86_rom_close; - media->map = x86_rom_map; - media->unmap = x86_rom_unmap; - media->read = x86_rom_read; return 0; } -int init_default_cbfs_media(struct cbfs_media *media) { - return init_x86rom_cbfs_media(media); +int libpayload_init_default_cbfs_media(void) +{ + return init_x86rom_cbfs_media(); } diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 943f8ed..3d93c88 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -52,7 +52,6 @@ static uint8_t *fbaddr; #define PIVOT_H_MASK (PIVOT_H_LEFT|PIVOT_H_CENTER|PIVOT_H_RIGHT) #define PIVOT_V_MASK (PIVOT_V_TOP|PIVOT_V_CENTER|PIVOT_V_BOTTOM) #define ROUNDUP(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) -#define ABS(x) ((x) < 0 ? -(x) : (x)) static char initialized = 0; diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h index 801bdfc..12ea408 100644 --- a/payloads/libpayload/include/cbfs.h +++ b/payloads/libpayload/include/cbfs.h @@ -53,11 +53,11 @@ const struct cbfs_header *get_cbfs_header(void); struct cbfs_file *cbfs_find(const char *name); void *cbfs_find_file(const char *name, int type); -int cbfs_execute_stage(struct cbfs_media *media, const char *name); -void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, +int cbfs_execute_stage(struct region_device *media, const char *name); +void *cbfs_load_optionrom(struct region_device *media, uint16_t vendor, uint16_t device); -void *cbfs_load_payload(struct cbfs_media *media, const char *name); -void *cbfs_load_stage(struct cbfs_media *media, const char *name); +void *cbfs_load_payload(struct region_device *media, const char *name); +void *cbfs_load_stage(struct region_device *media, const char *name); /* Simple buffer for streaming media. */ struct cbfs_simple_buffer { @@ -68,7 +68,7 @@ struct cbfs_simple_buffer { }; void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, - struct cbfs_media *media, + struct region_device *media, size_t offset, size_t count); void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, @@ -78,6 +78,7 @@ void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, int run_address(void *f); /* Defined in individual arch / board implementation. */ -int init_default_cbfs_media(struct cbfs_media *media); +int libpayload_init_default_cbfs_media(void); +struct region_device *boot_device_ro(void); #endif diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index f94056d..b7234cd 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -50,6 +50,8 @@ #include <stddef.h> #include <stdint.h> #include <stdlib.h> +#include <region_device.h> + /** These are standard values for the known compression alogrithms that coreboot knows about for stages and @@ -211,43 +213,14 @@ struct cbfs_optionrom { uint32_t len; } __attribute__((packed)); -#define CBFS_MEDIA_INVALID_MAP_ADDRESS ((void*)(0xffffffff)) #define CBFS_DEFAULT_MEDIA ((void*)(0x0)) -/* Media for CBFS to load files. */ -struct cbfs_media { - - /* implementation dependent context, to hold resource references */ - void *context; - - /* opens media and returns 0 on success, -1 on failure */ - int (*open)(struct cbfs_media *media); - - /* returns number of bytes read from media into dest, starting from - * offset for count of bytes */ - size_t (*read)(struct cbfs_media *media, void *dest, size_t offset, - size_t count); - - /* returns a pointer to memory with count of bytes from media source - * starting from offset, or CBFS_MEDIA_INVALID_MAP_ADDRESS on failure. - * Note: mapped data can't be free unless unmap is called, even if you - * do close first. */ - void * (*map)(struct cbfs_media *media, size_t offset, size_t count); - - /* returns NULL and releases the memory by address, which was allocated - * by map */ - void * (*unmap)(struct cbfs_media *media, const void *address); - - /* closes media and returns 0 on success, -1 on failure. */ - int (*close)(struct cbfs_media *media); -}; - /* * Returns pointer to a copy of the file content or NULL on error. * If the file is compressed, data will be decompressed. * The caller owns the returned memory. */ -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, +void *cbfs_get_file_content(struct region_device *media, const char *name, int type, size_t *sz); /* returns decompressed size on success, 0 on failure */ @@ -255,11 +228,11 @@ int cbfs_decompress(int algo, void *src, void *dst, int len); /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media); +const struct cbfs_header *cbfs_get_header(struct region_device *media); /* Persistent handle to a CBFS file that has not yet been fully mapped. */ struct cbfs_handle { - struct cbfs_media media; /* copy of original media object */ + struct region_device *media; /* pointer to original media object */ u32 type; /* CBFS file type */ u32 media_offset; /* offset from beginning of media */ u32 attribute_offset; /* relative offset of attributes */ @@ -269,7 +242,8 @@ struct cbfs_handle { /* Returns handle to CBFS file, or NULL on error. Does not yet map contents. * Caller is responsible to free() returned handle after use. */ -struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name); +struct cbfs_handle *cbfs_get_handle(struct region_device *media, + const char *name); /* Given a cbfs_handle and an attribute tag, return a mapping for the first * instance of the attribute or NULL if none found. */ diff --git a/payloads/libpayload/include/cbfs_ram.h b/payloads/libpayload/include/cbfs_ram.h deleted file mode 100644 index 72839fe..0000000 --- a/payloads/libpayload/include/cbfs_ram.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2013 Google, Inc. - * - * This file is dual-licensed. You can choose between: - * - The GNU GPL, version 2, as published by the Free Software Foundation - * - The revised BSD license (without advertising clause) - * - * --------------------------------------------------------------------------- - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * --------------------------------------------------------------------------- - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * --------------------------------------------------------------------------- - */ - -#ifndef _CBFS_RAM_H_ -#define _CBFS_RAM_H_ - -#include <stdint.h> - -struct cbfs_media; - -/* The following functions return 0 for success. None-zero on error. */ -int init_cbfs_ram_media(struct cbfs_media *media, void *start, size_t size); -int setup_cbfs_from_ram(void *start, uint32_t size); -int setup_cbfs_from_flash(void); - -#endif /* _CBFS_RAM_H_ */ diff --git a/payloads/libpayload/include/mem_pool.h b/payloads/libpayload/include/mem_pool.h new file mode 100644 index 0000000..c21fa0e --- /dev/null +++ b/payloads/libpayload/include/mem_pool.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MEM_POOL_H_ +#define _MEM_POOL_H_ + +#include <stddef.h> +#include <stdint.h> + +/* + * The memory pool allows one to allocate memory from a fixed size buffer + * that also allows freeing semantics for reuse. However, the current + * limitation is that the most recent allocation is the only one that + * can be freed. If one tries to free any allocation that isn't the + * most recently allocated it will result in a leak within the memory pool. + * + * The memory returned by allocations are at least 8 byte aligned. Note + * that this requires the backing buffer to start on at least an 8 byte + * alignment. + */ + +struct mem_pool { + uint8_t *buf; + size_t size; + uint8_t *last_alloc; + size_t free_offset; +}; + +#define MEM_POOL_INIT(buf_, size_) \ + { \ + .buf = (buf_), \ + .size = (size_), \ + .last_alloc = NULL, \ + .free_offset = 0, \ + } + +static inline void mem_pool_reset(struct mem_pool *mp) +{ + mp->last_alloc = NULL; + mp->free_offset = 0; +} + +/* Initialize a memory pool. */ +static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz) +{ + mp->buf = buf; + mp->size = sz; + mem_pool_reset(mp); +} + +/* Allocate requested size from the memory pool. NULL returned on error. */ +void *mem_pool_alloc(struct mem_pool *mp, size_t sz); + +/* Free allocation from memory pool. */ +void mem_pool_free(struct mem_pool *mp, void *alloc); + +#endif /* _MEM_POOL_H_ */ diff --git a/payloads/libpayload/include/region_device.h b/payloads/libpayload/include/region_device.h new file mode 100644 index 0000000..8926ecf --- /dev/null +++ b/payloads/libpayload/include/region_device.h @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _REGION_H_ +#define _REGION_H_ + +#include <sys/types.h> +#include <stdint.h> +#include <stddef.h> +#include <mem_pool.h> + +/* + * Region support. + * + * Regions are intended to abstract away the access mechanisms for blocks of + * data. This could be SPI, eMMC, or a memory region as the backing store. + * They are accessed through a region_device. Subregions can be made by + * chaining together multiple region_devices. + */ + +struct region_device; + +/* + * Returns NULL on error otherwise a buffer is returned with the conents of + * the requested data at offset of size. + */ +void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size); + +/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */ +int rdev_munmap(const struct region_device *rd, void *mapping); + +/* + * Returns < 0 on error otherwise returns size of data read at provided + * offset filling in the buffer passed. + */ +ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset, + size_t size); + +/* + * Returns < 0 on error otherwise returns size of data wrote at provided + * offset from the buffer passed. + */ +ssize_t rdev_writeat(const struct region_device *rd, void *b, size_t offset, + size_t size); + +/* + * Returns < 0 on error otherwise returns size of data erased. + * If eraseat ops is not defined it returns size which indicates + * that operation was successful. + */ +ssize_t rdev_eraseat(const struct region_device *rd, size_t offset, + size_t size); + +/**************************************** + * Implementation of a region device * + ****************************************/ + +/* + * Create a child region of the parent provided the sub-region is within + * the parent's region. Returns < 0 on error otherwise 0 on success. Note + * that the child device only calls through the parent's operations. + */ +int rdev_chain(struct region_device *child, const struct region_device *parent, + size_t offset, size_t size); + + +/* A region_device operations. */ +struct region_device_ops { + void *(*mmap)(const struct region_device *, size_t, size_t); + int (*munmap)(const struct region_device *, void *); + ssize_t (*readat)(const struct region_device *, void *, size_t, size_t); + ssize_t (*writeat)(const struct region_device *, void *, size_t, + size_t); + ssize_t (*eraseat)(const struct region_device *, size_t, size_t); +}; + +struct region { + size_t offset; + size_t size; +}; + +struct region_device { + const struct region_device *root; + const struct region_device_ops *ops; + struct region region; +}; + +#define REGION_DEV_INIT(ops_, offset_, size_) \ + { \ + .root = NULL, \ + .ops = (ops_), \ + .region = { \ + .offset = (offset_), \ + .size = (size_), \ + }, \ + } + +/* Helper to dynamically initialize region device. */ +void region_device_init(struct region_device *rdev, + const struct region_device_ops *ops, size_t offset, + size_t size); + +static inline size_t region_offset(const struct region *r) +{ + return r->offset; +} + +static inline size_t region_sz(const struct region *r) +{ + return r->size; +} + +static inline const struct region *region_device_region( + const struct region_device *rdev) +{ + return &rdev->region; +} + +static inline size_t region_device_sz(const struct region_device *rdev) +{ + return region_sz(region_device_region(rdev)); +} + +static inline size_t region_device_offset(const struct region_device *rdev) +{ + return region_offset(region_device_region(rdev)); +} + +/* Memory map entire region device. Same semantics as rdev_mmap() above. */ +static inline void *rdev_mmap_full(const struct region_device *rd) +{ + return rdev_mmap(rd, 0, region_device_sz(rd)); +} + +/* + * Compute relative offset of the child (c) w.r.t. the parent (p). Returns < 0 + * when child is not within the parent's region. + */ +ssize_t rdev_relative_offset(const struct region_device *p, + const struct region_device *c); + +struct mem_region_device { + char *base; + struct region_device rdev; +}; + +/* Inititalize at runtime a mem_region_device. This would be used when + * the base and size are dynamic or can't be known during linking. + * There are two variants: read-only and read-write. */ +void mem_region_device_ro_init(struct mem_region_device *mdev, void *base, + size_t size); + +void mem_region_device_rw_init(struct mem_region_device *mdev, void *base, + size_t size); + +extern const struct region_device_ops mem_rdev_ro_ops; + +extern const struct region_device_ops mem_rdev_rw_ops; + +/* Statically initialize mem_region_device. */ +#define MEM_REGION_DEV_INIT(base_, size_, ops_) \ + { \ + .base = (void *)(base_), \ + .rdev = REGION_DEV_INIT((ops_), 0, (size_)), \ + } + +#define MEM_REGION_DEV_RO_INIT(base_, size_) \ + MEM_REGION_DEV_INIT(base_, size_, &mem_rdev_ro_ops) \ + +#define MEM_REGION_DEV_RW_INIT(base_, size_) \ + MEM_REGION_DEV_INIT(base_, size_, &mem_rdev_rw_ops) \ + +struct mmap_helper_region_device { + struct mem_pool pool; + struct region_device rdev; +}; + +#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \ + { \ + .rdev = REGION_DEV_INIT((ops_), (offset_), (size_)), \ + } + +void mmap_helper_device_init(struct mmap_helper_region_device *mdev, + void *cache, size_t cache_size); + +void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t); +int mmap_helper_rdev_munmap(const struct region_device *, void *); + +/* A translated region device provides the ability to publish a region device + * in one address space and use an access mechanism within another address + * space. The sub region is the window within the 1st address space and + * the request is modified prior to accessing the second address space + * provided by access_dev. */ +struct xlate_region_device { + const struct region_device *access_dev; + struct region sub_region; + struct region_device rdev; +}; + +extern const struct region_device_ops xlate_rdev_ro_ops; + +extern const struct region_device_ops xlate_rdev_rw_ops; + +#define XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, sub_size_, \ + parent_sz_, ops_) \ + { \ + .access_dev = access_dev_, \ + .sub_region = { \ + .offset = (sub_offset_), \ + .size = (sub_size_), \ + }, \ + .rdev = REGION_DEV_INIT((ops_), 0, (parent_sz_)), \ + } + +#define XLATE_REGION_DEV_RO_INIT(access_dev_, sub_offset_, sub_size_, \ + parent_sz_) \ + XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, \ + sub_size_, parent_sz_, &xlate_rdev_ro_ops), \ + +#define XLATE_REGION_DEV_RW_INIT(access_dev_, sub_offset_, sub_size_, \ + parent_sz_) \ + XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, \ + sub_size_, parent_sz_, &xlate_rdev_rw_ops), \ + +/* Helper to dynamically initialize xlate region device. */ +void xlate_region_device_ro_init(struct xlate_region_device *xdev, + const struct region_device *access_dev, + size_t sub_offset, size_t sub_size, + size_t parent_size); + +void xlate_region_device_rw_init(struct xlate_region_device *xdev, + const struct region_device *access_dev, + size_t sub_offset, size_t sub_size, + size_t parent_size); + +#endif /* _REGION_H_ */ diff --git a/payloads/libpayload/include/stddef.h b/payloads/libpayload/include/stddef.h index fe455b8..a35bd68 100644 --- a/payloads/libpayload/include/stddef.h +++ b/payloads/libpayload/include/stddef.h @@ -20,6 +20,8 @@ typedef __SIZE_TYPE__ ssize_t; offsetof(struct structure, member) == offset, \ "`struct " #structure "` offset for `" #member "` is not " #offset) +#define __unused __attribute__((unused)) + /* Standard units. */ #define KiB (1<<10) #define MiB (1<<20) diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index 689bf01..cf9156f 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -41,6 +41,25 @@ #define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL)) #define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0) +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define ABS(a) (((a) < 0) ? (-(a)) : (a)) +#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b)) +#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0) + +/** + * container_of - cast a member of a structure out to the containing structure + * @param ptr: the pointer to the member. + * @param type: the type of the container struct this is embedded in. + * @param member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const __typeof__(((type *)0)->member) * __mptr = (ptr); \ + (type *)((char *)__mptr - offsetof(type, member)); }) + /** * @defgroup malloc Memory allocation functions * @{ diff --git a/payloads/libpayload/libc/fmap.c b/payloads/libpayload/libc/fmap.c index af9902e..cf0c57c 100644 --- a/payloads/libpayload/libc/fmap.c +++ b/payloads/libpayload/libc/fmap.c @@ -41,15 +41,13 @@ int fmap_region_by_name(const uint32_t fmap_offset, const char * const name, struct fmap *fmap; struct fmap fmap_head; - struct cbfs_media default_media; - struct cbfs_media *media = &default_media; + struct region_device default_media; + struct region_device *media = &default_media; - if (init_default_cbfs_media(media) != 0) - return -1; - - media->open(media); + libpayload_init_default_cbfs_media(); + media = boot_device_ro(); - if (!media->read(media, &fmap_head, fmap_offset, sizeof(fmap_head))) + if (rdev_readat(media, &fmap_head, fmap_offset, sizeof(fmap_head)) < 0) return -1; if (memcmp(fmap_head.signature, FMAP_SIGNATURE, sizeof(fmap_head.signature))) { @@ -63,11 +61,9 @@ int fmap_region_by_name(const uint32_t fmap_offset, const char * const name, if (!fmap) return -1; - if (!media->read(media, fmap, fmap_offset, fmap_size)) + if (rdev_readat(media, fmap, fmap_offset, fmap_size) < 0) goto err; - media->close(media); - for (i = 0; i < fmap->nareas; i++) { if (strcmp((const char *)fmap->areas[i].name, name) != 0) continue; diff --git a/payloads/libpayload/libcbfs/Makefile.inc b/payloads/libpayload/libcbfs/Makefile.inc index 133b215..4a3ce1e 100644 --- a/payloads/libpayload/libcbfs/Makefile.inc +++ b/payloads/libpayload/libcbfs/Makefile.inc @@ -28,4 +28,5 @@ ## libcbfs-$(CONFIG_LP_CBFS) += cbfs.c -libcbfs-$(CONFIG_LP_CBFS) += ram_media.c +libcbfs-$(CONFIG_LP_CBFS) += region_device.c +libcbfs-$(CONFIG_LP_CBFS) += mem_pool.c diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index 38b1ff8..3751b95 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -83,7 +83,7 @@ static void tohex16(unsigned int val, char* dest) dest[3] = tohex4(val & 0xf); } -void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, +void *cbfs_load_optionrom(struct region_device *media, uint16_t vendor, uint16_t device) { char name[17] = "pciXXXX,XXXX.rom"; @@ -94,7 +94,7 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, return cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL); } -void * cbfs_load_stage(struct cbfs_media *media, const char *name) +void *cbfs_load_stage(struct region_device *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); @@ -131,7 +131,8 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) return (void *) entry; } -int cbfs_execute_stage(struct cbfs_media *media, const char *name) + +int cbfs_execute_stage(struct region_device *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); @@ -152,23 +153,23 @@ int cbfs_execute_stage(struct cbfs_media *media, const char *name) return result; } -void *cbfs_load_payload(struct cbfs_media *media, const char *name) +void *cbfs_load_payload(struct region_device *media, const char *name) { return (struct cbfs_payload *)cbfs_get_file_content( media, name, CBFS_TYPE_PAYLOAD, NULL); } -struct cbfs_file *cbfs_find(const char *name) { +struct cbfs_file *cbfs_find(const char *name) +{ struct cbfs_handle *handle = cbfs_get_handle(CBFS_DEFAULT_MEDIA, name); - struct cbfs_media *m = &handle->media; void *ret; if (!handle) return NULL; - ret = m->map(m, handle->media_offset, + ret = rdev_mmap(handle->media, handle->media_offset, handle->content_offset + handle->content_size); - if (ret == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + if (ret == NULL) { free(handle); return NULL; } @@ -177,30 +178,32 @@ struct cbfs_file *cbfs_find(const char *name) { return ret; } -void *cbfs_find_file(const char *name, int type) { +void *cbfs_find_file(const char *name, int type) +{ return cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type, NULL); } -const struct cbfs_header *get_cbfs_header(void) { +const struct cbfs_header *get_cbfs_header(void) +{ return cbfs_get_header(CBFS_DEFAULT_MEDIA); } /* Simple buffer */ void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, - struct cbfs_media *media, - size_t offset, size_t count) { + struct region_device *media, size_t offset, size_t count) +{ void *address = buffer->buffer + buffer->allocated;; DEBUG("simple_buffer_map(offset=%zu, count=%zu): " "allocated=%zu, size=%zu, last_allocate=%zu\n", offset, count, buffer->allocated, buffer->size, buffer->last_allocate); if (buffer->allocated + count >= buffer->size) - return CBFS_MEDIA_INVALID_MAP_ADDRESS; - if (media->read(media, address, offset, count) != count) { + return NULL; + if (rdev_readat(media, address, offset, count) != count) { ERROR("simple_buffer: fail to read %zd bytes from 0x%zx\n", count, offset); - return CBFS_MEDIA_INVALID_MAP_ADDRESS; + return NULL; } buffer->allocated += count; buffer->last_allocate = count; @@ -208,7 +211,8 @@ void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, } void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, - const void *address) { + const void *address) +{ // TODO Add simple buffer management so we can free more than last // allocated one. DEBUG("simple_buffer_unmap(address=0x%p): " diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index 7e660ce..a559713 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -54,32 +54,29 @@ /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) +const struct cbfs_header *cbfs_get_header(struct region_device *media) { int32_t rel_offset; const struct cbfs_header *header; - struct cbfs_media default_media; if (media == CBFS_DEFAULT_MEDIA) { - media = &default_media; - if (init_default_cbfs_media(media) != 0) { - ERROR("Failed to initialize default media.\n"); - return CBFS_HEADER_INVALID_ADDRESS; - } + libpayload_init_default_cbfs_media(); + media = boot_device_ro(); } - media->open(media); - if (!media->read(media, &rel_offset, (size_t)(0 - sizeof(int32_t)), - sizeof(int32_t))) { - ERROR("Could not read CBFS master header offset!\n"); - return CBFS_HEADER_INVALID_ADDRESS; - } - header = media->map(media, (size_t)rel_offset, sizeof(*header)); + /* Find the CBFS master header pointer/offset at 0xfffffffc. + * There is no return value check since the offset can be negative. */ + rdev_readat(media, &rel_offset, + lib_sysinfo.boot_media_size - sizeof(int32_t), + sizeof(int32_t)); + + rel_offset += lib_sysinfo.boot_media_size; + + header = rdev_mmap(media, rel_offset, sizeof(*header)); DEBUG("CBFS header at %#zx (-%#zx from end of image).\n", (size_t)rel_offset, (size_t)-rel_offset); - media->close(media); - if (header == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + if (header == NULL) { ERROR("Failed to load CBFS header from %#zx(-%#zx)\n", (size_t)rel_offset, (size_t)-rel_offset); return CBFS_HEADER_INVALID_ADDRESS; @@ -99,7 +96,7 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) } static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end, - struct cbfs_media *media) + struct region_device *media) { const struct cbfs_header *header; @@ -115,17 +112,17 @@ static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end, header = cbfs_get_header(media); if (header == CBFS_HEADER_INVALID_ADDRESS) return -1; - // Logical offset (for source media) of first file. + /* Logical offset (for source media) of first file. */ *offset = ntohl(header->offset); *cbfs_end = ntohl(header->romsize); #if IS_ENABLED(CONFIG_LP_ARCH_X86) - // resolve actual length of ROM used for CBFS components - // the bootblock size was not taken into account + /*resolve actual length of ROM used for CBFS components + * the bootblock size was not taken into account. */ *cbfs_end -= ntohl(header->bootblocksize); - // fine tune the length to handle alignment positioning. - // using (bootblock size) % align, to derive the - // number of bytes the bootblock is off from the alignment size. + /* fine tune the length to handle alignment positioning. + * using (bootblock size) % align, to derive the + * number of bytes the bootblock is off from the alignment size. */ if ((ntohl(header->bootblocksize) % CBFS_ALIGNMENT)) *cbfs_end -= (CBFS_ALIGNMENT - (ntohl(header->bootblocksize) % CBFS_ALIGNMENT)); @@ -135,10 +132,11 @@ static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end, return 0; } -/* public API starts here*/ -struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name) +/* Public API starts here. */ +struct cbfs_handle *cbfs_get_handle(struct region_device *media, + const char *name) { - const char *vardata; + char *vardata; uint32_t offset, cbfs_end, vardata_len; struct cbfs_file file; struct cbfs_handle *handle = malloc(sizeof(*handle)); @@ -147,33 +145,34 @@ struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name) return NULL; if (get_cbfs_range(&offset, &cbfs_end, media)) { - ERROR("Failed to find cbfs range\n"); + ERROR("Failed to find cbfs range.\n"); return NULL; } if (media == CBFS_DEFAULT_MEDIA) { - media = &handle->media; - if (init_default_cbfs_media(media) != 0) { - ERROR("Failed to initialize default media.\n"); - return NULL; - } + libpayload_init_default_cbfs_media(); + media = boot_device_ro(); + handle->media = media; } else { - memcpy(&handle->media, media, sizeof(*media)); + handle->media = malloc(sizeof(*media)); + if (!handle->media) + return NULL; + memcpy(handle->media, media, sizeof(*media)); } DEBUG("CBFS location: 0x%x~0x%x\n", offset, cbfs_end); DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); - media->open(media); while (offset < cbfs_end && - media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { + rdev_readat(media, &file, offset, sizeof(file)) == + sizeof(file)) { if (memcmp(CBFS_FILE_MAGIC, file.magic, sizeof(file.magic)) != 0) { uint32_t new_align = CBFS_ALIGNMENT; if (offset % CBFS_ALIGNMENT) new_align += CBFS_ALIGNMENT - (offset % CBFS_ALIGNMENT); - ERROR("ERROR: No file header found at 0x%xx - " + ERROR("ERROR: No file header found at 0x%x - " "try next aligned address: 0x%x.\n", offset, offset + new_align); offset += new_align; @@ -184,17 +183,16 @@ struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name) offset, vardata_len); // load file name (arbitrary length). - vardata = (const char*)media->map( - media, offset + sizeof(file), vardata_len); - if (vardata == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + vardata = rdev_mmap(media, offset + sizeof(file), + vardata_len); + if (vardata == NULL) { ERROR("ERROR: Failed to get filename: 0x%x.\n", offset); } else if (strcmp(vardata, name) == 0) { int file_offset = ntohl(file.offset), file_len = ntohl(file.len); DEBUG("Found file (offset=0x%x, len=%d).\n", offset + file_offset, file_len); - media->unmap(media, vardata); - media->close(media); + rdev_munmap(media, vardata); handle->type = ntohl(file.type); handle->media_offset = offset; handle->content_offset = file_offset; @@ -205,7 +203,7 @@ struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name) } else { DEBUG(" (unmatched file @0x%x: %s)\n", offset, vardata); - media->unmap(media, vardata); + rdev_munmap(media, vardata); } // Move to next file. @@ -213,14 +211,13 @@ struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name) if (offset % CBFS_ALIGNMENT) offset += CBFS_ALIGNMENT - (offset % CBFS_ALIGNMENT); } - media->close(media); LOG("WARNING: '%s' not found.\n", name); return NULL; } void *cbfs_get_contents(struct cbfs_handle *handle, size_t *size, size_t limit) { - struct cbfs_media *m = &handle->media; + struct region_device *m = handle->media; size_t on_media_size = handle->content_size; int algo = CBFS_COMPRESS_NONE; void *ret = NULL; @@ -247,9 +244,9 @@ void *cbfs_get_contents(struct cbfs_handle *handle, size_t *size, size_t limit) } } - void *data = m->map(m, handle->media_offset + handle->content_offset, + void *data = rdev_mmap(m, handle->media_offset + handle->content_offset, on_media_size); - if (data == CBFS_MEDIA_INVALID_MAP_ADDRESS) + if (data == NULL) return NULL; ret = malloc(*size); @@ -258,11 +255,11 @@ void *cbfs_get_contents(struct cbfs_handle *handle, size_t *size, size_t limit) ret = NULL; } - m->unmap(m, data); + rdev_munmap(m, data); return ret; } -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, +void *cbfs_get_file_content(struct region_device *media, const char *name, int type, size_t *sz) { void *ret = NULL; @@ -283,7 +280,7 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name, void *cbfs_get_attr(struct cbfs_handle *handle, uint32_t tag) { - struct cbfs_media *m = &handle->media; + struct region_device *m = handle->media; uint32_t offset = handle->media_offset + handle->attribute_offset; uint32_t end = handle->media_offset + handle->content_offset; struct cbfs_file_attribute attr; @@ -294,26 +291,23 @@ void *cbfs_get_attr(struct cbfs_handle *handle, uint32_t tag) if (handle->attribute_offset <= sizeof(struct cbfs_file)) return NULL; - m->open(m); while (offset + sizeof(attr) <= end) { - if (m->read(m, &attr, offset, sizeof(attr)) != sizeof(attr)) { + if (rdev_readat(m, &attr, offset, sizeof(attr)) != + sizeof(attr)) { ERROR("Failed to read attribute header %#x\n", offset); - m->close(m); return NULL; } if (ntohl(attr.tag) != tag) { offset += ntohl(attr.len); continue; } - ret = m->map(m, offset, ntohl(attr.len)); - if (ret == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + ret = rdev_mmap(m, offset, ntohl(attr.len)); + if (ret == NULL) { ERROR("Failed to map attribute at %#x\n", offset); - m->close(m); return NULL; } return ret; } - m->close(m); return NULL; } diff --git a/payloads/libpayload/libcbfs/mem_pool.c b/payloads/libpayload/libcbfs/mem_pool.c new file mode 100644 index 0000000..c1d3961 --- /dev/null +++ b/payloads/libpayload/libcbfs/mem_pool.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdlib.h> +#include <mem_pool.h> + +void *mem_pool_alloc(struct mem_pool *mp, size_t sz) +{ + void *p; + + /* Make all allocations be at least 8 byte aligned. */ + sz = ALIGN_UP(sz, 8); + + /* Determine if any space available. */ + if ((mp->size - mp->free_offset) < sz) + return NULL; + + p = &mp->buf[mp->free_offset]; + + mp->free_offset += sz; + mp->last_alloc = p; + + return p; +} + +void mem_pool_free(struct mem_pool *mp, void *p) +{ + /* Determine if p was the most recent allocation. */ + if (p == NULL || mp->last_alloc != p) + return; + + mp->free_offset = mp->last_alloc - mp->buf; + /* No way to track allocation before this one. */ + mp->last_alloc = NULL; +} diff --git a/payloads/libpayload/libcbfs/ram_media.c b/payloads/libpayload/libcbfs/ram_media.c deleted file mode 100644 index d5469f6..0000000 --- a/payloads/libpayload/libcbfs/ram_media.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2013 Google, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -#include <cbfs.h> -#include <cbfs_ram.h> -#include <string.h> -#include <stdio.h> -#include <stdlib.h> - -// Implementation of a media source based on given memory buffer. -struct ram_media { - char *start; - size_t size; -}; - -static int ram_open(struct cbfs_media *media) { - return 0; -} - -static void *ram_map(struct cbfs_media *media, size_t offset, size_t count) { - struct ram_media *m = (struct ram_media*)media->context; - /* assume addressing from top of image in this case */ - if (offset > 0xf0000000) { - offset = m->size + offset; - } - if (offset + count > m->size) { - printf("ERROR: ram_map: request out of range (0x%zx+0x%zx)\n", - offset, count); - return CBFS_MEDIA_INVALID_MAP_ADDRESS; - } - return (void*)(m->start + offset); -} - -static void *ram_unmap(struct cbfs_media *media, const void *address) { - return NULL; -} - -static size_t ram_read(struct cbfs_media *media, void *dest, size_t offset, - size_t count) { - void *ptr = ram_map(media, offset, count); - if (ptr == CBFS_MEDIA_INVALID_MAP_ADDRESS) - return 0; - memcpy(dest, ptr, count); - ram_unmap(media, ptr); - return count; -} - -static int ram_close(struct cbfs_media *media) { - return 0; -} - -int init_cbfs_ram_media(struct cbfs_media *media, void *start, size_t size) { - // TODO Find a way to release unused media. Maybe adding media->destroy. - struct ram_media *m = (struct ram_media*)malloc(sizeof(*m)); - m->start = start; - m->size = size; - media->context = (void*)m; - media->open = ram_open; - media->close = ram_close; - media->map = ram_map; - media->unmap = ram_unmap; - media->read = ram_read; - return 0; -} - -// Legacy setup_cbfs_from_*. -static int is_default_cbfs_media_initialized; -static struct cbfs_media default_cbfs_media; - -int setup_cbfs_from_ram(void *start, uint32_t size) { - int result = init_cbfs_ram_media(&default_cbfs_media, start, size); - if (result == 0) - is_default_cbfs_media_initialized = 1; - return result; -} - -extern int libpayload_init_default_cbfs_media(struct cbfs_media *media); -int setup_cbfs_from_flash(void) { - int result = libpayload_init_default_cbfs_media(&default_cbfs_media); - if (result == 0) - is_default_cbfs_media_initialized = 1; - return result; -} - -int init_default_cbfs_media(struct cbfs_media *media) { - int result = 0; - if (is_default_cbfs_media_initialized != 1) { - result = setup_cbfs_from_flash(); - } - if (result == 0) - memcpy(media, &default_cbfs_media, sizeof(*media)); - return result; -} diff --git a/payloads/libpayload/libcbfs/region_device.c b/payloads/libpayload/libcbfs/region_device.c new file mode 100644 index 0000000..f87075a --- /dev/null +++ b/payloads/libpayload/libcbfs/region_device.c @@ -0,0 +1,434 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdlib.h> +#include <string.h> +#include <region_device.h> + +static inline size_t region_end(const struct region *r) +{ + return region_sz(r) + region_offset(r); +} + +static int is_subregion(const struct region *p, const struct region *c) +{ + if (region_offset(c) < region_offset(p)) + return 0; + + if (region_sz(c) > region_sz(p)) + return 0; + + if (region_end(c) > region_end(p)) + return 0; + + return 1; +} + +static int normalize_and_ok(const struct region *outer, struct region *inner) +{ + inner->offset += region_offset(outer); + return is_subregion(outer, inner); +} + +static const struct region_device *rdev_root(const struct region_device *rdev) +{ + if (rdev->root == NULL) + return rdev; + return rdev->root; +} + +ssize_t rdev_relative_offset(const struct region_device *p, + const struct region_device *c) +{ + if (rdev_root(p) != rdev_root(c)) + return -1; + + if (!is_subregion(&p->region, &c->region)) + return -1; + + return region_device_offset(c) - region_device_offset(p); +} + +void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size) +{ + const struct region_device *rdev; + struct region req = { + .offset = offset, + .size = size, + }; + + if (!normalize_and_ok(&rd->region, &req)) + return NULL; + + rdev = rdev_root(rd); + + return rdev->ops->mmap(rdev, req.offset, req.size); +} + +int rdev_munmap(const struct region_device *rd, void *mapping) +{ + const struct region_device *rdev; + + rdev = rdev_root(rd); + + return rdev->ops->munmap(rdev, mapping); +} + +ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset, + size_t size) +{ + const struct region_device *rdev; + struct region req = { + .offset = offset, + .size = size, + }; + + if (!normalize_and_ok(&rd->region, &req)) + return -1; + + rdev = rdev_root(rd); + + return rdev->ops->readat(rdev, b, req.offset, req.size); +} + +ssize_t rdev_writeat(const struct region_device *rd, void *b, size_t offset, + size_t size) +{ + const struct region_device *rdev; + struct region req = { + .offset = offset, + .size = size, + }; + + if (!normalize_and_ok(&rd->region, &req)) + return -1; + + rdev = rdev_root(rd); + + if (rdev->ops->writeat == NULL) + return -1; + + return rdev->ops->writeat(rdev, b, req.offset, req.size); +} + +ssize_t rdev_eraseat(const struct region_device *rd, size_t offset, + size_t size) +{ + const struct region_device *rdev; + struct region req = { + .offset = offset, + .size = size, + }; + + if (!normalize_and_ok(&rd->region, &req)) + return -1; + + rdev = rdev_root(rd); + + /* If the eraseat ptr is NULL we assume that the erase + * function was completed successfully. */ + if (rdev->ops->eraseat == NULL) + return size; + + return rdev->ops->eraseat(rdev, req.offset, req.size); +} + +int rdev_chain(struct region_device *child, const struct region_device *parent, + size_t offset, size_t size) +{ + struct region req = { + .offset = offset, + .size = size, + }; + + if (!normalize_and_ok(&parent->region, &req)) + return -1; + + /* Keep track of root region device. Note the offsets are relative + * to the root device. */ + child->root = rdev_root(parent); + child->ops = NULL; + child->region.offset = req.offset; + child->region.size = req.size; + + return 0; +} + +static void mem_region_device_init(struct mem_region_device *mdev, + const struct region_device_ops *ops, void *base, size_t size) +{ + memset(mdev, 0, sizeof(*mdev)); + mdev->base = base; + mdev->rdev.ops = ops; + mdev->rdev.region.size = size; +} + +void mem_region_device_ro_init(struct mem_region_device *mdev, void *base, + size_t size) +{ + return mem_region_device_init(mdev, &mem_rdev_ro_ops, base, size); +} + +void mem_region_device_rw_init(struct mem_region_device *mdev, void *base, + size_t size) +{ + return mem_region_device_init(mdev, &mem_rdev_rw_ops, base, size); +} + +void region_device_init(struct region_device *rdev, + const struct region_device_ops *ops, size_t offset, + size_t size) +{ + memset(rdev, 0, sizeof(*rdev)); + rdev->root = NULL; + rdev->ops = ops; + rdev->region.offset = offset; + rdev->region.size = size; +} + +static void xlate_region_device_init(struct xlate_region_device *xdev, + const struct region_device_ops *ops, + const struct region_device *access_dev, + size_t sub_offset, size_t sub_size, + size_t parent_size) +{ + memset(xdev, 0, sizeof(*xdev)); + xdev->access_dev = access_dev; + xdev->sub_region.offset = sub_offset; + xdev->sub_region.size = sub_size; + region_device_init(&xdev->rdev, ops, 0, parent_size); +} + +void xlate_region_device_ro_init(struct xlate_region_device *xdev, + const struct region_device *access_dev, + size_t sub_offset, size_t sub_size, + size_t parent_size) +{ + xlate_region_device_init(xdev, &xlate_rdev_ro_ops, access_dev, + sub_offset, sub_size, parent_size); +} + +void xlate_region_device_rw_init(struct xlate_region_device *xdev, + const struct region_device *access_dev, + size_t sub_offset, size_t sub_size, + size_t parent_size) +{ + xlate_region_device_init(xdev, &xlate_rdev_rw_ops, access_dev, + sub_offset, sub_size, parent_size); +} + +static void *mdev_mmap(const struct region_device *rd, size_t offset, + size_t size __unused) +{ + const struct mem_region_device *mdev; + + mdev = container_of(rd, __typeof__(*mdev), rdev); + + return &mdev->base[offset]; +} + +static int mdev_munmap(const struct region_device *rd __unused, + void *mapping __unused) +{ + return 0; +} + +static ssize_t mdev_readat(const struct region_device *rd, void *b, + size_t offset, size_t size) +{ + const struct mem_region_device *mdev; + + mdev = container_of(rd, __typeof__(*mdev), rdev); + + memcpy(b, &mdev->base[offset], size); + + return size; +} + +static ssize_t mdev_writeat(const struct region_device *rd, void *b, + size_t offset, size_t size) +{ + const struct mem_region_device *mdev; + + mdev = container_of(rd, __typeof__(*mdev), rdev); + + memcpy(&mdev->base[offset], b, size); + + return size; +} + +static ssize_t mdev_eraseat(const struct region_device *rd, size_t offset, + size_t size) +{ + const struct mem_region_device *mdev; + + mdev = container_of(rd, __typeof__(*mdev), rdev); + + memset(&mdev->base[offset], 0, size); + + return size; +} + +const struct region_device_ops mem_rdev_ro_ops = { + .mmap = mdev_mmap, + .munmap = mdev_munmap, + .readat = mdev_readat, +}; + +const struct region_device_ops mem_rdev_rw_ops = { + .mmap = mdev_mmap, + .munmap = mdev_munmap, + .readat = mdev_readat, + .writeat = mdev_writeat, + .eraseat = mdev_eraseat, +}; + +void mmap_helper_device_init(struct mmap_helper_region_device *mdev, + void *cache, size_t cache_size) +{ + mem_pool_init(&mdev->pool, cache, cache_size); +} + +void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset, + size_t size) +{ + struct mmap_helper_region_device *mdev; + void *mapping; + + mdev = container_of((void *)rd, __typeof__(*mdev), rdev); + + mapping = mem_pool_alloc(&mdev->pool, size); + + if (mapping == NULL) + return NULL; + + if (rd->ops->readat(rd, mapping, offset, size) != size) { + mem_pool_free(&mdev->pool, mapping); + return NULL; + } + + return mapping; +} + +int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping) +{ + struct mmap_helper_region_device *mdev; + + mdev = container_of((void *)rd, __typeof__(*mdev), rdev); + + mem_pool_free(&mdev->pool, mapping); + + return 0; +} + +static void *xlate_mmap(const struct region_device *rd, size_t offset, + size_t size) +{ + const struct xlate_region_device *xldev; + struct region req = { + .offset = offset, + .size = size, + }; + + xldev = container_of(rd, __typeof__(*xldev), rdev); + + if (!is_subregion(&xldev->sub_region, &req)) + return NULL; + + offset -= region_offset(&xldev->sub_region); + + return rdev_mmap(xldev->access_dev, offset, size); +} + +static int xlate_munmap(const struct region_device *rd, void *mapping) +{ + const struct xlate_region_device *xldev; + + xldev = container_of(rd, __typeof__(*xldev), rdev); + + return rdev_munmap(xldev->access_dev, mapping); +} + +static ssize_t xlate_readat(const struct region_device *rd, void *b, + size_t offset, size_t size) +{ + struct region req = { + .offset = offset, + .size = size, + }; + const struct xlate_region_device *xldev; + + xldev = container_of(rd, __typeof__(*xldev), rdev); + + if (!is_subregion(&xldev->sub_region, &req)) + return -1; + + offset -= region_offset(&xldev->sub_region); + + return rdev_readat(xldev->access_dev, b, offset, size); +} + +static ssize_t xlate_writeat(const struct region_device *rd, void *b, + size_t offset, size_t size) +{ + struct region req = { + .offset = offset, + .size = size, + }; + const struct xlate_region_device *xldev; + + xldev = container_of(rd, __typeof__(*xldev), rdev); + + if (!is_subregion(&xldev->sub_region, &req)) + return -1; + + offset -= region_offset(&xldev->sub_region); + + return rdev_writeat(xldev->access_dev, b, offset, size); +} + +static ssize_t xlate_eraseat(const struct region_device *rd, + size_t offset, size_t size) +{ + struct region req = { + .offset = offset, + .size = size, + }; + const struct xlate_region_device *xldev; + + xldev = container_of(rd, __typeof__(*xldev), rdev); + + if (!is_subregion(&xldev->sub_region, &req)) + return -1; + + offset -= region_offset(&xldev->sub_region); + + return rdev_eraseat(xldev->access_dev, offset, size); +} + +const struct region_device_ops xlate_rdev_ro_ops = { + .mmap = xlate_mmap, + .munmap = xlate_munmap, + .readat = xlate_readat, +}; + +const struct region_device_ops xlate_rdev_rw_ops = { + .mmap = xlate_mmap, + .munmap = xlate_munmap, + .readat = xlate_readat, + .writeat = xlate_writeat, + .eraseat = xlate_eraseat, +};

1 0

Patch set updated for coreboot: libpayload: split "Drivers" config section in Kconfig
by Antonello Dettori 28 Jul '16

28 Jul '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15914 -gerrit commit b7df908dc8900ec4690a645b1b28cdf5c6e50ab6 Author: Antonello Dettori <dev(a)dettori.io> Date: Wed Jul 27 12:41:04 2016 +0200 libpayload: split "Drivers" config section in Kconfig Move the configuration of the timer, storage and USB drivers from the main Kconfig to three separate ones stored in the respective directories. This reduces the LOC of Kconfig and makes it more manageable. Change-Id: I0786dbc1d5d8317c8ccb600f5de9ef4a8243d035 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- payloads/libpayload/Kconfig | 283 +--------------------------- payloads/libpayload/drivers/storage/Kconfig | 59 ++++++ payloads/libpayload/drivers/timer/Kconfig | 129 +++++++++++++ payloads/libpayload/drivers/usb/Kconfig | 129 +++++++++++++ 4 files changed, 320 insertions(+), 280 deletions(-) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 276eb30..51826ea 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -354,286 +354,9 @@ config SPEAKER depends on ARCH_X86 default y -config STORAGE - bool "Support for storage devices" - default y - help - Select this option if you want support for storage devices (like - hard drives, memory sticks or optical drives). - -config STORAGE_64BIT_LBA - bool "Use 64-bit integers to address sectors" - depends on STORAGE - default n - help - If this is selected, sectors will be addressed by an 64-bit integer. - Select this to support LBA-48 for ATA drives. - -config STORAGE_ATA - bool "Support ATA drives (i.e. hard drives)" - depends on STORAGE - default y - help - Select this option if you want support for ATA storage devices - (i.e. hard drives). - -config STORAGE_ATAPI - bool "Support ATAPI drives (i.e. optical drives)" - depends on STORAGE - default y - select STORAGE_ATA - help - Select this option if you want support for ATAPI storage devices - (i.e. optical drives like CD or DVD drives). - -config STORAGE_AHCI - bool "Support for AHCI host controllers" - depends on STORAGE && (STORAGE_ATA || STORAGE_ATAPI) && PCI - default y - help - Select this option if you want support for SATA controllers in - AHCI mode. - -config STORAGE_AHCI_ONLY_TESTED - bool "Only enable tested controllers" - depends on STORAGE_AHCI - default y - help - If this option is selected only AHCI controllers which are known - to work will be used. - -config TIMER_RDTSC - bool - default y - depends on ARCH_X86 - -choice - prompt "Timer driver" - default TIMER_NONE - depends on !ARCH_X86 - -config TIMER_NONE - bool "None" - help - The timer driver is provided by the payload itself. - -config TIMER_MCT - bool "Exynos MCT" - -config TIMER_TEGRA_1US - bool "Tegra 1us" - -config TIMER_IPQ806X - bool "Timer for ipq806x platforms" - -config TIMER_ARMADA38X - bool "Timer for armada38x platforms" - help - This is the timer driver for marvell armada38x - platforms. - -config TIMER_IPQ40XX - bool "Timer for ipq40xx platforms" - help - This is the timer driver for QCA IPQ40xx based - platforms. - -config TIMER_RK - bool "Timer for Rockchip" - -config TIMER_BG4CD - bool "Marvell BG4CD" - -config TIMER_CYGNUS - bool "Timer for Cygnus" - -config TIMER_IMG_PISTACHIO - bool "Timer for IMG Pistachio" - -config TIMER_MTK - bool "Timer for MediaTek MT8173" - -endchoice - -config TIMER_MCT_HZ - int "Exynos MCT frequency" - depends on TIMER_MCT - default 24000000 - -config TIMER_MCT_ADDRESS - hex "Exynos MCT base address" - depends on TIMER_MCT - default 0x101c0000 - -config TIMER_RK_ADDRESS - hex "Rockchip timer base address" - depends on TIMER_RK - default 0xff810020 - -config TIMER_TEGRA_1US_ADDRESS - hex "Tegra u1s timer base address" - depends on TIMER_TEGRA_1US - default 0x60005010 - -config IPQ806X_TIMER_FREQ - int "Hardware timer frequency" - default 32000 - depends on TIMER_IPQ806X - help - IPQ hardware presently provides a single timer running at 32KHz, a - finer granulariry timer is available but is not yet enabled. - -config IPQ806X_TIMER_REG - hex "Timer register address" - default 0x0200A008 - depends on TIMER_IPQ806X - help - Address of the register to read a free running timer value. - -config ARMADA38X_TIMER_FREQ - int "Hardware timer frequency" - depends on TIMER_ARMADA38X - default 25000000 - -config ARMADA38X_TIMER_REG - hex "Timer register address" - default 0xF1020314 - depends on TIMER_ARMADA38X - -config IPROC_PERIPH_GLB_TIM_REG_BASE - hex "Cygnus timer base address" - depends on TIMER_CYGNUS - default 0x19020200 - -config TIMER_MTK_HZ - int "MediaTek GPT frequency" - depends on TIMER_MTK - default 13000000 - help - Clock frequency of MediaTek General Purpose Timer. - -config TIMER_MTK_ADDRESS - hex "MTK GPT register address" - depends on TIMER_MTK - default 0x10008048 - help - Address of GPT4's counter register to read the FREERUN-mode timer value. - -config USB - bool "USB Support" - default y - -config USB_UHCI - bool "Support for USB UHCI controllers" - depends on USB && ARCH_X86 - default y - help - Select this option if you are going to use USB 1.1 on an Intel based - system. - -config USB_OHCI - bool "Support for USB OHCI controllers" - depends on USB - default y - help - Select this option if you are going to use USB 1.1 on a non-Intel based - system. - -config USB_EHCI - bool "Support for USB EHCI controllers" - depends on USB - default y - help - Select this option if you want to use USB 2.0 - -config USB_XHCI - bool "Support for USB xHCI controllers" - depends on USB - default y - help - Select this option if you want to use USB 3.0 - -config USB_XHCI_MTK_QUIRK - bool "Support for USB xHCI controllers on MTK SoC" - depends on USB_XHCI - help - Select this option if you want to use USB 3.0 on MTK platform. - -config USB_DWC2 - bool "Support for USB DesignWare HCD controllers" - depends on USB - help - Select this option if you want to use DesignWare USB 2.0 host controller - -config USB_HID - bool "Support for USB keyboards" - depends on USB - default y - help - Select this option if you want to use devices complying to the - USB HID (Human Interface Device) standard. Such devices are for - example keyboards and mice. Currently only keyboards are supported. - Say Y here unless you know exactly what you are doing. - -config USB_HUB - bool "Support for USB hubs" - depends on USB - default y - help - Select this option if you want to compile in support for USB hubs. - Say Y here unless you know exactly what you are doing. - -config USB_EHCI_HOSTPC_ROOT_HUB_TT - bool "Support for USB EHCI ROOT HUB that has TT" - depends on USB_EHCI - default n - help - Select this option if USB EHCI root hub supports TT (Transaction - Translator). - To support this TT feature we read port-speed from non-standard - register HOSTPC (offset 84h of Operational Register base). - -config USB_MSC - bool "Support for USB storage" - depends on USB - default y - help - Select this option if you want to compile in support for USB mass - storage devices (USB memory sticks, hard drives, CDROM/DVD drives) - Say Y here unless you know exactly what you are doing. - -config USB_GEN_HUB - bool - default n if (!USB_HUB && !USB_XHCI) - default y if (USB_HUB || USB_XHCI) -config USB_PCI - bool "Auto-scan PCI bus for USB host controllers" - depends on USB - default y if ARCH_X86 - default n - -config UDC - bool "USB device mode support" - default n - help - Select this option to add support for running as - a USB device. - -config UDC_CI - bool "ChipIdea driver for USB device mode" - depends on UDC - default n - help - Select this option to add the driver for ChipIdea - USB device controller. - -config UDC_DWC2 - bool "Designware driver for USB device mode" - depends on UDC - default n - help - Select this option to add the driver for Designware - USB device controller. +source "drivers/timer/Kconfig" +source "drivers/storage/Kconfig" +source "drivers/usb/Kconfig" endmenu diff --git a/payloads/libpayload/drivers/storage/Kconfig b/payloads/libpayload/drivers/storage/Kconfig new file mode 100644 index 0000000..961144e --- /dev/null +++ b/payloads/libpayload/drivers/storage/Kconfig @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +config STORAGE + bool "Support for storage devices" + default y + help + Select this option if you want support for storage devices (like + hard drives, memory sticks or optical drives). + +config STORAGE_64BIT_LBA + bool "Use 64-bit integers to address sectors" + depends on STORAGE + default n + help + If this is selected, sectors will be addressed by an 64-bit integer. + Select this to support LBA-48 for ATA drives. + +config STORAGE_ATA + bool "Support ATA drives (i.e. hard drives)" + depends on STORAGE + default y + help + Select this option if you want support for ATA storage devices + (i.e. hard drives). + +config STORAGE_ATAPI + bool "Support ATAPI drives (i.e. optical drives)" + depends on STORAGE + default y + select STORAGE_ATA + help + Select this option if you want support for ATAPI storage devices + (i.e. optical drives like CD or DVD drives). + +config STORAGE_AHCI + bool "Support for AHCI host controllers" + depends on STORAGE && (STORAGE_ATA || STORAGE_ATAPI) && PCI + default y + help + Select this option if you want support for SATA controllers in + AHCI mode. + +config STORAGE_AHCI_ONLY_TESTED + bool "Only enable tested controllers" + depends on STORAGE_AHCI + default y + help + If this option is selected only AHCI controllers which are known + to work will be used. diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig new file mode 100644 index 0000000..8f047fa --- /dev/null +++ b/payloads/libpayload/drivers/timer/Kconfig @@ -0,0 +1,129 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +config TIMER_RDTSC + bool + default y + depends on ARCH_X86 + +choice + prompt "Timer driver" + default TIMER_NONE + depends on !ARCH_X86 + +config TIMER_NONE + bool "None" + help + The timer driver is provided by the payload itself. + +config TIMER_MCT + bool "Exynos MCT" + +config TIMER_TEGRA_1US + bool "Tegra 1us" + +config TIMER_IPQ806X + bool "Timer for ipq806x platforms" + +config TIMER_ARMADA38X + bool "Timer for armada38x platforms" + help + This is the timer driver for marvell armada38x + platforms. + +config TIMER_IPQ40XX + bool "Timer for ipq40xx platforms" + help + This is the timer driver for QCA IPQ40xx based + platforms. + +config TIMER_RK + bool "Timer for Rockchip" + +config TIMER_BG4CD + bool "Marvell BG4CD" + +config TIMER_CYGNUS + bool "Timer for Cygnus" + +config TIMER_IMG_PISTACHIO + bool "Timer for IMG Pistachio" + +config TIMER_MTK + bool "Timer for MediaTek MT8173" + +endchoice + +config TIMER_MCT_HZ + int "Exynos MCT frequency" + depends on TIMER_MCT + default 24000000 + +config TIMER_MCT_ADDRESS + hex "Exynos MCT base address" + depends on TIMER_MCT + default 0x101c0000 + +config TIMER_RK_ADDRESS + hex "Rockchip timer base address" + depends on TIMER_RK + default 0xff810020 + +config TIMER_TEGRA_1US_ADDRESS + hex "Tegra u1s timer base address" + depends on TIMER_TEGRA_1US + default 0x60005010 + +config IPQ806X_TIMER_FREQ + int "Hardware timer frequency" + default 32000 + depends on TIMER_IPQ806X + help + IPQ hardware presently provides a single timer running at 32KHz, a + finer granulariry timer is available but is not yet enabled. + +config IPQ806X_TIMER_REG + hex "Timer register address" + default 0x0200A008 + depends on TIMER_IPQ806X + help + Address of the register to read a free running timer value. + +config ARMADA38X_TIMER_FREQ + int "Hardware timer frequency" + depends on TIMER_ARMADA38X + default 25000000 + +config ARMADA38X_TIMER_REG + hex "Timer register address" + default 0xF1020314 + depends on TIMER_ARMADA38X + +config IPROC_PERIPH_GLB_TIM_REG_BASE + hex "Cygnus timer base address" + depends on TIMER_CYGNUS + default 0x19020200 + +config TIMER_MTK_HZ + int "MediaTek GPT frequency" + depends on TIMER_MTK + default 13000000 + help + Clock frequency of MediaTek General Purpose Timer. + +config TIMER_MTK_ADDRESS + hex "MTK GPT register address" + depends on TIMER_MTK + default 0x10008048 + help + Address of GPT4's counter register to read the FREERUN-mode timer value. + diff --git a/payloads/libpayload/drivers/usb/Kconfig b/payloads/libpayload/drivers/usb/Kconfig new file mode 100644 index 0000000..e1b68f7 --- /dev/null +++ b/payloads/libpayload/drivers/usb/Kconfig @@ -0,0 +1,129 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config USB + bool "USB Support" + default y + +config USB_UHCI + bool "Support for USB UHCI controllers" + depends on USB && ARCH_X86 + default y + help + Select this option if you are going to use USB 1.1 on an Intel based + system. + +config USB_OHCI + bool "Support for USB OHCI controllers" + depends on USB + default y + help + Select this option if you are going to use USB 1.1 on a non-Intel based + system. + +config USB_EHCI + bool "Support for USB EHCI controllers" + depends on USB + default y + help + Select this option if you want to use USB 2.0 + +config USB_XHCI + bool "Support for USB xHCI controllers" + depends on USB + default y + help + Select this option if you want to use USB 3.0 + +config USB_XHCI_MTK_QUIRK + bool "Support for USB xHCI controllers on MTK SoC" + depends on USB_XHCI + help + Select this option if you want to use USB 3.0 on MTK platform. + +config USB_DWC2 + bool "Support for USB DesignWare HCD controllers" + depends on USB + help + Select this option if you want to use DesignWare USB 2.0 host controller + +config USB_HID + bool "Support for USB keyboards" + depends on USB + default y + help + Select this option if you want to use devices complying to the + USB HID (Human Interface Device) standard. Such devices are for + example keyboards and mice. Currently only keyboards are supported. + Say Y here unless you know exactly what you are doing. + +config USB_HUB + bool "Support for USB hubs" + depends on USB + default y + help + Select this option if you want to compile in support for USB hubs. + Say Y here unless you know exactly what you are doing. + +config USB_EHCI_HOSTPC_ROOT_HUB_TT + bool "Support for USB EHCI ROOT HUB that has TT" + depends on USB_EHCI + default n + help + Select this option if USB EHCI root hub supports TT (Transaction + Translator). + To support this TT feature we read port-speed from non-standard + register HOSTPC (offset 84h of Operational Register base). + +config USB_MSC + bool "Support for USB storage" + depends on USB + default y + help + Select this option if you want to compile in support for USB mass + storage devices (USB memory sticks, hard drives, CDROM/DVD drives) + Say Y here unless you know exactly what you are doing. + +config USB_GEN_HUB + bool + default n if (!USB_HUB && !USB_XHCI) + default y if (USB_HUB || USB_XHCI) +config USB_PCI + bool "Auto-scan PCI bus for USB host controllers" + depends on USB + default y if ARCH_X86 + default n + +config UDC + bool "USB device mode support" + default n + help + Select this option to add support for running as + a USB device. + +config UDC_CI + bool "ChipIdea driver for USB device mode" + depends on UDC + default n + help + Select this option to add the driver for ChipIdea + USB device controller. + +config UDC_DWC2 + bool "Designware driver for USB device mode" + depends on UDC + default n + help + Select this option to add the driver for Designware + USB device controller. +

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New patch to review for coreboot: Documentation: Capitalize RAM and ROM
by HAOUAS Elyes 28 Jul '16

28 Jul '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15927 -gerrit commit 0cc08a23a0a0f035d79f8ded75602a70c4c6bb88 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 28 13:08:24 2016 +0200 Documentation: Capitalize RAM and ROM Change-Id: I06c1d0fe0e3d429e54d3777de679f9fc641f4eed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- Documentation/CorebootBuildingGuide.tex | 2 +- Documentation/Kconfig.tex | 6 +++--- Documentation/RFC/config.tex | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/CorebootBuildingGuide.tex b/Documentation/CorebootBuildingGuide.tex index dac031a..652fa05 100644 --- a/Documentation/CorebootBuildingGuide.tex +++ b/Documentation/CorebootBuildingGuide.tex @@ -70,7 +70,7 @@ base on the AMD platform. \item 2013/12/20 Add Git, Gerrit, toolchains building. \item 2009/04/19 replace LinuxBIOS with coreboot \item 2004/06/02 url and language fixes from Ken Fuchs $<$kfuchs(a)winternet.com$>$ - \item 2004/02/10 acpi and option rom updates + \item 2004/02/10 acpi and option ROM updates \item 2003/11/18 initial release \end{itemize} diff --git a/Documentation/Kconfig.tex b/Documentation/Kconfig.tex index 2b2bf7f..bac8f2b 100644 --- a/Documentation/Kconfig.tex +++ b/Documentation/Kconfig.tex @@ -13,7 +13,7 @@ Most Kconfig files set variables, which can be set as part of the Kconfig dialog For variables set by the user, see src/console/Kconfig. -For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as ram base. These are highly mainboard dependent. +For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as RAM base. These are highly mainboard dependent. Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally. @@ -28,8 +28,8 @@ We define the common rules for which variation to use below. \subsection{object file specification} There are several different types of objects specified in the tree. They are: \begin{description} -\item[obj]objects for the ram part of the code -\item[driver]drivers for the ram part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section. +\item[obj]objects for the RAM part of the code +\item[driver]drivers for the RAM part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section. \item[initobj]seperately-compiled code for the ROM section of coreboot \end{description} These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax. diff --git a/Documentation/RFC/config.tex b/Documentation/RFC/config.tex index 696ab7a..97fec9d 100644 --- a/Documentation/RFC/config.tex +++ b/Documentation/RFC/config.tex @@ -172,7 +172,7 @@ A sample file: \begin{verbatim} target x -# over-ride the default rom size in the mainboard file +# over-ride the default ROM size in the mainboard file option CONFIG_ROM_SIZE=1024*1024 mainboard amd/solo end

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Patch set updated for coreboot: ACPI: Add code to include ATSR structure in DMAR table
by Werner Zeh 28 Jul '16

28 Jul '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15911 -gerrit commit 32d9c61b49e34897b225aff5791b6770f151a598 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Jul 27 06:56:36 2016 +0200 ACPI: Add code to include ATSR structure in DMAR table When creating DMAR table one needs to report all PCI root ports in the scope of a ATSR structure. Add code to create this ATS reporting structure. In addition, a function to fix up the size of the ATSR structure is added as this is a new type and using the function acpi_dmar_drhd_fixup() can lead to confusion. Change-Id: Idc3f6025f597048151f0fd5ea6be04843041e1ab Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/arch/x86/acpi.c | 20 ++++++++++++++++++++ src/arch/x86/include/arch/acpi.h | 12 ++++++++++++ 2 files changed, 32 insertions(+) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 3661297..7d78f04 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -7,6 +7,7 @@ * Copyright (C) 2004 SUSE LINUX AG * Copyright (C) 2005-2009 coresystems GmbH * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2016 Siemens AG * * ACPI FADT, FACS, and DSDT table support added by * Nick Barker <nick.barker9(a)btinternet.com>, and those portions @@ -433,12 +434,31 @@ unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, return drhd->length; } +unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, + u16 segment) +{ + dmar_atsr_entry_t *atsr = (dmar_atsr_entry_t *)current; + memset(atsr, 0, sizeof(*atsr)); + atsr->type = DMAR_ATSR; + atsr->length = sizeof(*atsr); /* will be fixed up later */ + atsr->flags = flags; + atsr->segment = segment; + + return atsr->length; +} + void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current) { dmar_entry_t *drhd = (dmar_entry_t *)base; drhd->length = current - base; } +void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current) +{ + dmar_atsr_entry_t *atsr = (dmar_atsr_entry_t *)base; + atsr->length = current - base; +} + static unsigned long acpi_create_dmar_drhd_ds(unsigned long current, enum dev_scope_type type, u8 enumeration_id, u8 bus, u8 dev, u8 fn) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index dfbffb3..b27dfff 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -5,6 +5,7 @@ * Copyright (C) 2004 Nick Barker * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2016 Siemens AG * (Written by Stefan Reinauer <stepan(a)coresystems.de>) * * This program is free software; you can redistribute it and/or modify @@ -285,6 +286,14 @@ typedef struct dmar_entry { u64 bar; } __attribute__ ((packed)) dmar_entry_t; +typedef struct dmar_atsr_entry { + u16 type; + u16 length; + u8 flags; + u8 reserved; + u16 segment; +} __attribute__ ((packed)) dmar_atsr_entry_t; + /* DMAR (DMA Remapping Reporting Structure) */ typedef struct acpi_dmar { struct acpi_table_header header; @@ -607,7 +616,10 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, unsigned long (*acpi_fill_dmar) (unsigned long)); unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, u16 segment, u32 bar); +unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, + u16 segment); void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); +void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current); unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, u8 bus, u8 dev, u8 fn); unsigned long acpi_create_dmar_drhd_ds_ioapic(unsigned long current,

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Patch set updated for coreboot: ACPI: Add code to create root port entry in DMAR table
by Werner Zeh 28 Jul '16

28 Jul '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15912 -gerrit commit 8696717b321710a4b7962b2c1085d2fe8d6a1a05 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Jul 27 07:07:20 2016 +0200 ACPI: Add code to create root port entry in DMAR table PCI root ports need to be reported in DMAR table in the ATSR scope. Add code to create an entry for a PCI root port using the type "SCOPE_PCI_SUB". Change-Id: Ie2c46db7292d9f1637ffe2e9cfaf6619372ddf13 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/arch/x86/acpi.c | 7 +++++++ src/arch/x86/include/arch/acpi.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 7d78f04..5893461 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -477,6 +477,13 @@ static unsigned long acpi_create_dmar_drhd_ds(unsigned long current, return ds->length; } +unsigned long acpi_create_dmar_drhd_ds_pci_br(unsigned long current, u8 bus, + u8 dev, u8 fn) +{ + return acpi_create_dmar_drhd_ds(current, + SCOPE_PCI_SUB, 0, bus, dev, fn); +} + unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, u8 bus, u8 dev, u8 fn) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index b27dfff..5d08369 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -620,6 +620,8 @@ unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, u16 segment); void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current); +unsigned long acpi_create_dmar_drhd_ds_pci_br(unsigned long current, + u8 bus, u8 dev, u8 fn); unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, u8 bus, u8 dev, u8 fn); unsigned long acpi_create_dmar_drhd_ds_ioapic(unsigned long current,

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coreboot-gerrit July 2016