coreboot-gerrit July 2016

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Patch set updated for coreboot: mainboard/bap/ode_e21XX: Add board support
by Fabian Kunkel 28 Jul '16

28 Jul '16

Fabian Kunkel (fabi(a)adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15918 -gerrit commit cd1cdfe1115eb4832a87b95af6e87a2dbbb2d128 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Wed Jul 27 17:42:39 2016 +0200 mainboard/bap/ode_e21XX: Add board support Add next generation of BAPs (https://www.unibap.com/) SOC module, called ode_e21XX. Hardware is similar to e20XX (AMD G-Series GX-411GA Kabini), but it includes a new AMD G-Series GX-412HC (Steppe Eagle) and an updated Microsemi FPGA. Changes to Olivehillplus: - Add SuperIO Fintek F81866D - Soldered down DDR3 with ECC - User can choose between different DDR3 clk settings (lowest setting can save up to 1.2W) - Soldered down Microsemi M2S060 FPGA on PCIe lanes 2-3 Tested with: - Payload SeaBIOS 1.9.1 - Lubuntu 16.04, Kernel 4.4.0 - Windows 10 (UART functionality) Known problems: - S3 not working - IOMMU not working Change-Id: I41f6a3334ad2128695a3f7c0a6444f1678d2626e Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> --- src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex | 231 ++++++++++++++++++++++++ src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex | 231 ++++++++++++++++++++++++ src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex | 231 ++++++++++++++++++++++++ src/mainboard/bap/ode_e21XX/BiosCallOuts.c | 34 +++- src/mainboard/bap/ode_e21XX/Kconfig | 23 +++ src/mainboard/bap/ode_e21XX/Makefile.inc | 20 ++ src/mainboard/bap/ode_e21XX/OemCustomize.c | 28 +-- src/mainboard/bap/ode_e21XX/acpi/superio.asl | 48 +++++ src/mainboard/bap/ode_e21XX/board_info.txt | 4 +- src/mainboard/bap/ode_e21XX/devicetree.cb | 80 ++++++-- src/mainboard/bap/ode_e21XX/dsdt.asl | 2 + src/mainboard/bap/ode_e21XX/romstage.c | 16 +- 12 files changed, 894 insertions(+), 54 deletions(-) diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex new file mode 100644 index 0000000..507c9f1 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex @@ -0,0 +1,231 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Sage Electronic Engineering, LLC. +# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects +# (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC +# BAP ODE E21XX has 2GB ram soldered down on the Q7 +# Memory setting for DDR-1066 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 125 +11 + +# 1 SPD Revision - +# 0x12 = Revision 1.2 +12 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[7:4]: reserved +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 3 = 15 Row Address Bits +# bits[7:6]: reserved +19 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 2 = 16 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 1 = 1 bit (bus width extension ECC) +# bits[7:5]: reserved +0B + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x01 divisor +# bits[7:4]: 0x01 dividend +# 1/1 = 1ps +11 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns - used for DDR3 +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x0F = tCKmin of 1.875 ns = DDR3-1066 (533 MHz clock) +0F + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# Cas Latencies of 8 - 5 are supported +1E 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 = 13.125ns - DDR3-1066F +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x69 = 13.125ns - DDR3-1066F +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C = 7.5ns +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 = 13.125ns - DDR3-1066F +69 + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x12C = 37.5ns - DDR3-1066 (see byte 21) +2C + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x195 = 50.625ns - DDR3-1066F (see byte 21) +95 + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x500 = 160ns - for 2 Gigabit chips +80 07 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x0190 = 50ns - DDR3-1066, 2 KB page size +01 90 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 0 = DLL Off mode supported +03 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 0 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +04 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 0 = Signal Loading not specified +# bits[3:2]: reserved +# bits[6:4]: 0 = Die count not specified +# bit7 : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 00 00 00 00 + +# 39 - 59 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +00 + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +00 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +00 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 116 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x80AD = Hynix +80 AD + +# 119 Module ID: Module Manufacturing Location - oem specified +# 120 Module ID: Module Manufacture Year in BCD +# 0x00 = 2000 +00 00 + +# 121 Module ID: Module Manufacture week +# 0x00 = 0th week +00 + +# 122 - 125: Module Serial Number +00 00 00 00 + +# 126 - 127: Cyclical Redundancy Code +E9 40 diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex new file mode 100644 index 0000000..1991f84 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex @@ -0,0 +1,231 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Sage Electronic Engineering, LLC. +# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects +# (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC +# BAP ODE E21XX has 2GB ram soldered down on the Q7 +# Memory setting for DDR-1333 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 125 +11 + +# 1 SPD Revision - +# 0x13 = Revision 1.3 +13 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[7:4]: reserved +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 3 = 15 Row Address Bits +# bits[7:6]: reserved +19 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 2 = 16 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 1 = 1 bit (bus width extension ECC) +# bits[7:5]: reserved +0B + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x01 divisor +# bits[7:4]: 0x01 dividend +# 1/1 = 1ps +11 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns - used for DDR3 +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x0C = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock) +0C + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# Cas Latencies of 9 - 5 are supported (no 7) +36 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x6C = 13.5ns - DDR3-1333H +6C + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x6C = 13.5ns - DDR3-1333H +6C + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C = 7.5ns +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x6C = 13.5ns - DDR3-1333H +6C + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x120 = 36ns - DDR3-1333 (see byte 21) +20 + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x18C = 49.5ns - DDR3-1333H (see byte 21) +8C + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x500 = 160ns - for 2 Gigabit chips +80 07 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x0168 = 45ns - DDR3-1333, 2 KB page size +01 68 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 0 = DLL Off mode supported +03 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 0 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +04 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 0 = Signal Loading not specified +# bits[3:2]: reserved +# bits[6:4]: 0 = Die count not specified +# bit7 : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 00 00 00 00 + +# 39 - 59 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +00 + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +00 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +00 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 116 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x80AD = Hynix +80 AD + +# 119 Module ID: Module Manufacturing Location - oem specified +# 120 Module ID: Module Manufacture Year in BCD +# 0x00 = 2000 +00 00 + +# 121 Module ID: Module Manufacture week +# 0x00 = 0th week +00 + +# 122 - 125: Module Serial Number +00 00 00 00 + +# 126 - 127: Cyclical Redundancy Code +95 b9 diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex new file mode 100644 index 0000000..e657179 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex @@ -0,0 +1,231 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Sage Electronic Engineering, LLC. +# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects +# (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC +# BAP ODE E21XX has 2GB ram soldered down on the Q7 +# Memory setting for DDR-800 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 125 +11 + +# 1 SPD Revision - +# 0x11 = Revision 1.1 +11 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[7:4]: reserved +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 3 = 15 Row Address Bits +# bits[7:6]: reserved +19 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 2 = 16 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 1 = 1 bit (bus width extension ECC) +# bits[7:5]: reserved +0B + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x01 divisor +# bits[7:4]: 0x01 dividend +# 1/1 = 1ps +11 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns - used for DDR3 +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x14 = tCKmin of 2.5 ns = DDR3-800 (400 MHz clock) +14 + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# CAS Latencies of 6 - 5 are supported +06 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x78 = 15ns - DDR3-800E +78 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x6E = 15ns - DDR3-800E +78 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C = 7.5ns +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x6E = 15ns - DDR3-800E +78 + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x12C = 37.5ns - DDR3-800E (see byte 21) +2C + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x1A4 = 52.5ns - DDR3-800E (see byte 21) +A4 + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x780 = 208ns - for 4 Gigabit chips +80 07 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x0190 = 50ns - DDR3-800, 2 KB page size +01 90 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 0 = DLL Off mode supported +03 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 0 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +04 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 0 = Signal Loading not specified +# bits[3:2]: reserved +# bits[6:4]: 0 = Die count not specified +# bit7 : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 00 00 00 00 + +# 39 - 59 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +00 + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +00 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +00 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 116 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x80AD = Hynix +80 AD + +# 119 Module ID: Module Manufacturing Location - oem specified +# 120 Module ID: Module Manufacture Year in BCD +# 0x00 = 2000 +00 00 + +# 121 Module ID: Module Manufacture week +# 0x00 = 0th week +00 + +# 122 - 125: Module Serial Number +00 00 00 00 + +# 126 - 127: Cyclical Redundancy Code +48 91 diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 9528f72..1b37865 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -25,15 +25,17 @@ #endif #include "hudson.h" #include <stdlib.h> +#include <spd_cache.h> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); +static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, - {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD, board_ReadSpd_from_cbfs }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, @@ -303,3 +305,33 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) return AGESA_SUCCESS; } + +static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status = AGESA_UNSUPPORTED; +#ifdef __PRE_RAM__ + AGESA_READ_SPD_PARAMS *info = ConfigPtr; + u8 index; + + if (IS_ENABLED(CONFIG_BAP_E21_DDR3_1066)) + index = 1; + else if (IS_ENABLED(CONFIG_BAP_E21_DDR3_1333)) + index = 2; + else /* CONFIG_BAP_E21_DDR3_800 */ + index = 0; + + if (info->MemChannelId > 0) + return AGESA_UNSUPPORTED; + if (info->SocketId != 0) + return AGESA_UNSUPPORTED; + if (info->DimmId != 0) + return AGESA_UNSUPPORTED; + + /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ + if (read_spd_from_cbfs((u8 *)info->Buffer, index) < 0) + die("No SPD data\n"); + + Status = AGESA_SUCCESS; +#endif + return Status; +} diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index 426a994..b356749 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -26,6 +26,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA + select SUPERIO_FINTEK_F81866D + select SPD_CACHE config MAINBOARD_DIR string @@ -51,4 +53,25 @@ config HUDSON_LEGACY_FREE bool default y +choice + prompt "Select DDR3 clock" + default BAP_E21_DDR3_1333 + help + Select your preferenced DDR3 clock setting. + + Note: This option changes the total power consumption. + + If unsure, use DDR3-1333. + +config BAP_E21_DDR3_800 + bool "Select DDR3-800" + +config BAP_E21_DDR3_1066 + bool "Select DDR3-1066" + +config BAP_E21_DDR3_1333 + bool "Select DDR3-1333" + +endchoice + endif # BOARD_ODE_E21XX diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc index 37c1dce..4f4a11d 100644 --- a/src/mainboard/bap/ode_e21XX/Makefile.inc +++ b/src/mainboard/bap/ode_e21XX/Makefile.inc @@ -18,3 +18,23 @@ romstage-y += OemCustomize.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c + +## DIMM SPD for on-board memory +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = BAP_Q7_800 BAP_Q7_1066 BAP_Q7_1333 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/bap/ode_e21XX/OemCustomize.c b/src/mainboard/bap/ode_e21XX/OemCustomize.c index ac60c42..3750ba4 100644 --- a/src/mainboard/bap/ode_e21XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e21XX/OemCustomize.c @@ -18,20 +18,10 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { - /* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */ + /* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device 2, Function 4) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x01, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, HotplugDisabled, PcieGenMaxSupported, @@ -71,23 +61,17 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { - /* DP0 to HDMI0/DP */ + /* eDP0 to LVDS connector */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) }, - /* DP1 to FCH */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) - }, - /* DP2 to HDMI1/DP */ + /* DP1 to HDMI */ { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) }, }; diff --git a/src/mainboard/bap/ode_e21XX/acpi/superio.asl b/src/mainboard/bap/ode_e21XX/acpi/superio.asl new file mode 100644 index 0000000..92bd106 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/acpi/superio.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* SuperIO support for Windows */ + +Device (UAR1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) +} + +Device (UAR2) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 2) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3} + }) + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3} + }) +} diff --git a/src/mainboard/bap/ode_e21XX/board_info.txt b/src/mainboard/bap/ode_e21XX/board_info.txt index d2c6670..dffb350 100644 --- a/src/mainboard/bap/ode_e21XX/board_info.txt +++ b/src/mainboard/bap/ode_e21XX/board_info.txt @@ -1,5 +1,5 @@ -Board name: DB-FT3b (Olive Hill+) -Board URL: http://wwwd.amd.com/amd/devsite.nsf/platforms/DB-FT3.htm +Board name: ODE_e21xx +Board URL: http://www.unibap.com/advanced-heterogeneous-computing-modules/ Category: eval ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/bap/ode_e21XX/devicetree.cb b/src/mainboard/bap/ode_e21XX/devicetree.cb index ee0cd98..1a900c0 100644 --- a/src/mainboard/bap/ode_e21XX/devicetree.cb +++ b/src/mainboard/bap/ode_e21XX/devicetree.cb @@ -30,10 +30,9 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector + device pci 2.2 on end # PCIe Q7 Realtek GBit LAN + device pci 2.3 on end # PCIe CB Realtek GBit LAN + device pci 2.4 on end # PCIe x2 BAP FPGA device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 @@ -42,18 +41,67 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 11.0 on end # SATA device pci 12.0 on end # EHCI #0 device pci 13.0 on end # EHCI #1 - device pci 14.0 on # SMBus - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SMbus + device pci 14.0 on end # SMBus device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81866d + register "hwm_amd_tsi_addr" = "0x98" # Set to AMD + register "hwm_amd_tsi_control" = "0x02" # Set to AMD + register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM + register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode + register "hwm_fan3_control" = "0x00" # Fan control 23kHz + register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz + register "hwm_fan2_bound1" = "0x3C" # 60°C + register "hwm_fan2_bound2" = "0x32" # 50°C + register "hwm_fan2_bound3" = "0x28" # 40°C + register "hwm_fan2_bound4" = "0x1E" # 30°C + register "hwm_fan2_seg1_speed" = "0xFF" # 100% + register "hwm_fan2_seg2_speed" = "0xD9" # 85% + register "hwm_fan2_seg3_speed" = "0xB2" # 70% + register "hwm_fan2_seg4_speed" = "0x99" # 60% + register "hwm_fan2_seg5_speed" = "0x80" # 50% + register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 on # Hardware Monitor + io 0x60 = 0x295 + irq 0x70 = 0 + end + device pnp 4e.5 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.7 on end # WDT + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.12 off # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 4e.13 off # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 4e.14 off # COM5 + end + device pnp 4e.15 off # COM6 + end + end # f81866d + end #LPC device pci 14.7 on end # SD - device pci 16.0 on end # EHCI #2 end #chip southbridge/amd/pi/hudson device pci 18.0 on end @@ -62,10 +110,6 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2} }, // socket 0, channel 0, slots 0 & 1 - 8-bit SPD addresses - }" end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex end #domain diff --git a/src/mainboard/bap/ode_e21XX/dsdt.asl b/src/mainboard/bap/ode_e21XX/dsdt.asl index 45ae428..3afae7a 100644 --- a/src/mainboard/bap/ode_e21XX/dsdt.asl +++ b/src/mainboard/bap/ode_e21XX/dsdt.asl @@ -69,6 +69,8 @@ DefinitionBlock ( /* Describe PCI INT[A-H] for the Southbridge */ #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> + /* Add UART support for Windows */ + #include "acpi/superio.asl" } /* End \_SB scope */ diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index a5c529e..8466e25 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -32,6 +32,10 @@ #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81866d/f81866d.h> + +#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -54,7 +58,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); - + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); post_code(0x31); console_init(); } @@ -68,16 +72,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); - /* - * This refers to LpcClkDrvSth settling time. Without this setting, processor - * initialization is slow or incorrect, so this wait has been replicated from - * earlier development boards. - */ - { - int i; - for(i = 0; i < 200000; i++) inb(0xCD6); - } - post_code(0x37); AGESAWRAPPER(amdinitreset);

1 0

Patch set updated for coreboot: mainboard/bap/ode_e21XX: Add copy of amd/olivehillplus
by Fabian Kunkel 28 Jul '16

28 Jul '16

Fabian Kunkel (fabi(a)adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15917 -gerrit commit 8390e7e536d6506a8fcaa4023c32b69eeb862fd5 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Wed Jul 27 17:30:49 2016 +0200 mainboard/bap/ode_e21XX: Add copy of amd/olivehillplus Initial copy of olivehillplus. Change-Id: Ibe9b450c05bfad15a95852addb1465ac2d3cef61 Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> --- src/mainboard/bap/ode_e21XX/BiosCallOuts.c | 305 +++++++++++++++++++++++++ src/mainboard/bap/ode_e21XX/Kconfig | 54 +++++ src/mainboard/bap/ode_e21XX/Kconfig.name | 2 + src/mainboard/bap/ode_e21XX/Makefile.inc | 20 ++ src/mainboard/bap/ode_e21XX/OemCustomize.c | 122 ++++++++++ src/mainboard/bap/ode_e21XX/acpi/AmdImc.asl | 109 +++++++++ src/mainboard/bap/ode_e21XX/acpi/gpe.asl | 74 ++++++ src/mainboard/bap/ode_e21XX/acpi/ide.asl | 2 + src/mainboard/bap/ode_e21XX/acpi/mainboard.asl | 37 +++ src/mainboard/bap/ode_e21XX/acpi/routing.asl | 193 ++++++++++++++++ src/mainboard/bap/ode_e21XX/acpi/si.asl | 23 ++ src/mainboard/bap/ode_e21XX/acpi/sleep.asl | 95 ++++++++ src/mainboard/bap/ode_e21XX/acpi/thermal.asl | 2 + src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl | 36 +++ src/mainboard/bap/ode_e21XX/acpi_tables.c | 56 +++++ src/mainboard/bap/ode_e21XX/board_info.txt | 6 + src/mainboard/bap/ode_e21XX/cmos.layout | 74 ++++++ src/mainboard/bap/ode_e21XX/devicetree.cb | 72 ++++++ src/mainboard/bap/ode_e21XX/dsdt.asl | 87 +++++++ src/mainboard/bap/ode_e21XX/irq_tables.c | 103 +++++++++ src/mainboard/bap/ode_e21XX/mainboard.c | 41 ++++ src/mainboard/bap/ode_e21XX/mptable.c | 190 +++++++++++++++ src/mainboard/bap/ode_e21XX/romstage.c | 120 ++++++++++ 23 files changed, 1823 insertions(+) diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c new file mode 100644 index 0000000..9528f72 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -0,0 +1,305 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/pi/BiosCallOuts.h> +#include "Ids.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "cbfs.h" +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include "imc.h" +#endif +#include "hudson.h" +#include <stdlib.h> + +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, + {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * Realtek ALC272 CODEC Verb Table + */ +static const CODEC_ENTRY Alc272_VerbTbl[] = { + {0x11, 0x411111F0}, // - SPDIF_OUT2 + {0x12, 0x411111F0}, // - DMIC_1/2 + {0x13, 0x411111F0}, // - DMIC_3/4 + {0x14, 0x411111F0}, // Port D - LOUT1 + {0x15, 0x411111F0}, // Port A - LOUT2 + {0x16, 0x411111F0}, // + {0x17, 0x411111F0}, // Port H - MONO + {0x18, 0x01a19840}, // Port B - MIC1 + {0x19, 0x411111F0}, // Port F - MIC2 + {0x1a, 0x01813030}, // Port C - LINE1 + {0x1b, 0x411111F0}, // Port E - LINE2 + {0x1d, 0x40251E05}, // - PCBEEP + {0x1e, 0x01441120}, // - SPDIF_OUT1 + {0x21, 0x01214010}, // Port I - HPOUT + {0xff, 0xffffffff} +}; + +static const CODEC_TBL_LIST CodecTableList[] = +{ + {0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF + +/* + * Hardware Monitor Fan Control + * Hardware limitation: + * HWM will fail to read the input temperature via I2C if other + * software switches the I2C address. AMD recommends using IMC + * to control fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ + FCH_HWM_FAN_CTR oem_factl[5] = { + /*temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ + /* DB-FT3 FanOUT0 Fan header J32 */ + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + /* DB-FT3 FanOUT1 Fan header J31*/ + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + }; + LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); + + /* Enable IMC fan control. the recommended way */ +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + + /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */ + + FchParams->Imc.ImcEnable = TRUE; + FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + + LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); + + /* Thermal Zone Parameter */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; //6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; + + /* IMC Fan Policy temperature thresholds */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; + + /* IMC Fan Policy PWM Settings */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ + + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; + + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; + + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */ + + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0; + + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; + + /* IMC Function */ + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; //BIT0 | BIT4 |BIT8; + + /* NOTE: + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, + * AGESA put EcDefaultMessage as global data in ROM, so we can't override it. + * so we remove it from AGESA code. Please See FchInitLateHwm. + */ + +#else /* HWM fan control, using the alternative method */ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = TRUE; /* 1 enable, 0 disable TSI Auto Polling */ + +#endif /* CONFIG_HUDSON_IMC_FWM */ +} + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such Azalia, SATA, IMC etc. + */ +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; + if (StdHeader->Func == AMD_INIT_RESET) { + FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; + FchParams->FchReset.SataEnable = hudson_sata_enable(); + FchParams->FchReset.IdeEnable = hudson_ide_enable(); + FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->FchReset.Xhci1Enable = FALSE; + } else if (StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + + /* Azalia Controller OEM Codec Table Pointer */ + FchParams->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); + /* Azalia Controller Front Panel OEM Table Pointer */ + + /* Fan Control */ + oem_fan_control(FchParams); + + /* XHCI configuration */ + FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci1Enable = FALSE; + + /* sata configuration */ + FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; + switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams->Sata.SataIdeMode = TRUE; + break; + } + } + printk(BIOS_DEBUG, "Done\n"); + + return AGESA_SUCCESS; +} diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig new file mode 100644 index 0000000..426a994 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -0,0 +1,54 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ODE_E21XX + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_PI_00730F01 + select NORTHBRIDGE_AMD_PI_00730F01 + select SOUTHBRIDGE_AMD_PI_AVALON + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + +config MAINBOARD_DIR + string + default bap/ode_e21XX + +config MAINBOARD_PART_NUMBER + string + default "ODE_E21XX" + +config MAX_CPUS + int + default 4 + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config HUDSON_LEGACY_FREE + bool + default y + +endif # BOARD_ODE_E21XX diff --git a/src/mainboard/bap/ode_e21XX/Kconfig.name b/src/mainboard/bap/ode_e21XX/Kconfig.name new file mode 100644 index 0000000..5ef8804 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ODE_E21XX + bool "ODE_e21xx" diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc new file mode 100644 index 0000000..37c1dce --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/bap/ode_e21XX/OemCustomize.c b/src/mainboard/bap/ode_e21XX/OemCustomize.c new file mode 100644 index 0000000..ac60c42 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/OemCustomize.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/amd/pi/agesawrapper.h> + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +static const PCIe_PORT_DESCRIPTOR PortList [] = { + /* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x01, 0) + }, + /* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x05, 0) + } +}; + +static const PCIe_DDI_DESCRIPTOR DdiList [] = { + /* DP0 to HDMI0/DP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + }, + /* DP1 to FCH */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + }, + /* DP2 to HDMI1/DP */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; +} diff --git a/src/mainboard/bap/ode_e21XX/acpi/AmdImc.asl b/src/mainboard/bap/ode_e21XX/acpi/AmdImc.asl new file mode 100644 index 0000000..d3bb74e --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/acpi/AmdImc.asl @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Store(0, Local0) + While (LNotEqual(Local0, 0xFA)) { + Store(MRG0, Local0) + Sleep(10) + } +} + +//Init +Method (ITZE, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(1, MRG1) + Store(0, MRG2) + Store(0x98, MSTI) + WACK() + + Store(0, MRG0) + Store(0xB4, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() +} + +//Wake +Method (IMWK, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} diff --git a/src/mainboard/bap/ode_e21XX/acpi/gpe.asl b/src/mainboard/bap/ode_e21XX/acpi/gpe.asl new file mode 100644 index 0000000..9a84698 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/acpi/gpe.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/bap/ode_e21XX/acpi/ide.asl b/src/mainboard/bap/ode_e21XX/acpi/ide.asl new file mode 100644 index 0000000..4a3eac8 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/acpi/ide.asl @@ -0,0 +1,2 @@ +/* No license required */ +/* No IDE functionality */ diff --git a/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl b/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl new file mode 100644 index 0000000..0141481 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +/* AcpiGpe0Blk */ +OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, +} diff --git a/src/mainboard/bap/ode_e21XX/acpi/routing.asl b/src/mainboard/bap/ode_e21XX/acpi/routing.asl new file mode 100644 index 0000000..7cb7a2f --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/acpi/routing.asl @@ -0,0 +1,193 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F16 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 44 }, + Package(){0x0001FFFF, 1, 0, 45 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 24 }, + Package(){0x0002FFFF, 1, 0, 25 }, + Package(){0x0002FFFF, 2, 0, 26 }, + Package(){0x0002FFFF, 3, 0, 27 }, + + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + +}) + +Name(PS2, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS2, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GFX */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, +}) + +/* GPP 0 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 28 }, + Package(){0x0000FFFF, 1, 0, 29 }, + Package(){0x0000FFFF, 2, 0, 30 }, + Package(){0x0000FFFF, 3, 0, 31 }, +}) + +/* GPP 1 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, +}) + +/* GPP 2 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, +}) + +/* GPP 3 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) diff --git a/src/mainboard/bap/ode_e21XX/acpi/si.asl b/src/mainboard/bap/ode_e21XX/acpi/si.asl new file mode 100644 index 0000000..2923471 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/acpi/si.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ diff --git a/src/mainboard/bap/ode_e21XX/acpi/sleep.asl b/src/mainboard/bap/ode_e21XX/acpi/sleep.asl new file mode 100644 index 0000000..0734c8e --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/acpi/sleep.asl @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ + +External(\_SB.APTS, MethodObj) +External(\_SB.AWAK, MethodObj) + +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) + \_SB.APTS(Arg0) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* clear USB wake up signal */ + Store(1, USBS) + + \_SB.AWAK(Arg0) + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/bap/ode_e21XX/acpi/thermal.asl b/src/mainboard/bap/ode_e21XX/acpi/thermal.asl new file mode 100644 index 0000000..73077ac --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/acpi/thermal.asl @@ -0,0 +1,2 @@ +/* No license required */ +/* No thermal zone functionality */ diff --git a/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl b/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl new file mode 100644 index 0000000..1643fe7 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/bap/ode_e21XX/acpi_tables.c b/src/mainboard/bap/ode_e21XX/acpi_tables.c new file mode 100644 index 0000000..d5ebad4 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/acpi_tables.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/amd/pi/agesawrapper.h> + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam16.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + /* TODO: Remove the hardcode */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, + 0xFEC20000, 24); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/bap/ode_e21XX/board_info.txt b/src/mainboard/bap/ode_e21XX/board_info.txt new file mode 100644 index 0000000..d2c6670 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/board_info.txt @@ -0,0 +1,6 @@ +Board name: DB-FT3b (Olive Hill+) +Board URL: http://wwwd.amd.com/amd/devsite.nsf/platforms/DB-FT3.htm +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/bap/ode_e21XX/cmos.layout b/src/mainboard/bap/ode_e21XX/cmos.layout new file mode 100644 index 0000000..d83bb14 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/cmos.layout @@ -0,0 +1,74 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/bap/ode_e21XX/devicetree.cb b/src/mainboard/bap/ode_e21XX/devicetree.cb new file mode 100644 index 0000000..ee0cd98 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/devicetree.cb @@ -0,0 +1,72 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/pi/00730F01/root_complex + device cpu_cluster 0 on + chip cpu/amd/pi/00730F01 + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00730F01 # CPU side of HT root complex + + chip northbridge/amd/pi/00730F01 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # mPCIe slot + device pci 2.3 on end # Realtek NIC + device pci 2.4 on end # Edge Connector + device pci 2.5 on end # Edge Connector + device pci 8.0 on end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 + + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # EHCI #0 + device pci 13.0 on end # EHCI #1 + device pci 14.0 on # SMBus + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SMbus + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.7 on end # SD + device pci 16.0 on end # EHCI #2 + end #chip southbridge/amd/pi/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0xA2} }, // socket 0, channel 0, slots 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex + end #domain +end #northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/bap/ode_e21XX/dsdt.asl b/src/mainboard/bap/ode_e21XX/dsdt.asl new file mode 100644 index 0000000..45ae428 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/dsdt.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/pi/00730F01/acpi/cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/bap/ode_e21XX/irq_tables.c b/src/mainboard/bap/ode_e21XX/irq_tables.c new file mode 100644 index 0000000..c48a445 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/irq_tables.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam16.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c new file mode 100644 index 0000000..1e82768 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/mainboard.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <arch/acpi.h> +#include <northbridge/amd/pi/BiosCallOuts.h> +#include <cpu/amd/pi/s3_resume.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +/********************************************** + * enable the dedicated function in mainboard. + **********************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + if (acpi_is_wakeup_s3()) + agesawrapper_fchs3earlyrestore(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c new file mode 100644 index 0000000..a2ba7f4 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/mptable.c @@ -0,0 +1,190 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam15.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/pi/hudson/hudson.h> + +u8 picr_data[0x54] = { + 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x03,0x04,0x05,0x07 +}; +u8 intr_data[0x54] = { + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u8 byte; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_pci, 0x6, 0x0, 0x15); + PCI_INT(bus_pci, 0x6, 0x1, 0x16); + PCI_INT(bus_pci, 0x6, 0x2, 0x17); + PCI_INT(bus_pci, 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_pci, 0x7, 0x0, 0x16); + PCI_INT(bus_pci, 0x7, 0x1, 0x17); + PCI_INT(bus_pci, 0x7, 0x2, 0x14); + PCI_INT(bus_pci, 0x7, 0x3, 0x15); + } + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c new file mode 100644 index 0000000..a5c529e --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <commonlib/loglevel.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <cpu/amd/pi/s3_resume.h> + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + amd_initmmio(); + + hudson_lpc_port80(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + + post_code(0x31); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + /* + * This refers to LpcClkDrvSth settling time. Without this setting, processor + * initialization is slow or incorrect, so this wait has been replicated from + * earlier development boards. + */ + { + int i; + for(i = 0; i < 200000; i++) inb(0xCD6); + } + + post_code(0x37); + AGESAWRAPPER(amdinitreset); + + post_code(0x38); + printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); + + post_code(0x39); + AGESAWRAPPER(amdinitearly); + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + //PspMboxBiosCmdDramInfo(); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + AGESAWRAPPER(amdinitresume); + + AGESAWRAPPER(amds3laterestore); + + post_code(0x61); + prepare_for_resume(); + } + + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +}

1 0

Patch set updated for coreboot: src/mainboard: Add vendor ELMEX with two board templates
by Kyösti Mälkki 28 Jul '16

28 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15926 -gerrit commit 5a23a822cee7e4644c9f813cbaed7dba643414ae Author: Yuichi Ito <yui.corebt(a)gmail.com> Date: Thu Jul 28 13:34:18 2016 +0900 src/mainboard: Add vendor ELMEX with two board templates Both added boards used amd/persimmon as template. Change-Id: I263b54e0f49b6f1ba730c7f87de41f990ba8fe67 Signed-off-by: Yuichi Ito <yui.corebt(a)gmail.com> --- src/mainboard/elmex/Kconfig | 16 + src/mainboard/elmex/Kconfig.name | 2 + src/mainboard/elmex/pcm205400/BiosCallOuts.c | 93 ++++++ src/mainboard/elmex/pcm205400/Kconfig | 77 +++++ src/mainboard/elmex/pcm205400/Kconfig.name | 2 + src/mainboard/elmex/pcm205400/Makefile.inc | 29 ++ src/mainboard/elmex/pcm205400/OemCustomize.c | 157 ++++++++++ src/mainboard/elmex/pcm205400/OptionsIds.h | 56 ++++ .../elmex/pcm205400/PlatformGnbPcieComplex.h | 65 ++++ src/mainboard/elmex/pcm205400/acpi/gpe.asl | 78 +++++ src/mainboard/elmex/pcm205400/acpi/ide.asl | 240 +++++++++++++++ src/mainboard/elmex/pcm205400/acpi/mainboard.asl | 63 ++++ src/mainboard/elmex/pcm205400/acpi/routing.asl | 336 +++++++++++++++++++++ src/mainboard/elmex/pcm205400/acpi/sata.asl | 145 +++++++++ src/mainboard/elmex/pcm205400/acpi/sleep.asl | 117 +++++++ src/mainboard/elmex/pcm205400/acpi/superio.asl | 14 + src/mainboard/elmex/pcm205400/acpi/usb_oc.asl | 170 +++++++++++ src/mainboard/elmex/pcm205400/acpi_tables.c | 53 ++++ src/mainboard/elmex/pcm205400/board_info.txt | 5 + src/mainboard/elmex/pcm205400/buildOpts.c | 297 ++++++++++++++++++ src/mainboard/elmex/pcm205400/cmos.layout | 76 +++++ src/mainboard/elmex/pcm205400/devicetree.cb | 157 ++++++++++ src/mainboard/elmex/pcm205400/dsdt.asl | 63 ++++ src/mainboard/elmex/pcm205400/irq_tables.c | 111 +++++++ src/mainboard/elmex/pcm205400/mainboard.c | 178 +++++++++++ src/mainboard/elmex/pcm205400/mptable.c | 148 +++++++++ src/mainboard/elmex/pcm205400/platform_cfg.h | 254 ++++++++++++++++ src/mainboard/elmex/pcm205400/romstage.c | 111 +++++++ src/mainboard/elmex/pcm205401/BiosCallOuts.c | 93 ++++++ src/mainboard/elmex/pcm205401/Kconfig | 77 +++++ src/mainboard/elmex/pcm205401/Kconfig.name | 2 + src/mainboard/elmex/pcm205401/Makefile.inc | 29 ++ src/mainboard/elmex/pcm205401/OemCustomize.c | 157 ++++++++++ src/mainboard/elmex/pcm205401/OptionsIds.h | 56 ++++ .../elmex/pcm205401/PlatformGnbPcieComplex.h | 65 ++++ src/mainboard/elmex/pcm205401/acpi/gpe.asl | 78 +++++ src/mainboard/elmex/pcm205401/acpi/ide.asl | 240 +++++++++++++++ src/mainboard/elmex/pcm205401/acpi/mainboard.asl | 63 ++++ src/mainboard/elmex/pcm205401/acpi/routing.asl | 336 +++++++++++++++++++++ src/mainboard/elmex/pcm205401/acpi/sata.asl | 145 +++++++++ src/mainboard/elmex/pcm205401/acpi/sleep.asl | 117 +++++++ src/mainboard/elmex/pcm205401/acpi/superio.asl | 14 + src/mainboard/elmex/pcm205401/acpi/usb_oc.asl | 170 +++++++++++ src/mainboard/elmex/pcm205401/acpi_tables.c | 53 ++++ src/mainboard/elmex/pcm205401/board_info.txt | 5 + src/mainboard/elmex/pcm205401/buildOpts.c | 297 ++++++++++++++++++ src/mainboard/elmex/pcm205401/cmos.layout | 76 +++++ src/mainboard/elmex/pcm205401/devicetree.cb | 157 ++++++++++ src/mainboard/elmex/pcm205401/dsdt.asl | 63 ++++ src/mainboard/elmex/pcm205401/irq_tables.c | 111 +++++++ src/mainboard/elmex/pcm205401/mainboard.c | 178 +++++++++++ src/mainboard/elmex/pcm205401/mptable.c | 148 +++++++++ src/mainboard/elmex/pcm205401/platform_cfg.h | 254 ++++++++++++++++ src/mainboard/elmex/pcm205401/romstage.c | 111 +++++++ 54 files changed, 6208 insertions(+) diff --git a/src/mainboard/elmex/Kconfig b/src/mainboard/elmex/Kconfig new file mode 100644 index 0000000..d1fc9ad --- /dev/null +++ b/src/mainboard/elmex/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_ELMEX + +choice + prompt "Mainboard model" + +source "src/mainboard/elmex/*/Kconfig.name" + +endchoice + +source "src/mainboard/elmex/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "ELMEX" + +endif # VENDOR_ELMEX diff --git a/src/mainboard/elmex/Kconfig.name b/src/mainboard/elmex/Kconfig.name new file mode 100644 index 0000000..b2dcf2e --- /dev/null +++ b/src/mainboard/elmex/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ELMEX + bool "ELMEX" diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c new file mode 100644 index 0000000..9a2a9bb --- /dev/null +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "heapManager.h" +#include "SB800.h" +#include <stdlib.h> + +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/* Call the host environment interface to provide a user hook opportunity. */ +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. + // Make sure the right speed settings are selected. + ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + return AGESA_SUCCESS; +} + +/* PCIE slot reset control */ +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + PCIe_SLOT_RESET_INFO *ResetInfo; + + UINT32 GpioMmioAddr; + UINT32 AcpiMmioAddr; + UINT8 Data8; + UINT16 Data16; + + FcnData = Data; + ResetInfo = ConfigPtr; + // Get SB800 MMIO Base (AcpiMmioAddr) + WriteIo8(0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16=Data8<<8; + WriteIo8(0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16|=Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + Status = AGESA_UNSUPPORTED; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + switch (ResetInfo->ResetId) + { + case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); + Status = AGESA_SUCCESS; + break; + } + break; + } + return Status; +} diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig new file mode 100644 index 0000000..e279aea --- /dev/null +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -0,0 +1,77 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ELMEX_PCM205400 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_AGESA_FAMILY14 + select NORTHBRIDGE_AMD_AGESA_FAMILY14 + select SOUTHBRIDGE_AMD_CIMX_SB800 + select SUPERIO_FINTEK_F81865F + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select GFXUMA + +config MAINBOARD_DIR + string + default elmex/pcm205400 + +config MAINBOARD_PART_NUMBER + string + default "pcm205400" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 2 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +#config VGA_BIOS_FILE +# string "VGA BIOS path and filename" +# depends on VGA_BIOS +# default "rom/video/OntarioGenericVbios.bin" + +config VGA_BIOS_ID + string + default "1002,9802" + +config SB800_AHCI_ROM + bool + default n + +endif # BOARD_ELMEX_PCM205400 diff --git a/src/mainboard/elmex/pcm205400/Kconfig.name b/src/mainboard/elmex/pcm205400/Kconfig.name new file mode 100644 index 0000000..445b588 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ELMEX_PCM205400 + bool "pcm205400" diff --git a/src/mainboard/elmex/pcm205400/Makefile.inc b/src/mainboard/elmex/pcm205400/Makefile.inc new file mode 100644 index 0000000..ba56286 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/Makefile.inc @@ -0,0 +1,29 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ifeq ($(CONFIG_AHCI_BIOS),y) +stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID)) +cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom +pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE)) +pci$(stripped_ahcibios_id).rom-type := optionrom +endif + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c new file mode 100644 index 0000000..825364e --- /dev/null +++ b/src/mainboard/elmex/pcm205400/OemCustomize.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "PlatformGnbPcieComplex.h" + +#include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> +#include <PlatformMemoryConfiguration.h> + +#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE + +/** + * OemCustomizeInitEarly + * + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] *InitEarly + * + * @retval VOID + * + **/ + +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +{ + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + +PCIe_PORT_DESCRIPTOR PortList [] = { + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeLvds, Aux1, Hdp1} + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} + } +}; + +PCIe_COMPLEX_DESCRIPTOR Brazos = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + ASSERT(Status == AGESA_SUCCESS); + + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(Brazos); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(PortList); + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); + memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); + memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); + + + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + PSO_END +}; + +const struct OEM_HOOK OemCustomize = { + .InitEarly = OemInitEarly, +}; diff --git a/src/mainboard/elmex/pcm205400/OptionsIds.h b/src/mainboard/elmex/pcm205400/OptionsIds.h new file mode 100644 index 0000000..2d8381b --- /dev/null +++ b/src/mainboard/elmex/pcm205400/OptionsIds.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..4132c7c --- /dev/null +++ b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/elmex/pcm205400/acpi/gpe.asl b/src/mainboard/elmex/pcm205400/acpi/gpe.asl new file mode 100644 index 0000000..2f22758 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/gpe.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ + +/* Contains the GPEs for USB overcurrent */ +#include "usb_oc.asl" diff --git a/src/mainboard/elmex/pcm205400/acpi/ide.asl b/src/mainboard/elmex/pcm205400/acpi/ide.asl new file mode 100644 index 0000000..59ea078 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/ide.asl @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0, Serialized) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, Serialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF, 0, Serialized) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF, 0, Serialized) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/elmex/pcm205400/acpi/mainboard.asl b/src/mainboard/elmex/pcm205400/acpi/mainboard.asl new file mode 100644 index 0000000..b666a4f --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/mainboard.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Data to be patched by the BIOS during POST */ +/* FIXME the patching is not done yet! */ +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +Scope(\_SB) { + Method(OSFL, 0){ + + if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + + if(CondRefOf(\_OSI)) + { + Store(1, OSVR) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSVR) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSVR) /* Linux */ + } Else { + Store(4, OSVR) /* Gotta be WinCE */ + } + } + Return(OSVR) + } +} + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ diff --git a/src/mainboard/elmex/pcm205400/acpi/routing.asl b/src/mainboard/elmex/pcm205400/acpi/routing.asl new file mode 100644 index 0000000..6f94b45 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/routing.asl @@ -0,0 +1,336 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */ + Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */ + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 19 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + + /* TODO: pcie */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */ + Package(){0x0003FFFF, 0, 0, 0x14 }, + Package(){0x0003FFFF, 1, 0, 0x15 }, + Package(){0x0003FFFF, 2, 0, 0x16 }, + Package(){0x0003FFFF, 3, 0, 0x17 }, + Package(){0x0004FFFF, 0, 0, 0x15 }, + Package(){0x0004FFFF, 1, 0, 0x16 }, + Package(){0x0004FFFF, 2, 0, 0x17 }, + Package(){0x0004FFFF, 3, 0, 0x14 }, + Package(){0x0005FFFF, 0, 0, 0x16 }, + Package(){0x0005FFFF, 1, 0, 0x17 }, + Package(){0x0005FFFF, 2, 0, 0x14 }, + Package(){0x0005FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/elmex/pcm205400/acpi/sata.asl b/src/mainboard/elmex/pcm205400/acpi/sata.asl new file mode 100644 index 0000000..9e0e535 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/sata.asl @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/elmex/pcm205400/acpi/sleep.asl b/src/mainboard/elmex/pcm205400/acpi/sleep.asl new file mode 100644 index 0000000..b3fd07e --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/sleep.asl @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, Local1) + Store(Local1, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/elmex/pcm205400/acpi/superio.asl b/src/mainboard/elmex/pcm205400/acpi/superio.asl new file mode 100644 index 0000000..daf6e91 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/superio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl new file mode 100644 index 0000000..6e9c701 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/elmex/pcm205400/acpi_tables.c b/src/mainboard/elmex/pcm205400/acpi_tables.c new file mode 100644 index 0000000..9b92c05 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi_tables.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam14.h> + + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/elmex/pcm205400/board_info.txt b/src/mainboard/elmex/pcm205400/board_info.txt new file mode 100644 index 0000000..85cb19a --- /dev/null +++ b/src/mainboard/elmex/pcm205400/board_info.txt @@ -0,0 +1,5 @@ +Board name: DBFT1-00-EVAL-KT (Persimmon) +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c new file mode 100644 index 0000000..fe4e779 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -0,0 +1,297 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + */ + +#include <stdlib.h> +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT TRUE +#define INSTALL_FAMILY_15_SUPPORT FALSE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + +#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE +#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE + + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE TRUE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 + +/* + * Agesa configuration values selection. + * Uncomment and specify the value for the configuration options + * needed by the system. + */ +#include "AGESA.h" + +/* The fixed MTRR values to be set after memory initialization. */ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, + { CPU_LIST_TERMINAL } +}; + +/* Include the files that instantiate the configuration definitions. */ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ +// This is the delivery package title, "BrazosPI" +// This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + +// This is the release version number of the AGESA component +// This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + diff --git a/src/mainboard/elmex/pcm205400/cmos.layout b/src/mainboard/elmex/pcm205400/cmos.layout new file mode 100644 index 0000000..f47185f --- /dev/null +++ b/src/mainboard/elmex/pcm205400/cmos.layout @@ -0,0 +1,76 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/elmex/pcm205400/devicetree.cb b/src/mainboard/elmex/pcm205400/devicetree.cb new file mode 100644 index 0000000..afab841 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/devicetree.cb @@ -0,0 +1,157 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/agesa/family14/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge PCIe slot + device pci 7.0 off end # PCIE P2P bridge + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge + + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB 10-13 + device pci 16.2 off end # EHCI USB 10-13 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + + #set up SB800 Fan control registers and IMC fan controls + register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common + register "fan0_enabled" = "1" + register "fan1_enabled" = "1" + register "imc_fan_zone0_enabled" = "1" + register "imc_fan_zone1_enabled" = "1" + + register "fan0_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan1_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + + register "imc_zone0_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" + register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone0_temp_offset" = "0x00" # No temp offset + register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + register "imc_zone1_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" + register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone1_temp_offset" = "0x00" # No temp offset + register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + # T56N has a Maximum operating temperature of 90C + # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C + # ZONEX_FANSPEEDS - Fan speeds as a "percentage" + register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" + register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" + register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" + register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" + + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 +# These seem unnecessary + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #domain +end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl new file mode 100644 index 0000000..0cf657f --- /dev/null +++ b/src/mainboard/elmex/pcm205400/dsdt.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + #include "acpi/mainboard.asl" + + #include <cpu/amd/agesa/family14/acpi/cpu.asl> + + #include "acpi/routing.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + Device(PCI0) { + + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/cimx/sb800/acpi/fch.asl> + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + } + } /* End Scope(_SB) */ + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c new file mode 100644 index 0000000..0c53417 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam14.h> + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c new file mode 100644 index 0000000..e0440f2 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -0,0 +1,178 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <device/pci_def.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <southbridge/amd/cimx/cimx_util.h> +#include <arch/acpi.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/amd/mtrr.h> +#include "SBPLATFORM.h" +#include <southbridge/amd/cimx/sb800/pci_devs.h> +#include <northbridge/amd/agesa/family14/pci_devs.h> + +void set_pcie_reset(void); +void set_pcie_dereset(void); + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + * + * The Persimmon PCI INTA/B/C/D pins are connected to + * FCH pins INTE/F/G/H on the schematic so these need + * to be routed as well. + */ +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ + [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + /* IDE, SATA */ + [0x40] = 0x0B,0x0B, + /* GPPInt0 - 3 */ + [0x50] = 0x0A,0x0B,0x0A,0x0B +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22/20 INTA-C */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + /* IDE, SATA */ + [0x40] = 0x11,0x13, + /* GPPInt0 - 3 */ + [0x50] = 0x10,0x11,0x12,0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +/* + * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H + * but because PCI INT_PIN swizzling isnt implemented to match + * the IDSEL (dev 3) of the slot, the table is adjusted for the + * swizzle and INTA is connected to PIRQH so PINA/B/C/D on + * off-chip devices should get mapped to PIRQH/E/F/G. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void) +{ +} + +/** + * TODO + * mainboard specific SB CIMx callback + */ +void set_pcie_dereset(void) +{ +} + + +/********************************************** + * Enable the dedicated functions of the board. + **********************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* enable GPP CLK0 thru CLK1 */ + /* disable GPP CLK2 thru SLT_GFX_CLK */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + write8(misc_mem_clk_cntrl + 0, 0xFF); + write8(misc_mem_clk_cntrl + 1, 0x00); + write8(misc_mem_clk_cntrl + 2, 0x00); + write8(misc_mem_clk_cntrl + 3, 0x00); + write8(misc_mem_clk_cntrl + 4, 0x00); + + /* + * Initialize ASF registers to an arbitrary address because someone + * long ago set things up this way inside the SPD read code. The + * SPD read code has been made generic and moved out of the board + * directory, so the ASF init is being done here. + */ + pm_iowrite(0x29, 0x80); + pm_iowrite(0x28, 0x61); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c new file mode 100644 index 0000000..8e954cd --- /dev/null +++ b/src/mainboard/elmex/pcm205400/mptable.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam14.h> +#include <SBPLATFORM.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <drivers/generic/ioapic/chip.h> +#include <arch/ioapic.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + /* Intialize the MP_Table */ + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ + smp_write_processors(mc); + + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); + + /* IDE */ + PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + + /* on board NIC & Slot PCIE */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + + /* PCI slots */ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0 */ + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + } + + /* PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + /* PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + /* PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + /* PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/elmex/pcm205400/platform_cfg.h b/src/mainboard/elmex/pcm205400/platform_cfg.h new file mode 100644 index 0000000..660be41 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/platform_cfg.h @@ -0,0 +1,254 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + +/** + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M + * + * In SB800, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) +#endif /* BIOS_SIZE */ + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @brief + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CONFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @brief bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x07 + +/** + * @def SATA_CONTROLLER + * @brief INCHIP Sata Controller + */ +#define SATA_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def SATA_MODE + * @brief INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_MODE CONFIG_SB800_SATA_MODE + +/** + * @brief INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @brief INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_IDE_MODE IDE_LEGACY_MODE + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +/* NOTE: inagua have to using internal clock, + * otherwise can not detect sata drive + */ +#define SATA_CLOCK_SOURCE INTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @brief INCHIP HDA controller + */ +#define AZALIA_CONTROLLER AZALIA_AUTO + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#define AZALIA_PIN_CONFIG 1 + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A + +/** + * @def GPP_CONTROLLER + */ +#define GPP_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#define GPP_CFGMODE GPP_CFGMODE_X1111 + +/** + * @def NB_SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define NB_SB_GEN2 TRUE + +/** + * @def SB_GPP_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define SB_GPP_GEN2 TRUE + +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visible always, even port empty + * FALSE - ports invisible if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE + +/** + * @def GEC_CONFIG + * 0 - Enable + * 1 - Disable + */ +#define GEC_CONFIG 0 + +static const CODECENTRY persimmon_codec_alc269[] = +{ + /* NID, PinConfig */ + {0x12, 0x411111F0}, + {0x14, 0x99130110}, + {0x21, 0x0121401F}, + {0x17, 0x411111F0}, + {0x18, 0x01A19820}, + {0x19, 0x411111F0}, + {0x1A, 0x0181302F}, + {0x1B, 0x411111F0}, + {0x1D, 0x40069E05}, + {0x1E, 0x411111F0}, + {0x20, 0x0001FFFF}, + {0xff, 0xffffffff} /* end of table */ +}; + +static const CODECTBLLIST codec_tablelist[] = +{ + {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, + {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} +}; + +/** + * @def AZALIA_OEM_VERB_TABLE + * Mainboard specific codec verb table list + */ +#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) + +/* set up an ACPI preferred power management profile */ +/* from acpi.h + * PM_UNSPECIFIED = 0, + * PM_DESKTOP = 1, + * PM_MOBILE = 2, + * PM_WORKSTATION = 3, + * PM_ENTERPRISE_SERVER = 4, + * PM_SOHO_SERVER = 5, + * PM_APPLIANCE_PC = 6, + * PM_PERFORMANCE_SERVER = 7, + * PM_TABLET = 8 + */ +#define FADT_PM_PROFILE 1 + +#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c new file mode 100644 index 0000000..0aad4f5 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <commonlib/loglevel.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/x86/bist.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81865f/f81865f.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <sb_cimx.h> +#include "SBPLATFORM.h" +#include "cbmem.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> + + +#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + /* + * All cores: allow caching of flash chip code and data + * (there are no cache-as-ram reliability concerns with family 14h) + */ + __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ + __writemsr (0xc0010062, 0); + + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + sb_Poweron_Init(); + + post_code(0x31); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + agesawrapper_amdinitreset(); + + post_code(0x39); + agesawrapper_amdinitearly(); + + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + + post_code(0x42); + agesawrapper_amdinitenv(); + amd_initenv(); + + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); + printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); + + post_code(0x54); /* Should never see this post code. */ +} diff --git a/src/mainboard/elmex/pcm205401/BiosCallOuts.c b/src/mainboard/elmex/pcm205401/BiosCallOuts.c new file mode 100644 index 0000000..9a2a9bb --- /dev/null +++ b/src/mainboard/elmex/pcm205401/BiosCallOuts.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "heapManager.h" +#include "SB800.h" +#include <stdlib.h> + +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/* Call the host environment interface to provide a user hook opportunity. */ +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. + // Make sure the right speed settings are selected. + ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + return AGESA_SUCCESS; +} + +/* PCIE slot reset control */ +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + PCIe_SLOT_RESET_INFO *ResetInfo; + + UINT32 GpioMmioAddr; + UINT32 AcpiMmioAddr; + UINT8 Data8; + UINT16 Data16; + + FcnData = Data; + ResetInfo = ConfigPtr; + // Get SB800 MMIO Base (AcpiMmioAddr) + WriteIo8(0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16=Data8<<8; + WriteIo8(0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16|=Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + Status = AGESA_UNSUPPORTED; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + switch (ResetInfo->ResetId) + { + case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); + Status = AGESA_SUCCESS; + break; + } + break; + } + return Status; +} diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig new file mode 100644 index 0000000..e80e68b --- /dev/null +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -0,0 +1,77 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ELMEX_PCM205401 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_AGESA_FAMILY14 + select NORTHBRIDGE_AMD_AGESA_FAMILY14 + select SOUTHBRIDGE_AMD_CIMX_SB800 + select SUPERIO_FINTEK_F81865F + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select GFXUMA + +config MAINBOARD_DIR + string + default elmex/pcm205401 + +config MAINBOARD_PART_NUMBER + string + default "pcm205401" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 2 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +#config VGA_BIOS_FILE +# string "VGA BIOS path and filename" +# depends on VGA_BIOS +# default "rom/video/OntarioGenericVbios.bin" + +config VGA_BIOS_ID + string + default "1002,9802" + +config SB800_AHCI_ROM + bool + default n + +endif # BOARD_ELMEX_PCM205401 diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name new file mode 100644 index 0000000..f70b215 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ELMEX_PCM205401 + bool "pcm205401" diff --git a/src/mainboard/elmex/pcm205401/Makefile.inc b/src/mainboard/elmex/pcm205401/Makefile.inc new file mode 100644 index 0000000..ba56286 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/Makefile.inc @@ -0,0 +1,29 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ifeq ($(CONFIG_AHCI_BIOS),y) +stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID)) +cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom +pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE)) +pci$(stripped_ahcibios_id).rom-type := optionrom +endif + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/elmex/pcm205401/OemCustomize.c b/src/mainboard/elmex/pcm205401/OemCustomize.c new file mode 100644 index 0000000..825364e --- /dev/null +++ b/src/mainboard/elmex/pcm205401/OemCustomize.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "PlatformGnbPcieComplex.h" + +#include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> +#include <PlatformMemoryConfiguration.h> + +#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE + +/** + * OemCustomizeInitEarly + * + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] *InitEarly + * + * @retval VOID + * + **/ + +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +{ + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + +PCIe_PORT_DESCRIPTOR PortList [] = { + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeLvds, Aux1, Hdp1} + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} + } +}; + +PCIe_COMPLEX_DESCRIPTOR Brazos = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + ASSERT(Status == AGESA_SUCCESS); + + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(Brazos); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(PortList); + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); + memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); + memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); + + + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + PSO_END +}; + +const struct OEM_HOOK OemCustomize = { + .InitEarly = OemInitEarly, +}; diff --git a/src/mainboard/elmex/pcm205401/OptionsIds.h b/src/mainboard/elmex/pcm205401/OptionsIds.h new file mode 100644 index 0000000..2d8381b --- /dev/null +++ b/src/mainboard/elmex/pcm205401/OptionsIds.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..4132c7c --- /dev/null +++ b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/elmex/pcm205401/acpi/gpe.asl b/src/mainboard/elmex/pcm205401/acpi/gpe.asl new file mode 100644 index 0000000..2f22758 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/gpe.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ + +/* Contains the GPEs for USB overcurrent */ +#include "usb_oc.asl" diff --git a/src/mainboard/elmex/pcm205401/acpi/ide.asl b/src/mainboard/elmex/pcm205401/acpi/ide.asl new file mode 100644 index 0000000..59ea078 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/ide.asl @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0, Serialized) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, Serialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF, 0, Serialized) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF, 0, Serialized) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/elmex/pcm205401/acpi/mainboard.asl b/src/mainboard/elmex/pcm205401/acpi/mainboard.asl new file mode 100644 index 0000000..b666a4f --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/mainboard.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Data to be patched by the BIOS during POST */ +/* FIXME the patching is not done yet! */ +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +Scope(\_SB) { + Method(OSFL, 0){ + + if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + + if(CondRefOf(\_OSI)) + { + Store(1, OSVR) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSVR) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSVR) /* Linux */ + } Else { + Store(4, OSVR) /* Gotta be WinCE */ + } + } + Return(OSVR) + } +} + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ diff --git a/src/mainboard/elmex/pcm205401/acpi/routing.asl b/src/mainboard/elmex/pcm205401/acpi/routing.asl new file mode 100644 index 0000000..6f94b45 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/routing.asl @@ -0,0 +1,336 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */ + Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */ + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 19 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + + /* TODO: pcie */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */ + Package(){0x0003FFFF, 0, 0, 0x14 }, + Package(){0x0003FFFF, 1, 0, 0x15 }, + Package(){0x0003FFFF, 2, 0, 0x16 }, + Package(){0x0003FFFF, 3, 0, 0x17 }, + Package(){0x0004FFFF, 0, 0, 0x15 }, + Package(){0x0004FFFF, 1, 0, 0x16 }, + Package(){0x0004FFFF, 2, 0, 0x17 }, + Package(){0x0004FFFF, 3, 0, 0x14 }, + Package(){0x0005FFFF, 0, 0, 0x16 }, + Package(){0x0005FFFF, 1, 0, 0x17 }, + Package(){0x0005FFFF, 2, 0, 0x14 }, + Package(){0x0005FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/elmex/pcm205401/acpi/sata.asl b/src/mainboard/elmex/pcm205401/acpi/sata.asl new file mode 100644 index 0000000..9e0e535 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/sata.asl @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/elmex/pcm205401/acpi/sleep.asl b/src/mainboard/elmex/pcm205401/acpi/sleep.asl new file mode 100644 index 0000000..b3fd07e --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/sleep.asl @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, Local1) + Store(Local1, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/elmex/pcm205401/acpi/superio.asl b/src/mainboard/elmex/pcm205401/acpi/superio.asl new file mode 100644 index 0000000..daf6e91 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/superio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/elmex/pcm205401/acpi/usb_oc.asl b/src/mainboard/elmex/pcm205401/acpi/usb_oc.asl new file mode 100644 index 0000000..6e9c701 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/usb_oc.asl @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/elmex/pcm205401/acpi_tables.c b/src/mainboard/elmex/pcm205401/acpi_tables.c new file mode 100644 index 0000000..9b92c05 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi_tables.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam14.h> + + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/elmex/pcm205401/board_info.txt b/src/mainboard/elmex/pcm205401/board_info.txt new file mode 100644 index 0000000..85cb19a --- /dev/null +++ b/src/mainboard/elmex/pcm205401/board_info.txt @@ -0,0 +1,5 @@ +Board name: DBFT1-00-EVAL-KT (Persimmon) +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/elmex/pcm205401/buildOpts.c b/src/mainboard/elmex/pcm205401/buildOpts.c new file mode 100644 index 0000000..fe4e779 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/buildOpts.c @@ -0,0 +1,297 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + */ + +#include <stdlib.h> +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT TRUE +#define INSTALL_FAMILY_15_SUPPORT FALSE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + +#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE +#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE + + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE TRUE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 + +/* + * Agesa configuration values selection. + * Uncomment and specify the value for the configuration options + * needed by the system. + */ +#include "AGESA.h" + +/* The fixed MTRR values to be set after memory initialization. */ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, + { CPU_LIST_TERMINAL } +}; + +/* Include the files that instantiate the configuration definitions. */ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ +// This is the delivery package title, "BrazosPI" +// This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + +// This is the release version number of the AGESA component +// This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + diff --git a/src/mainboard/elmex/pcm205401/cmos.layout b/src/mainboard/elmex/pcm205401/cmos.layout new file mode 100644 index 0000000..f47185f --- /dev/null +++ b/src/mainboard/elmex/pcm205401/cmos.layout @@ -0,0 +1,76 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/elmex/pcm205401/devicetree.cb b/src/mainboard/elmex/pcm205401/devicetree.cb new file mode 100644 index 0000000..afab841 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/devicetree.cb @@ -0,0 +1,157 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/agesa/family14/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge PCIe slot + device pci 7.0 off end # PCIE P2P bridge + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge + + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB 10-13 + device pci 16.2 off end # EHCI USB 10-13 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + + #set up SB800 Fan control registers and IMC fan controls + register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common + register "fan0_enabled" = "1" + register "fan1_enabled" = "1" + register "imc_fan_zone0_enabled" = "1" + register "imc_fan_zone1_enabled" = "1" + + register "fan0_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan1_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + + register "imc_zone0_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" + register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone0_temp_offset" = "0x00" # No temp offset + register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + register "imc_zone1_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" + register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone1_temp_offset" = "0x00" # No temp offset + register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + # T56N has a Maximum operating temperature of 90C + # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C + # ZONEX_FANSPEEDS - Fan speeds as a "percentage" + register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" + register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" + register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" + register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" + + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 +# These seem unnecessary + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #domain +end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/elmex/pcm205401/dsdt.asl b/src/mainboard/elmex/pcm205401/dsdt.asl new file mode 100644 index 0000000..0cf657f --- /dev/null +++ b/src/mainboard/elmex/pcm205401/dsdt.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + #include "acpi/mainboard.asl" + + #include <cpu/amd/agesa/family14/acpi/cpu.asl> + + #include "acpi/routing.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + Device(PCI0) { + + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/cimx/sb800/acpi/fch.asl> + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + } + } /* End Scope(_SB) */ + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/elmex/pcm205401/irq_tables.c b/src/mainboard/elmex/pcm205401/irq_tables.c new file mode 100644 index 0000000..0c53417 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/irq_tables.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam14.h> + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/elmex/pcm205401/mainboard.c b/src/mainboard/elmex/pcm205401/mainboard.c new file mode 100644 index 0000000..e0440f2 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/mainboard.c @@ -0,0 +1,178 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <device/pci_def.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <southbridge/amd/cimx/cimx_util.h> +#include <arch/acpi.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/amd/mtrr.h> +#include "SBPLATFORM.h" +#include <southbridge/amd/cimx/sb800/pci_devs.h> +#include <northbridge/amd/agesa/family14/pci_devs.h> + +void set_pcie_reset(void); +void set_pcie_dereset(void); + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + * + * The Persimmon PCI INTA/B/C/D pins are connected to + * FCH pins INTE/F/G/H on the schematic so these need + * to be routed as well. + */ +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ + [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + /* IDE, SATA */ + [0x40] = 0x0B,0x0B, + /* GPPInt0 - 3 */ + [0x50] = 0x0A,0x0B,0x0A,0x0B +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22/20 INTA-C */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + /* IDE, SATA */ + [0x40] = 0x11,0x13, + /* GPPInt0 - 3 */ + [0x50] = 0x10,0x11,0x12,0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +/* + * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H + * but because PCI INT_PIN swizzling isnt implemented to match + * the IDSEL (dev 3) of the slot, the table is adjusted for the + * swizzle and INTA is connected to PIRQH so PINA/B/C/D on + * off-chip devices should get mapped to PIRQH/E/F/G. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void) +{ +} + +/** + * TODO + * mainboard specific SB CIMx callback + */ +void set_pcie_dereset(void) +{ +} + + +/********************************************** + * Enable the dedicated functions of the board. + **********************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* enable GPP CLK0 thru CLK1 */ + /* disable GPP CLK2 thru SLT_GFX_CLK */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + write8(misc_mem_clk_cntrl + 0, 0xFF); + write8(misc_mem_clk_cntrl + 1, 0x00); + write8(misc_mem_clk_cntrl + 2, 0x00); + write8(misc_mem_clk_cntrl + 3, 0x00); + write8(misc_mem_clk_cntrl + 4, 0x00); + + /* + * Initialize ASF registers to an arbitrary address because someone + * long ago set things up this way inside the SPD read code. The + * SPD read code has been made generic and moved out of the board + * directory, so the ASF init is being done here. + */ + pm_iowrite(0x29, 0x80); + pm_iowrite(0x28, 0x61); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/elmex/pcm205401/mptable.c b/src/mainboard/elmex/pcm205401/mptable.c new file mode 100644 index 0000000..8e954cd --- /dev/null +++ b/src/mainboard/elmex/pcm205401/mptable.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam14.h> +#include <SBPLATFORM.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <drivers/generic/ioapic/chip.h> +#include <arch/ioapic.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + /* Intialize the MP_Table */ + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ + smp_write_processors(mc); + + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); + + /* IDE */ + PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + + /* on board NIC & Slot PCIE */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + + /* PCI slots */ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0 */ + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + } + + /* PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + /* PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + /* PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + /* PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/elmex/pcm205401/platform_cfg.h b/src/mainboard/elmex/pcm205401/platform_cfg.h new file mode 100644 index 0000000..660be41 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/platform_cfg.h @@ -0,0 +1,254 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + +/** + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M + * + * In SB800, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) +#endif /* BIOS_SIZE */ + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @brief + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CONFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @brief bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x07 + +/** + * @def SATA_CONTROLLER + * @brief INCHIP Sata Controller + */ +#define SATA_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def SATA_MODE + * @brief INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_MODE CONFIG_SB800_SATA_MODE + +/** + * @brief INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @brief INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_IDE_MODE IDE_LEGACY_MODE + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +/* NOTE: inagua have to using internal clock, + * otherwise can not detect sata drive + */ +#define SATA_CLOCK_SOURCE INTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @brief INCHIP HDA controller + */ +#define AZALIA_CONTROLLER AZALIA_AUTO + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#define AZALIA_PIN_CONFIG 1 + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A + +/** + * @def GPP_CONTROLLER + */ +#define GPP_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#define GPP_CFGMODE GPP_CFGMODE_X1111 + +/** + * @def NB_SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define NB_SB_GEN2 TRUE + +/** + * @def SB_GPP_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define SB_GPP_GEN2 TRUE + +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visible always, even port empty + * FALSE - ports invisible if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE + +/** + * @def GEC_CONFIG + * 0 - Enable + * 1 - Disable + */ +#define GEC_CONFIG 0 + +static const CODECENTRY persimmon_codec_alc269[] = +{ + /* NID, PinConfig */ + {0x12, 0x411111F0}, + {0x14, 0x99130110}, + {0x21, 0x0121401F}, + {0x17, 0x411111F0}, + {0x18, 0x01A19820}, + {0x19, 0x411111F0}, + {0x1A, 0x0181302F}, + {0x1B, 0x411111F0}, + {0x1D, 0x40069E05}, + {0x1E, 0x411111F0}, + {0x20, 0x0001FFFF}, + {0xff, 0xffffffff} /* end of table */ +}; + +static const CODECTBLLIST codec_tablelist[] = +{ + {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, + {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} +}; + +/** + * @def AZALIA_OEM_VERB_TABLE + * Mainboard specific codec verb table list + */ +#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) + +/* set up an ACPI preferred power management profile */ +/* from acpi.h + * PM_UNSPECIFIED = 0, + * PM_DESKTOP = 1, + * PM_MOBILE = 2, + * PM_WORKSTATION = 3, + * PM_ENTERPRISE_SERVER = 4, + * PM_SOHO_SERVER = 5, + * PM_APPLIANCE_PC = 6, + * PM_PERFORMANCE_SERVER = 7, + * PM_TABLET = 8 + */ +#define FADT_PM_PROFILE 1 + +#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/elmex/pcm205401/romstage.c b/src/mainboard/elmex/pcm205401/romstage.c new file mode 100644 index 0000000..0aad4f5 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/romstage.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <commonlib/loglevel.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/x86/bist.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81865f/f81865f.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <sb_cimx.h> +#include "SBPLATFORM.h" +#include "cbmem.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> + + +#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + /* + * All cores: allow caching of flash chip code and data + * (there are no cache-as-ram reliability concerns with family 14h) + */ + __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ + __writemsr (0xc0010062, 0); + + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + sb_Poweron_Init(); + + post_code(0x31); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + agesawrapper_amdinitreset(); + + post_code(0x39); + agesawrapper_amdinitearly(); + + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + + post_code(0x42); + agesawrapper_amdinitenv(); + amd_initenv(); + + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); + printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); + + post_code(0x54); /* Should never see this post code. */ +}

1 0

Patch set updated for coreboot: mainboard/elmex: Add new board pcm205401
by Kyösti Mälkki 28 Jul '16

28 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15930 -gerrit commit 994a365d304f5c390cf189c65603096ade838f5c Author: Yuichi Ito <yui.corebt(a)gmail.com> Date: Thu Jul 28 13:34:18 2016 +0900 mainboard/elmex: Add new board pcm205401 Change-Id: I6c7e90db84f13ffbf9e629f2b92649895a466155 Signed-off-by: Yuichi Ito <yui.corebt(a)gmail.com> --- src/mainboard/elmex/pcm205401/BiosCallOuts.c | 34 ++--- src/mainboard/elmex/pcm205401/Kconfig | 7 +- src/mainboard/elmex/pcm205401/OemCustomize.c | 138 ++++++++++++++------- .../elmex/pcm205401/PlatformGnbPcieComplex.h | 110 ++++++++++------ src/mainboard/elmex/pcm205401/SBCimxPcieReset.h | 17 +++ src/mainboard/elmex/pcm205401/buildOpts.c | 67 +++++----- src/mainboard/elmex/pcm205401/devicetree.cb | 6 +- src/mainboard/elmex/pcm205401/irq_tables.c | 3 +- src/mainboard/elmex/pcm205401/mainboard.c | 86 ++++++++----- src/mainboard/elmex/pcm205401/mptable.c | 24 ++-- src/mainboard/elmex/pcm205401/platform_cfg.h | 10 +- src/mainboard/elmex/pcm205401/romstage.c | 13 +- 12 files changed, 321 insertions(+), 194 deletions(-) diff --git a/src/mainboard/elmex/pcm205401/BiosCallOuts.c b/src/mainboard/elmex/pcm205401/BiosCallOuts.c index 9a2a9bb..497ec58 100644 --- a/src/mainboard/elmex/pcm205401/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205401/BiosCallOuts.c @@ -20,11 +20,12 @@ #include "SB800.h" #include <stdlib.h> -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, + UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, + UINTN Data, VOID *ConfigPtr); -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, @@ -37,17 +38,19 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); -/* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +/* Call the host environment interface to provide a user hook opportunity. */ +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, + UINTN Data, VOID *ConfigPtr) { // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. // Make sure the right speed settings are selected. - ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + ((MEM_DATA_STRUCT *)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; } /* PCIE slot reset control */ -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, + UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -63,27 +66,26 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8<<8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); - Data16|=Data8; + Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + switch (ResetInfo->ResetId) { + case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); + Data8 |= BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig index e80e68b..a5f7426 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -61,14 +61,9 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string - default "1002,9802" + default "1002,9804" # FUSION_G_T40R config SB800_AHCI_ROM bool diff --git a/src/mainboard/elmex/pcm205401/OemCustomize.c b/src/mainboard/elmex/pcm205401/OemCustomize.c index 825364e..803dbf6 100644 --- a/src/mainboard/elmex/pcm205401/OemCustomize.c +++ b/src/mainboard/elmex/pcm205401/OemCustomize.c @@ -23,20 +23,20 @@ #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /** - * OemCustomizeInitEarly + * OemCustomizeInitEarly * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity * - * Parameters: - * @param[in] *InitEarly + * Parameters: + * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -45,52 +45,87 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; -PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) +PCIe_PORT_DESCRIPTOR PortList[] = { +// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, + GNB_GPP_PORT4_CHANNEL_TYPE, + 4, + GNB_GPP_PORT4_HOTPLUG_SUPPORT, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) +// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, + GNB_GPP_PORT5_CHANNEL_TYPE, + 5, + GNB_GPP_PORT5_HOTPLUG_SUPPORT, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) +// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, + GNB_GPP_PORT6_CHANNEL_TYPE, + 6, + GNB_GPP_PORT6_HOTPLUG_SUPPORT, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) +// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, + GNB_GPP_PORT7_CHANNEL_TYPE, + 7, + GNB_GPP_PORT7_HOTPLUG_SUPPORT, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_LINK_ASPM, + 0) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) +// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, + GNB_GPP_PORT8_CHANNEL_TYPE, + 8, + GNB_GPP_PORT8_HOTPLUG_SUPPORT, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_LINK_ASPM, + 0) } }; -PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) +PCIe_DDI_DESCRIPTOR DdiList[] = { +// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeLvds, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) +// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeDP, Aux2, Hdp2} } }; @@ -105,50 +140,57 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // GNB PCIe topology Porting // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR, + // PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + + sizeof(PortList) + + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + Status = HeapAllocateBuffer(&AllocHeapParams, &InitEarly->StdHeader); ASSERT(Status == AGESA_SUCCESS); - BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieComplexListPtr = + (PCIe_COMPLEX_DESCRIPTOR *)AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *)AllocHeapParams.BufferPtr; memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->PciePortList = + (PCIe_PORT_DESCRIPTOR *)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->DdiLinkList = + (PCIe_DDI_DESCRIPTOR *)BrazosPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; return AGESA_SUCCESS; } -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- +/*----------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *----------------------------------------------------------------------------- */ /* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. + * Platform Specific Overriding Table allows IBV/OEM to pass in platform + * information to AGESA (e.g. MemClk routing, the number of DIMM slots + * per channel,...). If PlatformSpecificTable is populated, AGESA will + * base its settings on the data from the table. Otherwise, it will use + * its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), PSO_END }; diff --git a/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h index 4132c7c..a713f0d 100644 --- a/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h +++ b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h @@ -21,45 +21,85 @@ #include "amdlib.h" #include <cpu/amd/agesa/s3_resume.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port4 + * GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT4_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT4_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT4_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT4_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 +#define GNB_GPP_PORT4_SPEED_MODE 2 +#define GNB_GPP_PORT4_LINK_ASPM 3 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port5 + * GNB_GPP_PORT5_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT5_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT5_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT5_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT5_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 +#define GNB_GPP_PORT5_SPEED_MODE 2 +#define GNB_GPP_PORT5_LINK_ASPM 3 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port6 + * GNB_GPP_PORT6_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT6_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT6_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT6_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT6_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 +#define GNB_GPP_PORT6_SPEED_MODE 2 +#define GNB_GPP_PORT6_LINK_ASPM 3 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port7 + * GNB_GPP_PORT7_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT7_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT7_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT7_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT7_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 +#define GNB_GPP_PORT7_SPEED_MODE 2 +#define GNB_GPP_PORT7_LINK_ASPM 3 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port8 + * GNB_GPP_PORT8_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT8_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT8_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT8_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT8_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 +#define GNB_GPP_PORT8_SPEED_MODE 2 +#define GNB_GPP_PORT8_LINK_ASPM 3 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/elmex/pcm205401/SBCimxPcieReset.h b/src/mainboard/elmex/pcm205401/SBCimxPcieReset.h new file mode 100644 index 0000000..e6c126a --- /dev/null +++ b/src/mainboard/elmex/pcm205401/SBCimxPcieReset.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 ELMEX Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void set_pcie_reset(void); +void set_pcie_dereset(void); diff --git a/src/mainboard/elmex/pcm205401/buildOpts.c b/src/mainboard/elmex/pcm205401/buildOpts.c index fe4e779..fa4fc0d 100644 --- a/src/mainboard/elmex/pcm205401/buildOpts.c +++ b/src/mainboard/elmex/pcm205401/buildOpts.c @@ -102,8 +102,8 @@ #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 @@ -130,9 +130,9 @@ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST (&OntarioApMtrrSettingsList) +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 //#define BLDCFG_ALLOCATED_BUSNUMS 0x20 @@ -171,12 +171,12 @@ #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //#define BLDCFG_ONLINE_SPARE FALSE //#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE @@ -206,8 +206,7 @@ #include "AGESA.h" /* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, @@ -222,7 +221,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -247,7 +246,8 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * development build from trunk will not be confused for a released version. * The release manager will need to remove the trailing 'X' and update the * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' + * should also be updated/incremented for the next expected version, + * + trailing 'X' ****************************************************************************/ // This is the delivery package title, "BrazosPI" // This string MUST be exactly 8 characters long @@ -255,35 +255,38 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0',\ + '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters + * in which there are no clearly defined defaults to be used in the common + * file. The values below are based on product and BKDG content, please consult + * the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/elmex/pcm205401/devicetree.cb b/src/mainboard/elmex/pcm205401/devicetree.cb index afab841..6269d09 100644 --- a/src/mainboard/elmex/pcm205401/devicetree.cb +++ b/src/mainboard/elmex/pcm205401/devicetree.cb @@ -47,7 +47,8 @@ chip northbridge/amd/agesa/family14/root_complex end end # SM device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 +# HDA is not used on board. + device pci 14.2 off end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/fintek/f81865f device pnp 4e.0 off # Floppy @@ -57,7 +58,8 @@ chip northbridge/amd/agesa/family14/root_complex end device pnp 4e.3 off end # Parallel Port device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard +# Keyboard interface on superI/O is not used. + device pnp 4e.5 off # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 diff --git a/src/mainboard/elmex/pcm205401/irq_tables.c b/src/mainboard/elmex/pcm205401/irq_tables.c index 0c53417..e4746f7 100644 --- a/src/mainboard/elmex/pcm205401/irq_tables.c +++ b/src/mainboard/elmex/pcm205401/irq_tables.c @@ -100,9 +100,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) sum = pirq->checksum - sum; - if (sum != pirq->checksum) { + if (sum != pirq->checksum) pirq->checksum = sum; - } printk(BIOS_INFO, "write_pirq_routing_table done.\n"); diff --git a/src/mainboard/elmex/pcm205401/mainboard.c b/src/mainboard/elmex/pcm205401/mainboard.c index e0440f2..27ee53c 100644 --- a/src/mainboard/elmex/pcm205401/mainboard.c +++ b/src/mainboard/elmex/pcm205401/mainboard.c @@ -29,9 +29,7 @@ #include "SBPLATFORM.h" #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> - -void set_pcie_reset(void); -void set_pcie_dereset(void); +#include "SBCimxPcieReset.h" /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -50,36 +48,36 @@ void set_pcie_dereset(void); */ static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + [0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x08] = 0x00, 0xF0, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ - [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F, /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + [0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, /* IDE, SATA */ - [0x40] = 0x0B,0x0B, + [0x40] = 0x0B, 0x0B, /* GPPInt0 - 3 */ - [0x50] = 0x0A,0x0B,0x0A,0x0B + [0x50] = 0x0A, 0x0B, 0x0A, 0x0B }; static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* USB Devs 18/19/22/20 INTA-C */ - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, /* IDE, SATA */ - [0x40] = 0x11,0x13, + [0x40] = 0x11, 0x13, /* GPPInt0 - 3 */ - [0x50] = 0x10,0x11,0x12,0x13 + [0x50] = 0x10, 0x11, 0x12, 0x13 }; /* @@ -99,30 +97,48 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { * swizzle and INTA is connected to PIRQH so PINA/B/C/D on * off-chip devices should get mapped to PIRQH/E/F/G. */ +/* + * GFX_DEVFN VGA: 01.0 + * NB_PCIE_PORT1_DEVFN NIC: 04.0 + * NB_PCIE_PORT3_DEVFN PCIe bdg: 06.0 + * SATA_DEVFN SATA: 11.0 + * OHCI1_DEVFN OHCI1: 12.0 + * EHCI1_DEVFN EHCI1: 12.2 + * OHCI2_DEVFN OHCI2: 13.0 + * EHCI2_DEVFN EHCI2: 13.2 + * SMBUS_DEVFN SMBUS: 14.0 + * IDE_DEVFN IDE: 14.1 + * HDA_DEVFN HDA: 14.2 + * SB_PCI_PORT_DEVFN PCI bdg: 14.4 + * OHCI4_DEVFN OHCI4: 14.5 + * OHCI3_DEVFN OHCI3: 16.0 + * EHCI3_DEVFN EHCI3: 16.2 + */ static const struct pirq_struct mainboard_pirq_data[] = { /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ - {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ - {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ - {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ - {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC} }, + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC} }, + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G} }, + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, }; /* PIRQ Setup */ static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = sizeof(mainboard_pirq_data) + / sizeof(struct pirq_struct); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } @@ -149,11 +165,13 @@ void set_pcie_dereset(void) **********************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + printk(BIOS_INFO, + "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); /* enable GPP CLK0 thru CLK1 */ /* disable GPP CLK2 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + write8(misc_mem_clk_cntrl + 0, 0xFF); write8(misc_mem_clk_cntrl + 1, 0x00); write8(misc_mem_clk_cntrl + 2, 0x00); diff --git a/src/mainboard/elmex/pcm205401/mptable.c b/src/mainboard/elmex/pcm205401/mptable.c index 8e954cd..04a9ade 100644 --- a/src/mainboard/elmex/pcm205401/mptable.c +++ b/src/mainboard/elmex/pcm205401/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); @@ -76,7 +76,8 @@ static void *smp_write_config_table(void *v) * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ + (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* APU Internal Graphic Device */ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); @@ -110,13 +111,18 @@ static void *smp_write_config_table(void *v) /* PCI slots */ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + //INTA -> INTE + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); + //INTB -> INTF + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); + //INTC -> INTG + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); + //INTD -> INTH + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); } /* PCIe PortA */ @@ -128,9 +134,10 @@ static void *smp_write_config_table(void *v) /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE |\ + MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); @@ -143,6 +150,7 @@ static void *smp_write_config_table(void *v) unsigned long write_smp_table(unsigned long addr) { void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ return (unsigned long)smp_write_config_table(v); } diff --git a/src/mainboard/elmex/pcm205401/platform_cfg.h b/src/mainboard/elmex/pcm205401/platform_cfg.h index 660be41..a7de71b 100644 --- a/src/mainboard/elmex/pcm205401/platform_cfg.h +++ b/src/mainboard/elmex/pcm205401/platform_cfg.h @@ -208,8 +208,7 @@ */ #define GEC_CONFIG 0 -static const CODECENTRY persimmon_codec_alc269[] = -{ +static const CODECENTRY persimmon_codec_alc269[] = { /* NID, PinConfig */ {0x12, 0x411111F0}, {0x14, 0x99130110}, @@ -225,10 +224,9 @@ static const CODECENTRY persimmon_codec_alc269[] = {0xff, 0xffffffff} /* end of table */ }; -static const CODECTBLLIST codec_tablelist[] = -{ - {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, - {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} +static const CODECTBLLIST codec_tablelist[] = { + {0x010ec0269, (CODECENTRY *)&persimmon_codec_alc269[0]}, + {0x0FFFFFFFFUL, (CODECENTRY *)0x0FFFFFFFFUL} }; /** diff --git a/src/mainboard/elmex/pcm205401/romstage.c b/src/mainboard/elmex/pcm205401/romstage.c index 0aad4f5..aef9d04 100644 --- a/src/mainboard/elmex/pcm205401/romstage.c +++ b/src/mainboard/elmex/pcm205401/romstage.c @@ -50,11 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + __writemsr(0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); + __writemsr(0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of + * boot time + */ + __writemsr(0xc0010062, 0); amd_initmmio(); @@ -83,6 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); @@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) agesawrapper_amdinitenv(); amd_initenv(); - } else { /* S3 detect */ + } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60);

1 0

Patch set updated for coreboot: mainboard/elmex: Add new board pcm205400
by Kyösti Mälkki 28 Jul '16

28 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15929 -gerrit commit bbd201d855967ec1b0a5556252d0ca55713e36f0 Author: Yuichi Ito <yui.corebt(a)gmail.com> Date: Thu Jul 28 13:34:18 2016 +0900 mainboard/elmex: Add new board pcm205400 Change-Id: I77cb76903fe3c1b500a306426f5399936382695b Signed-off-by: Yuichi Ito <yui.corebt(a)gmail.com> --- src/mainboard/elmex/pcm205400/BiosCallOuts.c | 34 ++--- src/mainboard/elmex/pcm205400/Kconfig | 7 +- src/mainboard/elmex/pcm205400/OemCustomize.c | 138 ++++++++++++++------- .../elmex/pcm205400/PlatformGnbPcieComplex.h | 110 ++++++++++------ src/mainboard/elmex/pcm205400/SBCimxPcieReset.h | 17 +++ src/mainboard/elmex/pcm205400/buildOpts.c | 67 +++++----- src/mainboard/elmex/pcm205400/devicetree.cb | 6 +- src/mainboard/elmex/pcm205400/irq_tables.c | 3 +- src/mainboard/elmex/pcm205400/mainboard.c | 86 ++++++++----- src/mainboard/elmex/pcm205400/mptable.c | 24 ++-- src/mainboard/elmex/pcm205400/platform_cfg.h | 10 +- src/mainboard/elmex/pcm205400/romstage.c | 13 +- 12 files changed, 321 insertions(+), 194 deletions(-) diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c index 9a2a9bb..9ccab9b 100644 --- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -20,11 +20,12 @@ #include "SB800.h" #include <stdlib.h> -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, + UINTN Data, VOID * ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, + UINTN Data, VOID *ConfigPtr); -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, @@ -37,17 +38,19 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); -/* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +/* Call the host environment interface to provide a user hook opportunity. */ +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, + UINTN Data, VOID *ConfigPtr) { // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. // Make sure the right speed settings are selected. - ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + ((MEM_DATA_STRUCT *)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; } /* PCIE slot reset control */ -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, + UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -63,27 +66,26 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8<<8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); - Data16|=Data8; + Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + switch (ResetInfo->ResetId) { + case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); + Data8 |= BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index e279aea..0aac747 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -61,14 +61,9 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string - default "1002,9802" + default "1002,9806" # FUSION_G_T56N config SB800_AHCI_ROM bool diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c index 825364e..803dbf6 100644 --- a/src/mainboard/elmex/pcm205400/OemCustomize.c +++ b/src/mainboard/elmex/pcm205400/OemCustomize.c @@ -23,20 +23,20 @@ #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /** - * OemCustomizeInitEarly + * OemCustomizeInitEarly * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity * - * Parameters: - * @param[in] *InitEarly + * Parameters: + * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -45,52 +45,87 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; -PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) +PCIe_PORT_DESCRIPTOR PortList[] = { +// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, + GNB_GPP_PORT4_CHANNEL_TYPE, + 4, + GNB_GPP_PORT4_HOTPLUG_SUPPORT, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) +// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, + GNB_GPP_PORT5_CHANNEL_TYPE, + 5, + GNB_GPP_PORT5_HOTPLUG_SUPPORT, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) +// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, + GNB_GPP_PORT6_CHANNEL_TYPE, + 6, + GNB_GPP_PORT6_HOTPLUG_SUPPORT, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) +// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, + GNB_GPP_PORT7_CHANNEL_TYPE, + 7, + GNB_GPP_PORT7_HOTPLUG_SUPPORT, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_LINK_ASPM, + 0) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) +// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, + GNB_GPP_PORT8_CHANNEL_TYPE, + 8, + GNB_GPP_PORT8_HOTPLUG_SUPPORT, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_LINK_ASPM, + 0) } }; -PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) +PCIe_DDI_DESCRIPTOR DdiList[] = { +// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeLvds, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) +// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeDP, Aux2, Hdp2} } }; @@ -105,50 +140,57 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // GNB PCIe topology Porting // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR, + // PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + + sizeof(PortList) + + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + Status = HeapAllocateBuffer(&AllocHeapParams, &InitEarly->StdHeader); ASSERT(Status == AGESA_SUCCESS); - BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieComplexListPtr = + (PCIe_COMPLEX_DESCRIPTOR *)AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *)AllocHeapParams.BufferPtr; memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->PciePortList = + (PCIe_PORT_DESCRIPTOR *)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->DdiLinkList = + (PCIe_DDI_DESCRIPTOR *)BrazosPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; return AGESA_SUCCESS; } -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- +/*----------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *----------------------------------------------------------------------------- */ /* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. + * Platform Specific Overriding Table allows IBV/OEM to pass in platform + * information to AGESA (e.g. MemClk routing, the number of DIMM slots + * per channel,...). If PlatformSpecificTable is populated, AGESA will + * base its settings on the data from the table. Otherwise, it will use + * its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), PSO_END }; diff --git a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h index 4132c7c..a713f0d 100644 --- a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h +++ b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h @@ -21,45 +21,85 @@ #include "amdlib.h" #include <cpu/amd/agesa/s3_resume.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port4 + * GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT4_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT4_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT4_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT4_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 +#define GNB_GPP_PORT4_SPEED_MODE 2 +#define GNB_GPP_PORT4_LINK_ASPM 3 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port5 + * GNB_GPP_PORT5_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT5_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT5_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT5_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT5_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 +#define GNB_GPP_PORT5_SPEED_MODE 2 +#define GNB_GPP_PORT5_LINK_ASPM 3 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port6 + * GNB_GPP_PORT6_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT6_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT6_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT6_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT6_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 +#define GNB_GPP_PORT6_SPEED_MODE 2 +#define GNB_GPP_PORT6_LINK_ASPM 3 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port7 + * GNB_GPP_PORT7_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT7_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT7_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT7_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT7_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 +#define GNB_GPP_PORT7_SPEED_MODE 2 +#define GNB_GPP_PORT7_LINK_ASPM 3 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port8 + * GNB_GPP_PORT8_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT8_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT8_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT8_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT8_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 +#define GNB_GPP_PORT8_SPEED_MODE 2 +#define GNB_GPP_PORT8_LINK_ASPM 3 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/elmex/pcm205400/SBCimxPcieReset.h b/src/mainboard/elmex/pcm205400/SBCimxPcieReset.h new file mode 100644 index 0000000..e6c126a --- /dev/null +++ b/src/mainboard/elmex/pcm205400/SBCimxPcieReset.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 ELMEX Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void set_pcie_reset(void); +void set_pcie_dereset(void); diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index fe4e779..fa4fc0d 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -102,8 +102,8 @@ #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 @@ -130,9 +130,9 @@ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST (&OntarioApMtrrSettingsList) +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 //#define BLDCFG_ALLOCATED_BUSNUMS 0x20 @@ -171,12 +171,12 @@ #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //#define BLDCFG_ONLINE_SPARE FALSE //#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE @@ -206,8 +206,7 @@ #include "AGESA.h" /* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, @@ -222,7 +221,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -247,7 +246,8 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * development build from trunk will not be confused for a released version. * The release manager will need to remove the trailing 'X' and update the * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' + * should also be updated/incremented for the next expected version, + * + trailing 'X' ****************************************************************************/ // This is the delivery package title, "BrazosPI" // This string MUST be exactly 8 characters long @@ -255,35 +255,38 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0',\ + '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters + * in which there are no clearly defined defaults to be used in the common + * file. The values below are based on product and BKDG content, please consult + * the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/elmex/pcm205400/devicetree.cb b/src/mainboard/elmex/pcm205400/devicetree.cb index afab841..6269d09 100644 --- a/src/mainboard/elmex/pcm205400/devicetree.cb +++ b/src/mainboard/elmex/pcm205400/devicetree.cb @@ -47,7 +47,8 @@ chip northbridge/amd/agesa/family14/root_complex end end # SM device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 +# HDA is not used on board. + device pci 14.2 off end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/fintek/f81865f device pnp 4e.0 off # Floppy @@ -57,7 +58,8 @@ chip northbridge/amd/agesa/family14/root_complex end device pnp 4e.3 off end # Parallel Port device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard +# Keyboard interface on superI/O is not used. + device pnp 4e.5 off # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c index 0c53417..e4746f7 100644 --- a/src/mainboard/elmex/pcm205400/irq_tables.c +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -100,9 +100,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) sum = pirq->checksum - sum; - if (sum != pirq->checksum) { + if (sum != pirq->checksum) pirq->checksum = sum; - } printk(BIOS_INFO, "write_pirq_routing_table done.\n"); diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index e0440f2..27ee53c 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -29,9 +29,7 @@ #include "SBPLATFORM.h" #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> - -void set_pcie_reset(void); -void set_pcie_dereset(void); +#include "SBCimxPcieReset.h" /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -50,36 +48,36 @@ void set_pcie_dereset(void); */ static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + [0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x08] = 0x00, 0xF0, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ - [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F, /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + [0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, /* IDE, SATA */ - [0x40] = 0x0B,0x0B, + [0x40] = 0x0B, 0x0B, /* GPPInt0 - 3 */ - [0x50] = 0x0A,0x0B,0x0A,0x0B + [0x50] = 0x0A, 0x0B, 0x0A, 0x0B }; static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* USB Devs 18/19/22/20 INTA-C */ - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, /* IDE, SATA */ - [0x40] = 0x11,0x13, + [0x40] = 0x11, 0x13, /* GPPInt0 - 3 */ - [0x50] = 0x10,0x11,0x12,0x13 + [0x50] = 0x10, 0x11, 0x12, 0x13 }; /* @@ -99,30 +97,48 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { * swizzle and INTA is connected to PIRQH so PINA/B/C/D on * off-chip devices should get mapped to PIRQH/E/F/G. */ +/* + * GFX_DEVFN VGA: 01.0 + * NB_PCIE_PORT1_DEVFN NIC: 04.0 + * NB_PCIE_PORT3_DEVFN PCIe bdg: 06.0 + * SATA_DEVFN SATA: 11.0 + * OHCI1_DEVFN OHCI1: 12.0 + * EHCI1_DEVFN EHCI1: 12.2 + * OHCI2_DEVFN OHCI2: 13.0 + * EHCI2_DEVFN EHCI2: 13.2 + * SMBUS_DEVFN SMBUS: 14.0 + * IDE_DEVFN IDE: 14.1 + * HDA_DEVFN HDA: 14.2 + * SB_PCI_PORT_DEVFN PCI bdg: 14.4 + * OHCI4_DEVFN OHCI4: 14.5 + * OHCI3_DEVFN OHCI3: 16.0 + * EHCI3_DEVFN EHCI3: 16.2 + */ static const struct pirq_struct mainboard_pirq_data[] = { /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ - {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ - {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ - {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ - {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC} }, + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC} }, + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G} }, + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, }; /* PIRQ Setup */ static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = sizeof(mainboard_pirq_data) + / sizeof(struct pirq_struct); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } @@ -149,11 +165,13 @@ void set_pcie_dereset(void) **********************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + printk(BIOS_INFO, + "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); /* enable GPP CLK0 thru CLK1 */ /* disable GPP CLK2 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + write8(misc_mem_clk_cntrl + 0, 0xFF); write8(misc_mem_clk_cntrl + 1, 0x00); write8(misc_mem_clk_cntrl + 2, 0x00); diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c index 8e954cd..04a9ade 100644 --- a/src/mainboard/elmex/pcm205400/mptable.c +++ b/src/mainboard/elmex/pcm205400/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); @@ -76,7 +76,8 @@ static void *smp_write_config_table(void *v) * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ + (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* APU Internal Graphic Device */ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); @@ -110,13 +111,18 @@ static void *smp_write_config_table(void *v) /* PCI slots */ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + //INTA -> INTE + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); + //INTB -> INTF + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); + //INTC -> INTG + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); + //INTD -> INTH + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); } /* PCIe PortA */ @@ -128,9 +134,10 @@ static void *smp_write_config_table(void *v) /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE |\ + MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); @@ -143,6 +150,7 @@ static void *smp_write_config_table(void *v) unsigned long write_smp_table(unsigned long addr) { void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ return (unsigned long)smp_write_config_table(v); } diff --git a/src/mainboard/elmex/pcm205400/platform_cfg.h b/src/mainboard/elmex/pcm205400/platform_cfg.h index 660be41..a7de71b 100644 --- a/src/mainboard/elmex/pcm205400/platform_cfg.h +++ b/src/mainboard/elmex/pcm205400/platform_cfg.h @@ -208,8 +208,7 @@ */ #define GEC_CONFIG 0 -static const CODECENTRY persimmon_codec_alc269[] = -{ +static const CODECENTRY persimmon_codec_alc269[] = { /* NID, PinConfig */ {0x12, 0x411111F0}, {0x14, 0x99130110}, @@ -225,10 +224,9 @@ static const CODECENTRY persimmon_codec_alc269[] = {0xff, 0xffffffff} /* end of table */ }; -static const CODECTBLLIST codec_tablelist[] = -{ - {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, - {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} +static const CODECTBLLIST codec_tablelist[] = { + {0x010ec0269, (CODECENTRY *)&persimmon_codec_alc269[0]}, + {0x0FFFFFFFFUL, (CODECENTRY *)0x0FFFFFFFFUL} }; /** diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index 0aad4f5..aef9d04 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -50,11 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + __writemsr(0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); + __writemsr(0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of + * boot time + */ + __writemsr(0xc0010062, 0); amd_initmmio(); @@ -83,6 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); @@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) agesawrapper_amdinitenv(); amd_initenv(); - } else { /* S3 detect */ + } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60);

1 0

Patch set updated for coreboot: mainboard/elmex: Add new board pcm205401
by Kyösti Mälkki 28 Jul '16

28 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15930 -gerrit commit 4a86255695fbc43873ffb1e47131094e516132fa Author: Yuichi Ito <yui.corebt(a)gmail.com> Date: Thu Jul 28 13:34:18 2016 +0900 mainboard/elmex: Add new board pcm205401 Change-Id: I6c7e90db84f13ffbf9e629f2b92649895a466155 Signed-off-by: Yuichi Ito <yui.corebt(a)gmail.com> --- src/mainboard/elmex/pcm205401/BiosCallOuts.c | 34 ++--- src/mainboard/elmex/pcm205401/Kconfig | 7 +- src/mainboard/elmex/pcm205401/OemCustomize.c | 138 ++++++++++++++------- .../elmex/pcm205401/PlatformGnbPcieComplex.h | 110 ++++++++++------ src/mainboard/elmex/pcm205401/SBCimxPcieReset.h | 17 +++ src/mainboard/elmex/pcm205401/buildOpts.c | 67 +++++----- src/mainboard/elmex/pcm205401/devicetree.cb | 6 +- src/mainboard/elmex/pcm205401/irq_tables.c | 3 +- src/mainboard/elmex/pcm205401/mainboard.c | 86 ++++++++----- src/mainboard/elmex/pcm205401/mptable.c | 24 ++-- src/mainboard/elmex/pcm205401/platform_cfg.h | 10 +- src/mainboard/elmex/pcm205401/romstage.c | 13 +- 12 files changed, 321 insertions(+), 194 deletions(-) diff --git a/src/mainboard/elmex/pcm205401/BiosCallOuts.c b/src/mainboard/elmex/pcm205401/BiosCallOuts.c index 9a2a9bb..497ec58 100644 --- a/src/mainboard/elmex/pcm205401/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205401/BiosCallOuts.c @@ -20,11 +20,12 @@ #include "SB800.h" #include <stdlib.h> -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, + UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, + UINTN Data, VOID *ConfigPtr); -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, @@ -37,17 +38,19 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); -/* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +/* Call the host environment interface to provide a user hook opportunity. */ +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, + UINTN Data, VOID *ConfigPtr) { // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. // Make sure the right speed settings are selected. - ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + ((MEM_DATA_STRUCT *)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; } /* PCIE slot reset control */ -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, + UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -63,27 +66,26 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8<<8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); - Data16|=Data8; + Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + switch (ResetInfo->ResetId) { + case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); + Data8 |= BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig index e80e68b..a5f7426 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -61,14 +61,9 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string - default "1002,9802" + default "1002,9804" # FUSION_G_T40R config SB800_AHCI_ROM bool diff --git a/src/mainboard/elmex/pcm205401/OemCustomize.c b/src/mainboard/elmex/pcm205401/OemCustomize.c index 825364e..803dbf6 100644 --- a/src/mainboard/elmex/pcm205401/OemCustomize.c +++ b/src/mainboard/elmex/pcm205401/OemCustomize.c @@ -23,20 +23,20 @@ #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /** - * OemCustomizeInitEarly + * OemCustomizeInitEarly * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity * - * Parameters: - * @param[in] *InitEarly + * Parameters: + * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -45,52 +45,87 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; -PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) +PCIe_PORT_DESCRIPTOR PortList[] = { +// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, + GNB_GPP_PORT4_CHANNEL_TYPE, + 4, + GNB_GPP_PORT4_HOTPLUG_SUPPORT, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) +// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, + GNB_GPP_PORT5_CHANNEL_TYPE, + 5, + GNB_GPP_PORT5_HOTPLUG_SUPPORT, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) +// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, + GNB_GPP_PORT6_CHANNEL_TYPE, + 6, + GNB_GPP_PORT6_HOTPLUG_SUPPORT, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) +// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, + GNB_GPP_PORT7_CHANNEL_TYPE, + 7, + GNB_GPP_PORT7_HOTPLUG_SUPPORT, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_LINK_ASPM, + 0) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) +// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, + GNB_GPP_PORT8_CHANNEL_TYPE, + 8, + GNB_GPP_PORT8_HOTPLUG_SUPPORT, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_LINK_ASPM, + 0) } }; -PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) +PCIe_DDI_DESCRIPTOR DdiList[] = { +// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeLvds, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) +// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeDP, Aux2, Hdp2} } }; @@ -105,50 +140,57 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // GNB PCIe topology Porting // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR, + // PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + + sizeof(PortList) + + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + Status = HeapAllocateBuffer(&AllocHeapParams, &InitEarly->StdHeader); ASSERT(Status == AGESA_SUCCESS); - BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieComplexListPtr = + (PCIe_COMPLEX_DESCRIPTOR *)AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *)AllocHeapParams.BufferPtr; memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->PciePortList = + (PCIe_PORT_DESCRIPTOR *)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->DdiLinkList = + (PCIe_DDI_DESCRIPTOR *)BrazosPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; return AGESA_SUCCESS; } -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- +/*----------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *----------------------------------------------------------------------------- */ /* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. + * Platform Specific Overriding Table allows IBV/OEM to pass in platform + * information to AGESA (e.g. MemClk routing, the number of DIMM slots + * per channel,...). If PlatformSpecificTable is populated, AGESA will + * base its settings on the data from the table. Otherwise, it will use + * its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), PSO_END }; diff --git a/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h index 4132c7c..a713f0d 100644 --- a/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h +++ b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h @@ -21,45 +21,85 @@ #include "amdlib.h" #include <cpu/amd/agesa/s3_resume.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port4 + * GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT4_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT4_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT4_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT4_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 +#define GNB_GPP_PORT4_SPEED_MODE 2 +#define GNB_GPP_PORT4_LINK_ASPM 3 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port5 + * GNB_GPP_PORT5_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT5_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT5_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT5_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT5_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 +#define GNB_GPP_PORT5_SPEED_MODE 2 +#define GNB_GPP_PORT5_LINK_ASPM 3 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port6 + * GNB_GPP_PORT6_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT6_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT6_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT6_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT6_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 +#define GNB_GPP_PORT6_SPEED_MODE 2 +#define GNB_GPP_PORT6_LINK_ASPM 3 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port7 + * GNB_GPP_PORT7_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT7_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT7_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT7_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT7_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 +#define GNB_GPP_PORT7_SPEED_MODE 2 +#define GNB_GPP_PORT7_LINK_ASPM 3 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port8 + * GNB_GPP_PORT8_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT8_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT8_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT8_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT8_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 +#define GNB_GPP_PORT8_SPEED_MODE 2 +#define GNB_GPP_PORT8_LINK_ASPM 3 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/elmex/pcm205401/SBCimxPcieReset.h b/src/mainboard/elmex/pcm205401/SBCimxPcieReset.h new file mode 100644 index 0000000..e6c126a --- /dev/null +++ b/src/mainboard/elmex/pcm205401/SBCimxPcieReset.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 ELMEX Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void set_pcie_reset(void); +void set_pcie_dereset(void); diff --git a/src/mainboard/elmex/pcm205401/buildOpts.c b/src/mainboard/elmex/pcm205401/buildOpts.c index fe4e779..fa4fc0d 100644 --- a/src/mainboard/elmex/pcm205401/buildOpts.c +++ b/src/mainboard/elmex/pcm205401/buildOpts.c @@ -102,8 +102,8 @@ #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 @@ -130,9 +130,9 @@ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST (&OntarioApMtrrSettingsList) +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 //#define BLDCFG_ALLOCATED_BUSNUMS 0x20 @@ -171,12 +171,12 @@ #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //#define BLDCFG_ONLINE_SPARE FALSE //#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE @@ -206,8 +206,7 @@ #include "AGESA.h" /* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, @@ -222,7 +221,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -247,7 +246,8 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * development build from trunk will not be confused for a released version. * The release manager will need to remove the trailing 'X' and update the * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' + * should also be updated/incremented for the next expected version, + * + trailing 'X' ****************************************************************************/ // This is the delivery package title, "BrazosPI" // This string MUST be exactly 8 characters long @@ -255,35 +255,38 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0',\ + '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters + * in which there are no clearly defined defaults to be used in the common + * file. The values below are based on product and BKDG content, please consult + * the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/elmex/pcm205401/devicetree.cb b/src/mainboard/elmex/pcm205401/devicetree.cb index afab841..6269d09 100644 --- a/src/mainboard/elmex/pcm205401/devicetree.cb +++ b/src/mainboard/elmex/pcm205401/devicetree.cb @@ -47,7 +47,8 @@ chip northbridge/amd/agesa/family14/root_complex end end # SM device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 +# HDA is not used on board. + device pci 14.2 off end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/fintek/f81865f device pnp 4e.0 off # Floppy @@ -57,7 +58,8 @@ chip northbridge/amd/agesa/family14/root_complex end device pnp 4e.3 off end # Parallel Port device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard +# Keyboard interface on superI/O is not used. + device pnp 4e.5 off # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 diff --git a/src/mainboard/elmex/pcm205401/irq_tables.c b/src/mainboard/elmex/pcm205401/irq_tables.c index 0c53417..e4746f7 100644 --- a/src/mainboard/elmex/pcm205401/irq_tables.c +++ b/src/mainboard/elmex/pcm205401/irq_tables.c @@ -100,9 +100,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) sum = pirq->checksum - sum; - if (sum != pirq->checksum) { + if (sum != pirq->checksum) pirq->checksum = sum; - } printk(BIOS_INFO, "write_pirq_routing_table done.\n"); diff --git a/src/mainboard/elmex/pcm205401/mainboard.c b/src/mainboard/elmex/pcm205401/mainboard.c index e0440f2..27ee53c 100644 --- a/src/mainboard/elmex/pcm205401/mainboard.c +++ b/src/mainboard/elmex/pcm205401/mainboard.c @@ -29,9 +29,7 @@ #include "SBPLATFORM.h" #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> - -void set_pcie_reset(void); -void set_pcie_dereset(void); +#include "SBCimxPcieReset.h" /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -50,36 +48,36 @@ void set_pcie_dereset(void); */ static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + [0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x08] = 0x00, 0xF0, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ - [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F, /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + [0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, /* IDE, SATA */ - [0x40] = 0x0B,0x0B, + [0x40] = 0x0B, 0x0B, /* GPPInt0 - 3 */ - [0x50] = 0x0A,0x0B,0x0A,0x0B + [0x50] = 0x0A, 0x0B, 0x0A, 0x0B }; static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* USB Devs 18/19/22/20 INTA-C */ - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, /* IDE, SATA */ - [0x40] = 0x11,0x13, + [0x40] = 0x11, 0x13, /* GPPInt0 - 3 */ - [0x50] = 0x10,0x11,0x12,0x13 + [0x50] = 0x10, 0x11, 0x12, 0x13 }; /* @@ -99,30 +97,48 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { * swizzle and INTA is connected to PIRQH so PINA/B/C/D on * off-chip devices should get mapped to PIRQH/E/F/G. */ +/* + * GFX_DEVFN VGA: 01.0 + * NB_PCIE_PORT1_DEVFN NIC: 04.0 + * NB_PCIE_PORT3_DEVFN PCIe bdg: 06.0 + * SATA_DEVFN SATA: 11.0 + * OHCI1_DEVFN OHCI1: 12.0 + * EHCI1_DEVFN EHCI1: 12.2 + * OHCI2_DEVFN OHCI2: 13.0 + * EHCI2_DEVFN EHCI2: 13.2 + * SMBUS_DEVFN SMBUS: 14.0 + * IDE_DEVFN IDE: 14.1 + * HDA_DEVFN HDA: 14.2 + * SB_PCI_PORT_DEVFN PCI bdg: 14.4 + * OHCI4_DEVFN OHCI4: 14.5 + * OHCI3_DEVFN OHCI3: 16.0 + * EHCI3_DEVFN EHCI3: 16.2 + */ static const struct pirq_struct mainboard_pirq_data[] = { /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ - {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ - {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ - {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ - {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC} }, + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC} }, + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G} }, + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, }; /* PIRQ Setup */ static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = sizeof(mainboard_pirq_data) + / sizeof(struct pirq_struct); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } @@ -149,11 +165,13 @@ void set_pcie_dereset(void) **********************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + printk(BIOS_INFO, + "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); /* enable GPP CLK0 thru CLK1 */ /* disable GPP CLK2 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + write8(misc_mem_clk_cntrl + 0, 0xFF); write8(misc_mem_clk_cntrl + 1, 0x00); write8(misc_mem_clk_cntrl + 2, 0x00); diff --git a/src/mainboard/elmex/pcm205401/mptable.c b/src/mainboard/elmex/pcm205401/mptable.c index 8e954cd..04a9ade 100644 --- a/src/mainboard/elmex/pcm205401/mptable.c +++ b/src/mainboard/elmex/pcm205401/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); @@ -76,7 +76,8 @@ static void *smp_write_config_table(void *v) * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ + (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* APU Internal Graphic Device */ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); @@ -110,13 +111,18 @@ static void *smp_write_config_table(void *v) /* PCI slots */ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + //INTA -> INTE + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); + //INTB -> INTF + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); + //INTC -> INTG + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); + //INTD -> INTH + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); } /* PCIe PortA */ @@ -128,9 +134,10 @@ static void *smp_write_config_table(void *v) /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE |\ + MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); @@ -143,6 +150,7 @@ static void *smp_write_config_table(void *v) unsigned long write_smp_table(unsigned long addr) { void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ return (unsigned long)smp_write_config_table(v); } diff --git a/src/mainboard/elmex/pcm205401/platform_cfg.h b/src/mainboard/elmex/pcm205401/platform_cfg.h index 660be41..a7de71b 100644 --- a/src/mainboard/elmex/pcm205401/platform_cfg.h +++ b/src/mainboard/elmex/pcm205401/platform_cfg.h @@ -208,8 +208,7 @@ */ #define GEC_CONFIG 0 -static const CODECENTRY persimmon_codec_alc269[] = -{ +static const CODECENTRY persimmon_codec_alc269[] = { /* NID, PinConfig */ {0x12, 0x411111F0}, {0x14, 0x99130110}, @@ -225,10 +224,9 @@ static const CODECENTRY persimmon_codec_alc269[] = {0xff, 0xffffffff} /* end of table */ }; -static const CODECTBLLIST codec_tablelist[] = -{ - {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, - {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} +static const CODECTBLLIST codec_tablelist[] = { + {0x010ec0269, (CODECENTRY *)&persimmon_codec_alc269[0]}, + {0x0FFFFFFFFUL, (CODECENTRY *)0x0FFFFFFFFUL} }; /** diff --git a/src/mainboard/elmex/pcm205401/romstage.c b/src/mainboard/elmex/pcm205401/romstage.c index 0aad4f5..aef9d04 100644 --- a/src/mainboard/elmex/pcm205401/romstage.c +++ b/src/mainboard/elmex/pcm205401/romstage.c @@ -50,11 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + __writemsr(0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); + __writemsr(0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of + * boot time + */ + __writemsr(0xc0010062, 0); amd_initmmio(); @@ -83,6 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); @@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) agesawrapper_amdinitenv(); amd_initenv(); - } else { /* S3 detect */ + } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60);

1 0

Patch set updated for coreboot: mainboard/elmex: Add new board pcm205400
by Kyösti Mälkki 28 Jul '16

28 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15929 -gerrit commit a2cebe9f507184436f885d0ce0a1e8cffeac024b Author: Yuichi Ito <yui.corebt(a)gmail.com> Date: Thu Jul 28 13:34:18 2016 +0900 mainboard/elmex: Add new board pcm205400 Change-Id: I77cb76903fe3c1b500a306426f5399936382695b Signed-off-by: Yuichi Ito <yui.corebt(a)gmail.com> --- src/mainboard/elmex/pcm205400/BiosCallOuts.c | 34 ++--- src/mainboard/elmex/pcm205400/Kconfig | 7 +- src/mainboard/elmex/pcm205400/OemCustomize.c | 138 ++++++++++++++------- .../elmex/pcm205400/PlatformGnbPcieComplex.h | 110 ++++++++++------ src/mainboard/elmex/pcm205400/SBCimxPcieReset.h | 17 +++ src/mainboard/elmex/pcm205400/buildOpts.c | 67 +++++----- src/mainboard/elmex/pcm205400/devicetree.cb | 6 +- src/mainboard/elmex/pcm205400/irq_tables.c | 3 +- src/mainboard/elmex/pcm205400/mainboard.c | 86 ++++++++----- src/mainboard/elmex/pcm205400/mptable.c | 24 ++-- src/mainboard/elmex/pcm205400/platform_cfg.h | 10 +- src/mainboard/elmex/pcm205400/romstage.c | 13 +- 12 files changed, 321 insertions(+), 194 deletions(-) diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c index 9a2a9bb..9ccab9b 100644 --- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -20,11 +20,12 @@ #include "SB800.h" #include <stdlib.h> -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, + UINTN Data, VOID * ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, + UINTN Data, VOID *ConfigPtr); -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, @@ -37,17 +38,19 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); -/* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +/* Call the host environment interface to provide a user hook opportunity. */ +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, + UINTN Data, VOID *ConfigPtr) { // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. // Make sure the right speed settings are selected. - ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + ((MEM_DATA_STRUCT *)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; } /* PCIE slot reset control */ -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, + UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -63,27 +66,26 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8<<8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); - Data16|=Data8; + Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + switch (ResetInfo->ResetId) { + case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); + Data8 |= BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index e279aea..0aac747 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -61,14 +61,9 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string - default "1002,9802" + default "1002,9806" # FUSION_G_T56N config SB800_AHCI_ROM bool diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c index 825364e..803dbf6 100644 --- a/src/mainboard/elmex/pcm205400/OemCustomize.c +++ b/src/mainboard/elmex/pcm205400/OemCustomize.c @@ -23,20 +23,20 @@ #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /** - * OemCustomizeInitEarly + * OemCustomizeInitEarly * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity * - * Parameters: - * @param[in] *InitEarly + * Parameters: + * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -45,52 +45,87 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; -PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) +PCIe_PORT_DESCRIPTOR PortList[] = { +// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, + GNB_GPP_PORT4_CHANNEL_TYPE, + 4, + GNB_GPP_PORT4_HOTPLUG_SUPPORT, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) +// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, + GNB_GPP_PORT5_CHANNEL_TYPE, + 5, + GNB_GPP_PORT5_HOTPLUG_SUPPORT, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) +// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, + GNB_GPP_PORT6_CHANNEL_TYPE, + 6, + GNB_GPP_PORT6_HOTPLUG_SUPPORT, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) +// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, + GNB_GPP_PORT7_CHANNEL_TYPE, + 7, + GNB_GPP_PORT7_HOTPLUG_SUPPORT, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_LINK_ASPM, + 0) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) +// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, + GNB_GPP_PORT8_CHANNEL_TYPE, + 8, + GNB_GPP_PORT8_HOTPLUG_SUPPORT, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_LINK_ASPM, + 0) } }; -PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) +PCIe_DDI_DESCRIPTOR DdiList[] = { +// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeLvds, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) +// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeDP, Aux2, Hdp2} } }; @@ -105,50 +140,57 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // GNB PCIe topology Porting // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR, + // PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + + sizeof(PortList) + + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + Status = HeapAllocateBuffer(&AllocHeapParams, &InitEarly->StdHeader); ASSERT(Status == AGESA_SUCCESS); - BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieComplexListPtr = + (PCIe_COMPLEX_DESCRIPTOR *)AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *)AllocHeapParams.BufferPtr; memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->PciePortList = + (PCIe_PORT_DESCRIPTOR *)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->DdiLinkList = + (PCIe_DDI_DESCRIPTOR *)BrazosPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; return AGESA_SUCCESS; } -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- +/*----------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *----------------------------------------------------------------------------- */ /* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. + * Platform Specific Overriding Table allows IBV/OEM to pass in platform + * information to AGESA (e.g. MemClk routing, the number of DIMM slots + * per channel,...). If PlatformSpecificTable is populated, AGESA will + * base its settings on the data from the table. Otherwise, it will use + * its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), PSO_END }; diff --git a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h index 4132c7c..a713f0d 100644 --- a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h +++ b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h @@ -21,45 +21,85 @@ #include "amdlib.h" #include <cpu/amd/agesa/s3_resume.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port4 + * GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT4_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT4_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT4_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT4_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 +#define GNB_GPP_PORT4_SPEED_MODE 2 +#define GNB_GPP_PORT4_LINK_ASPM 3 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port5 + * GNB_GPP_PORT5_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT5_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT5_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT5_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT5_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 +#define GNB_GPP_PORT5_SPEED_MODE 2 +#define GNB_GPP_PORT5_LINK_ASPM 3 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port6 + * GNB_GPP_PORT6_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT6_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT6_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT6_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT6_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 +#define GNB_GPP_PORT6_SPEED_MODE 2 +#define GNB_GPP_PORT6_LINK_ASPM 3 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port7 + * GNB_GPP_PORT7_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT7_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT7_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT7_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT7_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 +#define GNB_GPP_PORT7_SPEED_MODE 2 +#define GNB_GPP_PORT7_LINK_ASPM 3 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port8 + * GNB_GPP_PORT8_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT8_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT8_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT8_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT8_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 +#define GNB_GPP_PORT8_SPEED_MODE 2 +#define GNB_GPP_PORT8_LINK_ASPM 3 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/elmex/pcm205400/SBCimxPcieReset.h b/src/mainboard/elmex/pcm205400/SBCimxPcieReset.h new file mode 100644 index 0000000..e6c126a --- /dev/null +++ b/src/mainboard/elmex/pcm205400/SBCimxPcieReset.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 ELMEX Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void set_pcie_reset(void); +void set_pcie_dereset(void); diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index fe4e779..fa4fc0d 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -102,8 +102,8 @@ #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 @@ -130,9 +130,9 @@ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST (&OntarioApMtrrSettingsList) +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 //#define BLDCFG_ALLOCATED_BUSNUMS 0x20 @@ -171,12 +171,12 @@ #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //#define BLDCFG_ONLINE_SPARE FALSE //#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE @@ -206,8 +206,7 @@ #include "AGESA.h" /* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, @@ -222,7 +221,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -247,7 +246,8 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * development build from trunk will not be confused for a released version. * The release manager will need to remove the trailing 'X' and update the * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' + * should also be updated/incremented for the next expected version, + * + trailing 'X' ****************************************************************************/ // This is the delivery package title, "BrazosPI" // This string MUST be exactly 8 characters long @@ -255,35 +255,38 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0',\ + '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters + * in which there are no clearly defined defaults to be used in the common + * file. The values below are based on product and BKDG content, please consult + * the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/elmex/pcm205400/devicetree.cb b/src/mainboard/elmex/pcm205400/devicetree.cb index afab841..6269d09 100644 --- a/src/mainboard/elmex/pcm205400/devicetree.cb +++ b/src/mainboard/elmex/pcm205400/devicetree.cb @@ -47,7 +47,8 @@ chip northbridge/amd/agesa/family14/root_complex end end # SM device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 +# HDA is not used on board. + device pci 14.2 off end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/fintek/f81865f device pnp 4e.0 off # Floppy @@ -57,7 +58,8 @@ chip northbridge/amd/agesa/family14/root_complex end device pnp 4e.3 off end # Parallel Port device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard +# Keyboard interface on superI/O is not used. + device pnp 4e.5 off # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c index 0c53417..e4746f7 100644 --- a/src/mainboard/elmex/pcm205400/irq_tables.c +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -100,9 +100,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) sum = pirq->checksum - sum; - if (sum != pirq->checksum) { + if (sum != pirq->checksum) pirq->checksum = sum; - } printk(BIOS_INFO, "write_pirq_routing_table done.\n"); diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index e0440f2..27ee53c 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -29,9 +29,7 @@ #include "SBPLATFORM.h" #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> - -void set_pcie_reset(void); -void set_pcie_dereset(void); +#include "SBCimxPcieReset.h" /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -50,36 +48,36 @@ void set_pcie_dereset(void); */ static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + [0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x08] = 0x00, 0xF0, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ - [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F, /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + [0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, /* IDE, SATA */ - [0x40] = 0x0B,0x0B, + [0x40] = 0x0B, 0x0B, /* GPPInt0 - 3 */ - [0x50] = 0x0A,0x0B,0x0A,0x0B + [0x50] = 0x0A, 0x0B, 0x0A, 0x0B }; static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* USB Devs 18/19/22/20 INTA-C */ - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, /* IDE, SATA */ - [0x40] = 0x11,0x13, + [0x40] = 0x11, 0x13, /* GPPInt0 - 3 */ - [0x50] = 0x10,0x11,0x12,0x13 + [0x50] = 0x10, 0x11, 0x12, 0x13 }; /* @@ -99,30 +97,48 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { * swizzle and INTA is connected to PIRQH so PINA/B/C/D on * off-chip devices should get mapped to PIRQH/E/F/G. */ +/* + * GFX_DEVFN VGA: 01.0 + * NB_PCIE_PORT1_DEVFN NIC: 04.0 + * NB_PCIE_PORT3_DEVFN PCIe bdg: 06.0 + * SATA_DEVFN SATA: 11.0 + * OHCI1_DEVFN OHCI1: 12.0 + * EHCI1_DEVFN EHCI1: 12.2 + * OHCI2_DEVFN OHCI2: 13.0 + * EHCI2_DEVFN EHCI2: 13.2 + * SMBUS_DEVFN SMBUS: 14.0 + * IDE_DEVFN IDE: 14.1 + * HDA_DEVFN HDA: 14.2 + * SB_PCI_PORT_DEVFN PCI bdg: 14.4 + * OHCI4_DEVFN OHCI4: 14.5 + * OHCI3_DEVFN OHCI3: 16.0 + * EHCI3_DEVFN EHCI3: 16.2 + */ static const struct pirq_struct mainboard_pirq_data[] = { /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ - {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ - {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ - {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ - {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC} }, + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC} }, + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G} }, + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, }; /* PIRQ Setup */ static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = sizeof(mainboard_pirq_data) + / sizeof(struct pirq_struct); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } @@ -149,11 +165,13 @@ void set_pcie_dereset(void) **********************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + printk(BIOS_INFO, + "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); /* enable GPP CLK0 thru CLK1 */ /* disable GPP CLK2 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + write8(misc_mem_clk_cntrl + 0, 0xFF); write8(misc_mem_clk_cntrl + 1, 0x00); write8(misc_mem_clk_cntrl + 2, 0x00); diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c index 8e954cd..04a9ade 100644 --- a/src/mainboard/elmex/pcm205400/mptable.c +++ b/src/mainboard/elmex/pcm205400/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); @@ -76,7 +76,8 @@ static void *smp_write_config_table(void *v) * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ + (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* APU Internal Graphic Device */ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); @@ -110,13 +111,18 @@ static void *smp_write_config_table(void *v) /* PCI slots */ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + //INTA -> INTE + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); + //INTB -> INTF + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); + //INTC -> INTG + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); + //INTD -> INTH + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); } /* PCIe PortA */ @@ -128,9 +134,10 @@ static void *smp_write_config_table(void *v) /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE |\ + MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); @@ -143,6 +150,7 @@ static void *smp_write_config_table(void *v) unsigned long write_smp_table(unsigned long addr) { void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ return (unsigned long)smp_write_config_table(v); } diff --git a/src/mainboard/elmex/pcm205400/platform_cfg.h b/src/mainboard/elmex/pcm205400/platform_cfg.h index 660be41..a7de71b 100644 --- a/src/mainboard/elmex/pcm205400/platform_cfg.h +++ b/src/mainboard/elmex/pcm205400/platform_cfg.h @@ -208,8 +208,7 @@ */ #define GEC_CONFIG 0 -static const CODECENTRY persimmon_codec_alc269[] = -{ +static const CODECENTRY persimmon_codec_alc269[] = { /* NID, PinConfig */ {0x12, 0x411111F0}, {0x14, 0x99130110}, @@ -225,10 +224,9 @@ static const CODECENTRY persimmon_codec_alc269[] = {0xff, 0xffffffff} /* end of table */ }; -static const CODECTBLLIST codec_tablelist[] = -{ - {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, - {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} +static const CODECTBLLIST codec_tablelist[] = { + {0x010ec0269, (CODECENTRY *)&persimmon_codec_alc269[0]}, + {0x0FFFFFFFFUL, (CODECENTRY *)0x0FFFFFFFFUL} }; /** diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index 0aad4f5..aef9d04 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -50,11 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + __writemsr(0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); + __writemsr(0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of + * boot time + */ + __writemsr(0xc0010062, 0); amd_initmmio(); @@ -83,6 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); @@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) agesawrapper_amdinitenv(); amd_initenv(); - } else { /* S3 detect */ + } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60);

1 0

Patch set updated for coreboot: src/mainboard: Add vendor ELMEX with two board templates
by Kyösti Mälkki 28 Jul '16

28 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15928 -gerrit commit afb1d35fc600a16bf45b6e7f3300387c865e50c0 Author: Yuichi Ito <yui.corebt(a)gmail.com> Date: Thu Jul 28 13:34:18 2016 +0900 src/mainboard: Add vendor ELMEX with two board templates Both added boards used amd/persimmon as template. Change-Id: I263b54e0f49b6f1ba730c7f87de41f990ba8fe67 Signed-off-by: Yuichi Ito <yui.corebt(a)gmail.com> Change-Id: Ic172fc57ad0aa2b6a9be3f493664127a37861468 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/elmex/Kconfig | 16 + src/mainboard/elmex/Kconfig.name | 2 + src/mainboard/elmex/pcm205400/BiosCallOuts.c | 93 ++++++ src/mainboard/elmex/pcm205400/Kconfig | 77 +++++ src/mainboard/elmex/pcm205400/Kconfig.name | 2 + src/mainboard/elmex/pcm205400/Makefile.inc | 29 ++ src/mainboard/elmex/pcm205400/OemCustomize.c | 157 ++++++++++ src/mainboard/elmex/pcm205400/OptionsIds.h | 56 ++++ .../elmex/pcm205400/PlatformGnbPcieComplex.h | 65 ++++ src/mainboard/elmex/pcm205400/acpi/gpe.asl | 78 +++++ src/mainboard/elmex/pcm205400/acpi/ide.asl | 240 +++++++++++++++ src/mainboard/elmex/pcm205400/acpi/mainboard.asl | 63 ++++ src/mainboard/elmex/pcm205400/acpi/routing.asl | 336 +++++++++++++++++++++ src/mainboard/elmex/pcm205400/acpi/sata.asl | 145 +++++++++ src/mainboard/elmex/pcm205400/acpi/sleep.asl | 117 +++++++ src/mainboard/elmex/pcm205400/acpi/superio.asl | 14 + src/mainboard/elmex/pcm205400/acpi/usb_oc.asl | 170 +++++++++++ src/mainboard/elmex/pcm205400/acpi_tables.c | 53 ++++ src/mainboard/elmex/pcm205400/board_info.txt | 5 + src/mainboard/elmex/pcm205400/buildOpts.c | 297 ++++++++++++++++++ src/mainboard/elmex/pcm205400/cmos.layout | 76 +++++ src/mainboard/elmex/pcm205400/devicetree.cb | 157 ++++++++++ src/mainboard/elmex/pcm205400/dsdt.asl | 63 ++++ src/mainboard/elmex/pcm205400/irq_tables.c | 111 +++++++ src/mainboard/elmex/pcm205400/mainboard.c | 178 +++++++++++ src/mainboard/elmex/pcm205400/mptable.c | 148 +++++++++ src/mainboard/elmex/pcm205400/platform_cfg.h | 254 ++++++++++++++++ src/mainboard/elmex/pcm205400/romstage.c | 111 +++++++ src/mainboard/elmex/pcm205401/BiosCallOuts.c | 93 ++++++ src/mainboard/elmex/pcm205401/Kconfig | 77 +++++ src/mainboard/elmex/pcm205401/Kconfig.name | 2 + src/mainboard/elmex/pcm205401/Makefile.inc | 29 ++ src/mainboard/elmex/pcm205401/OemCustomize.c | 157 ++++++++++ src/mainboard/elmex/pcm205401/OptionsIds.h | 56 ++++ .../elmex/pcm205401/PlatformGnbPcieComplex.h | 65 ++++ src/mainboard/elmex/pcm205401/acpi/gpe.asl | 78 +++++ src/mainboard/elmex/pcm205401/acpi/ide.asl | 240 +++++++++++++++ src/mainboard/elmex/pcm205401/acpi/mainboard.asl | 63 ++++ src/mainboard/elmex/pcm205401/acpi/routing.asl | 336 +++++++++++++++++++++ src/mainboard/elmex/pcm205401/acpi/sata.asl | 145 +++++++++ src/mainboard/elmex/pcm205401/acpi/sleep.asl | 117 +++++++ src/mainboard/elmex/pcm205401/acpi/superio.asl | 14 + src/mainboard/elmex/pcm205401/acpi/usb_oc.asl | 170 +++++++++++ src/mainboard/elmex/pcm205401/acpi_tables.c | 53 ++++ src/mainboard/elmex/pcm205401/board_info.txt | 5 + src/mainboard/elmex/pcm205401/buildOpts.c | 297 ++++++++++++++++++ src/mainboard/elmex/pcm205401/cmos.layout | 76 +++++ src/mainboard/elmex/pcm205401/devicetree.cb | 157 ++++++++++ src/mainboard/elmex/pcm205401/dsdt.asl | 63 ++++ src/mainboard/elmex/pcm205401/irq_tables.c | 111 +++++++ src/mainboard/elmex/pcm205401/mainboard.c | 178 +++++++++++ src/mainboard/elmex/pcm205401/mptable.c | 148 +++++++++ src/mainboard/elmex/pcm205401/platform_cfg.h | 254 ++++++++++++++++ src/mainboard/elmex/pcm205401/romstage.c | 111 +++++++ 54 files changed, 6208 insertions(+) diff --git a/src/mainboard/elmex/Kconfig b/src/mainboard/elmex/Kconfig new file mode 100644 index 0000000..d1fc9ad --- /dev/null +++ b/src/mainboard/elmex/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_ELMEX + +choice + prompt "Mainboard model" + +source "src/mainboard/elmex/*/Kconfig.name" + +endchoice + +source "src/mainboard/elmex/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "ELMEX" + +endif # VENDOR_ELMEX diff --git a/src/mainboard/elmex/Kconfig.name b/src/mainboard/elmex/Kconfig.name new file mode 100644 index 0000000..b2dcf2e --- /dev/null +++ b/src/mainboard/elmex/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ELMEX + bool "ELMEX" diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c new file mode 100644 index 0000000..9a2a9bb --- /dev/null +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "heapManager.h" +#include "SB800.h" +#include <stdlib.h> + +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/* Call the host environment interface to provide a user hook opportunity. */ +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. + // Make sure the right speed settings are selected. + ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + return AGESA_SUCCESS; +} + +/* PCIE slot reset control */ +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + PCIe_SLOT_RESET_INFO *ResetInfo; + + UINT32 GpioMmioAddr; + UINT32 AcpiMmioAddr; + UINT8 Data8; + UINT16 Data16; + + FcnData = Data; + ResetInfo = ConfigPtr; + // Get SB800 MMIO Base (AcpiMmioAddr) + WriteIo8(0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16=Data8<<8; + WriteIo8(0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16|=Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + Status = AGESA_UNSUPPORTED; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + switch (ResetInfo->ResetId) + { + case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); + Status = AGESA_SUCCESS; + break; + } + break; + } + return Status; +} diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig new file mode 100644 index 0000000..e279aea --- /dev/null +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -0,0 +1,77 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ELMEX_PCM205400 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_AGESA_FAMILY14 + select NORTHBRIDGE_AMD_AGESA_FAMILY14 + select SOUTHBRIDGE_AMD_CIMX_SB800 + select SUPERIO_FINTEK_F81865F + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select GFXUMA + +config MAINBOARD_DIR + string + default elmex/pcm205400 + +config MAINBOARD_PART_NUMBER + string + default "pcm205400" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 2 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +#config VGA_BIOS_FILE +# string "VGA BIOS path and filename" +# depends on VGA_BIOS +# default "rom/video/OntarioGenericVbios.bin" + +config VGA_BIOS_ID + string + default "1002,9802" + +config SB800_AHCI_ROM + bool + default n + +endif # BOARD_ELMEX_PCM205400 diff --git a/src/mainboard/elmex/pcm205400/Kconfig.name b/src/mainboard/elmex/pcm205400/Kconfig.name new file mode 100644 index 0000000..445b588 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ELMEX_PCM205400 + bool "pcm205400" diff --git a/src/mainboard/elmex/pcm205400/Makefile.inc b/src/mainboard/elmex/pcm205400/Makefile.inc new file mode 100644 index 0000000..ba56286 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/Makefile.inc @@ -0,0 +1,29 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ifeq ($(CONFIG_AHCI_BIOS),y) +stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID)) +cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom +pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE)) +pci$(stripped_ahcibios_id).rom-type := optionrom +endif + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c new file mode 100644 index 0000000..825364e --- /dev/null +++ b/src/mainboard/elmex/pcm205400/OemCustomize.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "PlatformGnbPcieComplex.h" + +#include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> +#include <PlatformMemoryConfiguration.h> + +#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE + +/** + * OemCustomizeInitEarly + * + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] *InitEarly + * + * @retval VOID + * + **/ + +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +{ + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + +PCIe_PORT_DESCRIPTOR PortList [] = { + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeLvds, Aux1, Hdp1} + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} + } +}; + +PCIe_COMPLEX_DESCRIPTOR Brazos = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + ASSERT(Status == AGESA_SUCCESS); + + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(Brazos); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(PortList); + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); + memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); + memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); + + + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + PSO_END +}; + +const struct OEM_HOOK OemCustomize = { + .InitEarly = OemInitEarly, +}; diff --git a/src/mainboard/elmex/pcm205400/OptionsIds.h b/src/mainboard/elmex/pcm205400/OptionsIds.h new file mode 100644 index 0000000..2d8381b --- /dev/null +++ b/src/mainboard/elmex/pcm205400/OptionsIds.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..4132c7c --- /dev/null +++ b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/elmex/pcm205400/acpi/gpe.asl b/src/mainboard/elmex/pcm205400/acpi/gpe.asl new file mode 100644 index 0000000..2f22758 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/gpe.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ + +/* Contains the GPEs for USB overcurrent */ +#include "usb_oc.asl" diff --git a/src/mainboard/elmex/pcm205400/acpi/ide.asl b/src/mainboard/elmex/pcm205400/acpi/ide.asl new file mode 100644 index 0000000..59ea078 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/ide.asl @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0, Serialized) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, Serialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF, 0, Serialized) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF, 0, Serialized) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/elmex/pcm205400/acpi/mainboard.asl b/src/mainboard/elmex/pcm205400/acpi/mainboard.asl new file mode 100644 index 0000000..b666a4f --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/mainboard.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Data to be patched by the BIOS during POST */ +/* FIXME the patching is not done yet! */ +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +Scope(\_SB) { + Method(OSFL, 0){ + + if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + + if(CondRefOf(\_OSI)) + { + Store(1, OSVR) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSVR) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSVR) /* Linux */ + } Else { + Store(4, OSVR) /* Gotta be WinCE */ + } + } + Return(OSVR) + } +} + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ diff --git a/src/mainboard/elmex/pcm205400/acpi/routing.asl b/src/mainboard/elmex/pcm205400/acpi/routing.asl new file mode 100644 index 0000000..6f94b45 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/routing.asl @@ -0,0 +1,336 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */ + Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */ + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 19 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + + /* TODO: pcie */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */ + Package(){0x0003FFFF, 0, 0, 0x14 }, + Package(){0x0003FFFF, 1, 0, 0x15 }, + Package(){0x0003FFFF, 2, 0, 0x16 }, + Package(){0x0003FFFF, 3, 0, 0x17 }, + Package(){0x0004FFFF, 0, 0, 0x15 }, + Package(){0x0004FFFF, 1, 0, 0x16 }, + Package(){0x0004FFFF, 2, 0, 0x17 }, + Package(){0x0004FFFF, 3, 0, 0x14 }, + Package(){0x0005FFFF, 0, 0, 0x16 }, + Package(){0x0005FFFF, 1, 0, 0x17 }, + Package(){0x0005FFFF, 2, 0, 0x14 }, + Package(){0x0005FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/elmex/pcm205400/acpi/sata.asl b/src/mainboard/elmex/pcm205400/acpi/sata.asl new file mode 100644 index 0000000..9e0e535 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/sata.asl @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/elmex/pcm205400/acpi/sleep.asl b/src/mainboard/elmex/pcm205400/acpi/sleep.asl new file mode 100644 index 0000000..b3fd07e --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/sleep.asl @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, Local1) + Store(Local1, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/elmex/pcm205400/acpi/superio.asl b/src/mainboard/elmex/pcm205400/acpi/superio.asl new file mode 100644 index 0000000..daf6e91 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/superio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl new file mode 100644 index 0000000..6e9c701 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/elmex/pcm205400/acpi_tables.c b/src/mainboard/elmex/pcm205400/acpi_tables.c new file mode 100644 index 0000000..9b92c05 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/acpi_tables.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam14.h> + + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/elmex/pcm205400/board_info.txt b/src/mainboard/elmex/pcm205400/board_info.txt new file mode 100644 index 0000000..85cb19a --- /dev/null +++ b/src/mainboard/elmex/pcm205400/board_info.txt @@ -0,0 +1,5 @@ +Board name: DBFT1-00-EVAL-KT (Persimmon) +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c new file mode 100644 index 0000000..fe4e779 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -0,0 +1,297 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + */ + +#include <stdlib.h> +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT TRUE +#define INSTALL_FAMILY_15_SUPPORT FALSE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + +#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE +#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE + + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE TRUE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 + +/* + * Agesa configuration values selection. + * Uncomment and specify the value for the configuration options + * needed by the system. + */ +#include "AGESA.h" + +/* The fixed MTRR values to be set after memory initialization. */ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, + { CPU_LIST_TERMINAL } +}; + +/* Include the files that instantiate the configuration definitions. */ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ +// This is the delivery package title, "BrazosPI" +// This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + +// This is the release version number of the AGESA component +// This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + diff --git a/src/mainboard/elmex/pcm205400/cmos.layout b/src/mainboard/elmex/pcm205400/cmos.layout new file mode 100644 index 0000000..f47185f --- /dev/null +++ b/src/mainboard/elmex/pcm205400/cmos.layout @@ -0,0 +1,76 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/elmex/pcm205400/devicetree.cb b/src/mainboard/elmex/pcm205400/devicetree.cb new file mode 100644 index 0000000..afab841 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/devicetree.cb @@ -0,0 +1,157 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/agesa/family14/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge PCIe slot + device pci 7.0 off end # PCIE P2P bridge + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge + + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB 10-13 + device pci 16.2 off end # EHCI USB 10-13 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + + #set up SB800 Fan control registers and IMC fan controls + register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common + register "fan0_enabled" = "1" + register "fan1_enabled" = "1" + register "imc_fan_zone0_enabled" = "1" + register "imc_fan_zone1_enabled" = "1" + + register "fan0_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan1_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + + register "imc_zone0_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" + register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone0_temp_offset" = "0x00" # No temp offset + register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + register "imc_zone1_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" + register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone1_temp_offset" = "0x00" # No temp offset + register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + # T56N has a Maximum operating temperature of 90C + # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C + # ZONEX_FANSPEEDS - Fan speeds as a "percentage" + register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" + register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" + register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" + register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" + + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 +# These seem unnecessary + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #domain +end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl new file mode 100644 index 0000000..0cf657f --- /dev/null +++ b/src/mainboard/elmex/pcm205400/dsdt.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + #include "acpi/mainboard.asl" + + #include <cpu/amd/agesa/family14/acpi/cpu.asl> + + #include "acpi/routing.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + Device(PCI0) { + + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/cimx/sb800/acpi/fch.asl> + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + } + } /* End Scope(_SB) */ + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c new file mode 100644 index 0000000..0c53417 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam14.h> + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c new file mode 100644 index 0000000..e0440f2 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -0,0 +1,178 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <device/pci_def.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <southbridge/amd/cimx/cimx_util.h> +#include <arch/acpi.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/amd/mtrr.h> +#include "SBPLATFORM.h" +#include <southbridge/amd/cimx/sb800/pci_devs.h> +#include <northbridge/amd/agesa/family14/pci_devs.h> + +void set_pcie_reset(void); +void set_pcie_dereset(void); + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + * + * The Persimmon PCI INTA/B/C/D pins are connected to + * FCH pins INTE/F/G/H on the schematic so these need + * to be routed as well. + */ +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ + [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + /* IDE, SATA */ + [0x40] = 0x0B,0x0B, + /* GPPInt0 - 3 */ + [0x50] = 0x0A,0x0B,0x0A,0x0B +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22/20 INTA-C */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + /* IDE, SATA */ + [0x40] = 0x11,0x13, + /* GPPInt0 - 3 */ + [0x50] = 0x10,0x11,0x12,0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +/* + * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H + * but because PCI INT_PIN swizzling isnt implemented to match + * the IDSEL (dev 3) of the slot, the table is adjusted for the + * swizzle and INTA is connected to PIRQH so PINA/B/C/D on + * off-chip devices should get mapped to PIRQH/E/F/G. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void) +{ +} + +/** + * TODO + * mainboard specific SB CIMx callback + */ +void set_pcie_dereset(void) +{ +} + + +/********************************************** + * Enable the dedicated functions of the board. + **********************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* enable GPP CLK0 thru CLK1 */ + /* disable GPP CLK2 thru SLT_GFX_CLK */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + write8(misc_mem_clk_cntrl + 0, 0xFF); + write8(misc_mem_clk_cntrl + 1, 0x00); + write8(misc_mem_clk_cntrl + 2, 0x00); + write8(misc_mem_clk_cntrl + 3, 0x00); + write8(misc_mem_clk_cntrl + 4, 0x00); + + /* + * Initialize ASF registers to an arbitrary address because someone + * long ago set things up this way inside the SPD read code. The + * SPD read code has been made generic and moved out of the board + * directory, so the ASF init is being done here. + */ + pm_iowrite(0x29, 0x80); + pm_iowrite(0x28, 0x61); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c new file mode 100644 index 0000000..8e954cd --- /dev/null +++ b/src/mainboard/elmex/pcm205400/mptable.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam14.h> +#include <SBPLATFORM.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <drivers/generic/ioapic/chip.h> +#include <arch/ioapic.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + /* Intialize the MP_Table */ + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ + smp_write_processors(mc); + + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); + + /* IDE */ + PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + + /* on board NIC & Slot PCIE */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + + /* PCI slots */ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0 */ + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + } + + /* PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + /* PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + /* PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + /* PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/elmex/pcm205400/platform_cfg.h b/src/mainboard/elmex/pcm205400/platform_cfg.h new file mode 100644 index 0000000..660be41 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/platform_cfg.h @@ -0,0 +1,254 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + +/** + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M + * + * In SB800, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) +#endif /* BIOS_SIZE */ + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @brief + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CONFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @brief bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x07 + +/** + * @def SATA_CONTROLLER + * @brief INCHIP Sata Controller + */ +#define SATA_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def SATA_MODE + * @brief INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_MODE CONFIG_SB800_SATA_MODE + +/** + * @brief INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @brief INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_IDE_MODE IDE_LEGACY_MODE + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +/* NOTE: inagua have to using internal clock, + * otherwise can not detect sata drive + */ +#define SATA_CLOCK_SOURCE INTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @brief INCHIP HDA controller + */ +#define AZALIA_CONTROLLER AZALIA_AUTO + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#define AZALIA_PIN_CONFIG 1 + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A + +/** + * @def GPP_CONTROLLER + */ +#define GPP_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#define GPP_CFGMODE GPP_CFGMODE_X1111 + +/** + * @def NB_SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define NB_SB_GEN2 TRUE + +/** + * @def SB_GPP_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define SB_GPP_GEN2 TRUE + +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visible always, even port empty + * FALSE - ports invisible if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE + +/** + * @def GEC_CONFIG + * 0 - Enable + * 1 - Disable + */ +#define GEC_CONFIG 0 + +static const CODECENTRY persimmon_codec_alc269[] = +{ + /* NID, PinConfig */ + {0x12, 0x411111F0}, + {0x14, 0x99130110}, + {0x21, 0x0121401F}, + {0x17, 0x411111F0}, + {0x18, 0x01A19820}, + {0x19, 0x411111F0}, + {0x1A, 0x0181302F}, + {0x1B, 0x411111F0}, + {0x1D, 0x40069E05}, + {0x1E, 0x411111F0}, + {0x20, 0x0001FFFF}, + {0xff, 0xffffffff} /* end of table */ +}; + +static const CODECTBLLIST codec_tablelist[] = +{ + {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, + {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} +}; + +/** + * @def AZALIA_OEM_VERB_TABLE + * Mainboard specific codec verb table list + */ +#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) + +/* set up an ACPI preferred power management profile */ +/* from acpi.h + * PM_UNSPECIFIED = 0, + * PM_DESKTOP = 1, + * PM_MOBILE = 2, + * PM_WORKSTATION = 3, + * PM_ENTERPRISE_SERVER = 4, + * PM_SOHO_SERVER = 5, + * PM_APPLIANCE_PC = 6, + * PM_PERFORMANCE_SERVER = 7, + * PM_TABLET = 8 + */ +#define FADT_PM_PROFILE 1 + +#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c new file mode 100644 index 0000000..0aad4f5 --- /dev/null +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <commonlib/loglevel.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/x86/bist.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81865f/f81865f.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <sb_cimx.h> +#include "SBPLATFORM.h" +#include "cbmem.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> + + +#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + /* + * All cores: allow caching of flash chip code and data + * (there are no cache-as-ram reliability concerns with family 14h) + */ + __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ + __writemsr (0xc0010062, 0); + + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + sb_Poweron_Init(); + + post_code(0x31); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + agesawrapper_amdinitreset(); + + post_code(0x39); + agesawrapper_amdinitearly(); + + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + + post_code(0x42); + agesawrapper_amdinitenv(); + amd_initenv(); + + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); + printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); + + post_code(0x54); /* Should never see this post code. */ +} diff --git a/src/mainboard/elmex/pcm205401/BiosCallOuts.c b/src/mainboard/elmex/pcm205401/BiosCallOuts.c new file mode 100644 index 0000000..9a2a9bb --- /dev/null +++ b/src/mainboard/elmex/pcm205401/BiosCallOuts.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "heapManager.h" +#include "SB800.h" +#include <stdlib.h> + +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/* Call the host environment interface to provide a user hook opportunity. */ +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. + // Make sure the right speed settings are selected. + ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + return AGESA_SUCCESS; +} + +/* PCIE slot reset control */ +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + PCIe_SLOT_RESET_INFO *ResetInfo; + + UINT32 GpioMmioAddr; + UINT32 AcpiMmioAddr; + UINT8 Data8; + UINT16 Data16; + + FcnData = Data; + ResetInfo = ConfigPtr; + // Get SB800 MMIO Base (AcpiMmioAddr) + WriteIo8(0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16=Data8<<8; + WriteIo8(0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16|=Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + Status = AGESA_UNSUPPORTED; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + switch (ResetInfo->ResetId) + { + case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); + Status = AGESA_SUCCESS; + break; + } + break; + } + return Status; +} diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig new file mode 100644 index 0000000..e80e68b --- /dev/null +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -0,0 +1,77 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ELMEX_PCM205401 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_AGESA_FAMILY14 + select NORTHBRIDGE_AMD_AGESA_FAMILY14 + select SOUTHBRIDGE_AMD_CIMX_SB800 + select SUPERIO_FINTEK_F81865F + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select GFXUMA + +config MAINBOARD_DIR + string + default elmex/pcm205401 + +config MAINBOARD_PART_NUMBER + string + default "pcm205401" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 2 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +#config VGA_BIOS_FILE +# string "VGA BIOS path and filename" +# depends on VGA_BIOS +# default "rom/video/OntarioGenericVbios.bin" + +config VGA_BIOS_ID + string + default "1002,9802" + +config SB800_AHCI_ROM + bool + default n + +endif # BOARD_ELMEX_PCM205401 diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name new file mode 100644 index 0000000..f70b215 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ELMEX_PCM205401 + bool "pcm205401" diff --git a/src/mainboard/elmex/pcm205401/Makefile.inc b/src/mainboard/elmex/pcm205401/Makefile.inc new file mode 100644 index 0000000..ba56286 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/Makefile.inc @@ -0,0 +1,29 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ifeq ($(CONFIG_AHCI_BIOS),y) +stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID)) +cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom +pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE)) +pci$(stripped_ahcibios_id).rom-type := optionrom +endif + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/elmex/pcm205401/OemCustomize.c b/src/mainboard/elmex/pcm205401/OemCustomize.c new file mode 100644 index 0000000..825364e --- /dev/null +++ b/src/mainboard/elmex/pcm205401/OemCustomize.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "PlatformGnbPcieComplex.h" + +#include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> +#include <PlatformMemoryConfiguration.h> + +#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE + +/** + * OemCustomizeInitEarly + * + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] *InitEarly + * + * @retval VOID + * + **/ + +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +{ + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + +PCIe_PORT_DESCRIPTOR PortList [] = { + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeLvds, Aux1, Hdp1} + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} + } +}; + +PCIe_COMPLEX_DESCRIPTOR Brazos = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + ASSERT(Status == AGESA_SUCCESS); + + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(Brazos); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(PortList); + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); + memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); + memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); + + + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + PSO_END +}; + +const struct OEM_HOOK OemCustomize = { + .InitEarly = OemInitEarly, +}; diff --git a/src/mainboard/elmex/pcm205401/OptionsIds.h b/src/mainboard/elmex/pcm205401/OptionsIds.h new file mode 100644 index 0000000..2d8381b --- /dev/null +++ b/src/mainboard/elmex/pcm205401/OptionsIds.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..4132c7c --- /dev/null +++ b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/elmex/pcm205401/acpi/gpe.asl b/src/mainboard/elmex/pcm205401/acpi/gpe.asl new file mode 100644 index 0000000..2f22758 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/gpe.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ + +/* Contains the GPEs for USB overcurrent */ +#include "usb_oc.asl" diff --git a/src/mainboard/elmex/pcm205401/acpi/ide.asl b/src/mainboard/elmex/pcm205401/acpi/ide.asl new file mode 100644 index 0000000..59ea078 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/ide.asl @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0, Serialized) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, Serialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF, 0, Serialized) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF, 0, Serialized) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/elmex/pcm205401/acpi/mainboard.asl b/src/mainboard/elmex/pcm205401/acpi/mainboard.asl new file mode 100644 index 0000000..b666a4f --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/mainboard.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Data to be patched by the BIOS during POST */ +/* FIXME the patching is not done yet! */ +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +Scope(\_SB) { + Method(OSFL, 0){ + + if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + + if(CondRefOf(\_OSI)) + { + Store(1, OSVR) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSVR) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSVR) /* Linux */ + } Else { + Store(4, OSVR) /* Gotta be WinCE */ + } + } + Return(OSVR) + } +} + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ diff --git a/src/mainboard/elmex/pcm205401/acpi/routing.asl b/src/mainboard/elmex/pcm205401/acpi/routing.asl new file mode 100644 index 0000000..6f94b45 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/routing.asl @@ -0,0 +1,336 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */ + Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */ + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 19 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + + /* TODO: pcie */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */ + Package(){0x0003FFFF, 0, 0, 0x14 }, + Package(){0x0003FFFF, 1, 0, 0x15 }, + Package(){0x0003FFFF, 2, 0, 0x16 }, + Package(){0x0003FFFF, 3, 0, 0x17 }, + Package(){0x0004FFFF, 0, 0, 0x15 }, + Package(){0x0004FFFF, 1, 0, 0x16 }, + Package(){0x0004FFFF, 2, 0, 0x17 }, + Package(){0x0004FFFF, 3, 0, 0x14 }, + Package(){0x0005FFFF, 0, 0, 0x16 }, + Package(){0x0005FFFF, 1, 0, 0x17 }, + Package(){0x0005FFFF, 2, 0, 0x14 }, + Package(){0x0005FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/elmex/pcm205401/acpi/sata.asl b/src/mainboard/elmex/pcm205401/acpi/sata.asl new file mode 100644 index 0000000..9e0e535 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/sata.asl @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/elmex/pcm205401/acpi/sleep.asl b/src/mainboard/elmex/pcm205401/acpi/sleep.asl new file mode 100644 index 0000000..b3fd07e --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/sleep.asl @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, Local1) + Store(Local1, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/elmex/pcm205401/acpi/superio.asl b/src/mainboard/elmex/pcm205401/acpi/superio.asl new file mode 100644 index 0000000..daf6e91 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/superio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/elmex/pcm205401/acpi/usb_oc.asl b/src/mainboard/elmex/pcm205401/acpi/usb_oc.asl new file mode 100644 index 0000000..6e9c701 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi/usb_oc.asl @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/elmex/pcm205401/acpi_tables.c b/src/mainboard/elmex/pcm205401/acpi_tables.c new file mode 100644 index 0000000..9b92c05 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/acpi_tables.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam14.h> + + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/elmex/pcm205401/board_info.txt b/src/mainboard/elmex/pcm205401/board_info.txt new file mode 100644 index 0000000..85cb19a --- /dev/null +++ b/src/mainboard/elmex/pcm205401/board_info.txt @@ -0,0 +1,5 @@ +Board name: DBFT1-00-EVAL-KT (Persimmon) +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/elmex/pcm205401/buildOpts.c b/src/mainboard/elmex/pcm205401/buildOpts.c new file mode 100644 index 0000000..fe4e779 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/buildOpts.c @@ -0,0 +1,297 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + */ + +#include <stdlib.h> +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT TRUE +#define INSTALL_FAMILY_15_SUPPORT FALSE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + +#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE +#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE + + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE TRUE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 + +/* + * Agesa configuration values selection. + * Uncomment and specify the value for the configuration options + * needed by the system. + */ +#include "AGESA.h" + +/* The fixed MTRR values to be set after memory initialization. */ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, + { CPU_LIST_TERMINAL } +}; + +/* Include the files that instantiate the configuration definitions. */ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ +// This is the delivery package title, "BrazosPI" +// This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + +// This is the release version number of the AGESA component +// This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + diff --git a/src/mainboard/elmex/pcm205401/cmos.layout b/src/mainboard/elmex/pcm205401/cmos.layout new file mode 100644 index 0000000..f47185f --- /dev/null +++ b/src/mainboard/elmex/pcm205401/cmos.layout @@ -0,0 +1,76 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/elmex/pcm205401/devicetree.cb b/src/mainboard/elmex/pcm205401/devicetree.cb new file mode 100644 index 0000000..afab841 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/devicetree.cb @@ -0,0 +1,157 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/agesa/family14/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge PCIe slot + device pci 7.0 off end # PCIE P2P bridge + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge + + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB 10-13 + device pci 16.2 off end # EHCI USB 10-13 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + + #set up SB800 Fan control registers and IMC fan controls + register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common + register "fan0_enabled" = "1" + register "fan1_enabled" = "1" + register "imc_fan_zone0_enabled" = "1" + register "imc_fan_zone1_enabled" = "1" + + register "fan0_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan1_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + + register "imc_zone0_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" + register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone0_temp_offset" = "0x00" # No temp offset + register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + register "imc_zone1_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" + register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone1_temp_offset" = "0x00" # No temp offset + register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + # T56N has a Maximum operating temperature of 90C + # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C + # ZONEX_FANSPEEDS - Fan speeds as a "percentage" + register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" + register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" + register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" + register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" + + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 +# These seem unnecessary + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #domain +end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/elmex/pcm205401/dsdt.asl b/src/mainboard/elmex/pcm205401/dsdt.asl new file mode 100644 index 0000000..0cf657f --- /dev/null +++ b/src/mainboard/elmex/pcm205401/dsdt.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + #include "acpi/mainboard.asl" + + #include <cpu/amd/agesa/family14/acpi/cpu.asl> + + #include "acpi/routing.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + Device(PCI0) { + + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/cimx/sb800/acpi/fch.asl> + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + } + } /* End Scope(_SB) */ + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/elmex/pcm205401/irq_tables.c b/src/mainboard/elmex/pcm205401/irq_tables.c new file mode 100644 index 0000000..0c53417 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/irq_tables.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam14.h> + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/elmex/pcm205401/mainboard.c b/src/mainboard/elmex/pcm205401/mainboard.c new file mode 100644 index 0000000..e0440f2 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/mainboard.c @@ -0,0 +1,178 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <device/pci_def.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <southbridge/amd/cimx/cimx_util.h> +#include <arch/acpi.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/amd/mtrr.h> +#include "SBPLATFORM.h" +#include <southbridge/amd/cimx/sb800/pci_devs.h> +#include <northbridge/amd/agesa/family14/pci_devs.h> + +void set_pcie_reset(void); +void set_pcie_dereset(void); + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + * + * The Persimmon PCI INTA/B/C/D pins are connected to + * FCH pins INTE/F/G/H on the schematic so these need + * to be routed as well. + */ +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ + [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + /* IDE, SATA */ + [0x40] = 0x0B,0x0B, + /* GPPInt0 - 3 */ + [0x50] = 0x0A,0x0B,0x0A,0x0B +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22/20 INTA-C */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + /* IDE, SATA */ + [0x40] = 0x11,0x13, + /* GPPInt0 - 3 */ + [0x50] = 0x10,0x11,0x12,0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +/* + * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H + * but because PCI INT_PIN swizzling isnt implemented to match + * the IDSEL (dev 3) of the slot, the table is adjusted for the + * swizzle and INTA is connected to PIRQH so PINA/B/C/D on + * off-chip devices should get mapped to PIRQH/E/F/G. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void) +{ +} + +/** + * TODO + * mainboard specific SB CIMx callback + */ +void set_pcie_dereset(void) +{ +} + + +/********************************************** + * Enable the dedicated functions of the board. + **********************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* enable GPP CLK0 thru CLK1 */ + /* disable GPP CLK2 thru SLT_GFX_CLK */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + write8(misc_mem_clk_cntrl + 0, 0xFF); + write8(misc_mem_clk_cntrl + 1, 0x00); + write8(misc_mem_clk_cntrl + 2, 0x00); + write8(misc_mem_clk_cntrl + 3, 0x00); + write8(misc_mem_clk_cntrl + 4, 0x00); + + /* + * Initialize ASF registers to an arbitrary address because someone + * long ago set things up this way inside the SPD read code. The + * SPD read code has been made generic and moved out of the board + * directory, so the ASF init is being done here. + */ + pm_iowrite(0x29, 0x80); + pm_iowrite(0x28, 0x61); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/elmex/pcm205401/mptable.c b/src/mainboard/elmex/pcm205401/mptable.c new file mode 100644 index 0000000..8e954cd --- /dev/null +++ b/src/mainboard/elmex/pcm205401/mptable.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam14.h> +#include <SBPLATFORM.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <drivers/generic/ioapic/chip.h> +#include <arch/ioapic.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + /* Intialize the MP_Table */ + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ + smp_write_processors(mc); + + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); + + /* IDE */ + PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + + /* on board NIC & Slot PCIE */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + + /* PCI slots */ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0 */ + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + } + + /* PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + /* PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + /* PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + /* PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/elmex/pcm205401/platform_cfg.h b/src/mainboard/elmex/pcm205401/platform_cfg.h new file mode 100644 index 0000000..660be41 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/platform_cfg.h @@ -0,0 +1,254 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + +/** + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M + * + * In SB800, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) +#endif /* BIOS_SIZE */ + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @brief + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CONFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @brief bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x07 + +/** + * @def SATA_CONTROLLER + * @brief INCHIP Sata Controller + */ +#define SATA_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def SATA_MODE + * @brief INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_MODE CONFIG_SB800_SATA_MODE + +/** + * @brief INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @brief INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_IDE_MODE IDE_LEGACY_MODE + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +/* NOTE: inagua have to using internal clock, + * otherwise can not detect sata drive + */ +#define SATA_CLOCK_SOURCE INTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @brief INCHIP HDA controller + */ +#define AZALIA_CONTROLLER AZALIA_AUTO + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#define AZALIA_PIN_CONFIG 1 + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A + +/** + * @def GPP_CONTROLLER + */ +#define GPP_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#define GPP_CFGMODE GPP_CFGMODE_X1111 + +/** + * @def NB_SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define NB_SB_GEN2 TRUE + +/** + * @def SB_GPP_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define SB_GPP_GEN2 TRUE + +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visible always, even port empty + * FALSE - ports invisible if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE + +/** + * @def GEC_CONFIG + * 0 - Enable + * 1 - Disable + */ +#define GEC_CONFIG 0 + +static const CODECENTRY persimmon_codec_alc269[] = +{ + /* NID, PinConfig */ + {0x12, 0x411111F0}, + {0x14, 0x99130110}, + {0x21, 0x0121401F}, + {0x17, 0x411111F0}, + {0x18, 0x01A19820}, + {0x19, 0x411111F0}, + {0x1A, 0x0181302F}, + {0x1B, 0x411111F0}, + {0x1D, 0x40069E05}, + {0x1E, 0x411111F0}, + {0x20, 0x0001FFFF}, + {0xff, 0xffffffff} /* end of table */ +}; + +static const CODECTBLLIST codec_tablelist[] = +{ + {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, + {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} +}; + +/** + * @def AZALIA_OEM_VERB_TABLE + * Mainboard specific codec verb table list + */ +#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) + +/* set up an ACPI preferred power management profile */ +/* from acpi.h + * PM_UNSPECIFIED = 0, + * PM_DESKTOP = 1, + * PM_MOBILE = 2, + * PM_WORKSTATION = 3, + * PM_ENTERPRISE_SERVER = 4, + * PM_SOHO_SERVER = 5, + * PM_APPLIANCE_PC = 6, + * PM_PERFORMANCE_SERVER = 7, + * PM_TABLET = 8 + */ +#define FADT_PM_PROFILE 1 + +#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/elmex/pcm205401/romstage.c b/src/mainboard/elmex/pcm205401/romstage.c new file mode 100644 index 0000000..0aad4f5 --- /dev/null +++ b/src/mainboard/elmex/pcm205401/romstage.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <commonlib/loglevel.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/x86/bist.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81865f/f81865f.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <sb_cimx.h> +#include "SBPLATFORM.h" +#include "cbmem.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> + + +#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + /* + * All cores: allow caching of flash chip code and data + * (there are no cache-as-ram reliability concerns with family 14h) + */ + __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ + __writemsr (0xc0010062, 0); + + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + sb_Poweron_Init(); + + post_code(0x31); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + agesawrapper_amdinitreset(); + + post_code(0x39); + agesawrapper_amdinitearly(); + + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + + post_code(0x42); + agesawrapper_amdinitenv(); + amd_initenv(); + + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); + printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); + + post_code(0x54); /* Should never see this post code. */ +}

1 0

New patch to review for coreboot: mainboard/elmex: Add new board pcm205401
by Kyösti Mälkki 28 Jul '16

28 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15930 -gerrit commit 60e980bbbee49737bd00a095b7f2765d17682249 Author: Yuichi Ito <yui.corebt(a)gmail.com> Date: Thu Jul 28 13:34:18 2016 +0900 mainboard/elmex: Add new board pcm205401 Change-Id: I6c7e90db84f13ffbf9e629f2b92649895a466155 Signed-off-by: Yuichi Ito <yui.corebt(a)gmail.com> --- src/mainboard/elmex/pcm205401/BiosCallOuts.c | 34 ++--- src/mainboard/elmex/pcm205401/Kconfig | 7 +- src/mainboard/elmex/pcm205401/OemCustomize.c | 138 ++++++++++++++------- .../elmex/pcm205401/PlatformGnbPcieComplex.h | 110 ++++++++++------ src/mainboard/elmex/pcm205401/SBCimxPcieReset.h | 17 +++ src/mainboard/elmex/pcm205401/buildOpts.c | 67 +++++----- src/mainboard/elmex/pcm205401/devicetree.cb | 6 +- src/mainboard/elmex/pcm205401/irq_tables.c | 3 +- src/mainboard/elmex/pcm205401/mainboard.c | 86 ++++++++----- src/mainboard/elmex/pcm205401/mptable.c | 24 ++-- src/mainboard/elmex/pcm205401/platform_cfg.h | 10 +- src/mainboard/elmex/pcm205401/romstage.c | 13 +- 12 files changed, 321 insertions(+), 194 deletions(-) diff --git a/src/mainboard/elmex/pcm205401/BiosCallOuts.c b/src/mainboard/elmex/pcm205401/BiosCallOuts.c index 9a2a9bb..497ec58 100644 --- a/src/mainboard/elmex/pcm205401/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205401/BiosCallOuts.c @@ -20,11 +20,12 @@ #include "SB800.h" #include <stdlib.h> -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, + UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, + UINTN Data, VOID *ConfigPtr); -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, @@ -37,17 +38,19 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); -/* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +/* Call the host environment interface to provide a user hook opportunity. */ +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, + UINTN Data, VOID *ConfigPtr) { // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. // Make sure the right speed settings are selected. - ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + ((MEM_DATA_STRUCT *)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; } /* PCIE slot reset control */ -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, + UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -63,27 +66,26 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8<<8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); - Data16|=Data8; + Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + switch (ResetInfo->ResetId) { + case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); + Data8 |= BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig index e80e68b..a5f7426 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -61,14 +61,9 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string - default "1002,9802" + default "1002,9804" # FUSION_G_T40R config SB800_AHCI_ROM bool diff --git a/src/mainboard/elmex/pcm205401/OemCustomize.c b/src/mainboard/elmex/pcm205401/OemCustomize.c index 825364e..803dbf6 100644 --- a/src/mainboard/elmex/pcm205401/OemCustomize.c +++ b/src/mainboard/elmex/pcm205401/OemCustomize.c @@ -23,20 +23,20 @@ #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /** - * OemCustomizeInitEarly + * OemCustomizeInitEarly * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity * - * Parameters: - * @param[in] *InitEarly + * Parameters: + * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -45,52 +45,87 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; -PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) +PCIe_PORT_DESCRIPTOR PortList[] = { +// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, + GNB_GPP_PORT4_CHANNEL_TYPE, + 4, + GNB_GPP_PORT4_HOTPLUG_SUPPORT, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) +// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, + GNB_GPP_PORT5_CHANNEL_TYPE, + 5, + GNB_GPP_PORT5_HOTPLUG_SUPPORT, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) +// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, + GNB_GPP_PORT6_CHANNEL_TYPE, + 6, + GNB_GPP_PORT6_HOTPLUG_SUPPORT, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) +// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, + GNB_GPP_PORT7_CHANNEL_TYPE, + 7, + GNB_GPP_PORT7_HOTPLUG_SUPPORT, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_LINK_ASPM, + 0) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) +// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, + GNB_GPP_PORT8_CHANNEL_TYPE, + 8, + GNB_GPP_PORT8_HOTPLUG_SUPPORT, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_LINK_ASPM, + 0) } }; -PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) +PCIe_DDI_DESCRIPTOR DdiList[] = { +// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeLvds, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) +// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeDP, Aux2, Hdp2} } }; @@ -105,50 +140,57 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // GNB PCIe topology Porting // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR, + // PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + + sizeof(PortList) + + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + Status = HeapAllocateBuffer(&AllocHeapParams, &InitEarly->StdHeader); ASSERT(Status == AGESA_SUCCESS); - BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieComplexListPtr = + (PCIe_COMPLEX_DESCRIPTOR *)AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *)AllocHeapParams.BufferPtr; memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->PciePortList = + (PCIe_PORT_DESCRIPTOR *)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->DdiLinkList = + (PCIe_DDI_DESCRIPTOR *)BrazosPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; return AGESA_SUCCESS; } -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- +/*----------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *----------------------------------------------------------------------------- */ /* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. + * Platform Specific Overriding Table allows IBV/OEM to pass in platform + * information to AGESA (e.g. MemClk routing, the number of DIMM slots + * per channel,...). If PlatformSpecificTable is populated, AGESA will + * base its settings on the data from the table. Otherwise, it will use + * its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), PSO_END }; diff --git a/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h index 4132c7c..a713f0d 100644 --- a/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h +++ b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h @@ -21,45 +21,85 @@ #include "amdlib.h" #include <cpu/amd/agesa/s3_resume.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port4 + * GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT4_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT4_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT4_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT4_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 +#define GNB_GPP_PORT4_SPEED_MODE 2 +#define GNB_GPP_PORT4_LINK_ASPM 3 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port5 + * GNB_GPP_PORT5_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT5_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT5_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT5_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT5_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 +#define GNB_GPP_PORT5_SPEED_MODE 2 +#define GNB_GPP_PORT5_LINK_ASPM 3 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port6 + * GNB_GPP_PORT6_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT6_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT6_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT6_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT6_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 +#define GNB_GPP_PORT6_SPEED_MODE 2 +#define GNB_GPP_PORT6_LINK_ASPM 3 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port7 + * GNB_GPP_PORT7_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT7_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT7_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT7_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT7_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 +#define GNB_GPP_PORT7_SPEED_MODE 2 +#define GNB_GPP_PORT7_LINK_ASPM 3 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port8 + * GNB_GPP_PORT8_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT8_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT8_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT8_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT8_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 +#define GNB_GPP_PORT8_SPEED_MODE 2 +#define GNB_GPP_PORT8_LINK_ASPM 3 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/elmex/pcm205401/SBCimxPcieReset.h b/src/mainboard/elmex/pcm205401/SBCimxPcieReset.h new file mode 100644 index 0000000..e6c126a --- /dev/null +++ b/src/mainboard/elmex/pcm205401/SBCimxPcieReset.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 ELMEX Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void set_pcie_reset(void); +void set_pcie_dereset(void); diff --git a/src/mainboard/elmex/pcm205401/buildOpts.c b/src/mainboard/elmex/pcm205401/buildOpts.c index fe4e779..fa4fc0d 100644 --- a/src/mainboard/elmex/pcm205401/buildOpts.c +++ b/src/mainboard/elmex/pcm205401/buildOpts.c @@ -102,8 +102,8 @@ #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 @@ -130,9 +130,9 @@ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST (&OntarioApMtrrSettingsList) +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 //#define BLDCFG_ALLOCATED_BUSNUMS 0x20 @@ -171,12 +171,12 @@ #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //#define BLDCFG_ONLINE_SPARE FALSE //#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE @@ -206,8 +206,7 @@ #include "AGESA.h" /* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, @@ -222,7 +221,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -247,7 +246,8 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * development build from trunk will not be confused for a released version. * The release manager will need to remove the trailing 'X' and update the * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' + * should also be updated/incremented for the next expected version, + * + trailing 'X' ****************************************************************************/ // This is the delivery package title, "BrazosPI" // This string MUST be exactly 8 characters long @@ -255,35 +255,38 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0',\ + '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters + * in which there are no clearly defined defaults to be used in the common + * file. The values below are based on product and BKDG content, please consult + * the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/elmex/pcm205401/devicetree.cb b/src/mainboard/elmex/pcm205401/devicetree.cb index afab841..6269d09 100644 --- a/src/mainboard/elmex/pcm205401/devicetree.cb +++ b/src/mainboard/elmex/pcm205401/devicetree.cb @@ -47,7 +47,8 @@ chip northbridge/amd/agesa/family14/root_complex end end # SM device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 +# HDA is not used on board. + device pci 14.2 off end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/fintek/f81865f device pnp 4e.0 off # Floppy @@ -57,7 +58,8 @@ chip northbridge/amd/agesa/family14/root_complex end device pnp 4e.3 off end # Parallel Port device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard +# Keyboard interface on superI/O is not used. + device pnp 4e.5 off # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 diff --git a/src/mainboard/elmex/pcm205401/irq_tables.c b/src/mainboard/elmex/pcm205401/irq_tables.c index 0c53417..e4746f7 100644 --- a/src/mainboard/elmex/pcm205401/irq_tables.c +++ b/src/mainboard/elmex/pcm205401/irq_tables.c @@ -100,9 +100,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) sum = pirq->checksum - sum; - if (sum != pirq->checksum) { + if (sum != pirq->checksum) pirq->checksum = sum; - } printk(BIOS_INFO, "write_pirq_routing_table done.\n"); diff --git a/src/mainboard/elmex/pcm205401/mainboard.c b/src/mainboard/elmex/pcm205401/mainboard.c index e0440f2..27ee53c 100644 --- a/src/mainboard/elmex/pcm205401/mainboard.c +++ b/src/mainboard/elmex/pcm205401/mainboard.c @@ -29,9 +29,7 @@ #include "SBPLATFORM.h" #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> - -void set_pcie_reset(void); -void set_pcie_dereset(void); +#include "SBCimxPcieReset.h" /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -50,36 +48,36 @@ void set_pcie_dereset(void); */ static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + [0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x08] = 0x00, 0xF0, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ - [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F, /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + [0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, /* IDE, SATA */ - [0x40] = 0x0B,0x0B, + [0x40] = 0x0B, 0x0B, /* GPPInt0 - 3 */ - [0x50] = 0x0A,0x0B,0x0A,0x0B + [0x50] = 0x0A, 0x0B, 0x0A, 0x0B }; static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* USB Devs 18/19/22/20 INTA-C */ - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, /* IDE, SATA */ - [0x40] = 0x11,0x13, + [0x40] = 0x11, 0x13, /* GPPInt0 - 3 */ - [0x50] = 0x10,0x11,0x12,0x13 + [0x50] = 0x10, 0x11, 0x12, 0x13 }; /* @@ -99,30 +97,48 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { * swizzle and INTA is connected to PIRQH so PINA/B/C/D on * off-chip devices should get mapped to PIRQH/E/F/G. */ +/* + * GFX_DEVFN VGA: 01.0 + * NB_PCIE_PORT1_DEVFN NIC: 04.0 + * NB_PCIE_PORT3_DEVFN PCIe bdg: 06.0 + * SATA_DEVFN SATA: 11.0 + * OHCI1_DEVFN OHCI1: 12.0 + * EHCI1_DEVFN EHCI1: 12.2 + * OHCI2_DEVFN OHCI2: 13.0 + * EHCI2_DEVFN EHCI2: 13.2 + * SMBUS_DEVFN SMBUS: 14.0 + * IDE_DEVFN IDE: 14.1 + * HDA_DEVFN HDA: 14.2 + * SB_PCI_PORT_DEVFN PCI bdg: 14.4 + * OHCI4_DEVFN OHCI4: 14.5 + * OHCI3_DEVFN OHCI3: 16.0 + * EHCI3_DEVFN EHCI3: 16.2 + */ static const struct pirq_struct mainboard_pirq_data[] = { /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ - {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ - {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ - {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ - {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC} }, + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC} }, + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G} }, + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, }; /* PIRQ Setup */ static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = sizeof(mainboard_pirq_data) + / sizeof(struct pirq_struct); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } @@ -149,11 +165,13 @@ void set_pcie_dereset(void) **********************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + printk(BIOS_INFO, + "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); /* enable GPP CLK0 thru CLK1 */ /* disable GPP CLK2 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + write8(misc_mem_clk_cntrl + 0, 0xFF); write8(misc_mem_clk_cntrl + 1, 0x00); write8(misc_mem_clk_cntrl + 2, 0x00); diff --git a/src/mainboard/elmex/pcm205401/mptable.c b/src/mainboard/elmex/pcm205401/mptable.c index 8e954cd..04a9ade 100644 --- a/src/mainboard/elmex/pcm205401/mptable.c +++ b/src/mainboard/elmex/pcm205401/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); @@ -76,7 +76,8 @@ static void *smp_write_config_table(void *v) * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ + (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* APU Internal Graphic Device */ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); @@ -110,13 +111,18 @@ static void *smp_write_config_table(void *v) /* PCI slots */ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + //INTA -> INTE + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); + //INTB -> INTF + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); + //INTC -> INTG + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); + //INTD -> INTH + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); } /* PCIe PortA */ @@ -128,9 +134,10 @@ static void *smp_write_config_table(void *v) /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE |\ + MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); @@ -143,6 +150,7 @@ static void *smp_write_config_table(void *v) unsigned long write_smp_table(unsigned long addr) { void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ return (unsigned long)smp_write_config_table(v); } diff --git a/src/mainboard/elmex/pcm205401/platform_cfg.h b/src/mainboard/elmex/pcm205401/platform_cfg.h index 660be41..a7de71b 100644 --- a/src/mainboard/elmex/pcm205401/platform_cfg.h +++ b/src/mainboard/elmex/pcm205401/platform_cfg.h @@ -208,8 +208,7 @@ */ #define GEC_CONFIG 0 -static const CODECENTRY persimmon_codec_alc269[] = -{ +static const CODECENTRY persimmon_codec_alc269[] = { /* NID, PinConfig */ {0x12, 0x411111F0}, {0x14, 0x99130110}, @@ -225,10 +224,9 @@ static const CODECENTRY persimmon_codec_alc269[] = {0xff, 0xffffffff} /* end of table */ }; -static const CODECTBLLIST codec_tablelist[] = -{ - {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, - {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} +static const CODECTBLLIST codec_tablelist[] = { + {0x010ec0269, (CODECENTRY *)&persimmon_codec_alc269[0]}, + {0x0FFFFFFFFUL, (CODECENTRY *)0x0FFFFFFFFUL} }; /** diff --git a/src/mainboard/elmex/pcm205401/romstage.c b/src/mainboard/elmex/pcm205401/romstage.c index 0aad4f5..aef9d04 100644 --- a/src/mainboard/elmex/pcm205401/romstage.c +++ b/src/mainboard/elmex/pcm205401/romstage.c @@ -50,11 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + __writemsr(0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); + __writemsr(0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of + * boot time + */ + __writemsr(0xc0010062, 0); amd_initmmio(); @@ -83,6 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); @@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) agesawrapper_amdinitenv(); amd_initenv(); - } else { /* S3 detect */ + } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60);

1 0

New patch to review for coreboot: mainboard/elmex: Add new board pcm205400
by Kyösti Mälkki 28 Jul '16

28 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15929 -gerrit commit 2c809ea6f685bab824d315cfc9d92e4dcabec323 Author: Yuichi Ito <yui.corebt(a)gmail.com> Date: Thu Jul 28 13:34:18 2016 +0900 mainboard/elmex: Add new board pcm205400 Change-Id: I77cb76903fe3c1b500a306426f5399936382695b Signed-off-by: Yuichi Ito <yui.corebt(a)gmail.com> --- src/mainboard/elmex/pcm205400/BiosCallOuts.c | 34 ++--- src/mainboard/elmex/pcm205400/Kconfig | 7 +- src/mainboard/elmex/pcm205400/OemCustomize.c | 138 ++++++++++++++------- .../elmex/pcm205400/PlatformGnbPcieComplex.h | 110 ++++++++++------ src/mainboard/elmex/pcm205400/SBCimxPcieReset.h | 17 +++ src/mainboard/elmex/pcm205400/buildOpts.c | 67 +++++----- src/mainboard/elmex/pcm205400/devicetree.cb | 6 +- src/mainboard/elmex/pcm205400/irq_tables.c | 3 +- src/mainboard/elmex/pcm205400/mainboard.c | 86 ++++++++----- src/mainboard/elmex/pcm205400/mptable.c | 24 ++-- src/mainboard/elmex/pcm205400/platform_cfg.h | 10 +- src/mainboard/elmex/pcm205400/romstage.c | 13 +- 12 files changed, 321 insertions(+), 194 deletions(-) diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c index 9a2a9bb..9ccab9b 100644 --- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -20,11 +20,12 @@ #include "SB800.h" #include <stdlib.h> -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, + UINTN Data, VOID * ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, + UINTN Data, VOID *ConfigPtr); -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, @@ -37,17 +38,19 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); -/* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +/* Call the host environment interface to provide a user hook opportunity. */ +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, + UINTN Data, VOID *ConfigPtr) { // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. // Make sure the right speed settings are selected. - ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + ((MEM_DATA_STRUCT *)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; } /* PCIE slot reset control */ -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, + UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -63,27 +66,26 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8<<8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); - Data16|=Data8; + Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + switch (ResetInfo->ResetId) { + case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); + Data8 |= BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index e279aea..0aac747 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -61,14 +61,9 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string - default "1002,9802" + default "1002,9806" # FUSION_G_T56N config SB800_AHCI_ROM bool diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c index 825364e..803dbf6 100644 --- a/src/mainboard/elmex/pcm205400/OemCustomize.c +++ b/src/mainboard/elmex/pcm205400/OemCustomize.c @@ -23,20 +23,20 @@ #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /** - * OemCustomizeInitEarly + * OemCustomizeInitEarly * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity * - * Parameters: - * @param[in] *InitEarly + * Parameters: + * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -45,52 +45,87 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; -PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) +PCIe_PORT_DESCRIPTOR PortList[] = { +// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, + GNB_GPP_PORT4_CHANNEL_TYPE, + 4, + GNB_GPP_PORT4_HOTPLUG_SUPPORT, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) +// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, + GNB_GPP_PORT5_CHANNEL_TYPE, + 5, + GNB_GPP_PORT5_HOTPLUG_SUPPORT, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) +// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, + GNB_GPP_PORT6_CHANNEL_TYPE, + 6, + GNB_GPP_PORT6_HOTPLUG_SUPPORT, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) +// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, + GNB_GPP_PORT7_CHANNEL_TYPE, + 7, + GNB_GPP_PORT7_HOTPLUG_SUPPORT, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_LINK_ASPM, + 0) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) +// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, + GNB_GPP_PORT8_CHANNEL_TYPE, + 8, + GNB_GPP_PORT8_HOTPLUG_SUPPORT, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_LINK_ASPM, + 0) } }; -PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) +PCIe_DDI_DESCRIPTOR DdiList[] = { +// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeLvds, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) +// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeDP, Aux2, Hdp2} } }; @@ -105,50 +140,57 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // GNB PCIe topology Porting // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR, + // PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + + sizeof(PortList) + + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + Status = HeapAllocateBuffer(&AllocHeapParams, &InitEarly->StdHeader); ASSERT(Status == AGESA_SUCCESS); - BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieComplexListPtr = + (PCIe_COMPLEX_DESCRIPTOR *)AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *)AllocHeapParams.BufferPtr; memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->PciePortList = + (PCIe_PORT_DESCRIPTOR *)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->DdiLinkList = + (PCIe_DDI_DESCRIPTOR *)BrazosPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; return AGESA_SUCCESS; } -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- +/*----------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *----------------------------------------------------------------------------- */ /* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. + * Platform Specific Overriding Table allows IBV/OEM to pass in platform + * information to AGESA (e.g. MemClk routing, the number of DIMM slots + * per channel,...). If PlatformSpecificTable is populated, AGESA will + * base its settings on the data from the table. Otherwise, it will use + * its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), PSO_END }; diff --git a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h index 4132c7c..a713f0d 100644 --- a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h +++ b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h @@ -21,45 +21,85 @@ #include "amdlib.h" #include <cpu/amd/agesa/s3_resume.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port4 + * GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT4_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT4_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT4_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT4_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 +#define GNB_GPP_PORT4_SPEED_MODE 2 +#define GNB_GPP_PORT4_LINK_ASPM 3 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port5 + * GNB_GPP_PORT5_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT5_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT5_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT5_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT5_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 +#define GNB_GPP_PORT5_SPEED_MODE 2 +#define GNB_GPP_PORT5_LINK_ASPM 3 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port6 + * GNB_GPP_PORT6_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT6_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT6_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT6_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT6_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 +#define GNB_GPP_PORT6_SPEED_MODE 2 +#define GNB_GPP_PORT6_LINK_ASPM 3 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port7 + * GNB_GPP_PORT7_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT7_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT7_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT7_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT7_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 +#define GNB_GPP_PORT7_SPEED_MODE 2 +#define GNB_GPP_PORT7_LINK_ASPM 3 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* + * GNB GPP Port8 + * GNB_GPP_PORT8_PORT_PRESENT 0:Disable 1:Enable + * GNB_GPP_PORT8_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 + * GNB_GPP_PORT8_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 + * GNB_GPP_PORT8_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) + * 2:Half-swing(0db) 3:Half-swing(-3.5db) + * 4:extended length(-6db) 5:extended length(-8db) + * GNB_GPP_PORT8_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced + */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 +#define GNB_GPP_PORT8_SPEED_MODE 2 +#define GNB_GPP_PORT8_LINK_ASPM 3 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/elmex/pcm205400/SBCimxPcieReset.h b/src/mainboard/elmex/pcm205400/SBCimxPcieReset.h new file mode 100644 index 0000000..e6c126a --- /dev/null +++ b/src/mainboard/elmex/pcm205400/SBCimxPcieReset.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 ELMEX Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void set_pcie_reset(void); +void set_pcie_dereset(void); diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index fe4e779..fa4fc0d 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -102,8 +102,8 @@ #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 @@ -130,9 +130,9 @@ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST (&OntarioApMtrrSettingsList) +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 //#define BLDCFG_ALLOCATED_BUSNUMS 0x20 @@ -171,12 +171,12 @@ #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //#define BLDCFG_ONLINE_SPARE FALSE //#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE @@ -206,8 +206,7 @@ #include "AGESA.h" /* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, @@ -222,7 +221,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -247,7 +246,8 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * development build from trunk will not be confused for a released version. * The release manager will need to remove the trailing 'X' and update the * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' + * should also be updated/incremented for the next expected version, + * + trailing 'X' ****************************************************************************/ // This is the delivery package title, "BrazosPI" // This string MUST be exactly 8 characters long @@ -255,35 +255,38 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0',\ + '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters + * in which there are no clearly defined defaults to be used in the common + * file. The values below are based on product and BKDG content, please consult + * the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/elmex/pcm205400/devicetree.cb b/src/mainboard/elmex/pcm205400/devicetree.cb index afab841..6269d09 100644 --- a/src/mainboard/elmex/pcm205400/devicetree.cb +++ b/src/mainboard/elmex/pcm205400/devicetree.cb @@ -47,7 +47,8 @@ chip northbridge/amd/agesa/family14/root_complex end end # SM device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 +# HDA is not used on board. + device pci 14.2 off end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/fintek/f81865f device pnp 4e.0 off # Floppy @@ -57,7 +58,8 @@ chip northbridge/amd/agesa/family14/root_complex end device pnp 4e.3 off end # Parallel Port device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard +# Keyboard interface on superI/O is not used. + device pnp 4e.5 off # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c index 0c53417..e4746f7 100644 --- a/src/mainboard/elmex/pcm205400/irq_tables.c +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -100,9 +100,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) sum = pirq->checksum - sum; - if (sum != pirq->checksum) { + if (sum != pirq->checksum) pirq->checksum = sum; - } printk(BIOS_INFO, "write_pirq_routing_table done.\n"); diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index e0440f2..27ee53c 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -29,9 +29,7 @@ #include "SBPLATFORM.h" #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> - -void set_pcie_reset(void); -void set_pcie_dereset(void); +#include "SBCimxPcieReset.h" /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -50,36 +48,36 @@ void set_pcie_dereset(void); */ static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + [0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x08] = 0x00, 0xF0, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ - [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F, /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + [0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, /* IDE, SATA */ - [0x40] = 0x0B,0x0B, + [0x40] = 0x0B, 0x0B, /* GPPInt0 - 3 */ - [0x50] = 0x0A,0x0B,0x0A,0x0B + [0x50] = 0x0A, 0x0B, 0x0A, 0x0B }; static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* USB Devs 18/19/22/20 INTA-C */ - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, /* IDE, SATA */ - [0x40] = 0x11,0x13, + [0x40] = 0x11, 0x13, /* GPPInt0 - 3 */ - [0x50] = 0x10,0x11,0x12,0x13 + [0x50] = 0x10, 0x11, 0x12, 0x13 }; /* @@ -99,30 +97,48 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { * swizzle and INTA is connected to PIRQH so PINA/B/C/D on * off-chip devices should get mapped to PIRQH/E/F/G. */ +/* + * GFX_DEVFN VGA: 01.0 + * NB_PCIE_PORT1_DEVFN NIC: 04.0 + * NB_PCIE_PORT3_DEVFN PCIe bdg: 06.0 + * SATA_DEVFN SATA: 11.0 + * OHCI1_DEVFN OHCI1: 12.0 + * EHCI1_DEVFN EHCI1: 12.2 + * OHCI2_DEVFN OHCI2: 13.0 + * EHCI2_DEVFN EHCI2: 13.2 + * SMBUS_DEVFN SMBUS: 14.0 + * IDE_DEVFN IDE: 14.1 + * HDA_DEVFN HDA: 14.2 + * SB_PCI_PORT_DEVFN PCI bdg: 14.4 + * OHCI4_DEVFN OHCI4: 14.5 + * OHCI3_DEVFN OHCI3: 16.0 + * EHCI3_DEVFN EHCI3: 16.2 + */ static const struct pirq_struct mainboard_pirq_data[] = { /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ - {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ - {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ - {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ - {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC} }, + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC} }, + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G} }, + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, }; /* PIRQ Setup */ static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = sizeof(mainboard_pirq_data) + / sizeof(struct pirq_struct); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } @@ -149,11 +165,13 @@ void set_pcie_dereset(void) **********************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + printk(BIOS_INFO, + "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); /* enable GPP CLK0 thru CLK1 */ /* disable GPP CLK2 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + write8(misc_mem_clk_cntrl + 0, 0xFF); write8(misc_mem_clk_cntrl + 1, 0x00); write8(misc_mem_clk_cntrl + 2, 0x00); diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c index 8e954cd..04a9ade 100644 --- a/src/mainboard/elmex/pcm205400/mptable.c +++ b/src/mainboard/elmex/pcm205400/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); @@ -76,7 +76,8 @@ static void *smp_write_config_table(void *v) * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ + (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* APU Internal Graphic Device */ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); @@ -110,13 +111,18 @@ static void *smp_write_config_table(void *v) /* PCI slots */ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + //INTA -> INTE + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); + //INTB -> INTF + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); + //INTC -> INTG + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); + //INTD -> INTH + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); } /* PCIe PortA */ @@ -128,9 +134,10 @@ static void *smp_write_config_table(void *v) /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE |\ + MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); @@ -143,6 +150,7 @@ static void *smp_write_config_table(void *v) unsigned long write_smp_table(unsigned long addr) { void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ return (unsigned long)smp_write_config_table(v); } diff --git a/src/mainboard/elmex/pcm205400/platform_cfg.h b/src/mainboard/elmex/pcm205400/platform_cfg.h index 660be41..a7de71b 100644 --- a/src/mainboard/elmex/pcm205400/platform_cfg.h +++ b/src/mainboard/elmex/pcm205400/platform_cfg.h @@ -208,8 +208,7 @@ */ #define GEC_CONFIG 0 -static const CODECENTRY persimmon_codec_alc269[] = -{ +static const CODECENTRY persimmon_codec_alc269[] = { /* NID, PinConfig */ {0x12, 0x411111F0}, {0x14, 0x99130110}, @@ -225,10 +224,9 @@ static const CODECENTRY persimmon_codec_alc269[] = {0xff, 0xffffffff} /* end of table */ }; -static const CODECTBLLIST codec_tablelist[] = -{ - {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, - {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} +static const CODECTBLLIST codec_tablelist[] = { + {0x010ec0269, (CODECENTRY *)&persimmon_codec_alc269[0]}, + {0x0FFFFFFFFUL, (CODECENTRY *)0x0FFFFFFFFUL} }; /** diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index 0aad4f5..aef9d04 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -50,11 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + __writemsr(0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); + __writemsr(0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of + * boot time + */ + __writemsr(0xc0010062, 0); amd_initmmio(); @@ -83,6 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); @@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) agesawrapper_amdinitenv(); amd_initenv(); - } else { /* S3 detect */ + } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60);

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coreboot-gerrit July 2016