coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: viatool/quirks: Add newline to end of file
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit aad4587c033d311bb200e27847872ff4282cd642 Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Wed Jul 27 18:20:43 2016 +0200 viatool/quirks: Add newline to end of file Change-Id: If505021c6dd4bc1c98094dc6e4a3da1ea7753859 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/15916 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> See https://review.coreboot.org/15916 for details. -gerrit

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Patch merged into coreboot/master: checkpatch: add .checkpatch.conf
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit 2b119b380fa165a753831157a5e41f966ae31d92 Author: Martin Roth <martinroth(a)chromium.org> Date: Wed Jul 27 11:56:32 2016 -0600 checkpatch: add .checkpatch.conf Try to make checkpatch a little friendlier to the coreboot project. This is the checkpatch .conf from the Chrome OS tree. Change-Id: Ie45d5c93f97bd58f3ea31341b47c4ee2a8f02b1e Signed-off-by: Martin Roth <martinroth(a)chromium.org> Reviewed-on: https://review.coreboot.org/15919 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> See https://review.coreboot.org/15919 for details. -gerrit

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Patch merged into coreboot/master: intel/apollolake: Update gnvs for dptf
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit cd9e1e423f1cf0cf6b38ce51d21e78fc14e9818b Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jul 12 01:22:33 2016 -0700 intel/apollolake: Update gnvs for dptf This patch updates dptf variable in gnvs based on device configuration by reading the device tree structure. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal in Amenia and Reef board. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: I8ab34cdc94d8cdc840b02347569a9f07688e92cd Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Reviewed-on: https://review.coreboot.org/15620 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15620 for details. -gerrit

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Patch merged into coreboot/master: intel/apollolake: Add soc specific DPTF values
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit 5dd2b18540ed5beb272e79820f0d29f88e392b83 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jul 12 00:42:06 2016 -0700 intel/apollolake: Add soc specific DPTF values This patch adds apollolake soc specific change. DPTF ASL files are now in src/soc/intel/common so that they can be reused but different soc can have different values e.g., for skylake cpu soc thermal reporting device is at Bus 0, Device 4, Function 0 while for apollolake it is Bus 0, Device 0, Function 1. This patch adds a dptf asl file in soc directory where we can define all values which can change across soc's and can be included in mainboard dptf asl. BUG=chrome-os-partner:53096 TEST=In Amenia and Reef board verify that the thermal zones are enumerated under /sys/class/thermal in Amenia and Reef board. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: I888260a9c799d36512411a769f26dd30cf8d5788 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Reviewed-on: https://review.coreboot.org/15619 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/15619 for details. -gerrit

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Patch merged into coreboot/master: intel/common: Add ASL code for DPTF
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit 44887c3e36821379d6091812b83e1b7ff9f9af53 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jun 7 00:05:00 2016 -0700 intel/common: Add ASL code for DPTF This patch adds the common ASL code for Intel platforms. This is the basic ASL needed to add support for DPTF controlled devices. We are moving these commmon ASL files to src/soc/intel/common/acpi as these are same codes used in all Intel platforms and hence no need to duplicate. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: I01078382a9008263c6ad99f6bf07558885af6a63 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Reviewed-on: https://review.coreboot.org/15093 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/15093 for details. -gerrit

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Patch merged into coreboot/master: Documentation: Capitalize RAM, ROM and ACPI
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit e51387896ffa1c9a7337e9cd46f6b5f83c3b5deb Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 28 13:08:24 2016 +0200 Documentation: Capitalize RAM, ROM and ACPI Change-Id: I06c1d0fe0e3d429e54d3777de679f9fc641f4eed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/15927 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/15927 for details. -gerrit

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Patch set updated for coreboot: google/reef: Enable DPTF in mainboard
by Shaunak Saha 28 Jul '16

28 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15640 -gerrit commit fa55471974fe19aea7d399b8e9df8133de27c32f Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jul 12 16:03:29 2016 -0700 google/reef: Enable DPTF in mainboard This patch enables DPTF support for Google Reef platform, adds the ASL settings specific to Reef boards. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal in Reef boards. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: Ib43e4e9dd0d92fffc1b2c8459c552acd04ca0150 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/google/reef/acpi/dptf.asl | 94 +++++++++++++++++++++++++++++++++ src/mainboard/google/reef/devicetree.cb | 3 ++ src/mainboard/google/reef/dsdt.asl | 5 ++ 3 files changed, 102 insertions(+) diff --git a/src/mainboard/google/reef/acpi/dptf.asl b/src/mainboard/google/reef/acpi/dptf.asl new file mode 100644 index 0000000..35bbecb --- /dev/null +++ b/src/mainboard/google/reef/acpi/dptf.asl @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 6000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include soc specific DPTF changes */ +#include <soc/intel/apollolake/acpi/dptf.asl> +/* Include common dptf ASL files */ +#include <soc/intel/common/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index a04a3cd..0763a6d 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -31,6 +31,9 @@ chip soc/intel/apollolake # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 register "emmc_rx_cmd_data_cntl2" = "0x1001C" + # Enable DPTF + register "dptf_enable" = "1" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route, i.e., if this route changes then the affected GPE diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 7a88fb6..c035371 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -46,4 +46,9 @@ DefinitionBlock( /* Mainboard Specific devices */ #include "acpi/mainboard.asl" + + Scope (\_SB) { + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } }

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Patch merged into coreboot/master: intel/common/opregion.c: only write 16 bytes to 16 byte field
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit 2098778726a209b3a9465b203a3fdb72c45706c0 Author: Martin Roth <martinroth(a)google.com> Date: Mon Jul 25 16:14:25 2016 -0600 intel/common/opregion.c: only write 16 bytes to 16 byte field Including the terminating null, 17 characters were being written to the field, overwriting the a byte of the size field. Fortunately, the size was updated soon after this. Fixes coverity warning 1229570 - Destination buffer too small. Change-Id: I39285a9283dd9a17d638afe5b2755c7e420d7698 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/15889 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/15889 for details. -gerrit

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Patch set updated for coreboot: src/cpu: Capitalize ROM and RAM
by HAOUAS Elyes 28 Jul '16

28 Jul '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15935 -gerrit commit 2802e66cb1f99c2bcf9a55b6359be6824b1b5a64 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 28 19:15:34 2016 +0200 src/cpu: Capitalize ROM and RAM Change-Id: I103167a0c39627bcd2ca1d0d4288eb5df02a6cd2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/cpu/amd/agesa/cache_as_ram.inc | 2 +- src/cpu/amd/car/post_cache_as_ram.c | 2 +- src/cpu/amd/geode_gx2/cache_as_ram.inc | 2 +- src/cpu/amd/geode_lx/cache_as_ram.inc | 2 +- src/cpu/amd/pi/cache_as_ram.inc | 2 +- src/cpu/intel/haswell/cache_as_ram.inc | 2 +- src/cpu/intel/haswell/romstage.c | 6 +++--- src/cpu/intel/haswell/stage_cache.c | 2 +- src/cpu/intel/model_206ax/cache_as_ram.inc | 2 +- src/cpu/x86/16bit/entry16.inc | 2 +- src/cpu/x86/16bit/reset16.ld | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 2 +- 12 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 80344ce..293e9a5 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -80,7 +80,7 @@ cache_as_ram_setup: movl $0xc00000e3, 0x18(%edi) movl %eax, 0x1c(%edi) - # load rom based identity mapped page tables + # load ROM based identity mapped page tables mov %ecx, %eax mov %eax, %cr3 diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index ad5a5c7..19aa0a2 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -166,7 +166,7 @@ void post_cache_as_ram(void) void cache_as_ram_new_stack (void) { - print_car_debug("Disabling cache as ram now\n"); + print_car_debug("Disabling cache as RAM now\n"); disable_cache_as_ram_bsp(); disable_cache(); diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index bd9de28..c31b95d 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -171,7 +171,7 @@ done_cache_as_ram_main: pop %esi pop %edi - /* Clear the cache out to ram */ + /* Clear the cache out to RAM */ wbinvd /* re-enable the cache */ movl %cr0, %eax diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index cbc5cb8..d48f0e8 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -198,7 +198,7 @@ done_cache_as_ram_main: pop %esi pop %edi - /* Clear the cache out to ram */ + /* Clear the cache out to RAM */ wbinvd /* re-enable the cache */ movl %cr0, %eax diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc index fd5e66d..40ec1b2 100644 --- a/src/cpu/amd/pi/cache_as_ram.inc +++ b/src/cpu/amd/pi/cache_as_ram.inc @@ -81,7 +81,7 @@ cache_as_ram_setup: movl $0xc00000e3, 0x18(%edi) movl %eax, 0x1c(%edi) - # load rom based identity mapped page tables + # load ROM based identity mapped page tables mov %ecx, %eax mov %eax, %cr3 diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 9cdb176..276b9c3 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -145,7 +145,7 @@ clear_mtrrs: wrmsr post_code(0x27) - /* Enable caching for ram init code to run faster */ + /* Enable caching for RAM init code to run faster */ movl $MTRR_PHYS_BASE(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index a05d570..8b62d43 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -113,8 +113,8 @@ static void *setup_romstage_stack_after_car(void) num_mtrrs++; top_of_ram = (uint32_t)cbmem_top(); - /* Cache 8MiB below the top of ram. On haswell systems the top of - * ram under 4GiB is the start of the TSEG region. It is required to + /* Cache 8MiB below the top of RAM. On haswell systems the top of + * RAM under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later * for ramstage before setting up the entire RAM as cacheable. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ @@ -123,7 +123,7 @@ static void *setup_romstage_stack_after_car(void) slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); num_mtrrs++; - /* Cache 8MiB at the top of ram. Top of ram on haswell systems + /* Cache 8MiB at the top of RAM. Top of RAM on haswell systems * is where the TSEG region resides. However, it is not restricted * to SMM mode until SMM has been relocated. By setting the region * to cacheable it provides faster access when relocating the SMM diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c index ee945c7..009cc09 100644 --- a/src/cpu/intel/haswell/stage_cache.c +++ b/src/cpu/intel/haswell/stage_cache.c @@ -20,7 +20,7 @@ void stage_cache_external_region(void **base, size_t *size) { /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of ram is defined to be the TSEG base address. */ + * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); } diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 702881d..6702155 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -147,7 +147,7 @@ clear_mtrrs: wrmsr post_code(0x27) - /* Enable caching for ram init code to run faster */ + /* Enable caching for RAM init code to run faster */ movl $MTRR_PHYS_BASE(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 4c0d323..b4db834 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -95,7 +95,7 @@ _start16bit: * * Also load an IDT with NULL limit to prevent the 16bit IDT being used * in protected mode before c_start.S sets up a 32bit IDT when entering - * ram stage. In practise: CPU will shutdown on any exception. + * RAM stage. In practise: CPU will shutdown on any exception. * See IA32 manual Vol 3A 19.26 Interrupts. */ diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index d96755e..e630ce5 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -1,5 +1,5 @@ /* - * _ROMTOP : The top of the rom used where we + * _ROMTOP : The top of the ROM used where we * need to put the reset vector. */ diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 1abc28f..ea492dd 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -88,7 +88,7 @@ static void copy_secondary_start_to_lowest_1M(void) memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size); } - /* copy the _secondary_start to the ram below 1M*/ + /* copy the _secondary_start to the RAM below 1M*/ memcpy((unsigned char *)AP_SIPI_VECTOR, (unsigned char *)_secondary_start, code_size); printk(BIOS_DEBUG, "start_eip=0x%08lx, code_size=0x%08lx\n",

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New patch to review for coreboot: src/cpu: Capitalize ROM and RAM
by HAOUAS Elyes 28 Jul '16

28 Jul '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15935 -gerrit commit 0e7a108af5d907916f2481e0fc6210069feb12db Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 28 19:15:34 2016 +0200 src/cpu: Capitalize ROM and RAM Change-Id: I103167a0c39627bcd2ca1d0d4288eb5df02a6cd2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/cpu/amd/agesa/cache_as_ram.inc | 2 +- src/cpu/amd/car/post_cache_as_ram.c | 2 +- src/cpu/amd/geode_gx2/cache_as_ram.inc | 2 +- src/cpu/amd/geode_lx/cache_as_ram.inc | 2 +- src/cpu/amd/geode_lx/msrinit.c | 2 +- src/cpu/amd/pi/cache_as_ram.inc | 2 +- src/cpu/intel/haswell/cache_as_ram.inc | 2 +- src/cpu/intel/haswell/romstage.c | 6 +++--- src/cpu/intel/haswell/stage_cache.c | 2 +- src/cpu/intel/model_206ax/cache_as_ram.inc | 2 +- src/cpu/x86/16bit/entry16.inc | 2 +- src/cpu/x86/16bit/reset16.ld | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 2 +- 13 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 80344ce..293e9a5 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -80,7 +80,7 @@ cache_as_ram_setup: movl $0xc00000e3, 0x18(%edi) movl %eax, 0x1c(%edi) - # load rom based identity mapped page tables + # load ROM based identity mapped page tables mov %ecx, %eax mov %eax, %cr3 diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index ad5a5c7..19aa0a2 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -166,7 +166,7 @@ void post_cache_as_ram(void) void cache_as_ram_new_stack (void) { - print_car_debug("Disabling cache as ram now\n"); + print_car_debug("Disabling cache as RAM now\n"); disable_cache_as_ram_bsp(); disable_cache(); diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index bd9de28..c31b95d 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -171,7 +171,7 @@ done_cache_as_ram_main: pop %esi pop %edi - /* Clear the cache out to ram */ + /* Clear the cache out to RAM */ wbinvd /* re-enable the cache */ movl %cr0, %eax diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index cbc5cb8..d48f0e8 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -198,7 +198,7 @@ done_cache_as_ram_main: pop %esi pop %edi - /* Clear the cache out to ram */ + /* Clear the cache out to RAM */ wbinvd /* re-enable the cache */ movl %cr0, %eax diff --git a/src/cpu/amd/geode_lx/msrinit.c b/src/cpu/amd/geode_lx/msrinit.c index e6e6247..178f77d 100644 --- a/src/cpu/amd/geode_lx/msrinit.c +++ b/src/cpu/amd/geode_lx/msrinit.c @@ -42,7 +42,7 @@ static const msrinit_t msr_table[] = * currently 1Mb. * These registers will be set to their correct value by the Northbridge init code. * - * WARNING: if ramstage could not be loaded, these registers are probably + * WARNING: if RAMstage could not be loaded, these registers are probably * incorrectly set here. You may comment the following two lines and set RAMBASE * to 0x4000 to revert to the previous behavior for LX-boards. */ diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc index fd5e66d..40ec1b2 100644 --- a/src/cpu/amd/pi/cache_as_ram.inc +++ b/src/cpu/amd/pi/cache_as_ram.inc @@ -81,7 +81,7 @@ cache_as_ram_setup: movl $0xc00000e3, 0x18(%edi) movl %eax, 0x1c(%edi) - # load rom based identity mapped page tables + # load ROM based identity mapped page tables mov %ecx, %eax mov %eax, %cr3 diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 9cdb176..276b9c3 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -145,7 +145,7 @@ clear_mtrrs: wrmsr post_code(0x27) - /* Enable caching for ram init code to run faster */ + /* Enable caching for RAM init code to run faster */ movl $MTRR_PHYS_BASE(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index a05d570..8b62d43 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -113,8 +113,8 @@ static void *setup_romstage_stack_after_car(void) num_mtrrs++; top_of_ram = (uint32_t)cbmem_top(); - /* Cache 8MiB below the top of ram. On haswell systems the top of - * ram under 4GiB is the start of the TSEG region. It is required to + /* Cache 8MiB below the top of RAM. On haswell systems the top of + * RAM under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later * for ramstage before setting up the entire RAM as cacheable. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ @@ -123,7 +123,7 @@ static void *setup_romstage_stack_after_car(void) slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); num_mtrrs++; - /* Cache 8MiB at the top of ram. Top of ram on haswell systems + /* Cache 8MiB at the top of RAM. Top of RAM on haswell systems * is where the TSEG region resides. However, it is not restricted * to SMM mode until SMM has been relocated. By setting the region * to cacheable it provides faster access when relocating the SMM diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c index ee945c7..009cc09 100644 --- a/src/cpu/intel/haswell/stage_cache.c +++ b/src/cpu/intel/haswell/stage_cache.c @@ -20,7 +20,7 @@ void stage_cache_external_region(void **base, size_t *size) { /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of ram is defined to be the TSEG base address. */ + * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); } diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 702881d..6702155 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -147,7 +147,7 @@ clear_mtrrs: wrmsr post_code(0x27) - /* Enable caching for ram init code to run faster */ + /* Enable caching for RAM init code to run faster */ movl $MTRR_PHYS_BASE(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 4c0d323..b4db834 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -95,7 +95,7 @@ _start16bit: * * Also load an IDT with NULL limit to prevent the 16bit IDT being used * in protected mode before c_start.S sets up a 32bit IDT when entering - * ram stage. In practise: CPU will shutdown on any exception. + * RAM stage. In practise: CPU will shutdown on any exception. * See IA32 manual Vol 3A 19.26 Interrupts. */ diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index d96755e..e630ce5 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -1,5 +1,5 @@ /* - * _ROMTOP : The top of the rom used where we + * _ROMTOP : The top of the ROM used where we * need to put the reset vector. */ diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 1abc28f..ea492dd 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -88,7 +88,7 @@ static void copy_secondary_start_to_lowest_1M(void) memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size); } - /* copy the _secondary_start to the ram below 1M*/ + /* copy the _secondary_start to the RAM below 1M*/ memcpy((unsigned char *)AP_SIPI_VECTOR, (unsigned char *)_secondary_start, code_size); printk(BIOS_DEBUG, "start_eip=0x%08lx, code_size=0x%08lx\n",

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coreboot-gerrit July 2016