coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

1 participants
1820 discussions

New patch to review for coreboot: board id gpios
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15562 -gerrit commit 7297fb85b253d4e0127bb46acbc3bfb5ed643fa4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 23:16:01 2016 -0500 board id gpios Change-Id: I9cac82158e70e0af1b454ec4581c2e4622b95b4b --- src/mainboard/google/reef/mainboard.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 2b121ef..588c739 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -14,6 +14,7 @@ */ #include <arch/acpi.h> +#include <boardid.h> #include <console/console.h> #include <device/device.h> #include <nhlt.h> @@ -24,6 +25,11 @@ static void mainboard_init(void *chip_info) { + int boardid; + + boardid = board_id(); + printk(BIOS_INFO, "Board ID: %d\n", boardid); + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); mainboard_ec_init(); }

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Patch set updated for coreboot: mainboard/google/reef: add board_id() support
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15561 -gerrit commit e7e75fa7a537f51941efb57a63aebaf87e850d30 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:53:51 2016 -0500 mainboard/google/reef: add board_id() support The board build version is provided by the EC on reef. Provide the necessary functional support for coreboot to differentiate the board versions. BUG=chrome-os-partner:54959,chrome-os-partner:54960 BRANCH=None TEST=Built and tested on reef. Change-Id: I1b7e8b2f4142753cde736148ca9495bcc625f318 Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/mainboard/google/reef/Makefile.inc | 2 ++ src/mainboard/google/reef/boardid.c | 28 ++++++++++++++++++++++++++++ src/mainboard/google/reef/gpio.h | 8 ++++---- 3 files changed, 34 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc index f8fbbf3..6db0f2f 100644 --- a/src/mainboard/google/reef/Makefile.inc +++ b/src/mainboard/google/reef/Makefile.inc @@ -2,7 +2,9 @@ bootblock-y += bootblock.c bootblock-y += ec.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += boardid.c +ramstage-y += boardid.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/reef/boardid.c b/src/mainboard/google/reef/boardid.c new file mode 100644 index 0000000..4eb9f48 --- /dev/null +++ b/src/mainboard/google/reef/boardid.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + +uint8_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) + id = google_chromeec_get_board_version(); + + return id; +} diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index d541a34..14cf880c 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -243,8 +243,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */ - PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- unused */ - PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- unused */ + PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */ /* SIO_SPI_0 - Used for FP */ @@ -312,7 +312,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_37, UP_20K, DEEP), /* unused */ /* LPSS_UART[0:2] */ - PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - unused */ + PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - MEM_CONFIG2*/ /* Next 2 are straps. */ PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ @@ -320,7 +320,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */ - PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1), /* LPSS_UART1_CTS */ + PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */

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New patch to review for coreboot: mainboard/google/reef: add board_id() support
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15561 -gerrit commit 146dd7e9cfeda9530faebe266ffe264aa6905e07 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:53:51 2016 -0500 mainboard/google/reef: add board_id() support The board build version is provided by the EC on reef. Provide the necessary functional support for coreboot to differentiate the board versions. BUG=chrome-os-partner:54959,chrome-os-partner:54960 BRANCH=None TEST=Built and tested on reef. Change-Id: I1b7e8b2f4142753cde736148ca9495bcc625f318 Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/mainboard/google/reef/Makefile.inc | 2 ++ src/mainboard/google/reef/boardid.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc index f8fbbf3..6db0f2f 100644 --- a/src/mainboard/google/reef/Makefile.inc +++ b/src/mainboard/google/reef/Makefile.inc @@ -2,7 +2,9 @@ bootblock-y += bootblock.c bootblock-y += ec.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += boardid.c +ramstage-y += boardid.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/reef/boardid.c b/src/mainboard/google/reef/boardid.c new file mode 100644 index 0000000..4eb9f48 --- /dev/null +++ b/src/mainboard/google/reef/boardid.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + +uint8_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) + id = google_chromeec_get_board_version(); + + return id; +}

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New patch to review for coreboot: mainboard/google/reef: add memory SKU id support
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15560 -gerrit commit c6ea41e1a3bcd69bc11eeff604c32c6079b54594 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:51:05 2016 -0500 mainboard/google/reef: add memory SKU id support While the proto boards didn't have a memory SKU notion the EVT boards do. Therefore, provide support for selecting the proper memory SKU information based on the memory id straps. This works on EVT boards because the pins used for the strapping weren't used on proto. However, internal pullups need to be enabled so that proto boards read the correct id. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: I8653260e5d1b9adc83b78ea2770c683b72535e11 Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/mainboard/google/reef/gpio.h | 10 ++++++ src/mainboard/google/reef/romstage.c | 66 +++++++++++++++++++++++++++++++----- 2 files changed, 68 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 91e8bb1..d541a34 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -346,5 +346,15 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ }; +/* + * The proto boards didn't have memory SKU pins, but the same ones can be + * utilized as post proto boards because the pins used were never connected + * or no peripheral utilized the signals on proto boards. + */ +#define MEM_CONFIG3 GPIO_45 +#define MEM_CONFIG2 GPIO_38 +#define MEM_CONFIG1 GPIO_102 +#define MEM_CONFIG0 GPIO_101 + #endif /* __ACPI__ */ #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index ecf6fa5..e1d8c57 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -13,8 +13,10 @@ * GNU General Public License for more details. */ +#include <gpio.h> #include <soc/meminit.h> #include <soc/romstage.h> +#include "gpio.h" static const struct lpddr4_swizzle_cfg board_swizzle = { /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ @@ -60,15 +62,63 @@ static const struct lpddr4_swizzle_cfg board_swizzle = { }, }; +/* + * Proto boards didn't have a memory SKU id. The configuration pins use + * an internal weak pullup with stronger pulldowns for the 0 bits. As + * proto boards didn't use the memory SKU pins the sku id reads as 4'b1111, + * i.e. 15. + */ +#define PROTO_SKU 15 + +static const struct lpddr4_sku skus[] = { + /* K4F6E304HB-MGCJ - both logical channels */ + [0] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_16Gb_DENSITY, + .ch1_density = LP4_16Gb_DENSITY, + }, + /* K4F8E304HB-MGCJ - both logical channels */ + [1] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_8Gb_DENSITY, + .ch1_density = LP4_8Gb_DENSITY, + }, + /* MT53B512M32D2NP-062WT:C - both logical channels */ + [2] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_16Gb_DENSITY, + .ch1_density = LP4_16Gb_DENSITY, + /* MT53B256M32D1NP-062 WT:C - both logical channels */ + }, + [3] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_8Gb_DENSITY, + .ch1_density = LP4_8Gb_DENSITY, + }, + /* K4F8E304HB-MGCH - both logical channels */ + [PROTO_SKU] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_8Gb_DENSITY, + .ch1_density = LP4_8Gb_DENSITY, + }, +}; + +static const struct lpddr4_cfg lp4cfg = { + .skus = skus, + .num_skus = ARRAY_SIZE(skus), + .swizzle_config = &board_swizzle, +}; + void mainboard_memory_init_params(struct FSPM_UPD *memupd) { - struct FSP_M_CONFIG *cfg = &memupd->FspmConfig; + int mem_sku; + gpio_t pads[] = { MEM_CONFIG3, MEM_CONFIG2, MEM_CONFIG1, MEM_CONFIG0 }; + + /* + * Read memory SKU id with internal pullups enabled to handle + * proto boards with no SKU id pins. + */ + mem_sku = gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); - /* Use a default 2400 speed. */ - meminit_lpddr4(cfg, LP4_SPEED_2400); - /* Enable both logical channels with a 8Gb density. */ - meminit_lpddr4_enable_channel(cfg, LP4_LCH0, LP4_8Gb_DENSITY, - &board_swizzle); - meminit_lpddr4_enable_channel(cfg, LP4_LCH1, LP4_8Gb_DENSITY, - &board_swizzle); + meminit_lpddr4_by_sku(&memupd->FspmConfig, &lp4cfg, mem_sku); }

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New patch to review for coreboot: soc/intel/apollolake: add LPDDR4 sku selection support
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15559 -gerrit commit dd4b17816c0816f99714f3a81a7d60d16735c59f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:45:57 2016 -0500 soc/intel/apollolake: add LPDDR4 sku selection support Instead of having all the mainboards put similar logic into their own code provide common mechansim for memory SKU selection. A function, meminit_lpddr4_by_sku(), is added that selects the proper configuration based on the SKU id and configuration passed in. LPDDR4 speed as well as DRAM device density configuration is associated for each logical channel per SKU id. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: Ifc6a734040bb61a58bc3d4c128a6420a71245c6c Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/soc/intel/apollolake/include/soc/meminit.h | 20 ++++++++++++++++ src/soc/intel/apollolake/meminit.c | 32 ++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index 14b1ef5..94c9032 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -16,6 +16,7 @@ #ifndef _SOC_APOLLOLAKE_MEMINIT_H_ #define _SOC_APOLLOLAKE_MEMINIT_H_ +#include <stddef.h> #include <stdint.h> /* @@ -94,4 +95,23 @@ void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan, int device_density, const struct lpddr4_swizzle_cfg *scfg); +struct lpddr4_sku { + int speed; + int ch0_density; + int ch1_density; +}; + +struct lpddr4_cfg { + const struct lpddr4_sku *skus; + size_t num_skus; + const struct lpddr4_swizzle_cfg *swizzle_config; +}; + +/* + * Initialize LPDDR4 settings by the provided lpddr4_cfg information and sku id. + * The sku id is an index into the sku array within the lpddr4_cfg struct. + */ +void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, + const struct lpddr4_cfg *lpcfg, size_t sku_id); + #endif /* _SOC_APOLLOLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 8b661c9..8954769 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -211,3 +211,35 @@ void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan, break; } } + +void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, + const struct lpddr4_cfg *lpcfg, size_t sku_id) +{ + const struct lpddr4_sku *sku; + + if (sku_id >= lpcfg->num_skus) { + printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n", + sku_id, lpcfg->num_skus); + return; + } + + printk(BIOS_INFO, "LPDDR4 SKU id = 0x%zx\n", sku_id); + + sku = &lpcfg->skus[sku_id]; + + meminit_lpddr4(cfg, sku->speed); + + if (sku->ch0_density) { + printk(BIOS_INFO, "LPDDR4 Ch0 density = %d\n", + sku->ch0_density); + meminit_lpddr4_enable_channel(cfg, LP4_LCH0, sku->ch0_density, + lpcfg->swizzle_config); + } + + if (sku->ch1_density) { + printk(BIOS_INFO, "LPDDR4 Ch1 density = %d\n", + sku->ch1_density); + meminit_lpddr4_enable_channel(cfg, LP4_LCH1, sku->ch1_density, + lpcfg->swizzle_config); + } +}

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New patch to review for coreboot: soc/intel/apollolake: make internal pulls weak for gpio inputs
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15558 -gerrit commit 5beb28b345529f5a17157a87e5e7fb86d7e6ee66 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:41:24 2016 -0500 soc/intel/apollolake: make internal pulls weak for gpio inputs The internal pulls for gpio_input_pullup() and gpio_input_pulldown() were using fairly strong pulls. Weaken them so that external pulls can override the internal ones. This matches the current assumptions of lib/gpio.c. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: Ifda1d04d40141325f78db277eb0bd55574994abf Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/soc/intel/apollolake/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index 525c972..699c8fe 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -71,13 +71,13 @@ void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) void gpio_input_pulldown(gpio_t gpio) { - struct pad_config cfg = PAD_CFG_GPI(gpio, DN_5K, DEEP); + struct pad_config cfg = PAD_CFG_GPI(gpio, DN_20K, DEEP); gpio_configure_pad(&cfg); } void gpio_input_pullup(gpio_t gpio) { - struct pad_config cfg = PAD_CFG_GPI(gpio, UP_5K, DEEP); + struct pad_config cfg = PAD_CFG_GPI(gpio, UP_20K, DEEP); gpio_configure_pad(&cfg); }

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New patch to review for coreboot: lib/gpio: add pullup & pulldown gpio_base2_value() variants
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15557 -gerrit commit 6816e68e0994c1e1e0cd3e547d9a268eefcbcb35 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:37:10 2016 -0500 lib/gpio: add pullup & pulldown gpio_base2_value() variants Provide common implementations for gpio_base2_value() variants which configure the gpio for internal pullups and pulldowns. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: I9be8813328e99d28eb4145501450caab25d51f37 Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/include/gpio.h | 5 +++++ src/lib/gpio.c | 35 +++++++++++++++++++++++++++++++---- 2 files changed, 36 insertions(+), 4 deletions(-) diff --git a/src/include/gpio.h b/src/include/gpio.h index 69a0828..3a8951c 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -56,8 +56,13 @@ uint16_t gpio_acpi_pin(gpio_t gpio); * * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1]. * num_gpio: number of pins to read. + * + * There are also pulldown and pullup variants which default each gpio to + * be configured with an internal pulldown and pullup, respectively. */ int gpio_base2_value(gpio_t gpio[], int num_gpio); +int gpio_pulldown_base2_value(gpio_t gpio[], int num_gpio); +int gpio_pullup_base2_value(gpio_t gpio[], int num_gpio); /* * Read the value presented by the set of GPIOs, when each pin is interpreted diff --git a/src/lib/gpio.c b/src/lib/gpio.c index 81d6f6b..03cc455 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -19,13 +19,10 @@ #include <delay.h> #include <gpio.h> -int gpio_base2_value(gpio_t gpio[], int num_gpio) +static int _gpio_base2_value(gpio_t gpio[], int num_gpio) { int i, result = 0; - for (i = 0; i < num_gpio; i++) - gpio_input(gpio[i]); - /* Wait until signals become stable */ udelay(10); @@ -35,6 +32,36 @@ int gpio_base2_value(gpio_t gpio[], int num_gpio) return result; } +int gpio_base2_value(gpio_t gpio[], int num_gpio) +{ + int i; + + for (i = 0; i < num_gpio; i++) + gpio_input(gpio[i]); + + return _gpio_base2_value(gpio, num_gpio); +} + +int gpio_pulldown_base2_value(gpio_t gpio[], int num_gpio) +{ + int i; + + for (i = 0; i < num_gpio; i++) + gpio_input_pulldown(gpio[i]); + + return _gpio_base2_value(gpio, num_gpio); +} + +int gpio_pullup_base2_value(gpio_t gpio[], int num_gpio) +{ + int i; + + for (i = 0; i < num_gpio; i++) + gpio_input_pullup(gpio[i]); + + return _gpio_base2_value(gpio, num_gpio); +} + int _gpio_base3_value(gpio_t gpio[], int num_gpio, int binary_first) { /*

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Patch set updated for coreboot: drivers/i2c/da7219: Add driver for generating device in SSDT
by Duncan Laurie 07 Jul '16

07 Jul '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15538 -gerrit commit 4cedc27a4439daf8a27fd2a250b27567e88eeb6f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jul 2 20:00:56 2016 -0700 drivers/i2c/da7219: Add driver for generating device in SSDT Add a device driver to generate the device and required properties into the SSDT. This driver uses the ACPI Device Property interface to generate the required parameters into the _DSD table format expected by the kernel. This was tested on the reef mainboard to ensure that the SSDT contained the equivalent parameters that are provided by the current DSDT object. Change-Id: Ia809e953932a7e127352a7ef193974d95e511565 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/i2c/da7219/Kconfig | 2 + src/drivers/i2c/da7219/Makefile.inc | 1 + src/drivers/i2c/da7219/chip.h | 106 +++++++++++++++++++++++++++++++ src/drivers/i2c/da7219/da7219.c | 122 ++++++++++++++++++++++++++++++++++++ 4 files changed, 231 insertions(+) diff --git a/src/drivers/i2c/da7219/Kconfig b/src/drivers/i2c/da7219/Kconfig new file mode 100644 index 0000000..5539af1 --- /dev/null +++ b/src/drivers/i2c/da7219/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_DA7219 + bool diff --git a/src/drivers/i2c/da7219/Makefile.inc b/src/drivers/i2c/da7219/Makefile.inc new file mode 100644 index 0000000..354a330 --- /dev/null +++ b/src/drivers/i2c/da7219/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_DA7219) += da7219.c diff --git a/src/drivers/i2c/da7219/chip.h b/src/drivers/i2c/da7219/chip.h new file mode 100644 index 0000000..823b940 --- /dev/null +++ b/src/drivers/i2c/da7219/chip.h @@ -0,0 +1,106 @@ +#include <arch/acpi_device.h> + +/* + * Dialog Semiconductor DA7219 Audio Codec devicetree bindings + * linux/Documentation/devicetree/bindings/sound/da7219.txt + */ +struct drivers_i2c_da7219_config { + /* Interrupt configuration */ + struct acpi_irq irq; + + /* I2C Bus Frequency in Hertz (default 400kHz) */ + unsigned bus_speed; + + /* + * micbias-lvl : Voltage (mV) for Mic Bias + * [<1600>, <1800>, <2000>, <2200>, <2400>, <2600>] + */ + unsigned micbias_lvl; + + /* + * mic-amp-in-sel : Mic input source type + * ["diff", "se_p", "se_n"] + */ + const char *mic_amp_in_sel; + + /* + * Properties for da7219_aad child node + */ + + /* + * micbias-pulse-lvl : Mic bias higher voltage pulse level (mV) + * [<2800>, <2900>] + */ + unsigned micbias_pulse_lvl; + + /* + * micbias-pulse-time : Mic bias higher voltage pulse duration (ms) + */ + unsigned micbias_pulse_time; + + /* + * btn-cfg : Periodic button press measurements for 4-pole jack (ms) + * [<2>, <5>, <10>, <50>, <100>, <200>, <500>] + */ + unsigned btn_cfg; + + /* + * mic-det-thr : Impedance threshold for mic detection measurement (Ohms) + * [<200>, <500>, <750>, <1000>] + */ + unsigned mic_det_thr; + + /* + * jack-ins-deb : Debounce time for jack insertion (ms) + * [<5>, <10>, <20>, <50>, <100>, <200>, <500>, <1000>] + */ + unsigned jack_ins_deb; + + /* + * jack-det-rate : Jack type detection latency (3/4 pole) + * ["32ms_64ms", "64ms_128ms", "128ms_256ms", "256ms_512ms"] + */ + const char *jack_det_rate; + + /* + * jack-rem-deb : Debounce time for jack removal (ms) + * [<1>, <5>, <10>, <20>] + */ + unsigned jack_rem_deb; + + /* + * a-d-btn-thr : Impedance threshold between buttons A and D + * [0x0 - 0xFF] + */ + unsigned a_d_btn_thr; + + /* + * d-b-btn-thr : Impedance threshold between buttons D and B + * [0x0 - 0xFF] + */ + unsigned d_b_btn_thr; + + /* + * b-c-btn-thr : Impedance threshold between buttons B and C + * [0x0 - 0xFF] + */ + unsigned b_c_btn_thr; + + /* + * c-mic-btn-thr : Impedance threshold between button C and Mic + * [0x0 - 0xFF] + */ + unsigned c_mic_btn_thr; + + /* + * btn-avg : Number of 8-bit readings for averaged button measurement + * [<1>, <2>, <4>, <8>] + */ + unsigned btn_avg; + + /* + * adc-1bit-rpt : Repeat count for 1-bit button measurement + * [<1>, <2>, <4>, <8>] + */ + unsigned adc_1bit_rpt; +}; diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c new file mode 100644 index 0000000..b29a4a1 --- /dev/null +++ b/src/drivers/i2c/da7219/da7219.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +#define DA7219_ACPI_NAME "DLG7" +#define DA7219_ACPI_HID "DLGS7219" + +static void da7219_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_da7219_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dsd, *aad; + + if (!dev->enabled || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", DA7219_ACPI_HID); + acpigen_write_name_integer("_UID", 1); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_name_integer("_S0W", 4); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpi_device_write_interrupt(&config->irq); + acpigen_write_resourcetemplate_footer(); + + /* AAD Child Device Properties */ + aad = acpi_dp_new_table("DAAD"); + acpi_dp_add_integer(aad, "dlg,btn-cfg", config->btn_cfg); + acpi_dp_add_integer(aad, "dlg,mic-det-thr", config->mic_det_thr); + acpi_dp_add_integer(aad, "dlg,jack-ins-deb", config->jack_ins_deb); + acpi_dp_add_string(aad, "dlg,jack-det-rate", config->jack_det_rate); + acpi_dp_add_integer(aad, "dlg,jack-rem-deb", config->jack_rem_deb); + acpi_dp_add_integer(aad, "dlg,a-d-btn-thr", config->a_d_btn_thr); + acpi_dp_add_integer(aad, "dlg,d-b-btn-thr", config->d_b_btn_thr); + acpi_dp_add_integer(aad, "dlg,b-c-btn-thr", config->b_c_btn_thr); + acpi_dp_add_integer(aad, "dlg,c-mic-btn-thr", config->c_mic_btn_thr); + acpi_dp_add_integer(aad, "dlg,btn-avg", config->btn_avg); + acpi_dp_add_integer(aad, "dlg,adc-1bit-rpt", config->adc_1bit_rpt); + acpi_dp_add_integer(aad, "dlg,micbias-pulse-lvl", + config->micbias_pulse_lvl); + acpi_dp_add_integer(aad, "dlg,micbias-pulse-time", + config->micbias_pulse_time); + + /* DA7219 Properties */ + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_integer(dsd, "dlg,micbias-lvl", config->micbias_lvl); + acpi_dp_add_string(dsd, "dlg,mic-amp-in-sel", config->mic_amp_in_sel); + acpi_dp_add_child(dsd, "da7219_aad", aad); + + /* Write Device Property Hierarchy */ + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s address 0%xh irq %d\n", + acpi_device_path(dev), dev->chip_ops->name, + dev->path.i2c.device, config->irq.pin); +} + +static const char *da7219_acpi_name(struct device *dev) +{ + return DA7219_ACPI_NAME; +} +#endif + +static struct device_operations da7219_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &da7219_acpi_name, + .acpi_fill_ssdt_generator = &da7219_fill_ssdt, +#endif +}; + +static void da7219_enable(struct device *dev) +{ + dev->ops = &da7219_ops; +} + +struct chip_operations drivers_i2c_da7219_ops = { + CHIP_NAME("Dialog Semiconductor DA7219 Audio Codec") + .enable_dev = &da7219_enable +};

1 0

Patch set updated for coreboot: mainboard/google/reef: Use device driver for DA7219 configuration
by Duncan Laurie 07 Jul '16

07 Jul '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15539 -gerrit commit 3de294db8c5ed53023d562d37a9f78bcdf7dd018 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jul 2 20:05:43 2016 -0700 mainboard/google/reef: Use device driver for DA7219 configuration Use the device driver for DA7219 device configuration in the SSDT and remove the static copy in the DSDT. Tested on reef to ensure that the generated SSDT contents are equivalent to the current DSDT contents. Change-Id: I288eb05d0cb3f5310c4dca4aa1eab5a029f216af Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 3 ++ src/mainboard/google/reef/acpi/mainboard.asl | 60 ---------------------------- src/mainboard/google/reef/devicetree.cb | 20 +++++++++- 3 files changed, 22 insertions(+), 61 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 194a6ba..3ca1af1 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -25,6 +25,9 @@ config CHROMEOS select VBOOT_OPROM_MATTERS select VIRTUAL_DEV_SWITCH +config DRIVERS_I2C_DA7219 + default y + config DRIVERS_I2C_GENERIC default y diff --git a/src/mainboard/google/reef/acpi/mainboard.asl b/src/mainboard/google/reef/acpi/mainboard.asl index 6e6d61f..5b6e976 100644 --- a/src/mainboard/google/reef/acpi/mainboard.asl +++ b/src/mainboard/google/reef/acpi/mainboard.asl @@ -38,63 +38,3 @@ Scope (\_SB.PCI0.LPCB) /* Chrome OS Embedded Controller */ #include "ec.asl" } - -Scope (\_SB.PCI0.I2C0) -{ - /* Headphone Codec */ - Device (HPDA) - { - Name (_HID, "DLGS7219") - Name (_DDN, "Dialog DA7219 Codec") - Name (_UID, 1) - Name (_S0W, 4) - Name (_DSD, Package () { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "dlg,micbias-lvl", 2600 }, - Package () { "dlg,mic-amp-in-sel", "diff" }, - }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package () { - Package () {"da7219_aad", "DAAD"}, - } - }) - - Name (DAAD, Package () { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "dlg,btn-cfg", 50 }, - Package () { "dlg,mic-det-thr", 500 }, - Package () { "dlg,jack-ins-deb", 20 }, - Package () { "dlg,jack-det-rate", "32ms_64ms" }, - Package () { "dlg,jack-rem-deb", 1 }, - Package () { "dlg,a-d-btn-thr", 0xa }, - Package () { "dlg,d-b-btn-thr", 0x16 }, - Package () { "dlg,b-c-btn-thr", 0x21 }, - Package () { "dlg,c-mic-btn-thr", 0x3E }, - Package () { "dlg,btn-avg", 4 }, - Package () { "dlg,adc-1bit-rpt", 1 }, - } - }) - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - BOARD_HP_MIC_CODEC_I2C_ADDR, - ControllerInitiated, - 400000, - AddressingMode7Bit, - "\\_SB.PCI0.I2C0", - ) - Interrupt (ResourceConsumer, Level, ActiveLow) - { - BOARD_HP_MIC_CODEC_IRQ - } - }) - - Method (_STA) - { - Return (0xF) - } - } -} diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index e0831f4..b931a89 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -57,7 +57,25 @@ chip soc/intel/apollolake device pci 14.1 off end # - Root Port 1 - PCIe-B 1 device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI - device pci 16.0 on end # - I2C 0 + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end device pci 16.1 on end # - I2C 1 device pci 16.2 on end # - I2C 2 device pci 16.3 on end # - I2C 3

1 0

Patch set updated for coreboot: acpi: Change device properties to work as a tree
by Duncan Laurie 07 Jul '16

07 Jul '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15537 -gerrit commit 53a96c1f5b7676c7a98ed71f6644ab73e9f0762b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jul 2 19:56:06 2016 -0700 acpi: Change device properties to work as a tree There is a second ACPI _DSD document from the UEFI Forum that details how _DSD style tables can be nested, creating a tree of similarly formatted tables. This document is linked from acpi_device.h. In order to support this the device property interface needs to be more flexible and build up a tree of properties to write all entries at once instead of writing each entry as it is generated. In the end this is a more flexible solution that can support drivers that need child tables like the DA7219 codec, while only requiring minor changes to the existing drivers that use the device property interface. This was tested on reef (apollolake) and chell (skylake) boards to ensure that there was no change in the generated SSDT AML. Change-Id: Ia22e3a5fd3982ffa7c324bee1a8d190d49f853dd Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/arch/x86/acpi_device.c | 354 ++++++++++++++++++++++-------- src/arch/x86/include/arch/acpi_device.h | 114 ++++++---- src/drivers/generic/max98357a/max98357a.c | 9 +- src/drivers/i2c/nau8825/nau8825.c | 14 +- src/soc/intel/skylake/sd.c | 7 +- 5 files changed, 345 insertions(+), 153 deletions(-) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index f8f6a6d..ce31dc8 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -24,14 +24,31 @@ #include <gpio.h> #endif -/* - * Pointer to length field in device properties package - * Location is set in dp_header() and length filled in by dp_footer() - */ -static char *dp_count_ptr; - -/* Count of the number of device properties in the current set */ -static char dp_count; +#define ACPI_DP_UUID "daffd814-6eba-4d8c-8a91-bc9bbf4aa301" +#define ACPI_DP_CHILD_UUID "dbb8e3e6-5886-4ba6-8795-1319f52a966b" + +enum acpi_dp_type { + ACPI_DP_TYPE_INTEGER, + ACPI_DP_TYPE_STRING, + ACPI_DP_TYPE_REFERENCE, + ACPI_DP_TYPE_TABLE, + ACPI_DP_TYPE_ARRAY, + ACPI_DP_TYPE_CHILD, +}; + +struct acpi_dp { + enum acpi_dp_type type; + const char *name; + struct acpi_dp *next; + union { + struct acpi_dp *child; + struct acpi_dp *array; + }; + union { + uint64_t integer; + const char *string; + }; +}; /* Write empty word value and return pointer to it */ static void *acpi_device_write_zero_len(void) @@ -473,39 +490,8 @@ void acpi_device_write_spi(const struct acpi_spi *spi) acpi_device_fill_len(desc_length); } -/* Write a header for using _DSD to export Device Properties */ -void acpi_dp_write_header(void) -{ - /* Name (_DSD) */ - acpigen_write_name("_DSD"); - - /* Package (2) */ - acpigen_write_package(2); - - /* ToUUID (ACPI_DP_UUID) */ - acpigen_write_uuid(ACPI_DP_UUID); - - /* Package (X) */ - acpigen_emit_byte(0x12); - acpigen_write_len_f(); - dp_count_ptr = acpigen_get_current(); - acpigen_emit_byte(0); /* Number of elements, filled by dp_footer */ - - /* Reset element counter */ - dp_count = 0; -} - -/* Fill in length values from writing Device Properties */ -void acpi_dp_write_footer(void) -{ - /* Patch device property element count */ - *dp_count_ptr = dp_count; - - acpigen_pop_len(); /* Inner package length */ - acpigen_pop_len(); /* Outer package length */ -} - -void acpi_dp_write_value(const struct acpi_dp *prop) +static void acpi_dp_write_array(const struct acpi_dp *array); +static void acpi_dp_write_value(const struct acpi_dp *prop) { switch (prop->type) { case ACPI_DP_TYPE_INTEGER: @@ -515,86 +501,266 @@ void acpi_dp_write_value(const struct acpi_dp *prop) acpigen_write_string(prop->string); break; case ACPI_DP_TYPE_REFERENCE: + case ACPI_DP_TYPE_CHILD: acpigen_emit_namestring(prop->string); break; + case ACPI_DP_TYPE_ARRAY: + acpi_dp_write_array(prop->array); + break; + default: + break; } } -/* Write Device Property key with value as an integer */ -void acpi_dp_write_keyval(const char *key, const struct acpi_dp *prop) +/* Package (2) { "prop->name", VALUE } */ +static void acpi_dp_write_property(const struct acpi_dp *prop) { acpigen_write_package(2); - acpigen_write_string(key); + acpigen_write_string(prop->name); acpi_dp_write_value(prop); acpigen_pop_len(); - dp_count++; } -/* Write Device Property key with value as an integer */ -void acpi_dp_write_integer(const char *key, uint64_t value) +/* Write array of Device Properties */ +static void acpi_dp_write_array(const struct acpi_dp *array) { - const struct acpi_dp prop = ACPI_DP_INTEGER(value); - acpi_dp_write_keyval(key, &prop); -} + const struct acpi_dp *dp; + char *pkg_count; -/* Write Device Property key with value as a string */ -void acpi_dp_write_string(const char *key, const char *value) -{ - const struct acpi_dp prop = ACPI_DP_STRING(value); - acpi_dp_write_keyval(key, &prop); + /* Package element count determined as it is populated */ + pkg_count = acpigen_write_package(0); + + for (dp = array; dp; dp = dp->next) { + acpi_dp_write_value(dp); + (*pkg_count)++; + } + + acpigen_pop_len(); } -/* Write Device Property key with value as a reference */ -void acpi_dp_write_reference(const char *key, const char *value) +static void acpi_dp_free(struct acpi_dp *dp) { - const struct acpi_dp prop = ACPI_DP_REFERENCE(value); - acpi_dp_write_keyval(key, &prop); + while (dp) { + struct acpi_dp *p = dp->next; + + switch (dp->type) { + case ACPI_DP_TYPE_CHILD: + acpi_dp_free(dp->child); + break; + case ACPI_DP_TYPE_ARRAY: + acpi_dp_free(dp->array); + break; + default: + break; + } + + free(dp); + dp = p; + } } -/* Write array of Device Properties */ -void acpi_dp_write_array(const char *key, const struct acpi_dp *array, int len) +void acpi_dp_write(struct acpi_dp *table) { - int i; - acpigen_write_package(2); - acpigen_write_string(key); - acpigen_write_package(len); - for (i = 0; i < len; i++) - acpi_dp_write_value(&array[i]); + struct acpi_dp *dp, *prop; + char *dp_count, *prop_count; + int child_count = 0; + + if (!table || table->type != ACPI_DP_TYPE_TABLE) + return; + + /* Name (name) */ + acpigen_write_name(table->name); + + /* Device Property list starts with the next entry */ + prop = table->next; + + /* Package (DP), default to 2 elements (assuming no children) */ + dp_count = acpigen_write_package(2); + + /* ToUUID (ACPI_DP_UUID) */ + acpigen_write_uuid(ACPI_DP_UUID); + + /* Package (PROP), element count determined as it is populated */ + prop_count = acpigen_write_package(0); + + /* Print base properties */ + for (dp = prop; dp; dp = dp->next) { + if (dp->type == ACPI_DP_TYPE_CHILD) { + child_count++; + } else { + (*prop_count)++; + acpi_dp_write_property(dp); + } + } + + /* Package (PROP) length */ acpigen_pop_len(); + + if (child_count) { + /* Update DP package count to 4 */ + *dp_count = 4; + + /* ToUUID (ACPI_DP_CHILD_UUID) */ + acpigen_write_uuid(ACPI_DP_CHILD_UUID); + + /* Print child pointer properties */ + acpigen_write_package(child_count); + + for (dp = prop; dp; dp = dp->next) + if (dp->type == ACPI_DP_TYPE_CHILD) + acpi_dp_write_property(dp); + + acpigen_pop_len(); + } + + /* Package (DP) length */ acpigen_pop_len(); - dp_count++; + + /* Recursively parse children into separate tables */ + for (dp = prop; dp; dp = dp->next) + if (dp->type == ACPI_DP_TYPE_CHILD) + acpi_dp_write(dp->child); + + /* Clean up */ + acpi_dp_free(table); +} + +static struct acpi_dp *acpi_dp_new(struct acpi_dp *dp, enum acpi_dp_type type, + const char *name) +{ + struct acpi_dp *new; + + new = malloc(sizeof(struct acpi_dp)); + if (!new) + return NULL; + + memset(new, 0, sizeof(*new)); + new->type = type; + new->name = name; + + if (dp) { + /* Add to end of property list */ + while (dp->next) + dp = dp->next; + dp->next = new; + } + + return new; +} + +struct acpi_dp *acpi_dp_new_table(const char *name) +{ + return acpi_dp_new(NULL, ACPI_DP_TYPE_TABLE, name); +} + +struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, + uint64_t value) +{ + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_INTEGER, name); + + if (new) + new->integer = value; + + return new; +} + +struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, + const char *string) +{ + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_STRING, name); + + if (new) + new->string = string; + + return new; +} + +struct acpi_dp *acpi_dp_add_reference(struct acpi_dp *dp, const char *name, + const char *reference) +{ + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_REFERENCE, name); + + if (new) + new->string = reference; + + return new; } -/* Write array of Device Properties with values as integers */ -void acpi_dp_write_integer_array(const char *key, uint64_t *array, int len) +struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, + struct acpi_dp *child) { + struct acpi_dp *new; + + if (!child || child->type != ACPI_DP_TYPE_TABLE) + return NULL; + + new = acpi_dp_new(dp, ACPI_DP_TYPE_CHILD, name); + if (new) { + new->child = child; + new->string = child->name; + } + + return new; +} + +struct acpi_dp *acpi_dp_add_array(struct acpi_dp *dp, struct acpi_dp *array) +{ + struct acpi_dp *new; + + if (!array || array->type != ACPI_DP_TYPE_TABLE) + return NULL; + + new = acpi_dp_new(dp, ACPI_DP_TYPE_ARRAY, array->name); + if (new) + new->array = array; + + return new; +} + +struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, + uint64_t *array, int len) +{ + struct acpi_dp *dp_array; int i; - acpigen_write_package(2); - acpigen_write_string(key); - acpigen_write_package(len); + + if (len <= 0) + return NULL; + + dp_array = acpi_dp_new_table(name); + if (!dp_array) + return NULL; + for (i = 0; i < len; i++) - acpigen_write_integer(array[i]); - acpigen_pop_len(); - acpigen_pop_len(); - dp_count++; + if (!acpi_dp_add_integer(dp_array, NULL, array[i])) + break; + + acpi_dp_add_array(dp, dp_array); + + return dp_array; } -/* - * Device Properties for GPIO binding - * linux/Documentation/acpi/gpio-properties.txt - */ -void acpi_dp_write_gpio(const char *key, const char *ref, int index, - int pin, int active_low) +struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, + const char *ref, int index, int pin, + int active_low) { - const struct acpi_dp gpio_prop[] = { - /* The device that has _CRS containing GpioIo()/GpioInt() */ - ACPI_DP_REFERENCE(ref), - /* Index of the GPIO resource in _CRS starting from zero */ - ACPI_DP_INTEGER(index), - /* Pin in the GPIO resource, typically zero */ - ACPI_DP_INTEGER(pin), - /* Set if pin is active low */ - ACPI_DP_INTEGER(active_low) - }; - acpi_dp_write_array(key, gpio_prop, ARRAY_SIZE(gpio_prop)); + struct acpi_dp *gpio = acpi_dp_new_table(name); + + if (!gpio) + return NULL; + + /* The device that has _CRS containing GpioIO()/GpioInt() */ + acpi_dp_add_reference(gpio, NULL, ref); + + /* Index of the GPIO resource in _CRS starting from zero */ + acpi_dp_add_integer(gpio, NULL, index); + + /* Pin in the GPIO resource, typically zero */ + acpi_dp_add_integer(gpio, NULL, pin); + + /* Set if pin is active low */ + acpi_dp_add_integer(gpio, NULL, active_low); + + acpi_dp_add_array(dp, gpio); + + return gpio; } diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index 65f49b2..4b3a469 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -229,63 +229,85 @@ struct acpi_spi { void acpi_device_write_spi(const struct acpi_spi *spi); /* - * Device Properties with _DSD - * http://uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.p… - */ - -#define ACPI_DP_UUID "daffd814-6eba-4d8c-8a91-bc9bbf4aa301" - -enum acpi_dp_type { - ACPI_DP_TYPE_INTEGER, - ACPI_DP_TYPE_STRING, - ACPI_DP_TYPE_REFERENCE, -}; - -struct acpi_dp { - enum acpi_dp_type type; - union { - uint64_t integer; - const char *string; - }; -}; - -#define ACPI_DP_INTEGER(x) { .type = ACPI_DP_TYPE_INTEGER, .integer = x } -#define ACPI_DP_STRING(x) { .type = ACPI_DP_TYPE_STRING, .string = x } -#define ACPI_DP_REFERENCE(x) { .type = ACPI_DP_TYPE_REFERENCE, .string = x } - -/* * Writing Device Properties objects via _DSD + * + * http://uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.p… + * http://uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extens… + * + * The Device Property Hierarchy can be multiple levels deep with multiple + * children possible in each level. In order to support this flexibility + * the device property hierarchy must be built up before being written out. + * + * For example: + * + * // Child table with string and integer + * struct acpi_dp *child = acpi_dp_new_table("CHLD"); + * acpi_dp_add_string(child, "childstring", "CHILD"); + * acpi_dp_add_integer(child, "childint", 100); + * + * // _DSD table with integer and gpio and child pointer + * struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + * acpi_dp_add_integer(dsd, "number1", 1); + * acpi_dp_add_gpio(dsd, "gpio", "\_SB.PCI0.GPIO", 0, 0, 1); + * acpi_dp_add_child(dsd, "child", child); + * + * // Write entries into SSDT and clean up resources + * acpi_dp_write(dsd); + * + * Name(_DSD, Package() { + * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") + * Package() { + * Package() { "gpio", Package() { \_SB.PCI0.GPIO, 0, 0, 0 } } + * Package() { "number1", 1 } + * } + * ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b") + * Package() { + * Package() { "child", CHLD } + * } + * } + * Name(CHLD, Package() { + * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") + * Package() { + * Package() { "childstring", "CHILD" } + * Package() { "childint", 100 } + * } + * } */ -/* Start a set of Device Properties with _DSD and UUID */ -void acpi_dp_write_header(void); +struct acpi_dp; -/* End the Device Properties set and fill in length values */ -void acpi_dp_write_footer(void); +/* Start a new Device Property table with provided ACPI reference */ +struct acpi_dp *acpi_dp_new_table(const char *ref); -/* Write a Device Property value, but not the key */ -void acpi_dp_write_value(const struct acpi_dp *prop); +/* Add integer Device Property */ +struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, + uint64_t value); -/* Write a Device Property, both key and value */ -void acpi_dp_write_keyval(const char *key, const struct acpi_dp *prop); +/* Add string Device Property */ +struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, + const char *string); -/* Write an integer as a Device Property */ -void acpi_dp_write_integer(const char *key, uint64_t value); +/* Add ACPI reference Device Property */ +struct acpi_dp *acpi_dp_add_reference(struct acpi_dp *dp, const char *name, + const char *reference); -/* Write a string as a Device Property */ -void acpi_dp_write_string(const char *key, const char *value); +/* Add an array of Device Properties */ +struct acpi_dp *acpi_dp_add_array(struct acpi_dp *dp, struct acpi_dp *array); -/* Write an ACPI reference as a Device Property */ -void acpi_dp_write_reference(const char *key, const char *value); +/* Add an array of integers Device Property */ +struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, + uint64_t *array, int len); -/* Write an array of Device Properties */ -void acpi_dp_write_array(const char *key, const struct acpi_dp *array, int len); +/* Add a GPIO binding Device Property */ +struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, + const char *ref, int index, int pin, + int active_low); -/* Write an array of integers as Device Properties */ -void acpi_dp_write_integer_array(const char *key, uint64_t *array, int len); +/* Add a child table of Device Properties */ +struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, + struct acpi_dp *child); -/* Write a GPIO binding Device Property */ -void acpi_dp_write_gpio(const char *key, const char *ref, int index, - int pin, int active_low); +/* Write Device Property hierarchy and clean up resources */ +void acpi_dp_write(struct acpi_dp *table); #endif diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 0d522d4..25e5104 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -32,6 +32,7 @@ static void max98357a_fill_ssdt(struct device *dev) { struct drivers_generic_max98357a_config *config = dev->chip_info; const char *path; + struct acpi_dp *dp; if (!dev->enabled || !config) return; @@ -51,12 +52,12 @@ static void max98357a_fill_ssdt(struct device *dev) acpigen_write_resourcetemplate_footer(); /* _DSD for devicetree properties */ - acpi_dp_write_header(); /* This points to the first pin in the first gpio entry in _CRS */ path = acpi_device_path(dev); - acpi_dp_write_gpio("sdmode-gpio", path, 0, 0, 0); - acpi_dp_write_integer("sdmode-delay", config->sdmode_delay); - acpi_dp_write_footer(); + dp = acpi_dp_new_table("_DSD"); + acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0, 0); + acpi_dp_add_integer(dp, "sdmode-delay", config->sdmode_delay); + acpi_dp_write(dp); acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c index 71aacea..a86eff4 100644 --- a/src/drivers/i2c/nau8825/nau8825.c +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -28,7 +28,9 @@ #define NAU8825_ACPI_NAME "NAU8" #define NAU8825_ACPI_HID "10508825" -#define NAU8825_DP_INT(key,val) acpi_dp_write_integer("nuvoton," key, (val)) + +#define NAU8825_DP_INT(key,val) \ + acpi_dp_add_integer(dp, "nuvoton," key, (val)) static void nau8825_fill_ssdt(struct device *dev) { @@ -40,6 +42,7 @@ static void nau8825_fill_ssdt(struct device *dev) .speed = config->bus_speed ? : I2C_SPEED_FAST, .resource = scope, }; + struct acpi_dp *dp = NULL; if (!dev->enabled || !scope) return; @@ -62,7 +65,7 @@ static void nau8825_fill_ssdt(struct device *dev) acpigen_write_resourcetemplate_footer(); /* Device Properties */ - acpi_dp_write_header(); + dp = acpi_dp_new_table("_DSD"); NAU8825_DP_INT("jkdet-enable", config->jkdet_enable); NAU8825_DP_INT("jkdet-pull-enable", config->jkdet_pull_enable); NAU8825_DP_INT("jkdet-pull-up", config->jkdet_pull_up); @@ -77,10 +80,9 @@ static void nau8825_fill_ssdt(struct device *dev) NAU8825_DP_INT("jack-insert-debounce", config->jack_insert_debounce); NAU8825_DP_INT("jack-eject-deboune", config->jack_eject_debounce); NAU8825_DP_INT("sar-threshold-num", config->sar_threshold_num); - acpi_dp_write_integer_array("nuvoton,sar-threshold", - config->sar_threshold, - config->sar_threshold_num); - acpi_dp_write_footer(); + acpi_dp_add_integer_array(dp, "nuvoton,sar-threshold", + config->sar_threshold, config->sar_threshold_num); + acpi_dp_write(dp); acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ diff --git a/src/soc/intel/skylake/sd.c b/src/soc/intel/skylake/sd.c index 80adb9c..a75cf63 100644 --- a/src/soc/intel/skylake/sd.c +++ b/src/soc/intel/skylake/sd.c @@ -38,6 +38,7 @@ static void sd_fill_ssdt(struct device *dev) .pin_count = 1, .pins = { config->sdcard_cd_gpio_default } }; + struct acpi_dp *dp; if (!dev->enabled) return; @@ -62,9 +63,9 @@ static void sd_fill_ssdt(struct device *dev) acpigen_write_resourcetemplate_footer(); /* Bind the cd-gpio name to the GpioInt() resource */ - acpi_dp_write_header(); - acpi_dp_write_gpio("cd-gpio", path, 0, 0, 1); - acpi_dp_write_footer(); + dp = acpi_dp_new_table("_DSD"); + acpi_dp_add_gpio(dp, "cd-gpio", path, 0, 0, 1); + acpi_dp_write(dp); acpigen_pop_len(); }

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coreboot-gerrit July 2016