coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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1820 discussions

Patch set updated for coreboot: mainboard/google/reef: add board_id() support
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15561 -gerrit commit 04583b7d737f5bc905d485331381ab8dc9d1824b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:53:51 2016 -0500 mainboard/google/reef: add board_id() support The board build version is provided by the EC on reef. Provide the necessary functional support for coreboot to differentiate the board versions. BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I1b7e8b2f4142753cde736148ca9495bcc625f318 Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/mainboard/google/reef/Makefile.inc | 2 ++ src/mainboard/google/reef/boardid.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc index f8fbbf3..6db0f2f 100644 --- a/src/mainboard/google/reef/Makefile.inc +++ b/src/mainboard/google/reef/Makefile.inc @@ -2,7 +2,9 @@ bootblock-y += bootblock.c bootblock-y += ec.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += boardid.c +ramstage-y += boardid.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/reef/boardid.c b/src/mainboard/google/reef/boardid.c new file mode 100644 index 0000000..4eb9f48 --- /dev/null +++ b/src/mainboard/google/reef/boardid.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + +uint8_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) + id = google_chromeec_get_board_version(); + + return id; +}

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Patch set updated for coreboot: mainboard/google/reef: apply EVT board changes
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15562 -gerrit commit e0d94e249f081d1b7fa3abbe1aaeff50bb58b404 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 23:16:01 2016 -0500 mainboard/google/reef: apply EVT board changes Based on the board revision apply the correct GPIO changes. The only differences are the addition of 2 peripheral wake signals and a dedicated peripheral reset line. BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I9cac82158e70e0af1b454ec4581c2e4622b95b4b Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/mainboard/google/reef/gpio.h | 16 +++++++++++++--- src/mainboard/google/reef/mainboard.c | 15 +++++++++++++++ 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 14cf880c..cbad4c6 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -274,7 +274,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_0, UP_20K, DEEP), PAD_CFG_GPI(GPIO_1, UP_20K, DEEP), PAD_CFG_GPI(GPIO_2, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), PAD_CFG_GPI(GPIO_4, UP_20K, DEEP), PAD_CFG_GPI(GPIO_5, UP_20K, DEEP), PAD_CFG_GPI(GPIO_6, UP_20K, DEEP), @@ -287,7 +286,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */ - PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_18, NONE, DEEP, LEVEL, NONE), /* Trackpad IRQ */ @@ -319,7 +317,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ - PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */ PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ @@ -356,5 +353,18 @@ static const struct pad_config early_gpio_table[] = { #define MEM_CONFIG1 GPIO_102 #define MEM_CONFIG0 GPIO_101 +static const struct pad_config proto_diff_table[] = { + PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */ +}; + +/* Wake peripheral signals post proto. */ +static const struct pad_config nonproto_diff_table[] = { + PAD_CFG_GPI_SCI(GPIO_3, UP_20K, DEEP, LEVEL, NONE), /* FP_INT_L */ + PAD_CFG_GPI_SCI(GPIO_15, NONE, DEEP, LEVEL, NONE), /* TRACKPAD_INT_1V8_ODL */ + PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ +}; + #endif /* __ACPI__ */ #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 2b121ef..def6900 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -14,6 +14,7 @@ */ #include <arch/acpi.h> +#include <boardid.h> #include <console/console.h> #include <device/device.h> #include <nhlt.h> @@ -24,7 +25,21 @@ static void mainboard_init(void *chip_info) { + int boardid; + + boardid = board_id(); + printk(BIOS_INFO, "Board ID: %d\n", boardid); + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* Apply proto board settings if board matches. */ + if (boardid == 0) + gpio_configure_pads(proto_diff_table, + ARRAY_SIZE(proto_diff_table)); + else + gpio_configure_pads(nonproto_diff_table, + ARRAY_SIZE(nonproto_diff_table)); + mainboard_ec_init(); }

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New patch to review for coreboot: siemens/mc_bdx1: Move SCI to IRQ 10
by Werner Zeh 07 Jul '16

07 Jul '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15563 -gerrit commit 38221c1498877b49ca092f665645013cd7a6d9a7 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jul 7 07:10:50 2016 +0200 siemens/mc_bdx1: Move SCI to IRQ 10 IRQ 9 is used for different purpose on this board so move SCI away to IRQ10. Change-Id: I107bfb5ec8cd05f844ee75550779be7746e77a88 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_bdx1/mainboard.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index bad072b..80b43cd 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -32,6 +32,7 @@ #include <hwilib.h> #include <i210.h> #include <soc/pci_devs.h> +#include <soc/irq.h> #define MAX_PATH_DEPTH 12 #define MAX_NUM_MAPPINGS 10 @@ -91,6 +92,17 @@ static void mainboard_enable(device_t dev) } +static void mainboard_init(void *chip_info) +{ + uint8_t actl = 0; + device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + + /* Route SCI to IRQ10 to free IRQ9 slot. */ + actl = pci_read_config8(dev, ACPI_CNTL_OFFSET); + actl &= ~SCIS_MASK; + actl |= SCIS_IRQ10; + pci_write_config8(dev, ACPI_CNTL_OFFSET, actl); +} static void mainboard_final(void *chip_info) { void *spi_base = NULL; @@ -183,5 +195,6 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, + .init = mainboard_init, .final = mainboard_final };

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Patch set updated for coreboot: mainboard/google/reef: add board_id() support
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15561 -gerrit commit d94275b9f8942265d9a30b66fe6bac405c168a1d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:53:51 2016 -0500 mainboard/google/reef: add board_id() support The board build version is provided by the EC on reef. Provide the necessary functional support for coreboot to differentiate the board versions. BUG=chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I1b7e8b2f4142753cde736148ca9495bcc625f318 Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/mainboard/google/reef/Makefile.inc | 2 ++ src/mainboard/google/reef/boardid.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc index f8fbbf3..6db0f2f 100644 --- a/src/mainboard/google/reef/Makefile.inc +++ b/src/mainboard/google/reef/Makefile.inc @@ -2,7 +2,9 @@ bootblock-y += bootblock.c bootblock-y += ec.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += boardid.c +ramstage-y += boardid.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/reef/boardid.c b/src/mainboard/google/reef/boardid.c new file mode 100644 index 0000000..4eb9f48 --- /dev/null +++ b/src/mainboard/google/reef/boardid.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + +uint8_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) + id = google_chromeec_get_board_version(); + + return id; +}

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Patch set updated for coreboot: mainboard/google/reef: add memory SKU id support
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15560 -gerrit commit c49aed109c6590b277bd0e6d93ca329e9590f9ae Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:51:05 2016 -0500 mainboard/google/reef: add memory SKU id support While the proto boards didn't have a memory SKU notion the EVT boards do. Therefore, provide support for selecting the proper memory SKU information based on the memory id straps. This works on EVT boards because the pins used for the strapping weren't used on proto. However, internal pullups need to be enabled so that proto boards read the correct id. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: I8653260e5d1b9adc83b78ea2770c683b72535e11 Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/mainboard/google/reef/gpio.h | 18 +++++++--- src/mainboard/google/reef/romstage.c | 66 +++++++++++++++++++++++++++++++----- 2 files changed, 72 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 91e8bb1..14cf880c 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -243,8 +243,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */ - PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- unused */ - PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- unused */ + PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */ /* SIO_SPI_0 - Used for FP */ @@ -312,7 +312,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_37, UP_20K, DEEP), /* unused */ /* LPSS_UART[0:2] */ - PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - unused */ + PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - MEM_CONFIG2*/ /* Next 2 are straps. */ PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ @@ -320,7 +320,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */ - PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1), /* LPSS_UART1_CTS */ + PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ @@ -346,5 +346,15 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ }; +/* + * The proto boards didn't have memory SKU pins, but the same ones can be + * utilized as post proto boards because the pins used were never connected + * or no peripheral utilized the signals on proto boards. + */ +#define MEM_CONFIG3 GPIO_45 +#define MEM_CONFIG2 GPIO_38 +#define MEM_CONFIG1 GPIO_102 +#define MEM_CONFIG0 GPIO_101 + #endif /* __ACPI__ */ #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index ecf6fa5..e1d8c57 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -13,8 +13,10 @@ * GNU General Public License for more details. */ +#include <gpio.h> #include <soc/meminit.h> #include <soc/romstage.h> +#include "gpio.h" static const struct lpddr4_swizzle_cfg board_swizzle = { /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ @@ -60,15 +62,63 @@ static const struct lpddr4_swizzle_cfg board_swizzle = { }, }; +/* + * Proto boards didn't have a memory SKU id. The configuration pins use + * an internal weak pullup with stronger pulldowns for the 0 bits. As + * proto boards didn't use the memory SKU pins the sku id reads as 4'b1111, + * i.e. 15. + */ +#define PROTO_SKU 15 + +static const struct lpddr4_sku skus[] = { + /* K4F6E304HB-MGCJ - both logical channels */ + [0] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_16Gb_DENSITY, + .ch1_density = LP4_16Gb_DENSITY, + }, + /* K4F8E304HB-MGCJ - both logical channels */ + [1] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_8Gb_DENSITY, + .ch1_density = LP4_8Gb_DENSITY, + }, + /* MT53B512M32D2NP-062WT:C - both logical channels */ + [2] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_16Gb_DENSITY, + .ch1_density = LP4_16Gb_DENSITY, + /* MT53B256M32D1NP-062 WT:C - both logical channels */ + }, + [3] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_8Gb_DENSITY, + .ch1_density = LP4_8Gb_DENSITY, + }, + /* K4F8E304HB-MGCH - both logical channels */ + [PROTO_SKU] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_8Gb_DENSITY, + .ch1_density = LP4_8Gb_DENSITY, + }, +}; + +static const struct lpddr4_cfg lp4cfg = { + .skus = skus, + .num_skus = ARRAY_SIZE(skus), + .swizzle_config = &board_swizzle, +}; + void mainboard_memory_init_params(struct FSPM_UPD *memupd) { - struct FSP_M_CONFIG *cfg = &memupd->FspmConfig; + int mem_sku; + gpio_t pads[] = { MEM_CONFIG3, MEM_CONFIG2, MEM_CONFIG1, MEM_CONFIG0 }; + + /* + * Read memory SKU id with internal pullups enabled to handle + * proto boards with no SKU id pins. + */ + mem_sku = gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); - /* Use a default 2400 speed. */ - meminit_lpddr4(cfg, LP4_SPEED_2400); - /* Enable both logical channels with a 8Gb density. */ - meminit_lpddr4_enable_channel(cfg, LP4_LCH0, LP4_8Gb_DENSITY, - &board_swizzle); - meminit_lpddr4_enable_channel(cfg, LP4_LCH1, LP4_8Gb_DENSITY, - &board_swizzle); + meminit_lpddr4_by_sku(&memupd->FspmConfig, &lp4cfg, mem_sku); }

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Patch set updated for coreboot: mainboard/google/reef: apply EVT board changes
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15562 -gerrit commit 16f8def3e54bf694a2fa35eb644e31a9903cb240 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 23:16:01 2016 -0500 mainboard/google/reef: apply EVT board changes Based on the board revision apply the correct GPIO changes. The only differences are the addition of peripheral wake signals. BUG=chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I9cac82158e70e0af1b454ec4581c2e4622b95b4b Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/mainboard/google/reef/gpio.h | 13 +++++++++++-- src/mainboard/google/reef/mainboard.c | 14 ++++++++++++++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 14cf880c..c54ba4c 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -274,7 +274,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_0, UP_20K, DEEP), PAD_CFG_GPI(GPIO_1, UP_20K, DEEP), PAD_CFG_GPI(GPIO_2, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), PAD_CFG_GPI(GPIO_4, UP_20K, DEEP), PAD_CFG_GPI(GPIO_5, UP_20K, DEEP), PAD_CFG_GPI(GPIO_6, UP_20K, DEEP), @@ -287,7 +286,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */ - PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_18, NONE, DEEP, LEVEL, NONE), /* Trackpad IRQ */ @@ -356,5 +354,16 @@ static const struct pad_config early_gpio_table[] = { #define MEM_CONFIG1 GPIO_102 #define MEM_CONFIG0 GPIO_101 +static const struct pad_config wake_signals_proto[] = { + PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), /* unused */ +}; + +/* Wake peripheral signals post proto. */ +static const struct pad_config wake_signals[] = { + PAD_CFG_GPI_SCI(GPIO_15, NONE, DEEP, LEVEL, NONE), /* TRACKPAD_INT_1V8_ODL */ + PAD_CFG_GPI_SCI(GPIO_3, UP_20K, DEEP, LEVEL, NONE), /* FP_INT_L */ +}; + #endif /* __ACPI__ */ #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 2b121ef..c66bb91 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -14,6 +14,7 @@ */ #include <arch/acpi.h> +#include <boardid.h> #include <console/console.h> #include <device/device.h> #include <nhlt.h> @@ -24,7 +25,20 @@ static void mainboard_init(void *chip_info) { + int boardid; + + boardid = board_id(); + printk(BIOS_INFO, "Board ID: %d\n", boardid); + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* Apply proto board settings if board matches. */ + if (boardid == 0) + gpio_configure_pads(wake_signals_proto, + ARRAY_SIZE(wake_signals_proto)); + else + gpio_configure_pads(wake_signals, ARRAY_SIZE(wake_signals)); + mainboard_ec_init(); }

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Patch set updated for coreboot: mainboard/google/reef: add board_id() support
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15561 -gerrit commit 42f973b071c84bbfa71e816ff88b8a1ffca25e4d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:53:51 2016 -0500 mainboard/google/reef: add board_id() support The board build version is provided by the EC on reef. Provide the necessary functional support for coreboot to differentiate the board versions. BUG=chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I1b7e8b2f4142753cde736148ca9495bcc625f318 Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/mainboard/google/reef/Makefile.inc | 2 ++ src/mainboard/google/reef/boardid.c | 28 ++++++++++++++++++++++++++++ src/mainboard/google/reef/gpio.h | 8 ++++---- 3 files changed, 34 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc index f8fbbf3..6db0f2f 100644 --- a/src/mainboard/google/reef/Makefile.inc +++ b/src/mainboard/google/reef/Makefile.inc @@ -2,7 +2,9 @@ bootblock-y += bootblock.c bootblock-y += ec.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += boardid.c +ramstage-y += boardid.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/reef/boardid.c b/src/mainboard/google/reef/boardid.c new file mode 100644 index 0000000..4eb9f48 --- /dev/null +++ b/src/mainboard/google/reef/boardid.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + +uint8_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) + id = google_chromeec_get_board_version(); + + return id; +} diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index d541a34..14cf880c 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -243,8 +243,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */ - PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- unused */ - PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- unused */ + PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */ /* SIO_SPI_0 - Used for FP */ @@ -312,7 +312,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_37, UP_20K, DEEP), /* unused */ /* LPSS_UART[0:2] */ - PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - unused */ + PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - MEM_CONFIG2*/ /* Next 2 are straps. */ PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ @@ -320,7 +320,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */ - PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1), /* LPSS_UART1_CTS */ + PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */

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Patch set updated for coreboot: mainboard/google/reef: apply EVT board changes
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15562 -gerrit commit f99ac39dddfb094fefb03a0ed525df796bebab1c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 23:16:01 2016 -0500 mainboard/google/reef: apply EVT board changes Based on the board revision apply the correct GPIO changes. The only differences are the addition of peripheral wake signals. BUG=chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I9cac82158e70e0af1b454ec4581c2e4622b95b4b Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/mainboard/google/reef/gpio.h | 13 +++++++++++-- src/mainboard/google/reef/mainboard.c | 14 ++++++++++++++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 14cf880c..c54ba4c 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -274,7 +274,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_0, UP_20K, DEEP), PAD_CFG_GPI(GPIO_1, UP_20K, DEEP), PAD_CFG_GPI(GPIO_2, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), PAD_CFG_GPI(GPIO_4, UP_20K, DEEP), PAD_CFG_GPI(GPIO_5, UP_20K, DEEP), PAD_CFG_GPI(GPIO_6, UP_20K, DEEP), @@ -287,7 +286,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */ - PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_18, NONE, DEEP, LEVEL, NONE), /* Trackpad IRQ */ @@ -356,5 +354,16 @@ static const struct pad_config early_gpio_table[] = { #define MEM_CONFIG1 GPIO_102 #define MEM_CONFIG0 GPIO_101 +static const struct pad_config wake_signals_proto[] = { + PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), /* unused */ +}; + +/* Wake peripheral signals post proto. */ +static const struct pad_config wake_signals[] = { + PAD_CFG_GPI_SCI(GPIO_15, NONE, DEEP, LEVEL, NONE), /* TRACKPAD_INT_1V8_ODL */ + PAD_CFG_GPI_SCI(GPIO_3, UP_20K, DEEP, LEVEL, NONE), /* FP_INT_L */ +}; + #endif /* __ACPI__ */ #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 2b121ef..c66bb91 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -14,6 +14,7 @@ */ #include <arch/acpi.h> +#include <boardid.h> #include <console/console.h> #include <device/device.h> #include <nhlt.h> @@ -24,7 +25,20 @@ static void mainboard_init(void *chip_info) { + int boardid; + + boardid = board_id(); + printk(BIOS_INFO, "Board ID: %d\n", boardid); + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* Apply proto board settings if board matches. */ + if (boardid == 0) + gpio_configure_pads(wake_signals_proto, + ARRAY_SIZE(wake_signals_proto)); + else + gpio_configure_pads(wake_signals, ARRAY_SIZE(wake_signals)); + mainboard_ec_init(); }

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Patch merged into coreboot/master: siemens/mc_bdx1: Set up opcode menu for SPI controller
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit e1d6aa6e4195f5fce6cb65d39d36289e6786fa36 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Jul 6 11:59:10 2016 +0200 siemens/mc_bdx1: Set up opcode menu for SPI controller Since SPI controller opcode registers are locked by FSP, they need to be initialized to a known good state before ReadyToBoot event and after every SPI flash access (e.g. for MRC cache) has been finished in order to enable the OS to use SPI controller without constraints. Change-Id: I0a66344cd44e036c3999ae98d539072299cf5112 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/15547 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/15547 for details. -gerrit

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Patch merged into coreboot/master: intel/fsp_broadwell_de: Do not use hard coded SCI IRQ for ACPI
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit 93db5a5eeea78423ca763bff013d3610655e3776 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Jul 6 12:58:57 2016 +0200 intel/fsp_broadwell_de: Do not use hard coded SCI IRQ for ACPI The SCI interrupt can be routed to different IRQs using ACPI control register. Instead of using hard coded IRQ9 for ACPI table generation read back the register and return the used IRQ number. This way SCI IRQ can be modified (e.g. for a given mainboard) and ACPI tables will remain consistent. Change-Id: I534fc69eb1df28cd8d733d1ac6b2081d2dcf7511 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/15548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: York Yang <york.yang(a)intel.com> See https://review.coreboot.org/15548 for details. -gerrit

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coreboot-gerrit July 2016