coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: WIP: soc/intel/apollolake: Cache cbmem region
by Andrey Petrov 27 Jun '16

27 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15456 -gerrit commit 1160bb247a773f1f493fe9e68ea6d1f388be6ec1 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jun 24 18:40:28 2016 -0700 WIP: soc/intel/apollolake: Cache cbmem region Configure write-back MTRRs so that 16 MiB under cbmem_top is cached. This allows caching of FSP reserved memory and postcar stage itself. On CAR teardown the memory is flushed with clflush instruction. Depending on what cache configuration is used, either L1 (NEM) or both L1 and L2 (CQOS) storage is used for caching purposes. This is WIP patch, because currently location of cbmem_top can not be known before memory is trained. So addresses are hardcoded. BUG=chrome-os-partner:51959 TEST=run primitive memtest on 16 MiB cached memory region after mem is trained, observe x7 improvement on L1 only, x12 on L2 of 256 KiB Change-Id: I62aad238a3056f9bbe5327dfb33a2a1112d61194 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/exit_car.S | 8 ++++++++ src/soc/intel/apollolake/romstage.c | 9 ++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S index e5706cf..c0fb39b 100644 --- a/src/soc/intel/apollolake/exit_car.S +++ b/src/soc/intel/apollolake/exit_car.S @@ -38,6 +38,14 @@ chipset_teardown_car: and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr + /* Flush down whatever we have */ + mov $0x7a000000, %eax +loop: + clflush (%eax) + add $CACHE_LINE_SIZE, %eax + cmp $0x7b000000, %eax + jl loop + #if IS_ENABLED(CONFIG_CAR_CQOS) mov $MTRR_L2_QOS_MASK(0), %ecx rdmsr diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index ce28326..1fa52fd 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -112,7 +112,7 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; size_t mrc_data_size; uintptr_t top_of_ram; - int prev_sleep_state; + int prev_sleep_state, mtrr; struct romstage_handoff *handoff; struct chipset_power_state *ps = car_get_var_ptr(&power_state); @@ -129,6 +129,13 @@ asmlinkage void car_stage_entry(void) range_entry_init(&reg_car, (uintptr_t)_car_relocatable_data_end, (uintptr_t)_car_region_end, 0); + mtrr = get_free_var_mtrr(); + if (mtrr==-1) + printk(BIOS_CRIT, "no available MTRRs to cache cbmem!\n"); + else + /* Make sure cbmem 16 MiB under CBMEM is cachable */ + set_var_mtrr(mtrr, 0x7a000000, 16 * MiB, MTRR_TYPE_WRBACK); + if (fsp_memory_init(&hob_list_ptr, &reg_car) != FSP_SUCCESS) { die("FSP memory init failed. Giving up."); }

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New patch to review for coreboot: soc/intel/apollolake: Add CQOS CAR implementation
by Andrey Petrov 27 Jun '16

27 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15455 -gerrit commit 52a959fca4938ac39bda7e3e1cb4dfef606862e3 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Jun 27 13:39:34 2016 -0700 soc/intel/apollolake: Add CQOS CAR implementation Add new Cache Quality of Service option that allows to configure cache non-evict mode by manipulating CQOS settings. Also, CQOS allows using cache non-evict mode simultaneously with regular evicting caching. BUG=chrome-os-partner:51959 Change-Id: Ic7f9899918f94a5788b02a4fbd2f5d5ba9aaf91d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/bootblock/bootblock.c | 4 ++++ src/soc/intel/apollolake/car.c | 7 +++++++ src/soc/intel/apollolake/exit_car.S | 29 ++++++++++++++++++++++++-- src/soc/intel/apollolake/include/soc/cpu.h | 12 +++++++++++ 4 files changed, 50 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 8c1ff91..00c280a 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -168,5 +168,9 @@ void bootblock_soc_early_init(void) enable_spibar(); +#if IS_ENABLED(CONFIG_CAR_CQOS) + cache_qos_select_mask(1); +#endif + cache_bios_region(); } diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index 68bcb31..bb96419 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -56,3 +56,10 @@ void platform_segment_loaded(uintptr_t start, size_t size, int flags) flush_l1d_to_l2(); } + +void cache_qos_select_mask(uint8_t mask) +{ + msr_t msr = rdmsr(MTRR_IA32_PQR_ASSOC); + msr.hi |= mask; + wrmsr(MTRR_IA32_PQR_ASSOC, msr); +} diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S index 339242b..e5706cf 100644 --- a/src/soc/intel/apollolake/exit_car.S +++ b/src/soc/intel/apollolake/exit_car.S @@ -27,14 +27,38 @@ chipset_teardown_car: */ pop %ebx - /* invalidate cache contents. */ - invd + /* + * Flush all cache lines into the DRAM. Since we are running in the + * very region, disable MTRR first. + */ + /* Disable MTRRs. */ mov $(MTRR_DEF_TYPE_MSR), %ecx rdmsr and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr +#if IS_ENABLED(CONFIG_CAR_CQOS) + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + mov $~0, %al + wrmsr + + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + mov $~0, %al + wrmsr + + /* reset CLOS selector */ + mov $MTRR_IA32_PQR_ASSOC, %ecx + rdmsr + and $~(1 << 0 | 1 << 1), %edx + wrmsr +#endif + /* invalidate cache contents. */ + invd + +#if IS_ENABLED(CONFIG_CAR_NEM) /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ mov $(MSR_EVICT_CTL), %ecx rdmsr @@ -42,6 +66,7 @@ chipset_teardown_car: wrmsr and $(~(1 << 0)), %eax wrmsr +#endif /* Return to caller. */ jmp *%ebx diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 78fc0b0..13a47cd 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -23,6 +23,7 @@ #include <device/device.h> void apollolake_init_cpus(struct device *dev); +void cache_qos_select_mask(uint8_t mask); #endif #define CPUID_APOLLOLAKE_A0 0x506c8 @@ -35,6 +36,17 @@ void apollolake_init_cpus(struct device *dev); #define MSR_EMULATE_PM_TMR 0x121 #define EMULATE_PM_TMR_EN (1 << 16) +#define MTRR_L2_QOS_MASK(reg) (0xd10 + reg) +#define MTRR_IA32_PQR_ASSOC 0xc8f +/* 16 way cache, 8 bits per QOS, 64 byte cache line, 1024 sets */ +#define CACHE_WAYS 16 +#define CACHE_BITS_PER_MASK 8 +#define CACHE_LINE_SIZE 64 +#define CACHE_SETS 1024 +/* Each bit in QOS mask controls this many bytes */ +#define CACHE_QOS_SIZE_PER_BIT ((CACHE_WAYS / CACHE_BITS_PER_MASK) * \ + CACHE_LINE_SIZE * CACHE_SETS) + #define BASE_CLOCK_MHZ 100 /* Common Timer Copy (CTC) frequency - 19.2MHz. */

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New patch to review for coreboot: WIP: soc/intel/apollolake: Update stage link addresses for 768 KiB cache
by Andrey Petrov 27 Jun '16

27 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15454 -gerrit commit 3e7cce7678b0dfad543affc3e6e5843d6be9d9da Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jun 24 18:15:09 2016 -0700 WIP: soc/intel/apollolake: Update stage link addresses for 768 KiB cache Update link addresses for romstage and verstage. Also change build time relocation address for FSP-M to match. Actual addresses are ballpark estimate and need to be validated. BUG=chrome-os-partner:51959 Change-Id: Ia51a341f05b33151ea5fda9f8620408b5a15bc19 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index fd4e5ac..cbe1da8 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -120,13 +120,13 @@ config X86_TOP4G_BOOTMEDIA_MAP config ROMSTAGE_ADDR hex - default 0xfef3e000 + default 0xfef11000 help The base address (in CAR) where romstage should be linked config VERSTAGE_ADDR hex - default 0xfef60000 + default 0xfef09000 help The base address (in CAR) where verstage should be linked @@ -136,7 +136,7 @@ config CACHE_MRC_SETTINGS config FSP_M_ADDR hex - default 0xfef60000 + default 0xfef40000 help The address FSP-M will be relocated to during build time

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New patch to review for coreboot: WIP: soc/intel/apollolake: Change default CAR size to 768 KiB
by Andrey Petrov 27 Jun '16

27 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15453 -gerrit commit d1fb0de07a0d573cd9c251304ef4ba2d47d741a3 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Jun 27 13:37:51 2016 -0700 WIP: soc/intel/apollolake: Change default CAR size to 768 KiB As whole 1024 KiB is not used, it is possible to shrink CAR size to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used to setup it. This is part of preparation for CQOS enabling. BUG=chrome-os-partner:51959 Change-Id: I56326a1790df202a0e428e092dd90286c58763c5 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 26 ++++++++++++- src/soc/intel/apollolake/bootblock/cache_as_ram.S | 46 +++++++++++++++++++++++ 2 files changed, 71 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 98ce7d8..fd4e5ac 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -77,7 +77,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex "Length in bytes of cache-as-RAM" - default 0x100000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage. @@ -182,4 +182,28 @@ config IFWI_FILE_NAME help Name of file to store in the IFWI region. +choice + prompt "Cache-as-ram implementation" + default CAR_CQOS + help + This option allows you to select how cache-as-ram (CAR) is set up. + +config CAR_NEM + bool "Non-evict mode" + help + Traditionally, CAR is set up by using Non-Evict mode. This method + does not allow CAR and cache to co-exist, because cache fills are + block in NEM mode. + + +config CAR_CQOS + bool "Cache Quality of Service" + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up portion of L2 cache for + CAR and use remainded for actual caching. + +endchoice + + endif diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index 8647206..3c97bb2 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -70,6 +70,31 @@ clear_var_mtrr: post_code(0x24) +#if (CONFIG_DCACHE_RAM_SIZE == 0xc0000) /* 768 KiB */ + /* 512 KiB */ + mov $MTRR_PHYS_BASE(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK(0), %ecx + mov $~(0x80000 - 1), %eax /* size mask */ + or $MTRR_PHYS_MASK_VALID, %eax + wrmsr + + /* 256 KiB */ + mov $MTRR_PHYS_BASE(1), %ecx + mov $(CONFIG_DCACHE_RAM_BASE + 0x80000), %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK(1), %ecx + mov $~(0x40000 - 1), %eax /* size mask */ + or $MTRR_PHYS_MASK_VALID, %eax + wrmsr +#else /* Configure CAR region as write-back (WB) */ mov $MTRR_PHYS_BASE(0), %ecx mov $CONFIG_DCACHE_RAM_BASE, %eax @@ -82,6 +107,7 @@ clear_var_mtrr: mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */ or $MTRR_PHYS_MASK_VALID, %eax wrmsr +#endif post_code(0x25) @@ -97,12 +123,30 @@ clear_var_mtrr: invd mov %eax, %cr0 +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (setup stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr +#endif +#if IS_ENABLED(CONFIG_CAR_CQOS) + /* Mask 0 is used for CAR */ + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + /* Calculate how many bits to be used for CAR */ + mov $(1 << (CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT) - 1), %al + wrmsr + + /* Mask 1 is used for evicatable cache */ + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + /* Invert bits that are to be used for cache */ + mov $(1 << (CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT) - 1), %al + xor $~0, %al + wrmsr +#endif post_code(0x26) /* Clear the cache memory region. This will also fill up the cache */ @@ -113,11 +157,13 @@ clear_var_mtrr: post_code(0x27) +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr +#endif post_code(0x28)

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New patch to review for coreboot: buildgcc: Never set GMP CFLAGS manually in order to get the right flags
by Paul Kocialkowski 27 Jun '16

27 Jun '16

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15452 -gerrit commit baadd6aa8e89f4c17189309bf3b54640a2c12de0 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Fri Jun 17 21:41:00 2016 -0700 buildgcc: Never set GMP CFLAGS manually in order to get the right flags When no CFLAGS are explicitly provided to it, the GMP configure script will figure out the best optimization flags to use on its own. In particular, it will setup the march, mfpu and mtune flags based on hardware detection. However, when CFLAGS are provided, they are used as-is and such detection doesn't happen. When the march, mfpu and mtune flags are not provided (which happens when GMP wasn't built already), not only will related optimizations be disabled, but some code might not build because of missing support. This happens with NEON instructions on ARMv7 hosts. Thus, it is better not to set CFLAGS and leave it up to the GMP configure script to get them right and still reuse those later. Change-Id: I6ffcbac1298523d1b8ddf29a8bca1b00298828a7 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- util/crossgcc/buildgcc | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 1e761da..118a50b 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -404,10 +404,6 @@ GNU General Public License for more details. EOF } -have_hostcflags_from_gmp() { - grep -q __GMP_CFLAGS $DESTDIR$TARGETDIR/include/gmp.h >/dev/null 2>&1 -} - set_hostcflags_from_gmp() { # Now set CFLAGS to match GMP CFLAGS but strip out -pedantic # as GCC 4.6.x fails if it's there. @@ -416,7 +412,7 @@ set_hostcflags_from_gmp() { } build_GMP() { - CC="$CC" CFLAGS="$HOSTCFLAGS" \ + CC="$CC" \ ../${GMP_DIR}/configure --disable-shared --enable-fat \ --prefix=$TARGETDIR $OPTIONS \ || touch .failed @@ -788,11 +784,6 @@ elif [ $UNAME = "NetBSD" ]; then fi fi # GCC -export HOSTCFLAGS="-Os" -if have_hostcflags_from_gmp; then - set_hostcflags_from_gmp -fi - if [ "$USECCACHE" = 1 ]; then CC="ccache $CC" fi

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Patch merged into coreboot/master: intel/amenia: disable unused devices
by gerrit＠coreboot.org 27 Jun '16

27 Jun '16

the following patch was just integrated into master: commit c58b9c9d76c3cd8ac7707d01c5bcfd147cd34bdb Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Wed Jun 22 18:47:47 2016 -0700 intel/amenia: disable unused devices BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I486a4c5e8970047477068e22b799d06caea03330 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Reviewed-on: https://review.coreboot.org/15338 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15338 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: add code to disable unused device
by gerrit＠coreboot.org 27 Jun '16

27 Jun '16

the following patch was just integrated into master: commit b023e5e32f763c2f48ac14fab4979d3493b39983 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Wed Jun 22 18:32:17 2016 -0700 soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/15337 for details. -gerrit

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New patch to review for coreboot: tegra124: Build verstage when CHROMEOS is selected
by Paul Kocialkowski 27 Jun '16

27 Jun '16

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15451 -gerrit commit 647b469959a6868cf8dc4aacfe8372e55e1661e5 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Jun 27 19:08:59 2016 +0200 tegra124: Build verstage when CHROMEOS is selected This includes the proper Kconfig options (based on the chromium os coreboot configuration) for setting up verstage on tegra124 devices. Change-Id: I4a1976ff684a417cae6fa718ef53cad763cee47d Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/soc/nvidia/tegra124/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 49929ad..227efca 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -18,6 +18,9 @@ if SOC_NVIDIA_TEGRA124 config CHROMEOS select VBOOT_OPROM_MATTERS + select VBOOT_STARTS_IN_BOOTBLOCK + select SEPARATE_VERSTAGE + select CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL config TEGRA124_MODEL_TD570D bool "TD570D"

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New patch to review for coreboot: nyan: Call early_mainboard_init before cbmem init in romstage
by Paul Kocialkowski 27 Jun '16

27 Jun '16

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15450 -gerrit commit ccc03fb081e3b7ad587f822d817fac04e464e820 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Jun 27 18:17:14 2016 +0200 nyan: Call early_mainboard_init before cbmem init in romstage cbmem init will eventually trigger init hooks, including vb2_fill_handoff_cbmem when verified boot is enabled, which fills the vboot handoff structure and calls vboot_wants_oprom that uses vbnv. When vbnv is obtained from the EC (that's the case on nyan), the EC SPI bus has to be properly configured or register access will hang. Such configuration is performed in early_mainboard_init, thus it has to be called before cbmem_initialize_empty. Change-Id: I2e0b5a369c5fb24efae4ac40d83a31f5cf4a078d Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/mainboard/google/nyan/romstage.c | 4 ++-- src/mainboard/google/nyan_big/romstage.c | 4 ++-- src/mainboard/google/nyan_blaze/romstage.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index d09bf5e..6f98bd7 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -79,11 +79,11 @@ static void __attribute__((noinline)) romstage(void) hard_reset(); } + early_mainboard_init(); + /* FIXME: this may require coordination with moving timestamps */ cbmem_initialize_empty(); - early_mainboard_init(); - run_ramstage(); } diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index d09bf5e..6f98bd7 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -79,11 +79,11 @@ static void __attribute__((noinline)) romstage(void) hard_reset(); } + early_mainboard_init(); + /* FIXME: this may require coordination with moving timestamps */ cbmem_initialize_empty(); - early_mainboard_init(); - run_ramstage(); } diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 373d43b..4899a54 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -83,11 +83,11 @@ static void __attribute__((noinline)) romstage(void) hard_reset(); } + early_mainboard_init(); + /* FIXME: this may require coordination with moving timestamps */ cbmem_initialize_empty(); - early_mainboard_init(); - run_ramstage(); }

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Patch set updated for coreboot: tegra124: Actually align the framebuffer's bytes-per-line to 32
by Paul Kocialkowski 27 Jun '16

27 Jun '16

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14816 -gerrit commit cdfb2145c56325ffc81c17ca70042b1f1819ce79 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Sat May 14 15:25:51 2016 +0200 tegra124: Actually align the framebuffer's bytes-per-line to 32 The previous change with that intent aligned the framebuffer's bytes-per-line to 64 instead of 32: commit 8957dd6b52919ed634aa502dfd5b6316a6e6e055 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Sun May 1 18:38:04 2016 +0200 tegra124: Align the framebuffer's bytes-per-line to 32 Change-Id: I88bba2ff355a51d42cab6a869ec1e9c534160b9c Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/soc/nvidia/tegra124/display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 0fc15cb..9ec34d4 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -334,6 +334,6 @@ void display_startup(device_t dev) edid.mode.va = config->yres; edid.mode.ha = config->xres; edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel, 64); + config->framebuffer_bits_per_pixel, 32); set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); }

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coreboot-gerrit June 2016