coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake: Add CQOS CAR implementation
by Andrey Petrov 28 Jun '16

28 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15455 -gerrit commit 582ec37a2cf226c0ed69bc912516cbf1b953778a Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Jun 27 13:39:34 2016 -0700 soc/intel/apollolake: Add CQOS CAR implementation Add new Cache Quality of Service option that allows to configure cache non-evict mode by manipulating CQOS settings. Also, CQOS allows using cache non-evict mode simultaneously with regular evicting caching. BUG=chrome-os-partner:51959 Change-Id: Ic7f9899918f94a5788b02a4fbd2f5d5ba9aaf91d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/bootblock/bootblock.c | 4 ++++ src/soc/intel/apollolake/bootblock/cache_as_ram.S | 20 ++++++++++++++++ src/soc/intel/apollolake/car.c | 7 ++++++ src/soc/intel/apollolake/exit_car.S | 29 +++++++++++++++++++++-- src/soc/intel/apollolake/include/soc/cpu.h | 12 ++++++++++ 5 files changed, 70 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 8c1ff91..00c280a 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -168,5 +168,9 @@ void bootblock_soc_early_init(void) enable_spibar(); +#if IS_ENABLED(CONFIG_CAR_CQOS) + cache_qos_select_mask(1); +#endif + cache_bios_region(); } diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index a362969..3c97bb2 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -123,12 +123,30 @@ clear_var_mtrr: invd mov %eax, %cr0 +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (setup stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr +#endif + +#if IS_ENABLED(CONFIG_CAR_CQOS) + /* Mask 0 is used for CAR */ + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + /* Calculate how many bits to be used for CAR */ + mov $(1 << (CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT) - 1), %al + wrmsr + /* Mask 1 is used for evicatable cache */ + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + /* Invert bits that are to be used for cache */ + mov $(1 << (CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT) - 1), %al + xor $~0, %al + wrmsr +#endif post_code(0x26) /* Clear the cache memory region. This will also fill up the cache */ @@ -139,11 +157,13 @@ clear_var_mtrr: post_code(0x27) +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr +#endif post_code(0x28) diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index 68bcb31..bb96419 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -56,3 +56,10 @@ void platform_segment_loaded(uintptr_t start, size_t size, int flags) flush_l1d_to_l2(); } + +void cache_qos_select_mask(uint8_t mask) +{ + msr_t msr = rdmsr(MTRR_IA32_PQR_ASSOC); + msr.hi |= mask; + wrmsr(MTRR_IA32_PQR_ASSOC, msr); +} diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S index 339242b..e5706cf 100644 --- a/src/soc/intel/apollolake/exit_car.S +++ b/src/soc/intel/apollolake/exit_car.S @@ -27,14 +27,38 @@ chipset_teardown_car: */ pop %ebx - /* invalidate cache contents. */ - invd + /* + * Flush all cache lines into the DRAM. Since we are running in the + * very region, disable MTRR first. + */ + /* Disable MTRRs. */ mov $(MTRR_DEF_TYPE_MSR), %ecx rdmsr and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr +#if IS_ENABLED(CONFIG_CAR_CQOS) + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + mov $~0, %al + wrmsr + + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + mov $~0, %al + wrmsr + + /* reset CLOS selector */ + mov $MTRR_IA32_PQR_ASSOC, %ecx + rdmsr + and $~(1 << 0 | 1 << 1), %edx + wrmsr +#endif + /* invalidate cache contents. */ + invd + +#if IS_ENABLED(CONFIG_CAR_NEM) /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ mov $(MSR_EVICT_CTL), %ecx rdmsr @@ -42,6 +66,7 @@ chipset_teardown_car: wrmsr and $(~(1 << 0)), %eax wrmsr +#endif /* Return to caller. */ jmp *%ebx diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 78fc0b0..13a47cd 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -23,6 +23,7 @@ #include <device/device.h> void apollolake_init_cpus(struct device *dev); +void cache_qos_select_mask(uint8_t mask); #endif #define CPUID_APOLLOLAKE_A0 0x506c8 @@ -35,6 +36,17 @@ void apollolake_init_cpus(struct device *dev); #define MSR_EMULATE_PM_TMR 0x121 #define EMULATE_PM_TMR_EN (1 << 16) +#define MTRR_L2_QOS_MASK(reg) (0xd10 + reg) +#define MTRR_IA32_PQR_ASSOC 0xc8f +/* 16 way cache, 8 bits per QOS, 64 byte cache line, 1024 sets */ +#define CACHE_WAYS 16 +#define CACHE_BITS_PER_MASK 8 +#define CACHE_LINE_SIZE 64 +#define CACHE_SETS 1024 +/* Each bit in QOS mask controls this many bytes */ +#define CACHE_QOS_SIZE_PER_BIT ((CACHE_WAYS / CACHE_BITS_PER_MASK) * \ + CACHE_LINE_SIZE * CACHE_SETS) + #define BASE_CLOCK_MHZ 100 /* Common Timer Copy (CTC) frequency - 19.2MHz. */

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Patch set updated for coreboot: WIP: soc/intel/apollolake: Update stage link addresses for 768 KiB cache
by Andrey Petrov 28 Jun '16

28 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15454 -gerrit commit 6aff62f952d762bee833c0bef437cdf7d2c538e2 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jun 24 18:15:09 2016 -0700 WIP: soc/intel/apollolake: Update stage link addresses for 768 KiB cache Update link addresses for romstage and verstage. Also change build time relocation address for FSP-M to match. Actual addresses are ballpark estimate and need to be validated. BUG=chrome-os-partner:51959 Change-Id: Ia51a341f05b33151ea5fda9f8620408b5a15bc19 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index f51dbfb..c49d67d 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -120,13 +120,13 @@ config X86_TOP4G_BOOTMEDIA_MAP config ROMSTAGE_ADDR hex - default 0xfef3e000 + default 0xfef11000 help The base address (in CAR) where romstage should be linked config VERSTAGE_ADDR hex - default 0xfef60000 + default 0xfef09000 help The base address (in CAR) where verstage should be linked @@ -136,7 +136,7 @@ config CACHE_MRC_SETTINGS config FSP_M_ADDR hex - default 0xfef60000 + default 0xfef40000 help The address FSP-M will be relocated to during build time

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Patch set updated for coreboot: vbnv: Flush vbnv cache if it is dirty
by Furquan Shaikh 28 Jun '16

28 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15457 -gerrit commit 4537b43bb08e7e8710d088f8a09a44df941a62a0 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jun 27 15:16:42 2016 -0700 vbnv: Flush vbnv cache if it is dirty Maintain a flag to indicate if the cache is dirty (i.e. if the cache content was updated in vbnv layer). Add a new API to allow caller to update the vbnv cache on storage based on either: 1. Update requested by caller, or 2. Cache is dirty Change-Id: I239939d5f9731d89a9d53fe662321b93fc1ab113 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/vendorcode/google/chromeos/vbnv.c | 22 +++++++++++++++++++++- src/vendorcode/google/chromeos/vbnv.h | 1 + .../google/chromeos/vboot2/vboot_logic.c | 9 ++++----- 3 files changed, 26 insertions(+), 6 deletions(-) diff --git a/src/vendorcode/google/chromeos/vbnv.c b/src/vendorcode/google/chromeos/vbnv.c index 92f03fb..0c9e32f 100644 --- a/src/vendorcode/google/chromeos/vbnv.c +++ b/src/vendorcode/google/chromeos/vbnv.c @@ -14,6 +14,7 @@ */ #include <arch/early_variables.h> +#include <console/console.h> #include <string.h> #include <types.h> #include "chromeos.h" @@ -21,6 +22,7 @@ #include "vbnv_layout.h" static int vbnv_initialized CAR_GLOBAL; +static int vbnv_dirty CAR_GLOBAL; static uint8_t vbnv[VBNV_BLOCK_SIZE] CAR_GLOBAL; /* Wrappers for accessing the variables marked as CAR_GLOBAL. */ @@ -67,6 +69,7 @@ static void reset_vbnv(uint8_t *vbnv_copy) HEADER_FIRMWARE_SETTINGS_RESET | HEADER_KERNEL_SETTINGS_RESET; vbnv_copy[CRC_OFFSET] = crc8_vbnv(vbnv_copy, CRC_OFFSET); + car_set_var(vbnv_dirty, true); } /* Read VBNV data into cache. */ @@ -103,9 +106,17 @@ void read_vbnv(uint8_t *vbnv_copy) /* * Write VBNV data to configured storage backend. * This assumes that the caller has updated the CRC already. + * Checks to see if upper layer requests update or if cache is dirty. If not, + * vbnv is not updated. */ -void save_vbnv(const uint8_t *vbnv_copy) +void save_vbnv_if_needed(const uint8_t *vbnv_copy, bool update) { + /* Bail out if upper layer doesn't require update and cache is clean. */ + if (!update && !car_get_var(vbnv_dirty)) + return; + + printk(BIOS_INFO, "Saving nvdata\n"); + if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)) save_vbnv_cmos(vbnv_copy); else if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_EC)) @@ -115,6 +126,15 @@ void save_vbnv(const uint8_t *vbnv_copy) /* Clear initialized flag to force cached data to be updated */ car_set_var(vbnv_initialized, 0); + + /* Clear dirty flag to indicate that cache was flushed. */ + car_set_var(vbnv_dirty, false); +} + +/* Wrapper function to force vbnv update. */ +void save_vbnv(const uint8_t *vbnv_copy) +{ + save_vbnv_if_needed(vbnv_copy, true); } /* Save a recovery reason into VBNV. */ diff --git a/src/vendorcode/google/chromeos/vbnv.h b/src/vendorcode/google/chromeos/vbnv.h index 5d21cc8..b19b11a 100644 --- a/src/vendorcode/google/chromeos/vbnv.h +++ b/src/vendorcode/google/chromeos/vbnv.h @@ -20,6 +20,7 @@ /* Generic functions */ void read_vbnv(uint8_t *vbnv_copy); +void save_vbnv_if_needed(const uint8_t *vbnv_copy, bool update); void save_vbnv(const uint8_t *vbnv_copy); int verify_vbnv(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c index a81a9c2..a5ff68a 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c @@ -266,11 +266,10 @@ static int locate_firmware(struct vb2_context *ctx, */ static void save_if_needed(struct vb2_context *ctx) { - if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { - printk(BIOS_INFO, "Saving nvdata\n"); - save_vbnv(ctx->nvdata); - ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED; - } + save_vbnv_if_needed(ctx->nvdata, !!(ctx->flags & + VB2_CONTEXT_NVDATA_CHANGED)); + ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED; + if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) { printk(BIOS_INFO, "Saving secdata\n"); antirollback_write_space_firmware(ctx);

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New patch to review for coreboot: soc/intel/apollolake: Update Upd header files for FSP Label 143_10
by Brandon Breitenstein 28 Jun '16

28 Jun '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15459 -gerrit commit 5f1333978e30e0ce45a12ee0ba16ccb7de8d1c31 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Jun 24 10:41:39 2016 -0700 soc/intel/apollolake: Update Upd header files for FSP Label 143_10 New UPDs added to header files as well as many comment fixes. Memory infor is now defined in FspmUpd.h and added ability to skip CSE RBP for coreboot. BUG=chrome-os-partner:54677 BRANCH=none TEST=built and tested with FSP 143_10 version Change-Id: I7e1f531ebbe343b45151a265ac715ae74aeffcad Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 47 +++++++++++- src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 83 +++++++++++----------- 2 files changed, 85 insertions(+), 45 deletions(-) diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index 5f5f367..3eee20b 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -36,6 +36,42 @@ are permitted provided that the following conditions are met: #include "FspUpd.h" #include <fsp/upd.h> +#define MAX_CHANNELS_NUM 4 +#define MAX_DIMMS_NUM 1 + +struct DIMM_INFO { + uint8_t DimmId; + uint32_t SizeInMb; + uint16_t MfgId; + /** Module part number for DRR3 is 18 bytes + but DRR4 is 20 bytes as per JEDEC Spec, so + reserving 20 bytes **/ + uint8_t ModulePartNum[20]; +} __attribute__((packed)); + +struct CHANNEL_INFO { + uint8_t ChannelId; + uint8_t DimmCount; + struct DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} __attribute__((packed)); + +struct FSP_SMBIOS_MEMORY_INFO { + uint8_t Revision; + uint8_t DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + uint16_t MemoryType; + uint16_t MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + uint8_t ErrorCorrectionType; + uint8_t ChannelCount; + struct CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} __attribute__((packed)); + + /** Fsp M Configuration **/ struct FSP_M_CONFIG { @@ -528,9 +564,16 @@ struct FSP_M_CONFIG { **/ void* MrcBootDataPtr; -/** Offset 0x0135 +/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB + Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of + CSE. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + uint8_t SkipCseRbp; + +/** Offset 0x0136 **/ - uint8_t ReservedFspmUpd[27]; + uint8_t ReservedFspmUpd[26]; } __attribute__((packed)); /** Fsp M Test Configuration diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h index d4ecd36..8dd824b 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h @@ -587,10 +587,9 @@ struct FSP_S_CONFIG { **/ uint8_t HpetFunctionNumber; -/** Offset 0x00AF - Hpet Base Address - Hpet Base Address. 0xFED00000(Default). +/** Offset 0x00AF **/ - uint32_t HpetBase; + uint32_t UnusedUpdSpace1; /** Offset 0x00B3 - IoApic Valid BDF Value Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. @@ -635,7 +634,7 @@ struct FSP_S_CONFIG { **/ uint8_t IshEnable; -/** Offset 0x00BB - ISH Controller +/** Offset 0x00BB - BIOS Interface Lock Down Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. 0:Disable, 1:Enable(Default). $EN_DIS @@ -663,7 +662,7 @@ struct FSP_S_CONFIG { Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t S0ixEnable; + uint8_t LPSS_S0ixEnable; /** Offset 0x00C0 - LPSS I2C Clock Gating Configuration Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). @@ -770,8 +769,8 @@ struct FSP_S_CONFIG { **/ uint8_t Spi2Enable; -/** Offset 0x00DE - UART Debug Bass Address - UART Debug Bass Address. 0x00000000(Default). +/** Offset 0x00DE - UART Debug Base Address + UART Debug Base Address. 0x00000000(Default). **/ uint32_t Uart2KernelDebugBaseAddress; @@ -810,7 +809,7 @@ struct FSP_S_CONFIG { **/ uint8_t PcieRootPortPeerMemoryWriteEnable; -/** Offset 0x00E8 - PCIE SWSMI Nubmer +/** Offset 0x00E8 - PCIE SWSMI Number This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). **/ uint8_t PcieAspmSwSmiNumber; @@ -932,7 +931,7 @@ struct FSP_S_CONFIG { uint8_t PcieRpCompletionTimeout[6]; /** Offset 0x0173 - PTM Support - Enable/Diable PTM Support. 0:Disable(Default), 1:Enable. + Enable/Disable PTM Support. 0:Disable(Default), 1:Enable. **/ uint8_t PtmEnable[6]; @@ -957,7 +956,7 @@ struct FSP_S_CONFIG { **/ uint8_t PcieRpLtrConfigLock[6]; -/** Offset 0x0191 - PME_B0_S5 Diable bit +/** Offset 0x0191 - PME_B0_S5 Disable bit PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. $EN_DIS **/ @@ -1029,8 +1028,8 @@ struct FSP_S_CONFIG { uint8_t SataPortsHotPlug[2]; /** Offset 0x01A0 - Mechanical Presence Switch - Controls reporting if this port has an Mechanical Presence Switch.\nNote:Requires - hardware support. 0:Disable, 1:Enable(Default). + Controls reporting if this port has an Mechanical Presence Switch.\n + Note:Requires hardware support. 0:Disable, 1:Enable(Default). **/ uint8_t SataPortsInterlockSw[2]; @@ -1075,20 +1074,9 @@ struct FSP_S_CONFIG { **/ uint16_t SubSystemId; -/** Offset 0x01B4 - PM Base Address - PM Base Address. 0x400(Default). +/** Offset 0x01B4 **/ - uint16_t AcpiBase; - -/** Offset 0x01B6 - PMC Base Address - PMC Base Address. 0xD10010000(Default). -**/ - uint32_t PmcBase; - -/** Offset 0x01BA - P2SB Base Address - P2SB Base Address. 0xD0000000(Default). -**/ - uint32_t P2sbBase; + uint8_t UnusedUpdSpace2[10]; /** Offset 0x01BE - CRIDSettings PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. @@ -1150,7 +1138,7 @@ struct FSP_S_CONFIG { /** Offset 0x01C8 - Start Frame Pulse Width Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. - $EN_DIS + 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk **/ uint8_t StartFramePulse; @@ -1166,10 +1154,9 @@ struct FSP_S_CONFIG { **/ uint8_t ArpEnable; -/** Offset 0x01CB - SMBus Base Address (IO space) - SMBUS Base Address (IO space). 0xEFA0(Default). +/** Offset 0x01CB **/ - uint16_t SmbusIoBase; + uint16_t UnusedUpdSpace3; /** Offset 0x01CD - SMBus Table Elements The number of elements in the Reserved SMBus Address Table. 0x0080(Default). @@ -1189,14 +1176,14 @@ struct FSP_S_CONFIG { uint8_t DisableComplianceMode; /** Offset 0x0250 - USB Per-Port Control - Control each of the USB ports (0~3) enable/disable. 0:Disable(Default), 1:Enable. + Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t UsbPerPortCtl; /** Offset 0x0251 - xHCI Mode - Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default), 3:SmartAuto. - $EN_DIS + Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default) + 0:Disable, 1:Enable, 2:Auto **/ uint8_t Usb30Mode; @@ -1224,7 +1211,7 @@ struct FSP_S_CONFIG { /** Offset 0x026E - XDCI Support Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. - $EN_DIS + 0:Disable, 1:PCI_Mode, 2:ACPI_mode **/ uint8_t UsbOtg; @@ -1293,8 +1280,10 @@ struct FSP_S_CONFIG { uint16_t PcieRpLtrMaxSnoopLatency[6]; /** Offset 0x028A - Snoop Latency Override - Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually - enter override values.\nAuto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). + Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). **/ uint8_t PcieRpSnoopLatencyOverrideMode[6]; @@ -1315,9 +1304,10 @@ struct FSP_S_CONFIG { uint16_t PcieRpLtrMaxNonSnoopLatency[6]; /** Offset 0x02AE - Non Snoop Latency Override - Non Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually - enter override values.\nAuto: Maintain default BIOS flow. 0:Disable, 1:Enable, - 2:Auto(Default). + Non Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). **/ uint8_t PcieRpNonSnoopLatencyOverrideMode[6]; @@ -1361,7 +1351,7 @@ struct FSP_S_CONFIG { **/ uint8_t TcoTimerHaltLock; -/** Offset 0x02D5 - Power Button Override Peroid +/** Offset 0x02D5 - Power Button Override Period specifies how long will PMC wait before initiating a global reset. 000b-4s(default), 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.) 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s @@ -1369,7 +1359,7 @@ struct FSP_S_CONFIG { uint8_t PwrBtnOverridePeriod; /** Offset 0x02D6 - Power Button Native Mode Disable - Diable power button native mode, when 1, this will result in the PMC logic constantly + Disable power button native mode, when 1, this will result in the PMC logic constantly seeing the power button as de-asserted. 0 (default)) $EN_DIS **/ @@ -1479,13 +1469,20 @@ struct FSP_S_CONFIG { /** Offset 0x0326 - Os Selection Mode Select OS mode. 0:Windows(default), 1:Android, 2:Win7 - $EN_DIS + 0:Windows, 1:Android, 2:Win7 **/ uint8_t OsSelection; -/** Offset 0x0327 +/** Offset 0x0327 - Monitor Mwait Enable + Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux + based OS, this should be Disabled. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t MonitorMwaitEnable; + +/** Offset 0x0328 **/ - uint8_t ReservedFspsUpd[9]; + uint8_t ReservedFspsUpd[8]; } __attribute__((packed)); /** Fsp S Test Configuration

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New patch to review for coreboot: soc/intel/apollolake: Remove UPDs that are no longer valid
by Brandon Breitenstein 28 Jun '16

28 Jun '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15458 -gerrit commit abe74ce8ab28998bd93d5f25b925b337808d0587 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Jun 24 12:09:50 2016 -0700 soc/intel/apollolake: Remove UPDs that are no longer valid Removing base address upds that are no longer valid from coreboot This is required for use with the FSP 143_10 header files. BUG=chrome-os-partner:54677 BRANCH=none TEST=built image with FSP 143_10 headers Change-Id: Id34c6a397d7de432c2450a7617d28b57bfe0d804 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/chip.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 821570b..044ef91 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -253,12 +253,6 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) if (cfg->emmc_rx_cmd_data_cntl2 != 0) silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; - /* Our defaults may not match FSP defaults, so set them explicitly */ - silconfig->AcpiBase = ACPI_PMIO_BASE; - /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ - silconfig->PmcBase = PMC_BAR0 + 0x1000; - silconfig->P2sbBase = P2SB_BAR; - silconfig->IshEnable = cfg->integrated_sensor_hub_enable; /* Disable setting of EISS bit in FSP. */

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New patch to review for coreboot: vbnv: Flush vbnv cache if it is dirty
by Furquan Shaikh 28 Jun '16

28 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15457 -gerrit commit b7b2b7654b5e54e483a8c2c6777eb1dc698f78e5 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jun 27 15:16:42 2016 -0700 vbnv: Flush vbnv cache if it is dirty Maintain a flag to indicate if the cache is dirty (i.e. if the cache content was updated in vbnv layer). Add a new API to allow caller to update the vbnv cache on storage based on either: 1. Update requested by caller, or 2. Cache is dirty Change-Id: I239939d5f9731d89a9d53fe662321b93fc1ab113 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/vendorcode/google/chromeos/vbnv.c | 22 +++++++++++++++++++++- src/vendorcode/google/chromeos/vbnv.h | 1 + .../google/chromeos/vboot2/vboot_logic.c | 9 ++++----- 3 files changed, 26 insertions(+), 6 deletions(-) diff --git a/src/vendorcode/google/chromeos/vbnv.c b/src/vendorcode/google/chromeos/vbnv.c index 92f03fb..3f70662 100644 --- a/src/vendorcode/google/chromeos/vbnv.c +++ b/src/vendorcode/google/chromeos/vbnv.c @@ -14,6 +14,7 @@ */ #include <arch/early_variables.h> +#include <console/console.h> #include <string.h> #include <types.h> #include "chromeos.h" @@ -21,6 +22,7 @@ #include "vbnv_layout.h" static int vbnv_initialized CAR_GLOBAL; +static int vbnv_dirty CAR_GLOBAL; static uint8_t vbnv[VBNV_BLOCK_SIZE] CAR_GLOBAL; /* Wrappers for accessing the variables marked as CAR_GLOBAL. */ @@ -67,6 +69,7 @@ static void reset_vbnv(uint8_t *vbnv_copy) HEADER_FIRMWARE_SETTINGS_RESET | HEADER_KERNEL_SETTINGS_RESET; vbnv_copy[CRC_OFFSET] = crc8_vbnv(vbnv_copy, CRC_OFFSET); + car_set_var(vbnv_dirty, 1); } /* Read VBNV data into cache. */ @@ -103,9 +106,17 @@ void read_vbnv(uint8_t *vbnv_copy) /* * Write VBNV data to configured storage backend. * This assumes that the caller has updated the CRC already. + * Checks to see if upper layer requests update or if cache is dirty. If not, + * vbnv is not updated. */ -void save_vbnv(const uint8_t *vbnv_copy) +void save_vbnv_if_needed(const uint8_t *vbnv_copy, bool update) { + /* Bail out if upper layer doesn't require update and cache is clean. */ + if (!update && !car_get_var(vbnv_dirty)) + return; + + printk(BIOS_INFO, "Saving nvdata\n"); + if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)) save_vbnv_cmos(vbnv_copy); else if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_EC)) @@ -115,6 +126,15 @@ void save_vbnv(const uint8_t *vbnv_copy) /* Clear initialized flag to force cached data to be updated */ car_set_var(vbnv_initialized, 0); + + /* Clear dirty flag to indicate that cache was flushed. */ + car_set_var(vbnv_dirty, 0); +} + +/* Wrapper function to force vbnv update. */ +void save_vbnv(const uint8_t *vbnv_copy) +{ + save_vbnv_if_needed(vbnv_copy, true); } /* Save a recovery reason into VBNV. */ diff --git a/src/vendorcode/google/chromeos/vbnv.h b/src/vendorcode/google/chromeos/vbnv.h index 5d21cc8..b19b11a 100644 --- a/src/vendorcode/google/chromeos/vbnv.h +++ b/src/vendorcode/google/chromeos/vbnv.h @@ -20,6 +20,7 @@ /* Generic functions */ void read_vbnv(uint8_t *vbnv_copy); +void save_vbnv_if_needed(const uint8_t *vbnv_copy, bool update); void save_vbnv(const uint8_t *vbnv_copy); int verify_vbnv(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c index a81a9c2..a5ff68a 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c @@ -266,11 +266,10 @@ static int locate_firmware(struct vb2_context *ctx, */ static void save_if_needed(struct vb2_context *ctx) { - if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { - printk(BIOS_INFO, "Saving nvdata\n"); - save_vbnv(ctx->nvdata); - ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED; - } + save_vbnv_if_needed(ctx->nvdata, !!(ctx->flags & + VB2_CONTEXT_NVDATA_CHANGED)); + ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED; + if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) { printk(BIOS_INFO, "Saving secdata\n"); antirollback_write_space_firmware(ctx);

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Patch set updated for coreboot: WIP: soc/intel/apollolake: Cache cbmem region
by Andrey Petrov 28 Jun '16

28 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15456 -gerrit commit 62bfe0add03efce7fe71b5436ae251785c0f2a7a Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jun 24 18:40:28 2016 -0700 WIP: soc/intel/apollolake: Cache cbmem region Configure write-back MTRRs so that 16 MiB under cbmem_top is cached. This allows caching of FSP reserved memory and postcar stage itself. On CAR teardown the memory is flushed with clflush instruction. Depending on what cache configuration is used, either L1 (NEM) or both L1 and L2 (CQOS) storage is used for caching purposes. This is WIP patch, because currently location of cbmem_top can not be known before memory is trained. So addresses are hardcoded. BUG=chrome-os-partner:51959 TEST=run primitive memtest on 16 MiB cached memory region after mem is trained, observe x7 improvement on L1 only, x12 on L2 of 256 KiB Change-Id: I62aad238a3056f9bbe5327dfb33a2a1112d61194 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/exit_car.S | 8 ++++++++ src/soc/intel/apollolake/romstage.c | 9 ++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S index e5706cf..c0fb39b 100644 --- a/src/soc/intel/apollolake/exit_car.S +++ b/src/soc/intel/apollolake/exit_car.S @@ -38,6 +38,14 @@ chipset_teardown_car: and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr + /* Flush down whatever we have */ + mov $0x7a000000, %eax +loop: + clflush (%eax) + add $CACHE_LINE_SIZE, %eax + cmp $0x7b000000, %eax + jl loop + #if IS_ENABLED(CONFIG_CAR_CQOS) mov $MTRR_L2_QOS_MASK(0), %ecx rdmsr diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index ce28326..1fa52fd 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -112,7 +112,7 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; size_t mrc_data_size; uintptr_t top_of_ram; - int prev_sleep_state; + int prev_sleep_state, mtrr; struct romstage_handoff *handoff; struct chipset_power_state *ps = car_get_var_ptr(&power_state); @@ -129,6 +129,13 @@ asmlinkage void car_stage_entry(void) range_entry_init(&reg_car, (uintptr_t)_car_relocatable_data_end, (uintptr_t)_car_region_end, 0); + mtrr = get_free_var_mtrr(); + if (mtrr==-1) + printk(BIOS_CRIT, "no available MTRRs to cache cbmem!\n"); + else + /* Make sure cbmem 16 MiB under CBMEM is cachable */ + set_var_mtrr(mtrr, 0x7a000000, 16 * MiB, MTRR_TYPE_WRBACK); + if (fsp_memory_init(&hob_list_ptr, &reg_car) != FSP_SUCCESS) { die("FSP memory init failed. Giving up."); }

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Patch set updated for coreboot: WIP: soc/intel/apollolake: Change default CAR size to 768 KiB
by Andrey Petrov 28 Jun '16

28 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15453 -gerrit commit 8a57f5e0c82eb3ed4e367eb1172a0b7f93b5b8dd Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Jun 27 13:37:51 2016 -0700 WIP: soc/intel/apollolake: Change default CAR size to 768 KiB As whole 1024 KiB is not used, it is possible to shrink CAR size to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used to setup it. This is part of preparation for CQOS enabling. BUG=chrome-os-partner:51959 Change-Id: I56326a1790df202a0e428e092dd90286c58763c5 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 26 ++++++++++++- src/soc/intel/apollolake/bootblock/cache_as_ram.S | 46 +++++++++++++++++++++++ 2 files changed, 71 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 98ce7d8..fd4e5ac 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -77,7 +77,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex "Length in bytes of cache-as-RAM" - default 0x100000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage. @@ -182,4 +182,28 @@ config IFWI_FILE_NAME help Name of file to store in the IFWI region. +choice + prompt "Cache-as-ram implementation" + default CAR_CQOS + help + This option allows you to select how cache-as-ram (CAR) is set up. + +config CAR_NEM + bool "Non-evict mode" + help + Traditionally, CAR is set up by using Non-Evict mode. This method + does not allow CAR and cache to co-exist, because cache fills are + block in NEM mode. + + +config CAR_CQOS + bool "Cache Quality of Service" + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up portion of L2 cache for + CAR and use remainded for actual caching. + +endchoice + + endif diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index 8647206..3c97bb2 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -70,6 +70,31 @@ clear_var_mtrr: post_code(0x24) +#if (CONFIG_DCACHE_RAM_SIZE == 0xc0000) /* 768 KiB */ + /* 512 KiB */ + mov $MTRR_PHYS_BASE(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK(0), %ecx + mov $~(0x80000 - 1), %eax /* size mask */ + or $MTRR_PHYS_MASK_VALID, %eax + wrmsr + + /* 256 KiB */ + mov $MTRR_PHYS_BASE(1), %ecx + mov $(CONFIG_DCACHE_RAM_BASE + 0x80000), %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK(1), %ecx + mov $~(0x40000 - 1), %eax /* size mask */ + or $MTRR_PHYS_MASK_VALID, %eax + wrmsr +#else /* Configure CAR region as write-back (WB) */ mov $MTRR_PHYS_BASE(0), %ecx mov $CONFIG_DCACHE_RAM_BASE, %eax @@ -82,6 +107,7 @@ clear_var_mtrr: mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */ or $MTRR_PHYS_MASK_VALID, %eax wrmsr +#endif post_code(0x25) @@ -97,12 +123,30 @@ clear_var_mtrr: invd mov %eax, %cr0 +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (setup stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr +#endif +#if IS_ENABLED(CONFIG_CAR_CQOS) + /* Mask 0 is used for CAR */ + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + /* Calculate how many bits to be used for CAR */ + mov $(1 << (CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT) - 1), %al + wrmsr + + /* Mask 1 is used for evicatable cache */ + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + /* Invert bits that are to be used for cache */ + mov $(1 << (CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT) - 1), %al + xor $~0, %al + wrmsr +#endif post_code(0x26) /* Clear the cache memory region. This will also fill up the cache */ @@ -113,11 +157,13 @@ clear_var_mtrr: post_code(0x27) +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr +#endif post_code(0x28)

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Patch set updated for coreboot: soc/intel/apollolake: Add CQOS CAR implementation
by Andrey Petrov 28 Jun '16

28 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15455 -gerrit commit 19784455771fee44f75e53e6fdac9115ea86f40f Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Jun 27 13:39:34 2016 -0700 soc/intel/apollolake: Add CQOS CAR implementation Add new Cache Quality of Service option that allows to configure cache non-evict mode by manipulating CQOS settings. Also, CQOS allows using cache non-evict mode simultaneously with regular evicting caching. BUG=chrome-os-partner:51959 Change-Id: Ic7f9899918f94a5788b02a4fbd2f5d5ba9aaf91d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/bootblock/bootblock.c | 4 ++++ src/soc/intel/apollolake/car.c | 7 +++++++ src/soc/intel/apollolake/exit_car.S | 29 ++++++++++++++++++++++++-- src/soc/intel/apollolake/include/soc/cpu.h | 12 +++++++++++ 4 files changed, 50 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 8c1ff91..00c280a 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -168,5 +168,9 @@ void bootblock_soc_early_init(void) enable_spibar(); +#if IS_ENABLED(CONFIG_CAR_CQOS) + cache_qos_select_mask(1); +#endif + cache_bios_region(); } diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index 68bcb31..bb96419 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -56,3 +56,10 @@ void platform_segment_loaded(uintptr_t start, size_t size, int flags) flush_l1d_to_l2(); } + +void cache_qos_select_mask(uint8_t mask) +{ + msr_t msr = rdmsr(MTRR_IA32_PQR_ASSOC); + msr.hi |= mask; + wrmsr(MTRR_IA32_PQR_ASSOC, msr); +} diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S index 339242b..e5706cf 100644 --- a/src/soc/intel/apollolake/exit_car.S +++ b/src/soc/intel/apollolake/exit_car.S @@ -27,14 +27,38 @@ chipset_teardown_car: */ pop %ebx - /* invalidate cache contents. */ - invd + /* + * Flush all cache lines into the DRAM. Since we are running in the + * very region, disable MTRR first. + */ + /* Disable MTRRs. */ mov $(MTRR_DEF_TYPE_MSR), %ecx rdmsr and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr +#if IS_ENABLED(CONFIG_CAR_CQOS) + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + mov $~0, %al + wrmsr + + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + mov $~0, %al + wrmsr + + /* reset CLOS selector */ + mov $MTRR_IA32_PQR_ASSOC, %ecx + rdmsr + and $~(1 << 0 | 1 << 1), %edx + wrmsr +#endif + /* invalidate cache contents. */ + invd + +#if IS_ENABLED(CONFIG_CAR_NEM) /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ mov $(MSR_EVICT_CTL), %ecx rdmsr @@ -42,6 +66,7 @@ chipset_teardown_car: wrmsr and $(~(1 << 0)), %eax wrmsr +#endif /* Return to caller. */ jmp *%ebx diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 78fc0b0..13a47cd 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -23,6 +23,7 @@ #include <device/device.h> void apollolake_init_cpus(struct device *dev); +void cache_qos_select_mask(uint8_t mask); #endif #define CPUID_APOLLOLAKE_A0 0x506c8 @@ -35,6 +36,17 @@ void apollolake_init_cpus(struct device *dev); #define MSR_EMULATE_PM_TMR 0x121 #define EMULATE_PM_TMR_EN (1 << 16) +#define MTRR_L2_QOS_MASK(reg) (0xd10 + reg) +#define MTRR_IA32_PQR_ASSOC 0xc8f +/* 16 way cache, 8 bits per QOS, 64 byte cache line, 1024 sets */ +#define CACHE_WAYS 16 +#define CACHE_BITS_PER_MASK 8 +#define CACHE_LINE_SIZE 64 +#define CACHE_SETS 1024 +/* Each bit in QOS mask controls this many bytes */ +#define CACHE_QOS_SIZE_PER_BIT ((CACHE_WAYS / CACHE_BITS_PER_MASK) * \ + CACHE_LINE_SIZE * CACHE_SETS) + #define BASE_CLOCK_MHZ 100 /* Common Timer Copy (CTC) frequency - 19.2MHz. */

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Patch set updated for coreboot: WIP: soc/intel/apollolake: Update stage link addresses for 768 KiB cache
by Andrey Petrov 28 Jun '16

28 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15454 -gerrit commit 97d08821c867f711aa0840c60dba44e2f7139387 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jun 24 18:15:09 2016 -0700 WIP: soc/intel/apollolake: Update stage link addresses for 768 KiB cache Update link addresses for romstage and verstage. Also change build time relocation address for FSP-M to match. Actual addresses are ballpark estimate and need to be validated. BUG=chrome-os-partner:51959 Change-Id: Ia51a341f05b33151ea5fda9f8620408b5a15bc19 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index fd4e5ac..cbe1da8 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -120,13 +120,13 @@ config X86_TOP4G_BOOTMEDIA_MAP config ROMSTAGE_ADDR hex - default 0xfef3e000 + default 0xfef11000 help The base address (in CAR) where romstage should be linked config VERSTAGE_ADDR hex - default 0xfef60000 + default 0xfef09000 help The base address (in CAR) where verstage should be linked @@ -136,7 +136,7 @@ config CACHE_MRC_SETTINGS config FSP_M_ADDR hex - default 0xfef60000 + default 0xfef40000 help The address FSP-M will be relocated to during build time

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