coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: vbnv: Do not silently reset cache in read_vbnv
by Furquan Shaikh 28 Jun '16

28 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15457 -gerrit commit 40aae009b0715ce19b940e1af6700f0b9db8f105 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jun 27 16:19:09 2016 -0700 vbnv: Do not silently reset cache in read_vbnv Currently, read_vbnv performs a reset of the vbnv cache if it is not valid. However, this information is not passed up to the vboot layer, thus resulting in missed write-back of vbnv cache to storage if vboot does not update the cache itself. Update read_vbnv to return a value depending upon whether it wants a write-back to be performed when save is called. Return value: 0 = No write-back required 1 = Write-back of VBNV cache is required. Change-Id: I239939d5f9731d89a9d53fe662321b93fc1ab113 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/vendorcode/google/chromeos/vbnv.c | 15 +++++++++++---- src/vendorcode/google/chromeos/vbnv.h | 7 ++++++- src/vendorcode/google/chromeos/vboot2/vboot_logic.c | 8 ++++++-- 3 files changed, 23 insertions(+), 7 deletions(-) diff --git a/src/vendorcode/google/chromeos/vbnv.c b/src/vendorcode/google/chromeos/vbnv.c index 92f03fb..baccb23 100644 --- a/src/vendorcode/google/chromeos/vbnv.c +++ b/src/vendorcode/google/chromeos/vbnv.c @@ -85,8 +85,12 @@ int verify_vbnv(uint8_t *vbnv_copy) (crc8_vbnv(vbnv_copy, CRC_OFFSET) == vbnv_copy[CRC_OFFSET]); } -/* Read VBNV data from configured storage backend. */ -void read_vbnv(uint8_t *vbnv_copy) +/* + * Read VBNV data from configured storage backend. + * If VBNV verification fails, reset the vbnv copy. + * Returns 1 if write-back of vbnv copy is required. Else, returns 0. + */ +int read_vbnv(uint8_t *vbnv_copy) { if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)) read_vbnv_cmos(vbnv_copy); @@ -96,8 +100,11 @@ void read_vbnv(uint8_t *vbnv_copy) read_vbnv_flash(vbnv_copy); /* Check data for consistency */ - if (!verify_vbnv(vbnv_copy)) - reset_vbnv(vbnv_copy); + if (verify_vbnv(vbnv_copy)) + return 0; + + reset_vbnv(vbnv_copy); + return 1; } /* diff --git a/src/vendorcode/google/chromeos/vbnv.h b/src/vendorcode/google/chromeos/vbnv.h index 5d21cc8..a66d687 100644 --- a/src/vendorcode/google/chromeos/vbnv.h +++ b/src/vendorcode/google/chromeos/vbnv.h @@ -19,7 +19,12 @@ #include <types.h> /* Generic functions */ -void read_vbnv(uint8_t *vbnv_copy); +/* + * Return value for read_vbnv: + * 1 = write-back of vbnv copy is required. + * 0 = otherwise + */ +int read_vbnv(uint8_t *vbnv_copy); void save_vbnv(const uint8_t *vbnv_copy); int verify_vbnv(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c index a81a9c2..116c949 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c @@ -301,8 +301,12 @@ void verstage_main(void) /* Set up context and work buffer */ vb2_init_work_context(&ctx); - /* Read nvdata from a non-volatile storage */ - read_vbnv(ctx.nvdata); + /* + * Read nvdata from a non-volatile storage and mark data as changed + * if instructed. + */ + if (read_vbnv(ctx.nvdata)) + ctx.flags |= VB2_CONTEXT_NVDATA_CHANGED; /* Set S3 resume flag if vboot should behave differently when selecting * which slot to boot. This is only relevant to vboot if the platform

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Patch set updated for coreboot: vbnv: Do not silently reset cache in read_vbnv
by Furquan Shaikh 28 Jun '16

28 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15457 -gerrit commit 2aed33345f3fc90da0e14c49f3fbc98fc7424b61 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jun 27 16:19:09 2016 -0700 vbnv: Do not silently reset cache in read_vbnv Currently, read_vbnv performs a reset of the vbnv cache if it is not valid. However, this information is not passed up to the vboot layer, thus resulting in missed write-back of vbnv cache to storage if vboot does not update the cache itself. Update read_vbnv to return a value depending upon whether it wants a write-back to be performed when save is called. Return value: 0 = No write-back required 1 = Write-back of VBNV cache is required. Change-Id: I239939d5f9731d89a9d53fe662321b93fc1ab113 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/vendorcode/google/chromeos/vbnv.c | 15 +++++++++++---- src/vendorcode/google/chromeos/vbnv.h | 2 +- src/vendorcode/google/chromeos/vboot2/vboot_logic.c | 3 ++- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/vendorcode/google/chromeos/vbnv.c b/src/vendorcode/google/chromeos/vbnv.c index 92f03fb..7b257f7 100644 --- a/src/vendorcode/google/chromeos/vbnv.c +++ b/src/vendorcode/google/chromeos/vbnv.c @@ -85,8 +85,12 @@ int verify_vbnv(uint8_t *vbnv_copy) (crc8_vbnv(vbnv_copy, CRC_OFFSET) == vbnv_copy[CRC_OFFSET]); } -/* Read VBNV data from configured storage backend. */ -void read_vbnv(uint8_t *vbnv_copy) +/* + * Read VBNV data from configured storage backend. + * If VBNV verification fails, reset the vbnv copy. + * Returns 1 if write-back of vbnv copy is required. Else, returns 0. + */ +uint8_t read_vbnv(uint8_t *vbnv_copy) { if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)) read_vbnv_cmos(vbnv_copy); @@ -96,8 +100,11 @@ void read_vbnv(uint8_t *vbnv_copy) read_vbnv_flash(vbnv_copy); /* Check data for consistency */ - if (!verify_vbnv(vbnv_copy)) - reset_vbnv(vbnv_copy); + if (verify_vbnv(vbnv_copy)) + return 0; + + reset_vbnv(vbnv_copy); + return 1; } /* diff --git a/src/vendorcode/google/chromeos/vbnv.h b/src/vendorcode/google/chromeos/vbnv.h index 5d21cc8..e8cd99d 100644 --- a/src/vendorcode/google/chromeos/vbnv.h +++ b/src/vendorcode/google/chromeos/vbnv.h @@ -19,7 +19,7 @@ #include <types.h> /* Generic functions */ -void read_vbnv(uint8_t *vbnv_copy); +uint8_t read_vbnv(uint8_t *vbnv_copy); void save_vbnv(const uint8_t *vbnv_copy); int verify_vbnv(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c index a81a9c2..e704d1f 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c @@ -302,7 +302,8 @@ void verstage_main(void) vb2_init_work_context(&ctx); /* Read nvdata from a non-volatile storage */ - read_vbnv(ctx.nvdata); + if (read_vbnv(ctx.nvdata)) + ctx.flags |= VB2_CONTEXT_NVDATA_CHANGED; /* Set S3 resume flag if vboot should behave differently when selecting * which slot to boot. This is only relevant to vboot if the platform

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Patch set updated for coreboot: soc/intel/apollolake: Update Upd header files for FSP Label 143_10
by Brandon Breitenstein 28 Jun '16

28 Jun '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15459 -gerrit commit b61ea8515c0b9222a146794587f0caeef3ce1a23 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Jun 24 10:41:39 2016 -0700 soc/intel/apollolake: Update Upd header files for FSP Label 143_10 New UPDs added to header files as well as many comment fixes. Memory infor is now defined in FspmUpd.h and added ability to skip CSE RBP for coreboot. Removes some UPDs that are no longer available from source. BUG=chrome-os-partner:54677 BRANCH=none TEST=built and tested with FSP 143_10 version Change-Id: I7e1f531ebbe343b45151a265ac715ae74aeffcad Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/chip.c | 6 -- src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 47 +++++++++++- src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 83 +++++++++++----------- 3 files changed, 85 insertions(+), 51 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 821570b..044ef91 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -253,12 +253,6 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) if (cfg->emmc_rx_cmd_data_cntl2 != 0) silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; - /* Our defaults may not match FSP defaults, so set them explicitly */ - silconfig->AcpiBase = ACPI_PMIO_BASE; - /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ - silconfig->PmcBase = PMC_BAR0 + 0x1000; - silconfig->P2sbBase = P2SB_BAR; - silconfig->IshEnable = cfg->integrated_sensor_hub_enable; /* Disable setting of EISS bit in FSP. */ diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index 5f5f367..3eee20b 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -36,6 +36,42 @@ are permitted provided that the following conditions are met: #include "FspUpd.h" #include <fsp/upd.h> +#define MAX_CHANNELS_NUM 4 +#define MAX_DIMMS_NUM 1 + +struct DIMM_INFO { + uint8_t DimmId; + uint32_t SizeInMb; + uint16_t MfgId; + /** Module part number for DRR3 is 18 bytes + but DRR4 is 20 bytes as per JEDEC Spec, so + reserving 20 bytes **/ + uint8_t ModulePartNum[20]; +} __attribute__((packed)); + +struct CHANNEL_INFO { + uint8_t ChannelId; + uint8_t DimmCount; + struct DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} __attribute__((packed)); + +struct FSP_SMBIOS_MEMORY_INFO { + uint8_t Revision; + uint8_t DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + uint16_t MemoryType; + uint16_t MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + uint8_t ErrorCorrectionType; + uint8_t ChannelCount; + struct CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} __attribute__((packed)); + + /** Fsp M Configuration **/ struct FSP_M_CONFIG { @@ -528,9 +564,16 @@ struct FSP_M_CONFIG { **/ void* MrcBootDataPtr; -/** Offset 0x0135 +/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB + Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of + CSE. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + uint8_t SkipCseRbp; + +/** Offset 0x0136 **/ - uint8_t ReservedFspmUpd[27]; + uint8_t ReservedFspmUpd[26]; } __attribute__((packed)); /** Fsp M Test Configuration diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h index d4ecd36..8dd824b 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h @@ -587,10 +587,9 @@ struct FSP_S_CONFIG { **/ uint8_t HpetFunctionNumber; -/** Offset 0x00AF - Hpet Base Address - Hpet Base Address. 0xFED00000(Default). +/** Offset 0x00AF **/ - uint32_t HpetBase; + uint32_t UnusedUpdSpace1; /** Offset 0x00B3 - IoApic Valid BDF Value Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. @@ -635,7 +634,7 @@ struct FSP_S_CONFIG { **/ uint8_t IshEnable; -/** Offset 0x00BB - ISH Controller +/** Offset 0x00BB - BIOS Interface Lock Down Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. 0:Disable, 1:Enable(Default). $EN_DIS @@ -663,7 +662,7 @@ struct FSP_S_CONFIG { Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t S0ixEnable; + uint8_t LPSS_S0ixEnable; /** Offset 0x00C0 - LPSS I2C Clock Gating Configuration Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). @@ -770,8 +769,8 @@ struct FSP_S_CONFIG { **/ uint8_t Spi2Enable; -/** Offset 0x00DE - UART Debug Bass Address - UART Debug Bass Address. 0x00000000(Default). +/** Offset 0x00DE - UART Debug Base Address + UART Debug Base Address. 0x00000000(Default). **/ uint32_t Uart2KernelDebugBaseAddress; @@ -810,7 +809,7 @@ struct FSP_S_CONFIG { **/ uint8_t PcieRootPortPeerMemoryWriteEnable; -/** Offset 0x00E8 - PCIE SWSMI Nubmer +/** Offset 0x00E8 - PCIE SWSMI Number This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). **/ uint8_t PcieAspmSwSmiNumber; @@ -932,7 +931,7 @@ struct FSP_S_CONFIG { uint8_t PcieRpCompletionTimeout[6]; /** Offset 0x0173 - PTM Support - Enable/Diable PTM Support. 0:Disable(Default), 1:Enable. + Enable/Disable PTM Support. 0:Disable(Default), 1:Enable. **/ uint8_t PtmEnable[6]; @@ -957,7 +956,7 @@ struct FSP_S_CONFIG { **/ uint8_t PcieRpLtrConfigLock[6]; -/** Offset 0x0191 - PME_B0_S5 Diable bit +/** Offset 0x0191 - PME_B0_S5 Disable bit PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. $EN_DIS **/ @@ -1029,8 +1028,8 @@ struct FSP_S_CONFIG { uint8_t SataPortsHotPlug[2]; /** Offset 0x01A0 - Mechanical Presence Switch - Controls reporting if this port has an Mechanical Presence Switch.\nNote:Requires - hardware support. 0:Disable, 1:Enable(Default). + Controls reporting if this port has an Mechanical Presence Switch.\n + Note:Requires hardware support. 0:Disable, 1:Enable(Default). **/ uint8_t SataPortsInterlockSw[2]; @@ -1075,20 +1074,9 @@ struct FSP_S_CONFIG { **/ uint16_t SubSystemId; -/** Offset 0x01B4 - PM Base Address - PM Base Address. 0x400(Default). +/** Offset 0x01B4 **/ - uint16_t AcpiBase; - -/** Offset 0x01B6 - PMC Base Address - PMC Base Address. 0xD10010000(Default). -**/ - uint32_t PmcBase; - -/** Offset 0x01BA - P2SB Base Address - P2SB Base Address. 0xD0000000(Default). -**/ - uint32_t P2sbBase; + uint8_t UnusedUpdSpace2[10]; /** Offset 0x01BE - CRIDSettings PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. @@ -1150,7 +1138,7 @@ struct FSP_S_CONFIG { /** Offset 0x01C8 - Start Frame Pulse Width Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. - $EN_DIS + 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk **/ uint8_t StartFramePulse; @@ -1166,10 +1154,9 @@ struct FSP_S_CONFIG { **/ uint8_t ArpEnable; -/** Offset 0x01CB - SMBus Base Address (IO space) - SMBUS Base Address (IO space). 0xEFA0(Default). +/** Offset 0x01CB **/ - uint16_t SmbusIoBase; + uint16_t UnusedUpdSpace3; /** Offset 0x01CD - SMBus Table Elements The number of elements in the Reserved SMBus Address Table. 0x0080(Default). @@ -1189,14 +1176,14 @@ struct FSP_S_CONFIG { uint8_t DisableComplianceMode; /** Offset 0x0250 - USB Per-Port Control - Control each of the USB ports (0~3) enable/disable. 0:Disable(Default), 1:Enable. + Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t UsbPerPortCtl; /** Offset 0x0251 - xHCI Mode - Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default), 3:SmartAuto. - $EN_DIS + Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default) + 0:Disable, 1:Enable, 2:Auto **/ uint8_t Usb30Mode; @@ -1224,7 +1211,7 @@ struct FSP_S_CONFIG { /** Offset 0x026E - XDCI Support Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. - $EN_DIS + 0:Disable, 1:PCI_Mode, 2:ACPI_mode **/ uint8_t UsbOtg; @@ -1293,8 +1280,10 @@ struct FSP_S_CONFIG { uint16_t PcieRpLtrMaxSnoopLatency[6]; /** Offset 0x028A - Snoop Latency Override - Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually - enter override values.\nAuto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). + Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). **/ uint8_t PcieRpSnoopLatencyOverrideMode[6]; @@ -1315,9 +1304,10 @@ struct FSP_S_CONFIG { uint16_t PcieRpLtrMaxNonSnoopLatency[6]; /** Offset 0x02AE - Non Snoop Latency Override - Non Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually - enter override values.\nAuto: Maintain default BIOS flow. 0:Disable, 1:Enable, - 2:Auto(Default). + Non Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). **/ uint8_t PcieRpNonSnoopLatencyOverrideMode[6]; @@ -1361,7 +1351,7 @@ struct FSP_S_CONFIG { **/ uint8_t TcoTimerHaltLock; -/** Offset 0x02D5 - Power Button Override Peroid +/** Offset 0x02D5 - Power Button Override Period specifies how long will PMC wait before initiating a global reset. 000b-4s(default), 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.) 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s @@ -1369,7 +1359,7 @@ struct FSP_S_CONFIG { uint8_t PwrBtnOverridePeriod; /** Offset 0x02D6 - Power Button Native Mode Disable - Diable power button native mode, when 1, this will result in the PMC logic constantly + Disable power button native mode, when 1, this will result in the PMC logic constantly seeing the power button as de-asserted. 0 (default)) $EN_DIS **/ @@ -1479,13 +1469,20 @@ struct FSP_S_CONFIG { /** Offset 0x0326 - Os Selection Mode Select OS mode. 0:Windows(default), 1:Android, 2:Win7 - $EN_DIS + 0:Windows, 1:Android, 2:Win7 **/ uint8_t OsSelection; -/** Offset 0x0327 +/** Offset 0x0327 - Monitor Mwait Enable + Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux + based OS, this should be Disabled. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t MonitorMwaitEnable; + +/** Offset 0x0328 **/ - uint8_t ReservedFspsUpd[9]; + uint8_t ReservedFspsUpd[8]; } __attribute__((packed)); /** Fsp S Test Configuration

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Patch set updated for coreboot: util/crossgcc: Implement buildgcc script checksum verification
by Philipp Deppenwiese 28 Jun '16

28 Jun '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15170 -gerrit commit 6e0af5884fb2e65782eda2625d394afc69959827 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Mon Jun 13 17:01:07 2016 -0700 util/crossgcc: Implement buildgcc script checksum verification In order to build a secure toolchain https and checksum verification should be used for the sources. The hash alogrithm has changed from SHA1 to SHA384 for security reasons. Add gpg verification for file hash upgrades by developers. Change-Id: Id45097fc7e8435fadce4bda75769592af2730b0c Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- util/crossgcc/buildgcc | 134 ++++++++++++++++----- util/crossgcc/gpg.keyring | Bin 0 -> 222182 bytes util/crossgcc/sum/Python-3.5.1.tar.xz.cksum | 2 +- .../sum/acpica-unix2-20160318.tar.gz.cksum | 2 +- util/crossgcc/sum/binutils-2.26.tar.bz2.cksum | 2 +- util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum | 2 +- .../sum/clang-tools-extra-3.8.0.src.tar.xz.cksum | 2 +- .../sum/compiler-rt-3.8.0.src.tar.xz.cksum | 2 +- util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum | 2 +- util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum | 2 +- util/crossgcc/sum/gdb-7.11.tar.xz.cksum | 2 +- util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum | 2 +- util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum | 2 +- util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum | 2 +- util/crossgcc/sum/make-4.1.tar.bz2.cksum | 2 +- util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum | 2 +- util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum | 2 +- util/lint/lint-stable-003-whitespace | 2 +- 18 files changed, 118 insertions(+), 48 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 1e761da..c4518b3 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -47,26 +47,28 @@ EXPAT_VERSION=2.1.1 CLANG_VERSION=3.8.0 MAKE_VERSION=4.1 +GPG_KEYRING=$(pwd)/gpg.keyring + # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if # a completely new URL is added here, it probably needs to be added # to the jenkins build as well, or the builder won't download it. -GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.xz" -MPFR_ARCHIVE="http://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz" -MPC_ARCHIVE="http://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" +GMP_ARCHIVE="https://ftp.gnu.org/gnu/gmp/gmp-${GMP_VERSION}.tar.xz" +MPFR_ARCHIVE="https://ftp.gnu.org/gnu/mpfr/mpfr-${MPFR_VERSION}.tar.xz" +MPC_ARCHIVE="https://ftp.gnu.org/gnu/mpc/mpc-${MPC_VERSION}.tar.gz" LIBELF_ARCHIVE="http://www.mr511.de/software/libelf-${LIBELF_VERSION}.tar.gz" -GCC_ARCHIVE="http://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.bz2" -BINUTILS_ARCHIVE="http://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.bz2" -GDB_ARCHIVE="http://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz" +GCC_ARCHIVE="https://ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.bz2" +BINUTILS_ARCHIVE="https://ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.bz2" +GDB_ARCHIVE="https://ftp.gnu.org/gnu/gdb/gdb-${GDB_VERSION}.tar.xz" IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz" -PYTHON_ARCHIVE="http://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}…" -EXPAT_ARCHIVE="http://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.t…" +PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION…" +EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.…" # CLANG toolchain archive locations LLVM_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz" CFE_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src.tar.xz" CRT_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src.…" CTE_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION…" -MAKE_ARCHIVE="http://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2" +MAKE_ARCHIVE="https://ftp.gnu.org/gnu/make/make-${MAKE_VERSION}.tar.bz2" ALL_ARCHIVES="$GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE $LIBELF_ARCHIVE \ $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE $IASL_ARCHIVE \ @@ -202,50 +204,114 @@ check_for_library() { rm -rf "${LIBTEST_FILE}.c" "${LIBTEST_FILE}" } -check_sum() { - test -z "$CHECKSUM" || \ - test "$(cat sum/$1.cksum 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@')" = \ - "$($CHECKSUM tarballs/$1 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@')" +verify_signature() { + if [ -f "sum/${2}.cksum" ] ; then + return + fi + + if [ -z "${CHECKSUM}" ] ; then + printf "\n${RED}Checksum tool not found.${NC}\n" + exit 1 + fi + + if [ -z "${GPG}" ] ; then + printf "\n${RED}GPG tool not found.${NC}\n" + exit 1 + fi + + if [ ! -f "${GPG_KEYRING}" ] ; then + printf "\n${RED}The gpg keyring can't be found not found.${NC}\n" + exit 1 + fi + + if [ ! -f "tarballs/${1}" ] ; then + printf "\n${RED}No signature found for package: ${2} !! PLEASE CHECK MANUALLY WHAT YOU DOWNLOADED.${NC}\n" + return + fi + + if [ ! -f "tarballs/${2}" ] ; then + printf "\n${RED}Source file couldn't be downloaded.${NC}\n" + exit 1 + fi + + ${GPG} --no-default-keyring --keyring ${GPG_KEYRING} --status-fd 1 --verify "tarballs/${1}" "tarballs/${2}" &>/dev/null + if [ "${?}" == "0" ] ; then + return + fi + + printf "\n${RED}Failed to verify signature of package.${NC}\n" + exit 1 } -compute_sum() { +calculate_checksum() { test ! -f sum/$1.cksum && test -f tarballs/$1 && \ (test -z "$CHECKSUM" || $CHECKSUM tarballs/$1 > sum/$1.cksum ) && \ - printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}" + printf "\n(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.${NC})" +} + +verify_checksum() { + if [ -z "${CHECKSUM}" ] ; then + printf "\n${RED}Checksum tool not found.${NC}\n" + exit 1 + fi + + local static_hash=$(cat sum/$1.cksum 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@') + local file_hash=$($CHECKSUM tarballs/$1 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@') + + if [ "${static_hash}" != "${file_hash}" ] ; then + printf "\n${RED}Failed to verify checksum of package ${1}.${NC}\n" + exit 1 + fi +} + +validate_url() { + if [[ `wget -S --spider $1 2>&1 | grep 'HTTP/1.1 200 OK'` ]]; then return 1; else return 0; fi } download_showing_percentage() { url=$1 - printf " ..${red} 0%%" - wget --no-check-certificate $url 2>&1 | while read line; do - printf "${red}" - echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' - printf "${NC}" - done + printf " ..${red} 0%%${NC}" + + validate_url ${url} + if [ "${?}" == "1" ] ; then + wget $url 2>&1 | while read line; do + printf "${red}" + echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' + printf "${NC}" + done + fi } download() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" + signature="${archive}.sig" - FILE=$(basename $archive) - printf " * $FILE " + SOURCE_FILE=$(basename ${archive}) + SIGNATURE_FILE=$(basename ${signature}) + printf " * ${SOURCE_FILE} " - if test -f tarballs/$FILE && check_sum $FILE ; then + if test -f tarballs/${SOURCE_FILE} ; then printf "(cached)" else printf "(downloading from $archive)" - rm -f tarballs/$FILE + rm -f tarballs/${SOURCE_FILE} cd tarballs - download_showing_percentage $archive + download_showing_percentage ${archive} + download_showing_percentage ${signature} cd .. - compute_sum $FILE + + verify_signature ${SIGNATURE_FILE} ${SOURCE_FILE} + calculate_checksum ${SOURCE_FILE} fi - if [ ! -f tarballs/$FILE ]; then - printf "\n${RED}Failed to download $FILE.${NC}\n" + if [ ! -f tarballs/${SOURCE_FILE} ]; then + printf "\n${RED}Failed to download ${SOURCE_FILE}.${NC}\n" exit 1 fi + + verify_checksum ${SOURCE_FILE} ${archive} + printf "\n" } @@ -253,6 +319,10 @@ unpack_and_patch() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" dir="$(eval echo \$$package"_DIR")" + FILE="$(basename $archive)" + + verify_checksum ${FILE} ${archive} + test -d ${dir} && test -f ${dir}/.unpack_success || ( printf " * $(basename $archive)\n" FLAGS=zxf @@ -723,11 +793,11 @@ esac TAR=$(searchtool tar) || exit $? PATCH=$(searchtool patch) || exit $? MAKE=$(searchtool make) || exit $? -SHA1SUM=$(searchtool sha1sum) -SHA512SUM=$(searchtool sha512sum) -CHECKSUM=$SHA1SUM +SHA384SUM=$(searchtool sha384sum) +CHECKSUM=$SHA384SUM LBZIP2=$(searchtool lbzip2 "" nofail) PIGZ=$(searchtool pigz "" nofail) +GPG=$(searchtool gpg) searchtool m4 > /dev/null searchtool bison > /dev/null diff --git a/util/crossgcc/gpg.keyring b/util/crossgcc/gpg.keyring new file mode 100644 index 0000000..8cbce7e Binary files /dev/null and b/util/crossgcc/gpg.keyring differ diff --git a/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum b/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum index 58affb0..5093e22 100644 --- a/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum +++ b/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum @@ -1 +1 @@ -0186da436db76776196612b98bb9c2f76acfe90e tarballs/Python-3.5.1.tar.xz +9aca49d2cde4760035f4fff23e8a446f6451e8effb6e6fab3f259645a631593acb2ce3412aadf810f103f3f6b561abe7 tarballs/Python-3.5.1.tar.xz diff --git a/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum index 2f9b331..793a794 100644 --- a/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum +++ b/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum @@ -1 +1 @@ -786811c1501b9cc90c988293a1c3afefa33b60cc tarballs/acpica-unix2-20160318.tar.gz +73305954ec571a19fd1ced884f5ce951b9a6c183faf111408fefddb1628ccc5aabcc9200d5f0619eb248f3d803e6ae98 tarballs/acpica-unix2-20160318.tar.gz diff --git a/util/crossgcc/sum/binutils-2.26.tar.bz2.cksum b/util/crossgcc/sum/binutils-2.26.tar.bz2.cksum index ac0a3c3..4d99d04 100644 --- a/util/crossgcc/sum/binutils-2.26.tar.bz2.cksum +++ b/util/crossgcc/sum/binutils-2.26.tar.bz2.cksum @@ -1 +1 @@ -a637508cffeb2323b14bc8dd65378819768ad4ff tarballs/binutils-2.26.tar.bz2 +ff22e865d7f4ac6fb5d408f92cbc0dcc749a36ee8c5f19a0292fc3d6f08e00f852e04734c47c9a578f092c6963b46878 tarballs/binutils-2.26.tar.bz2 diff --git a/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum index 7ba8c8c..b278aac 100644 --- a/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -2230ef962f2df3c13ec93f5b04b0e3cdff94b2ce tarballs/cfe-3.8.0.src.tar.xz +3edbe3cafc58ad6fc3d3a133156a656ea7756e8a36176b29bba63434d6f073cef63241cc6df8337fcab3832dd5b5c485 tarballs/cfe-3.8.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum index e9d8d72..dd5c566 100644 --- a/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -a99d8b6fc5e593c4671424b327779318a1856acf tarballs/clang-tools-extra-3.8.0.src.tar.xz +abd447239f09295f8592225bb7e07ba57cedc3d19a4972b45cd7d70a2db82106d1874a5be03656f8209a0e8a1308fb31 tarballs/clang-tools-extra-3.8.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum index 081705d..9239365 100644 --- a/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -480ea09e369dac6de1f3759b27fa19417b26b69e tarballs/compiler-rt-3.8.0.src.tar.xz +4560d512f3c3a0dbcc5c29ab7754b07d91ffa1ddc1c06a5215f3d325bc3f138ebf483e2a37abb10fc36cd125e6bf559e tarballs/compiler-rt-3.8.0.src.tar.xz diff --git a/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum b/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum index 882e501..11800c1 100644 --- a/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum +++ b/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum @@ -1 +1 @@ -ff91419882ac52151050dad0ee8190645fbeee08 tarballs/expat-2.1.1.tar.bz2 +816e8ca9ac57b6aac76e9979d11714313246492a49c228bb0a16d349174be45cd780d760524eb45acf12ff371e8b96a3 tarballs/expat-2.1.1.tar.bz2 diff --git a/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum b/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum index bb05e39..2b81f5e 100644 --- a/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum +++ b/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum @@ -1 +1 @@ -0612270b103941da08376df4d0ef4e5662a2e9eb tarballs/gcc-5.3.0.tar.bz2 +4184972f66dc929686c30936cf8f5085829d8584118ebc3e2ec53a40754afbefc351cfd2c211c09dd3b6eb4ab4759820 tarballs/gcc-5.3.0.tar.bz2 diff --git a/util/crossgcc/sum/gdb-7.11.tar.xz.cksum b/util/crossgcc/sum/gdb-7.11.tar.xz.cksum index ffe5a1c..9cc5d91 100644 --- a/util/crossgcc/sum/gdb-7.11.tar.xz.cksum +++ b/util/crossgcc/sum/gdb-7.11.tar.xz.cksum @@ -1 +1 @@ -466208d771d97d3dfcf965d5c835a669cff8d847 tarballs/gdb-7.11.tar.xz +82f89ef35ea1916d5faa67b7fefa2ac3627894d245c43fb4e20828274566cbbb5d7f83899baad77a3cf7fe9fec6f8c7b tarballs/gdb-7.11.tar.xz diff --git a/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum b/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum index 348b80f..7e00489 100644 --- a/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum +++ b/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum @@ -1 +1 @@ -99d691607613e749aa5d7c0c2a89aeab38fec070 tarballs/gmp-6.1.0.tar.xz +ec69b394cbcf887ab0717473b04bb70ce30102abf24869eca5acb781de405d3a5670fabb776ba68cfe6e117631522d9f tarballs/gmp-6.1.0.tar.xz diff --git a/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum b/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum index daa27c6..0d3f568 100644 --- a/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum +++ b/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum @@ -1 +1 @@ -c1d6ac5f182d19dd685c4dfd74eedbfe3992425d tarballs/libelf-0.8.13.tar.gz +07fc0b1a40ba3d2b003899df199d1043bb5d44cf7d913e6460c985582e5275b634edb6af6779255d770010fd7d09580e tarballs/libelf-0.8.13.tar.gz diff --git a/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum index 2f0af53..547ad8f 100644 --- a/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -723ac918979255706434a05f5af34b71c49c9971 tarballs/llvm-3.8.0.src.tar.xz +5d5a012e4d494a4534fcec7643ad28bab7467b96029b6d497e1d523357ae7c9e8bd86400dc90e261d791d6391a369b30 tarballs/llvm-3.8.0.src.tar.xz diff --git a/util/crossgcc/sum/make-4.1.tar.bz2.cksum b/util/crossgcc/sum/make-4.1.tar.bz2.cksum index 02807c6..455d779 100644 --- a/util/crossgcc/sum/make-4.1.tar.bz2.cksum +++ b/util/crossgcc/sum/make-4.1.tar.bz2.cksum @@ -1 +1 @@ -0d701882fd6fd61a9652cb8d866ad7fc7de54d58 tarballs/make-4.1.tar.bz2 +8a3adbc49c19db130bfd3c2b7df061d9419b77019d21d23765cf1c961bc6a35d611dbda4241316e98cecc09adccecd90 tarballs/make-4.1.tar.bz2 diff --git a/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum b/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum index c7ca1ac..70ee62f 100644 --- a/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum +++ b/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum @@ -1 +1 @@ -b8be66396c726fdc36ebb0f692ed8a8cca3bcc66 tarballs/mpc-1.0.3.tar.gz +dceeb2566d6145fa771641d22de3bef866fa601fe1fa964bc680a275919080bd12bc1abab4f68cecdbaef71d295b7397 tarballs/mpc-1.0.3.tar.gz diff --git a/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum b/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum index 90f90eb..54cd485 100644 --- a/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum +++ b/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum @@ -1 +1 @@ -cedc0055d55b6ee4cd17e1e6119ed412520ff81a tarballs/mpfr-3.1.4.tar.xz +30a2807378f578544538810b24bb65d44268015e5d2390d8ae6383fe3939b3bba1e85279789400a226b365010de4bbcd tarballs/mpfr-3.1.4.tar.xz diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 3dbd473..144cda1 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -15,5 +15,5 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$)"` | \ +grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.keyring$|\.patch$|\.bin$|\.hex$|\.jpg$)"` | \ sed -e "s,^.*$,File & has lines ending with whitespace.,"

1 0

Patch set updated for coreboot: soc/apollolake: Populate fields in FADT to enable\disable SCI
by Shaunak Saha 28 Jun '16

28 Jun '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15347 -gerrit commit 139f0dfebbcbc78edcdc2fac12ac7768971200e7 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Jun 24 14:13:45 2016 -0700 soc/apollolake: Populate fields in FADT to enable\disable SCI This will allow kernel to trigger a APM SMI to enable\disable SCI Change-Id: I1be79b7a3082c23fbaf204eff55360c46458e325 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index d24416f..a38c377 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -85,7 +85,9 @@ void acpi_fill_fadt(acpi_fadt_t * fadt) fadt->header.revision = ACPI_FADT_REV_ACPI_5_0; fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = 0; /* No Smi Handler as SMI_CMD is 0*/ + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT;

1 0

Patch set updated for coreboot: WIP: soc/intel/apollolake: Cache cbmem region
by Andrey Petrov 28 Jun '16

28 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15456 -gerrit commit f3733ddb21a0b6e54facbcd4e1ec8d369ca8e2ca Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jun 24 18:40:28 2016 -0700 WIP: soc/intel/apollolake: Cache cbmem region Configure write-back MTRRs so that 16 MiB under cbmem_top is cached. This allows caching of FSP reserved memory and postcar stage itself. On CAR teardown the memory is flushed with clflush instruction. Depending on what cache configuration is used, either L1 (NEM) or both L1 and L2 (CQOS) storage is used for caching purposes. This is WIP patch, because currently location of cbmem_top can not be known before memory is trained. So addresses are hardcoded. BUG=chrome-os-partner:51959 TEST=run primitive memtest on 16 MiB cached memory region after mem is trained, observe x7 improvement on L1 only, x12 on L2 of 256 KiB Change-Id: I62aad238a3056f9bbe5327dfb33a2a1112d61194 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/exit_car.S | 8 ++++++++ src/soc/intel/apollolake/romstage.c | 9 ++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S index e5706cf..c0fb39b 100644 --- a/src/soc/intel/apollolake/exit_car.S +++ b/src/soc/intel/apollolake/exit_car.S @@ -38,6 +38,14 @@ chipset_teardown_car: and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr + /* Flush down whatever we have */ + mov $0x7a000000, %eax +loop: + clflush (%eax) + add $CACHE_LINE_SIZE, %eax + cmp $0x7b000000, %eax + jl loop + #if IS_ENABLED(CONFIG_CAR_CQOS) mov $MTRR_L2_QOS_MASK(0), %ecx rdmsr diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index ce28326..1fa52fd 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -112,7 +112,7 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; size_t mrc_data_size; uintptr_t top_of_ram; - int prev_sleep_state; + int prev_sleep_state, mtrr; struct romstage_handoff *handoff; struct chipset_power_state *ps = car_get_var_ptr(&power_state); @@ -129,6 +129,13 @@ asmlinkage void car_stage_entry(void) range_entry_init(&reg_car, (uintptr_t)_car_relocatable_data_end, (uintptr_t)_car_region_end, 0); + mtrr = get_free_var_mtrr(); + if (mtrr==-1) + printk(BIOS_CRIT, "no available MTRRs to cache cbmem!\n"); + else + /* Make sure cbmem 16 MiB under CBMEM is cachable */ + set_var_mtrr(mtrr, 0x7a000000, 16 * MiB, MTRR_TYPE_WRBACK); + if (fsp_memory_init(&hob_list_ptr, &reg_car) != FSP_SUCCESS) { die("FSP memory init failed. Giving up."); }

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Patch set updated for coreboot: soc/intel/apollolake: Add CQOS CAR implementation
by Andrey Petrov 28 Jun '16

28 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15455 -gerrit commit 2a98349ad5f1097010f3b5810de2a5662895f42e Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Jun 27 13:39:34 2016 -0700 soc/intel/apollolake: Add CQOS CAR implementation Add new Cache Quality of Service option that allows to configure cache non-evict mode by manipulating CQOS settings. Also, CQOS allows using cache non-evict mode simultaneously with regular evicting caching. BUG=chrome-os-partner:51959 Change-Id: Ic7f9899918f94a5788b02a4fbd2f5d5ba9aaf91d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 23 ++++++++++++++++++ src/soc/intel/apollolake/bootblock/bootblock.c | 4 ++++ src/soc/intel/apollolake/bootblock/cache_as_ram.S | 20 ++++++++++++++++ src/soc/intel/apollolake/car.c | 7 ++++++ src/soc/intel/apollolake/exit_car.S | 29 +++++++++++++++++++++-- src/soc/intel/apollolake/include/soc/cpu.h | 12 ++++++++++ 6 files changed, 93 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index c49d67d..74b3bb5 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -182,4 +182,27 @@ config IFWI_FILE_NAME help Name of file to store in the IFWI region. +choice + prompt "Cache-as-ram implementation" + default CAR_CQOS + help + This option allows you to select how cache-as-ram (CAR) is set up. + +config CAR_NEM + bool "Non-evict mode" + help + Traditionally, CAR is set up by using Non-Evict mode. This method + does not allow CAR and cache to co-exist, because cache fills are + block in NEM mode. + + +config CAR_CQOS + bool "Cache Quality of Service" + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up portion of L2 cache for + CAR and use remainded for actual caching. + +endchoice + endif diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 8c1ff91..00c280a 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -168,5 +168,9 @@ void bootblock_soc_early_init(void) enable_spibar(); +#if IS_ENABLED(CONFIG_CAR_CQOS) + cache_qos_select_mask(1); +#endif + cache_bios_region(); } diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index a362969..3c97bb2 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -123,12 +123,30 @@ clear_var_mtrr: invd mov %eax, %cr0 +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (setup stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr +#endif + +#if IS_ENABLED(CONFIG_CAR_CQOS) + /* Mask 0 is used for CAR */ + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + /* Calculate how many bits to be used for CAR */ + mov $(1 << (CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT) - 1), %al + wrmsr + /* Mask 1 is used for evicatable cache */ + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + /* Invert bits that are to be used for cache */ + mov $(1 << (CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT) - 1), %al + xor $~0, %al + wrmsr +#endif post_code(0x26) /* Clear the cache memory region. This will also fill up the cache */ @@ -139,11 +157,13 @@ clear_var_mtrr: post_code(0x27) +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr +#endif post_code(0x28) diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index 68bcb31..bb96419 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -56,3 +56,10 @@ void platform_segment_loaded(uintptr_t start, size_t size, int flags) flush_l1d_to_l2(); } + +void cache_qos_select_mask(uint8_t mask) +{ + msr_t msr = rdmsr(MTRR_IA32_PQR_ASSOC); + msr.hi |= mask; + wrmsr(MTRR_IA32_PQR_ASSOC, msr); +} diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S index 339242b..e5706cf 100644 --- a/src/soc/intel/apollolake/exit_car.S +++ b/src/soc/intel/apollolake/exit_car.S @@ -27,14 +27,38 @@ chipset_teardown_car: */ pop %ebx - /* invalidate cache contents. */ - invd + /* + * Flush all cache lines into the DRAM. Since we are running in the + * very region, disable MTRR first. + */ + /* Disable MTRRs. */ mov $(MTRR_DEF_TYPE_MSR), %ecx rdmsr and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr +#if IS_ENABLED(CONFIG_CAR_CQOS) + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + mov $~0, %al + wrmsr + + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + mov $~0, %al + wrmsr + + /* reset CLOS selector */ + mov $MTRR_IA32_PQR_ASSOC, %ecx + rdmsr + and $~(1 << 0 | 1 << 1), %edx + wrmsr +#endif + /* invalidate cache contents. */ + invd + +#if IS_ENABLED(CONFIG_CAR_NEM) /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ mov $(MSR_EVICT_CTL), %ecx rdmsr @@ -42,6 +66,7 @@ chipset_teardown_car: wrmsr and $(~(1 << 0)), %eax wrmsr +#endif /* Return to caller. */ jmp *%ebx diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 78fc0b0..13a47cd 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -23,6 +23,7 @@ #include <device/device.h> void apollolake_init_cpus(struct device *dev); +void cache_qos_select_mask(uint8_t mask); #endif #define CPUID_APOLLOLAKE_A0 0x506c8 @@ -35,6 +36,17 @@ void apollolake_init_cpus(struct device *dev); #define MSR_EMULATE_PM_TMR 0x121 #define EMULATE_PM_TMR_EN (1 << 16) +#define MTRR_L2_QOS_MASK(reg) (0xd10 + reg) +#define MTRR_IA32_PQR_ASSOC 0xc8f +/* 16 way cache, 8 bits per QOS, 64 byte cache line, 1024 sets */ +#define CACHE_WAYS 16 +#define CACHE_BITS_PER_MASK 8 +#define CACHE_LINE_SIZE 64 +#define CACHE_SETS 1024 +/* Each bit in QOS mask controls this many bytes */ +#define CACHE_QOS_SIZE_PER_BIT ((CACHE_WAYS / CACHE_BITS_PER_MASK) * \ + CACHE_LINE_SIZE * CACHE_SETS) + #define BASE_CLOCK_MHZ 100 /* Common Timer Copy (CTC) frequency - 19.2MHz. */

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Patch set updated for coreboot: intel/sandybridge: read correct leaf for cpu family
by Ryan Salsamendi 28 Jun '16

28 Jun '16

Ryan Salsamendi (rsalsamendi(a)hotmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15346 -gerrit commit 06dd0347bef8090329129cdbf5b7d4239bd7c1be Author: Ryan Salsamendi <rsalsamendi(a)hotmail.com> Date: Fri Jun 24 12:01:11 2016 -0700 intel/sandybridge: read correct leaf for cpu family Reading cpuid leaf 0 is incorrect for testing cpu family. Use leaf 1 instead. See Intel SDM 2a Table 3-17. Change-Id: Ib2c95cdd1fb93db06a08ecd7266f6b88700caf83 Signed-off-by: Ryan Salsamendi <rsalsamendi(a)hotmail.com> --- src/northbridge/intel/sandybridge/raminit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index cf66a0d..4ac7f3d 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -913,7 +913,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) // ODT stretch reg = 0; - cpures = cpuid(0); + cpures = cpuid(1); cpu = cpures.eax; if (IS_IVY_CPU(cpu) || (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_D2(cpu))) { @@ -3779,7 +3779,7 @@ static void set_4f8c(void) struct cpuid_result cpures; u32 cpu; - cpures = cpuid(0); + cpures = cpuid(1); cpu = (cpures.eax); if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { MCHBAR32(0x4f8c) = 0x141D1519;

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Patch set updated for coreboot: WIP: soc/intel/apollolake: Cache cbmem region
by Andrey Petrov 28 Jun '16

28 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15456 -gerrit commit 02dd47ce7f3d1673403f99499127be2ebd0e4b3a Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jun 24 18:40:28 2016 -0700 WIP: soc/intel/apollolake: Cache cbmem region Configure write-back MTRRs so that 16 MiB under cbmem_top is cached. This allows caching of FSP reserved memory and postcar stage itself. On CAR teardown the memory is flushed with clflush instruction. Depending on what cache configuration is used, either L1 (NEM) or both L1 and L2 (CQOS) storage is used for caching purposes. This is WIP patch, because currently location of cbmem_top can not be known before memory is trained. So addresses are hardcoded. BUG=chrome-os-partner:51959 TEST=run primitive memtest on 16 MiB cached memory region after mem is trained, observe x7 improvement on L1 only, x12 on L2 of 256 KiB Change-Id: I62aad238a3056f9bbe5327dfb33a2a1112d61194 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/exit_car.S | 8 ++++++++ src/soc/intel/apollolake/romstage.c | 9 ++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S index e5706cf..c0fb39b 100644 --- a/src/soc/intel/apollolake/exit_car.S +++ b/src/soc/intel/apollolake/exit_car.S @@ -38,6 +38,14 @@ chipset_teardown_car: and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr + /* Flush down whatever we have */ + mov $0x7a000000, %eax +loop: + clflush (%eax) + add $CACHE_LINE_SIZE, %eax + cmp $0x7b000000, %eax + jl loop + #if IS_ENABLED(CONFIG_CAR_CQOS) mov $MTRR_L2_QOS_MASK(0), %ecx rdmsr diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index ce28326..1fa52fd 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -112,7 +112,7 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; size_t mrc_data_size; uintptr_t top_of_ram; - int prev_sleep_state; + int prev_sleep_state, mtrr; struct romstage_handoff *handoff; struct chipset_power_state *ps = car_get_var_ptr(&power_state); @@ -129,6 +129,13 @@ asmlinkage void car_stage_entry(void) range_entry_init(&reg_car, (uintptr_t)_car_relocatable_data_end, (uintptr_t)_car_region_end, 0); + mtrr = get_free_var_mtrr(); + if (mtrr==-1) + printk(BIOS_CRIT, "no available MTRRs to cache cbmem!\n"); + else + /* Make sure cbmem 16 MiB under CBMEM is cachable */ + set_var_mtrr(mtrr, 0x7a000000, 16 * MiB, MTRR_TYPE_WRBACK); + if (fsp_memory_init(&hob_list_ptr, &reg_car) != FSP_SUCCESS) { die("FSP memory init failed. Giving up."); }

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Patch set updated for coreboot: WIP: soc/intel/apollolake: Change default CAR size to 768 KiB
by Andrey Petrov 28 Jun '16

28 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15453 -gerrit commit b7955747ce115d8d22867f80562c36902d9fe2d4 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Jun 27 15:21:26 2016 -0700 WIP: soc/intel/apollolake: Change default CAR size to 768 KiB As whole 1024 KiB is not used, it is possible to shrink CAR size to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used to setup it. This is part of preparation for CQOS enabling. BUG=chrome-os-partner:51959 Change-Id: I56326a1790df202a0e428e092dd90286c58763c5 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 2 +- src/soc/intel/apollolake/bootblock/cache_as_ram.S | 26 +++++++++++++++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 98ce7d8..f51dbfb 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -77,7 +77,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex "Length in bytes of cache-as-RAM" - default 0x100000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage. diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index 8647206..a362969 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -70,6 +70,31 @@ clear_var_mtrr: post_code(0x24) +#if (CONFIG_DCACHE_RAM_SIZE == 0xc0000) /* 768 KiB */ + /* 512 KiB */ + mov $MTRR_PHYS_BASE(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK(0), %ecx + mov $~(0x80000 - 1), %eax /* size mask */ + or $MTRR_PHYS_MASK_VALID, %eax + wrmsr + + /* 256 KiB */ + mov $MTRR_PHYS_BASE(1), %ecx + mov $(CONFIG_DCACHE_RAM_BASE + 0x80000), %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK(1), %ecx + mov $~(0x40000 - 1), %eax /* size mask */ + or $MTRR_PHYS_MASK_VALID, %eax + wrmsr +#else /* Configure CAR region as write-back (WB) */ mov $MTRR_PHYS_BASE(0), %ecx mov $CONFIG_DCACHE_RAM_BASE, %eax @@ -82,6 +107,7 @@ clear_var_mtrr: mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */ or $MTRR_PHYS_MASK_VALID, %eax wrmsr +#endif post_code(0x25)

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coreboot-gerrit June 2016