coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: WIP: soc/intel/apollolake: Cache cbmem region
by Andrey Petrov 28 Jun '16

28 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15456 -gerrit commit 671b59f1cf7916eeea4a037a68765e63c5fa5656 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jun 24 18:40:28 2016 -0700 WIP: soc/intel/apollolake: Cache cbmem region Configure write-back MTRRs so that 16 MiB under cbmem_top is cached. This allows caching of FSP reserved memory and postcar stage itself. On CAR teardown the memory is flushed with clflush instruction. Depending on what cache configuration is used, either L1 (NEM) or both L1 and L2 (CQOS) storage is used for caching purposes. This is WIP patch, because currently location of cbmem_top can not be known before memory is trained. So addresses are hardcoded. BUG=chrome-os-partner:51959 TEST=run primitive memtest on 16 MiB cached memory region after mem is trained, observe x7 improvement on L1 only, x12 on L2 of 256 KiB Change-Id: I62aad238a3056f9bbe5327dfb33a2a1112d61194 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/exit_car.S | 8 ++++++++ src/soc/intel/apollolake/romstage.c | 9 ++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S index e5706cf..c0fb39b 100644 --- a/src/soc/intel/apollolake/exit_car.S +++ b/src/soc/intel/apollolake/exit_car.S @@ -38,6 +38,14 @@ chipset_teardown_car: and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr + /* Flush down whatever we have */ + mov $0x7a000000, %eax +loop: + clflush (%eax) + add $CACHE_LINE_SIZE, %eax + cmp $0x7b000000, %eax + jl loop + #if IS_ENABLED(CONFIG_CAR_CQOS) mov $MTRR_L2_QOS_MASK(0), %ecx rdmsr diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index ce28326..1fa52fd 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -112,7 +112,7 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; size_t mrc_data_size; uintptr_t top_of_ram; - int prev_sleep_state; + int prev_sleep_state, mtrr; struct romstage_handoff *handoff; struct chipset_power_state *ps = car_get_var_ptr(&power_state); @@ -129,6 +129,13 @@ asmlinkage void car_stage_entry(void) range_entry_init(&reg_car, (uintptr_t)_car_relocatable_data_end, (uintptr_t)_car_region_end, 0); + mtrr = get_free_var_mtrr(); + if (mtrr==-1) + printk(BIOS_CRIT, "no available MTRRs to cache cbmem!\n"); + else + /* Make sure cbmem 16 MiB under CBMEM is cachable */ + set_var_mtrr(mtrr, 0x7a000000, 16 * MiB, MTRR_TYPE_WRBACK); + if (fsp_memory_init(&hob_list_ptr, &reg_car) != FSP_SUCCESS) { die("FSP memory init failed. Giving up."); }

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Patch set updated for coreboot: soc/intel/apollolake: Add CQOS CAR implementation
by Andrey Petrov 28 Jun '16

28 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15455 -gerrit commit b442c398f96ba21689088bcfc0b08b791103c905 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Jun 27 13:39:34 2016 -0700 soc/intel/apollolake: Add CQOS CAR implementation Add new Cache Quality of Service option that allows to configure cache non-evict mode by manipulating CQOS settings. Also, CQOS allows using cache non-evict mode simultaneously with regular evicting caching. BUG=chrome-os-partner:51959 Change-Id: Ic7f9899918f94a5788b02a4fbd2f5d5ba9aaf91d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 23 ++++++++++++++++++ src/soc/intel/apollolake/bootblock/bootblock.c | 4 ++++ src/soc/intel/apollolake/bootblock/cache_as_ram.S | 20 ++++++++++++++++ src/soc/intel/apollolake/car.c | 7 ++++++ src/soc/intel/apollolake/exit_car.S | 29 +++++++++++++++++++++-- src/soc/intel/apollolake/include/soc/cpu.h | 12 ++++++++++ 6 files changed, 93 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index c49d67d..74b3bb5 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -182,4 +182,27 @@ config IFWI_FILE_NAME help Name of file to store in the IFWI region. +choice + prompt "Cache-as-ram implementation" + default CAR_CQOS + help + This option allows you to select how cache-as-ram (CAR) is set up. + +config CAR_NEM + bool "Non-evict mode" + help + Traditionally, CAR is set up by using Non-Evict mode. This method + does not allow CAR and cache to co-exist, because cache fills are + block in NEM mode. + + +config CAR_CQOS + bool "Cache Quality of Service" + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up portion of L2 cache for + CAR and use remainded for actual caching. + +endchoice + endif diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 8c1ff91..00c280a 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -168,5 +168,9 @@ void bootblock_soc_early_init(void) enable_spibar(); +#if IS_ENABLED(CONFIG_CAR_CQOS) + cache_qos_select_mask(1); +#endif + cache_bios_region(); } diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index a362969..54a1901 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -123,12 +123,30 @@ clear_var_mtrr: invd mov %eax, %cr0 +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (setup stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr +#endif + +#if IS_ENABLED(CONFIG_CAR_CQOS) + /* Mask 0 is used for CAR */ + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + /* Calculate how many bits to be used for CAR */ + mov $((1 << (CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT)) - 1), %al + wrmsr + /* Mask 1 is used for evicatable cache */ + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + /* Invert bits that are to be used for cache */ + mov $((1 << (CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT)) - 1), %al + xor $~0, %al + wrmsr +#endif post_code(0x26) /* Clear the cache memory region. This will also fill up the cache */ @@ -139,11 +157,13 @@ clear_var_mtrr: post_code(0x27) +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr +#endif post_code(0x28) diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index 68bcb31..bb96419 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -56,3 +56,10 @@ void platform_segment_loaded(uintptr_t start, size_t size, int flags) flush_l1d_to_l2(); } + +void cache_qos_select_mask(uint8_t mask) +{ + msr_t msr = rdmsr(MTRR_IA32_PQR_ASSOC); + msr.hi |= mask; + wrmsr(MTRR_IA32_PQR_ASSOC, msr); +} diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S index 339242b..e5706cf 100644 --- a/src/soc/intel/apollolake/exit_car.S +++ b/src/soc/intel/apollolake/exit_car.S @@ -27,14 +27,38 @@ chipset_teardown_car: */ pop %ebx - /* invalidate cache contents. */ - invd + /* + * Flush all cache lines into the DRAM. Since we are running in the + * very region, disable MTRR first. + */ + /* Disable MTRRs. */ mov $(MTRR_DEF_TYPE_MSR), %ecx rdmsr and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr +#if IS_ENABLED(CONFIG_CAR_CQOS) + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + mov $~0, %al + wrmsr + + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + mov $~0, %al + wrmsr + + /* reset CLOS selector */ + mov $MTRR_IA32_PQR_ASSOC, %ecx + rdmsr + and $~(1 << 0 | 1 << 1), %edx + wrmsr +#endif + /* invalidate cache contents. */ + invd + +#if IS_ENABLED(CONFIG_CAR_NEM) /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ mov $(MSR_EVICT_CTL), %ecx rdmsr @@ -42,6 +66,7 @@ chipset_teardown_car: wrmsr and $(~(1 << 0)), %eax wrmsr +#endif /* Return to caller. */ jmp *%ebx diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 78fc0b0..13a47cd 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -23,6 +23,7 @@ #include <device/device.h> void apollolake_init_cpus(struct device *dev); +void cache_qos_select_mask(uint8_t mask); #endif #define CPUID_APOLLOLAKE_A0 0x506c8 @@ -35,6 +36,17 @@ void apollolake_init_cpus(struct device *dev); #define MSR_EMULATE_PM_TMR 0x121 #define EMULATE_PM_TMR_EN (1 << 16) +#define MTRR_L2_QOS_MASK(reg) (0xd10 + reg) +#define MTRR_IA32_PQR_ASSOC 0xc8f +/* 16 way cache, 8 bits per QOS, 64 byte cache line, 1024 sets */ +#define CACHE_WAYS 16 +#define CACHE_BITS_PER_MASK 8 +#define CACHE_LINE_SIZE 64 +#define CACHE_SETS 1024 +/* Each bit in QOS mask controls this many bytes */ +#define CACHE_QOS_SIZE_PER_BIT ((CACHE_WAYS / CACHE_BITS_PER_MASK) * \ + CACHE_LINE_SIZE * CACHE_SETS) + #define BASE_CLOCK_MHZ 100 /* Common Timer Copy (CTC) frequency - 19.2MHz. */

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Patch set updated for coreboot: apollolake: Add ACPI device for audio controller
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15026 -gerrit commit f7c875bc4f81b0f6b802510d4391d1cb30ec281f Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Mar 8 17:33:29 2016 -0800 apollolake: Add ACPI device for audio controller Add the audio controller device to ACPI and define the _DSM handler to return the address of the NHLT table, if set in NVS. Change-Id: I619dbfb562b94255e42a3e5d5a3926c28b14db3e Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/acpi/pch_hda.asl | 84 +++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pch_hda.asl b/src/soc/intel/apollolake/acpi/pch_hda.asl new file mode 100644 index 0000000..33cd771 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pch_hda.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* Audio Controller - Device 14, Function 0 */ + +Device (HDAS) +{ + Name (_ADR, 0x000E0000) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate() { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, Cacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + } + ) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (LEqual (Arg2, Zero)) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If (LAnd (LEqual (Arg1, One), + LAnd (LNotEqual (NHLA, Zero), + LNotEqual (NHLL, Zero)))) { + Return (Buffer (One) { 0x03 }) + } + Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (LEqual (Arg2, One)) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + Store (NHLA, NBAS) + Store (NHLA, NMAS) + Store (NHLL, NLEN) + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +}

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Patch set updated for coreboot: mainboard/intel/amenia: Use common NHLT
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15024 -gerrit commit 542598c97dbe9aca2beacbdebbafafb6c4355783 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 16:08:45 2016 -0700 mainboard/intel/amenia: Use common NHLT Add ACPI NHLT table generation that the current hardware supports. Amenia has support for two audio codecs, Dialog for headsets and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 6 ++++ src/mainboard/intel/amenia/dsdt.asl | 11 ++++---- src/mainboard/intel/amenia/mainboard.c | 50 +++++++++++++++++++++++++++++++++- 3 files changed, 61 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index 6dd171c..abea9e6 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -52,4 +52,10 @@ config MAX_CPUS int default 8 +config INCLUDE_AUDIO_BLOBS + bool "Include blobs for audio." + select NHLT_DMIC_2CH_16B + select NHLT_DA7219 + select NHLT_MAX98357 + endif # BOARD_INTEL_AMENIA diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 4a64f87..46404ed 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2016 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -33,15 +33,16 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include <soc/intel/apollolake/acpi/northbridge.asl> - #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> } } /* Mainboard Specific devices */ #include "acpi/mainboard.asl" - /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> #include "acpi/superio.asl" } diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 22304f8..07e896e 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -16,8 +16,14 @@ */ #include <device/device.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <nhlt.h> #include <soc/gpio.h> +#include <soc/nhlt.h> #include <soc/pci_devs.h> +#include <stdlib.h> +#include <string.h> #include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ @@ -129,7 +135,6 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ PAD_CFG_NF(PMC_SPI_FS1, NATIVE, DEEP, NF2), /* HV_DDI2_HPD */ - }; static void mainboard_init(void *chip_info) @@ -138,6 +143,49 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (!nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Added 2CH DMIC array.\n"); + + /* Dialog for Headset codec. + * Headset codec is bi-directional but uses the same configuration + * settings for render and capture endpoints. + */ + if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; +} + struct chip_operations mainboard_ops = { .init = mainboard_init, + .enable_dev = mainboard_enable, };

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Patch set updated for coreboot: soc/intel/apollolake: Add NHLT table region to ACPI global nvs
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15025 -gerrit commit 83d588c73223739affd9627135f024feee8c395d Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Mar 31 15:41:30 2016 -0700 soc/intel/apollolake: Add NHLT table region to ACPI global nvs Add address and length of NHLT table in ACPI. Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/acpi/globalnvs.asl | 2 ++ src/soc/intel/apollolake/include/soc/nvs.h | 14 ++++++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 3597788..3f9683f 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -34,6 +34,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PWRS, 8, // 0x03 - AC Power State DPTE, 8, // 0x04 - Enable DPTF CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console + NHLA, 64, // 0x09 - NHLT Address + NHLL, 32, // 0x11 - NHLT Length /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index fda3556..1ff5f23 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,13 +28,15 @@ struct global_nvs_t { /* Miscellaneous */ - uint8_t pcnt; /* 0x00 - Processor Count */ - uint8_t ppcm; /* 0x01 - Max PPC State */ - uint8_t lids; /* 0x02 - LID State */ - uint8_t pwrs; /* 0x03 - AC Power State */ - uint8_t dpte; /* 0x04 - Enable DPTF */ + uint8_t pcnt; /* 0x00 - Processor Count */ + uint8_t ppcm; /* 0x01 - Max PPC State */ + uint8_t lids; /* 0x02 - LID State */ + uint8_t pwrs; /* 0x03 - AC Power State */ + uint8_t dpte; /* 0x04 - Enable DPTF */ uint32_t cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */ - uint8_t unused[247]; + uint64_t nhla; /* 0x09 - NHLT Address */ + uint32_t nhll; /* 0x11 - NHLT Length */ + uint8_t unused[235]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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Patch set updated for coreboot: soc/intel/apollolake: Use common NHLT
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15326 -gerrit commit 942ce5118a739298fa23c4abc989d318256e321c Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Wed Jun 22 17:38:12 2016 -0700 soc/intel/apollolake: Use common NHLT This makes use of common NHLT implmentation for audio on Intel's apollolake platform. Change-Id: I3ff87efc83bc243d51a8ddea896ae60f7bb7aec9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 23 +++++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 18 ++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d830a9f..9bc199d 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -17,6 +17,8 @@ config CPU_SPECIFIC_OPTIONS select SMP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS + # Audio options + select ACPI_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS @@ -184,4 +186,25 @@ config IFWI_FILE_NAME help Name of file to store in the IFWI region. +config NHLT_DMIC_2CH_16B + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for 2 channel 16B DMIC array. + +config NHLT_MAX98357 + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for headset codec. + +config NHLT_DA7219 + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for headset codec. + endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 38ed07d..a82dacd 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -56,6 +56,24 @@ ramstage-y += pmc.c ramstage-y += smi.c ramstage-y += reset.c +# DSP firmware settings files. +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs +DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin +MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin +DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin + +cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER) +$(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER) +$(MAX98357_RENDER)-type := raw + +cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE) +$(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE) +$(DA7219_RENDER_CAPTURE)-type := raw + postcar-y += exit_car.S postcar-y += memmap.c postcar-y += mmap_boot.c

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add NHLT add codec APIs and device/vendor ids
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15311 -gerrit commit 62cd82674e6c7da331e45b99a8e0a74f0980a5b3 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Jun 21 14:22:16 2016 -0700 soc/intel/apollolake: Add NHLT add codec APIs and device/vendor ids nhlt_add_<codec>_on_ssp uses codec configs, tdm configs and add the particular codec on a SSP port specified by mainboard. get_nhlt_link_type() returns a corresponding NHLT link type based on audio soc hardware interface passed as an argument. Also define vendor id for NHLT and device ids for NHLT Bluetooth, DMIC & SSPs. These ids are used to add NHLT endpoints for different audio codecs. These ids are platform dependent. Change-Id: Ic9bd26ebe8d6df60af23733e122fd8f3c0432e1f Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/nhlt.h | 39 +++++++++ src/soc/intel/apollolake/nhlt.c | 130 ++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index a82dacd..556abbb 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -55,6 +55,7 @@ ramstage-y += pmutil.c ramstage-y += pmc.c ramstage-y += smi.c ramstage-y += reset.c +ramstage-y += nhlt.c # DSP firmware settings files. NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs diff --git a/src/soc/intel/apollolake/include/soc/nhlt.h b/src/soc/intel/apollolake/include/soc/nhlt.h new file mode 100644 index 0000000..cc6486b --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/nhlt.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_NHLT_H_ +#define _SOC_APOLLOLAKE_NHLT_H_ + +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + +enum { + AUDIO_LINK_SSP0, + AUDIO_LINK_SSP1, + AUDIO_LINK_SSP2, + AUDIO_LINK_SSP3, + AUDIO_LINK_SSP4, + AUDIO_LINK_SSP5, + AUDIO_LINK_DMIC, +}; + +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels); +int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink); +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink); + +#endif diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c new file mode 100644 index 0000000..87fc65a --- /dev/null +++ b/src/soc/intel/apollolake/nhlt.c @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +static const struct nhlt_format_config dmic_2ch_cfg[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_format_config da7219_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "dialog-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_tdm_config tdm_cfg = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_format_config max98357_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "max98357-render-2ch-48khz-24b.bin", + }, +}; + +int nhlt_soc_get_link_type(int hwlink, int soc_devtype) +{ + int nhlt_link_type; + + switch (hwlink) { + case AUDIO_LINK_SSP0: + case AUDIO_LINK_SSP1: + case AUDIO_LINK_SSP3: + case AUDIO_LINK_SSP4: + case AUDIO_LINK_SSP5: + /* Only I2S devices. */ + if (soc_devtype != AUDIO_DEV_I2S) + return -1; + nhlt_link_type = NHLT_LINK_SSP; + break; + case AUDIO_LINK_SSP2: + /* Only Bluetooth devices on SSP2. */ + if (soc_devtype != AUDIO_DEV_BT) + return -1; + nhlt_link_type = NHLT_LINK_SSP; + break; + case AUDIO_LINK_DMIC: + // Only DMIC devices on DMIC links. + if (soc_devtype != AUDIO_DEV_DMIC) + return -1; + nhlt_link_type = NHLT_LINK_PDM; + break; + default: + return -1; + } + + return nhlt_link_type; +} + +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) +{ + if (num_channels != 2) { + printk(BIOS_ERR, "APL only supports 2CH DMIC array.\n"); + return -1; + } + + if (nhlt_add_dmic_array(nhlt, num_channels, dmic_2ch_cfg, + ARRAY_SIZE(dmic_2ch_cfg))) { + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + return -1; + } + + return 0; +} + +int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink) +{ + if (nhlt_add_codec_on_ssp(nhlt, hwlink, max98357_cfg, + ARRAY_SIZE(max98357_cfg), NULL, 0, NULL, 0)) { + printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n"); + return -1; + } + + return 0; +} + +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink) +{ + if (nhlt_add_codec_on_ssp(nhlt, hwlink, da7219_cfg, + ARRAY_SIZE(da7219_cfg), da7219_cfg, ARRAY_SIZE(da7219_cfg), &tdm_cfg, + sizeof(tdm_cfg))) { + printk(BIOS_ERR, "Couldn't add Dialog_7219 codec.\n"); + return -1; + } + + return 0; +}

1 0

Patch set updated for coreboot: lib/nhlt: Add common NHLT audio for Intel platforms
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15023 -gerrit commit 28458cc9e9f9f307cc835a89d6b8f5c2f23c253e Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Jun 23 14:46:27 2016 -0700 lib/nhlt: Add common NHLT audio for Intel platforms The use of a NHLT table is required to make audio work on the Intel SoCs employing the internal DSP. The table describes the audio endpoints (render vs capture) along with their supported formats. These formats are not only dependent on the audio peripheral but also hardware interfaces. As such each format has an associated blob of DSP settings to make the peripheral work. Lastly, each of these settings are provided by Intel and need to be generated for each device's hardware connection plus mode/format it supports. This patch does not include the DSP setting blobs. Change-Id: I3c75d3537288c47d29e8949ca253ea8c5c1a387d Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/include/nhlt.h | 44 +++++++++++++++ src/lib/nhlt.c | 157 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 199 insertions(+), 2 deletions(-) diff --git a/src/include/nhlt.h b/src/include/nhlt.h index f0b3b6f..c728764 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -23,6 +23,34 @@ struct nhlt; struct nhlt_endpoint; struct nhlt_format; struct nhlt_format_config; +struct nhlt_tdm_config; + +/* + * Add a dmic array composed of the provided number of channels. + * Returns 0 on success, < 0 on error. + */ +int nhlt_add_dmic_array(struct nhlt *nhlt, int num_channels, + const struct nhlt_format_config *dmic_ch_config, int num_fmt); + +/* + * Add audio codec on provided SSP link. Return 0 on succes, < 0 on error. + * + * The same DSP firmware settings can be used for both the capture and render + * endpoints in some cases. Most of the smart amps use different DSP firmware + * settings for capture and render endpoints. + * + * render_cfg, capture_cfg: These are the audio codec configuration defined + * in mainboard souce code. + * cfg_size: This is the number of configurations defined in codec config. + * Each configuration is added as an endpoint. + * tdm_config: This is also board specific and defined in mainboard.c + * hwlink: This is the SSP hardware port number. + * direction: This can be Render only, Capture only or Bi-directional. + */ +int nhlt_add_codec_on_ssp(struct nhlt *nhlt, int hwlink, + const struct nhlt_format_config *render_cfg, int r_num_fmt, + const struct nhlt_format_config *capture_cfg, int c_num_fmt, + const struct nhlt_tdm_config *tdm_config, size_t tdm_size); /* * Non HD Audio ACPI support. This table is typically used for Intel Smart @@ -108,6 +136,13 @@ int nhlt_endpoint_add_formats(struct nhlt_endpoint *endpoint, const struct nhlt_format_config *formats, size_t num_formats); +/* Returns corresponding nhlt link type based on hardware link number. + * Hardware link number is the SSP port number on which the particular + * is present. This is specified in mainboard.c. + * This is defined in soc/nhlt.c + */ +int nhlt_soc_get_link_type(int hwlink, int soc_devtype); + /* * Increment the instance id for a given link type. This function is * used for marking a device being completely added to the NHLT object. @@ -148,6 +183,15 @@ uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr); uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id); +/* + * NHLT device types. These values are used with nhlt_soc_add_endpoint(). + */ +enum { + AUDIO_DEV_I2S, + AUDIO_DEV_DMIC, + AUDIO_DEV_BT, +}; + /* Link and device types. */ enum { NHLT_LINK_HDA, diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index 11a397c..0746efa 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -15,9 +15,12 @@ #include <arch/acpi.h> #include <cbfs.h> +#include <cbmem.h> #include <commonlib/endian.h> #include <console/console.h> #include <nhlt.h> +#include <soc/nvs.h> +#include <soc/nhlt.h> #include <stdlib.h> #include <string.h> @@ -47,8 +50,7 @@ struct nhlt *nhlt_init(void) } struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type, - int device_type, int dir, - uint16_t vid, uint16_t did) + int device_type, int dir, uint16_t vid, uint16_t did) { struct nhlt_endpoint *endp; @@ -437,3 +439,154 @@ uintptr_t nhlt_serialize_oem_overrides(struct nhlt *nhlt, return acpi_addr; } + +struct nhlt_endpoint *nhlt_soc_add_endpoint(struct nhlt *nhlt, int soc_hwintf, + int soc_devtype, int dir) +{ + int nhlt_link_type; + int nhlt_dev_type; + uint16_t did; + struct nhlt_endpoint *endp; + + nhlt_link_type = nhlt_soc_get_link_type(soc_hwintf, soc_devtype); + + if (nhlt_link_type == -1) + return NULL; + + switch (soc_devtype) { + case AUDIO_DEV_I2S: + nhlt_dev_type = NHLT_SSP_DEV_I2S; + did = NHLT_DID_SSP; + break; + case AUDIO_DEV_DMIC: + nhlt_dev_type = NHLT_PDM_DEV; + did = NHLT_DID_DMIC; + break; + case AUDIO_DEV_BT: + nhlt_dev_type = NHLT_SSP_DEV_BT; + did = NHLT_DID_BT; + break; + default: + return NULL; + } + + endp = nhlt_add_endpoint(nhlt, nhlt_link_type, nhlt_dev_type, dir, + NHLT_VID, did); + + if (endp == NULL) + return NULL; + + /* Virtual bus id of SSP link is the hardware port id. */ + if (nhlt_link_type == NHLT_LINK_SSP) + endp->virtual_bus_id = soc_hwintf; + + return endp; +} + +uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) +{ + return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); +} + +uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, + uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs == NULL) + return acpi_addr; + + /* Update NHLT GNVS Data */ + gnvs->nhla = (uintptr_t)acpi_addr; + gnvs->nhll = nhlt_current_size(nhlt); + + return nhlt_serialize_oem_overrides(nhlt, acpi_addr, oem_id, + oem_table_id); +} + +int nhlt_add_dmic_array(struct nhlt *nhlt, int num_channels, + const struct nhlt_format_config *dmic_ch_cfg, int num_fmt) +{ + struct nhlt_endpoint *endp; + struct nhlt_dmic_array_config mic_config; + + if (num_channels != 2 && num_channels != 4) + return -1; + + endp = nhlt_soc_add_endpoint(nhlt, AUDIO_LINK_DMIC, AUDIO_DEV_DMIC, + NHLT_DIR_CAPTURE); + + if (endp == NULL) + return -1; + + memset(&mic_config, 0, sizeof(mic_config)); + mic_config.tdm_config.config_type = NHLT_TDM_MIC_ARRAY; + + switch (num_channels) { + case 2: + mic_config.array_type = NHLT_MIC_ARRAY_2CH_SMALL; + break; + case 4: + mic_config.array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED; + break; + } + + if (nhlt_endpoint_append_config(endp, &mic_config, sizeof(mic_config))) + return -1; + + return nhlt_endpoint_add_formats(endp, dmic_ch_cfg, num_fmt); +} + +int nhlt_add_codec_on_ssp(struct nhlt *nhlt, int hwlink, + const struct nhlt_format_config *render_cfg, int r_num_fmt, + const struct nhlt_format_config *capture_cfg, int c_num_fmt, + const struct nhlt_tdm_config *tdm_config, size_t tdm_size) +{ + struct nhlt_endpoint *endp; + + /* For Bi-directional amplifiers, both capture and render + * configuratoins are needed. + */ + if (render_cfg == NULL && capture_cfg == NULL) + return -1; + + /* Render Endpoint */ + if (render_cfg != NULL) { + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_RENDER); + if (endp == NULL) + return -1; + + if (tdm_config != NULL) { + if (nhlt_endpoint_append_config(endp, tdm_config, + tdm_size)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, render_cfg, r_num_fmt)) + return -1; + } + + /* Capture Endpoint */ + if (capture_cfg != NULL) { + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_CAPTURE); + if (endp == NULL) + return -1; + + if (tdm_config != NULL) { + if (nhlt_endpoint_append_config(endp, tdm_config, + tdm_size)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, capture_cfg, c_num_fmt)) + return -1; + } + + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return 0; +}

1 0

Patch set updated for coreboot: google/reef: disable unused devices
by Jagadish Krishnamoorthy 28 Jun '16

28 Jun '16

Jagadish Krishnamoorthy (jagadish.krishnamoorthy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15339 -gerrit commit b45de3fa75d849396e850fe8487c1a5e61751fb7 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Thu Jun 23 12:50:01 2016 -0700 google/reef: disable unused devices BRANCH=none BUG=chrome-os-partner:54325, chrome-os-partner:54581 TEST=device off in devicetree should disable the device. Change-Id: I5dada06cba0eea8a30f297e3a6940a36b2ff40ee Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> --- src/mainboard/google/reef/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index d8ddd46..d2b295f 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -56,7 +56,7 @@ chip soc/intel/apollolake device pci 14.0 on end # - Root Port 0 - PCIe-B 0 - Wifi device pci 14.1 off end # - Root Port 1 - PCIe-B 1 device pci 15.0 on end # - XHCI - device pci 15.1 on end # - XDCI + device pci 15.1 off end # - XDCI device pci 16.0 on end # - I2C 0 device pci 16.1 on end # - I2C 1 device pci 16.2 on end # - I2C 2 @@ -75,7 +75,7 @@ chip soc/intel/apollolake device pci 1a.0 on end # - PWM device pci 1b.0 on end # - SDCARD device pci 1c.0 on end # - eMMC - device pci 1e.0 on end # - SDIO + device pci 1e.0 off end # - SDIO device pci 1f.0 on # - LPC chip ec/google/chromeec device pnp 0c09.0 on end

1 0

Patch set updated for coreboot: cbfstool: Require "-m ARCH" to extract payloads and stages
by Antonello Dettori 28 Jun '16

28 Jun '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15438 -gerrit commit 6c21628a3cb8bb9f6df44d086b7d33c42104bc79 Author: Antonello Dettori <dev(a)dettori.io> Date: Sun Jun 26 00:24:25 2016 +0200 cbfstool: Require "-m ARCH" to extract payloads and stages Require the user to specify which architecture the payload/stage was built for before extracting it. Change-Id: I8ffe90a6af24e76739fd25456383a566edb0da7e Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- util/cbfstool/cbfs_image.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 5142a7a..1e38e4e 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -966,6 +966,11 @@ static int cbfs_stage_make_elf(struct buffer *buff, uint32_t arch) size_t empty_sz; int rmod_ret; + if (arch == CBFS_ARCHITECTURE_UNKNOWN) { + ERROR("You need to specify -m ARCH.\n"); + return -1; + } + if (cbfs_stage_decompress(&stage, buff)) { ERROR("Failed to decompress stage.\n"); return -1; @@ -1047,6 +1052,11 @@ static int cbfs_payload_make_elf(struct buffer *buff, uint32_t arch) size_t empty_sz; int segments = 0; + if (arch == CBFS_ARCHITECTURE_UNKNOWN) { + ERROR("You need to specify -m ARCH.\n"); + return -1; + } + /* Count the number of segments inside buffer */ while (true) { uint32_t payload_type = 0;

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coreboot-gerrit June 2016