coreboot-gerrit June 2016

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Patch set updated for coreboot: lib/nhlt: Add common NHLT audio for Intel platforms
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15023 -gerrit commit 249c0b783602d5037bd8e6f9ee59b69df26713c1 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Jun 23 14:46:27 2016 -0700 lib/nhlt: Add common NHLT audio for Intel platforms The use of a NHLT table is required to make audio work on the Intel SoCs employing the internal DSP. The table describes the audio endpoints (render vs capture) along with their supported formats. These formats are not only dependent on the audio peripheral but also hardware interfaces. As such each format has an associated blob of DSP settings to make the peripheral work. Lastly, each of these settings are provided by Intel and need to be generated for each device's hardware connection plus mode/format it supports. This patch does not include the DSP setting blobs. Change-Id: I3c75d3537288c47d29e8949ca253ea8c5c1a387d Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/include/nhlt.h | 45 +++++++++++++++++++++++++++ src/lib/nhlt.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 134 insertions(+), 2 deletions(-) diff --git a/src/include/nhlt.h b/src/include/nhlt.h index f0b3b6f..20d20ed 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -23,6 +23,51 @@ struct nhlt; struct nhlt_endpoint; struct nhlt_format; struct nhlt_format_config; +struct nhlt_tdm_config; + +/* + * NHLT device types. These values are used with nhlt_soc_add_endpoint(). + */ +enum { + AUDIO_DEV_I2S, + AUDIO_DEV_DMIC, + AUDIO_DEV_BT, +}; + +/* + * Returns corresponding nhlt link type based on hardware link number. + * Hardware link number is the SSP port number on which the particular + * is present, which is mainboard specfic. + * nhlt_soc_get_link_type() is SoC specific. + */ +int nhlt_soc_get_link_type(int hwlink, int soc_devtype); + +/* + * Add a dmic array composed of the provided number of channels. + * Returns 0 on success, < 0 on error. + */ +int nhlt_add_dmic_array(struct nhlt *nhlt, int num_channels, + const struct nhlt_format_config *dmic_ch_config, int num_fmt); + +/* + * Add audio codec on provided SSP link. Return 0 on succes, < 0 on error. + * + * The same DSP firmware settings can be used for both the capture and render + * endpoints in some cases. Most of the smart amps use different DSP firmware + * settings for capture and render endpoints. + * + * render_cfg, capture_cfg: These are the audio codec configuration defined + * in mainboard souce code. + * cfg_size: This is the number of configurations defined in codec config. + * Each configuration is added as an endpoint. + * tdm_config: This is also board specific and defined in mainboard.c + * hwlink: This is the SSP hardware port number. + * direction: This can be Render only, Capture only or Bi-directional. + */ +int nhlt_add_codec_on_ssp(struct nhlt *nhlt, int hwlink, + const struct nhlt_format_config *render_cfg, int r_num_fmt, + const struct nhlt_format_config *capture_cfg, int c_num_fmt, + const struct nhlt_tdm_config *tdm_config, size_t tdm_size); /* * Non HD Audio ACPI support. This table is typically used for Intel Smart diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index 11a397c..e31803d 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -15,9 +15,12 @@ #include <arch/acpi.h> #include <cbfs.h> +#include <cbmem.h> #include <commonlib/endian.h> #include <console/console.h> #include <nhlt.h> +#include <soc/nvs.h> +#include <soc/nhlt.h> #include <stdlib.h> #include <string.h> @@ -47,8 +50,7 @@ struct nhlt *nhlt_init(void) } struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type, - int device_type, int dir, - uint16_t vid, uint16_t did) + int device_type, int dir, uint16_t vid, uint16_t did) { struct nhlt_endpoint *endp; @@ -437,3 +439,88 @@ uintptr_t nhlt_serialize_oem_overrides(struct nhlt *nhlt, return acpi_addr; } + +int nhlt_add_dmic_array(struct nhlt *nhlt, int num_channels, + const struct nhlt_format_config *dmic_ch_cfg, int num_fmt) +{ + struct nhlt_endpoint *endp; + struct nhlt_dmic_array_config mic_config; + + if (num_channels != 2 && num_channels != 4) + return -1; + + endp = nhlt_soc_add_endpoint(nhlt, AUDIO_LINK_DMIC, AUDIO_DEV_DMIC, + NHLT_DIR_CAPTURE); + + if (endp == NULL) + return -1; + + memset(&mic_config, 0, sizeof(mic_config)); + mic_config.tdm_config.config_type = NHLT_TDM_MIC_ARRAY; + + switch (num_channels) { + case 2: + mic_config.array_type = NHLT_MIC_ARRAY_2CH_SMALL; + break; + case 4: + mic_config.array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED; + break; + } + + if (nhlt_endpoint_append_config(endp, &mic_config, sizeof(mic_config))) + return -1; + + return nhlt_endpoint_add_formats(endp, dmic_ch_cfg, num_fmt); +} + +int nhlt_add_codec_on_ssp(struct nhlt *nhlt, int hwlink, + const struct nhlt_format_config *render_cfg, int r_num_fmt, + const struct nhlt_format_config *capture_cfg, int c_num_fmt, + const struct nhlt_tdm_config *tdm_config, size_t tdm_size) +{ + struct nhlt_endpoint *endp; + + /* For Bi-directional amplifiers, both capture and render + * configuratoins are needed. + */ + if (render_cfg == NULL && capture_cfg == NULL) + return -1; + + /* Render Endpoint */ + if (render_cfg != NULL) { + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_RENDER); + if (endp == NULL) + return -1; + + if (tdm_config != NULL) { + if (nhlt_endpoint_append_config(endp, tdm_config, + tdm_size)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, render_cfg, r_num_fmt)) + return -1; + } + + /* Capture Endpoint */ + if (capture_cfg != NULL) { + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_CAPTURE); + if (endp == NULL) + return -1; + + if (tdm_config != NULL) { + if (nhlt_endpoint_append_config(endp, tdm_config, + tdm_size)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, capture_cfg, c_num_fmt)) + return -1; + } + + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return 0; +}

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Patch set updated for coreboot: soc/intel/apollolake: Add GPE routing code
by Shaunak Saha 28 Jun '16

28 Jun '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15324 -gerrit commit 98261fd94a77023fb6becc5f8187b69338e7bcb8 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jun 7 02:06:28 2016 -0700 soc/intel/apollolake: Add GPE routing code This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/chip.c | 6 +- src/soc/intel/apollolake/chip.h | 7 + src/soc/intel/apollolake/gpio.c | 85 ++++++++ src/soc/intel/apollolake/include/soc/gpio.h | 14 ++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 236 +++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pm.h | 9 +- 6 files changed, 354 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 821570b..fc0025a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -33,6 +33,7 @@ #include <soc/pci_devs.h> #include <spi-generic.h> #include <soc/pm.h> +#include <soc/gpio.h> #include "chip.h" @@ -274,7 +275,6 @@ struct chip_operations soc_intel_apollolake_ops = { static void fsp_notify_dummy(void *arg) { - enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; enum fsp_status ret; @@ -284,8 +284,10 @@ static void fsp_notify_dummy(void *arg) fsp_handle_reset(ret); } /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ - if (ph == READY_TO_BOOT) + if (ph == READY_TO_BOOT){ + pmc_gpe_init(); fsp_notify_dummy((void *)END_OF_FIRMWARE); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ef82c53..7599d4e 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -18,6 +18,8 @@ #ifndef _SOC_APOLLOLAKE_CHIP_H_ #define _SOC_APOLLOLAKE_CHIP_H_ +#include <soc/gpio_defs.h> + #define CLKREQ_DISABLED 0xf /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ @@ -79,6 +81,11 @@ struct soc_intel_apollolake_config { /* Integrated Sensor Hub */ uint8_t integrated_sensor_hub_enable; + + uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index d0ef648..0571e51 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -19,6 +19,14 @@ #include <gpio.h> #include <soc/gpio.h> #include <soc/iosf.h> +#include <soc/pm.h> +#include <soc/iomap.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <soc/pci_devs.h> +#include <device/pci.h> +#include "chip.h" + /* This list must be in order, from highest pad numbers, to lowest pad numbers*/ static const struct pad_community { @@ -132,3 +140,80 @@ const char *gpio_acpi_path(gpio_t gpio_num) return NULL; } + +#if ENV_RAMSTAGE + +void pmc_gpe_init(void) +{ + uint32_t gpio_cfg = 0; + uint32_t gpio_cfg_reg; + struct soc_intel_apollolake_config *config; + + struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN); + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + + uintptr_t pmc_bar = get_pmc_mmio_bar(); + + const uint32_t gpio_cfg_mask = + (GPE0_DWX_MASK << GPE0_DW0_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW2_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW3_SHIFT); + + /* Route the GPIOs to the GPE0 block. Determine that all values + * are different, and if they aren't use the reset values. + * DW0 is reserved/unused */ + if (config->gpe0_dw1 == config->gpe0_dw2 || + config->gpe0_dw2 == config->gpe0_dw3) { + printk(BIOS_INFO, "PMC: Using default GPE route.\n"); + gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG); + } else { + gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw3 << GPE0_DW3_SHIFT; + } + + gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; + gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; + + write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg); + + /* Set the routes in the GPIO communities as well. */ + gpio_route_gpe(); +} + +void gpio_route_gpe(void) +{ + int i; + uint32_t misccfg_mask; + uint32_t misccfg_value; + uint32_t gpe0_dw0; + uint32_t gpe0_dw1; + uint32_t gpe0_dw2; + + /* Set the group here for community specific MISCCFG register */ + gpe0_dw0 = GPP_7; /* GPE0b */ + gpe0_dw1 = GPP_0; /* GPE0c */ + gpe0_dw2 = GPP_0; /* GPE0d */ + + /*Program GPIO_MISCCFG */ + misccfg_mask = (uint32_t) ~(MISCCFG_GPE0_DW2_MASK | + MISCCFG_GPE0_DW1_MASK | + MISCCFG_GPE0_DW0_MASK); + misccfg_value = (uint32_t)((gpe0_dw2 << MISCCFG_GPE0_DW2_SHIFT) | + (gpe0_dw1 << MISCCFG_GPE0_DW1_SHIFT) | + (gpe0_dw0 << MISCCFG_GPE0_DW0_SHIFT)); + + for (i = 0; i < ARRAY_SIZE(gpio_communities); i++) { + const struct pad_community *comm = &gpio_communities[i]; + + iosf_write( comm->port,GPIO_MISCCFG,((iosf_read( comm->port, + GPIO_MISCCFG)& misccfg_mask) | misccfg_value)); + } +} + +#endif diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index c9d32cc..9bed198 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -22,6 +22,7 @@ /* __ACPI__ guard is needed to ignore below code in ACPI/ASL compilation */ #ifndef __ACPI__ #include <types.h> +#include <soc/gpio_defs.h> typedef uint32_t gpio_t; @@ -99,5 +100,18 @@ struct pad_config { void gpio_configure_pad(const struct pad_config *cfg); void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); +void pmc_gpe_init(void); + +/* + * Set the GPIO groups for the GPE blocks. The gpe0_route is interpreted + * as the packed configuration for GPE0_DW[2:0]. This basically sets the + * MISCCFG register bits: + * dw0 = gpe0_route[11:8] + * dw1 = gpe0_route[15:12] + * dw2 = gpe0_route[19:16]. + */ +void gpio_route_gpe(void); + #endif /* __ACPI__ */ + #endif /* _SOC_APOLLOLAKE_GPIO_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 30c4bdb..d96ffba 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -23,6 +23,242 @@ #ifndef _SOC_APOLLOLAKE_GPIO_DEFS_H_ #define _SOC_APOLLOLAKE_GPIO_DEFS_H_ +/* + * There are 8 GPIO groups. GPP_0 -> GPP_8 (Group 3 is not present) + */ +#define GPP_0 0 /* SOUTHWEST GPIO # 0 ~ 31 belong to GROUP0 */ +#define GPP_1 1 /* SOUTHWEST GPIO # 32 ~ 42 belong to GROUP1 */ +#define GPP_2 2 /* WEST GPIO # 0 ~ 25 belong to GROUP2 */ +#define GPP_4 4 /* NORTHWEST GPIO # 0 ~ 17 belong to GROUP4 */ +#define GPP_5 5 /* NORTHWEST GPIO # 32 ~ 63 belong to GROUP5, except # 52 and 60 */ +#define GPP_6 6 /* NORTHWEST GPIO # 64 ~ 76 belong to GROUP6 */ +#define GPP_7 7 /* NORTH GPIO # 0 ~ 31 belong to GROUP7 */ +#define GPP_8 8 /* NORTH GPIO # 32 ~ 61 belong to GROUP8 */ + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* SOUTHWEST */ +/* Group 0 */ +#define GPP_0_0 0 +#define GPP_0_1 1 +#define GPP_0_2 2 +#define GPP_0_3 3 +#define GPP_0_4 4 +#define GPP_0_5 5 +#define GPP_0_6 6 +#define GPP_0_7 7 +#define GPP_0_8 8 +#define GPP_0_9 9 +#define GPP_0_10 10 +#define GPP_0_11 11 +#define GPP_0_12 12 +#define GPP_0_13 13 +#define GPP_0_14 14 +#define GPP_0_15 15 +#define GPP_0_16 16 +#define GPP_0_17 17 +#define GPP_0_18 18 +#define GPP_0_19 19 +#define GPP_0_20 20 +#define GPP_0_21 21 +#define GPP_0_22 22 +#define GPP_0_23 23 +#define GPP_0_24 24 +#define GPP_0_25 25 +#define GPP_0_26 26 +#define GPP_0_27 27 +#define GPP_0_28 28 +#define GPP_0_29 29 +#define GPP_0_30 30 +#define GPP_0_31 31 + +/* Group 1 */ +#define GPP_1_0 32 +#define GPP_1_1 33 +#define GPP_1_2 34 +#define GPP_1_3 35 +#define GPP_1_4 36 +#define GPP_1_5 37 +#define GPP_1_6 38 +#define GPP_1_7 39 +#define GPP_1_8 40 +#define GPP_1_9 41 +#define GPP_1_10 42 + +/* WEST */ +/* Group 2 */ +#define GPP_2_0 0 +#define GPP_2_1 1 +#define GPP_2_2 2 +#define GPP_2_3 3 +#define GPP_2_4 4 +#define GPP_2_5 5 +#define GPP_2_6 6 +#define GPP_2_7 7 +#define GPP_2_8 8 +#define GPP_2_9 9 +#define GPP_2_10 10 +#define GPP_2_11 11 +#define GPP_2_12 12 +#define GPP_2_13 13 +#define GPP_2_14 14 +#define GPP_2_15 15 +#define GPP_2_16 16 +#define GPP_2_17 17 +#define GPP_2_18 18 +#define GPP_2_19 19 +#define GPP_2_20 20 +#define GPP_2_21 21 +#define GPP_2_22 22 +#define GPP_2_23 23 +#define GPP_2_24 24 +#define GPP_2_25 25 + +/* NORTHWEST */ +/* Group 4 */ +#define GPP_4_0 0 +#define GPP_4_1 1 +#define GPP_4_2 2 +#define GPP_4_3 3 +#define GPP_4_4 4 +#define GPP_4_5 5 +#define GPP_4_6 6 +#define GPP_4_7 7 +#define GPP_4_8 8 +#define GPP_4_9 9 +#define GPP_4_10 10 +#define GPP_4_11 11 +#define GPP_4_12 12 +#define GPP_4_13 13 +#define GPP_4_14 14 +#define GPP_4_15 15 +#define GPP_4_16 16 +#define GPP_4_17 17 + +/* Group 5 */ +#define GPP_5_0 33 +#define GPP_5_1 34 +#define GPP_5_2 35 +#define GPP_5_3 36 +#define GPP_5_4 37 +#define GPP_5_5 38 +#define GPP_5_6 39 +#define GPP_5_7 40 +#define GPP_5_8 41 +#define GPP_5_9 42 +#define GPP_5_10 43 +#define GPP_5_11 44 +#define GPP_5_12 45 +#define GPP_5_13 46 +#define GPP_5_14 47 +#define GPP_5_15 48 +#define GPP_5_16 49 +#define GPP_5_17 50 +#define GPP_5_18 51 +#define GPP_5_19 53 +#define GPP_5_20 54 +#define GPP_5_21 55 +#define GPP_5_22 56 +#define GPP_5_23 57 +#define GPP_5_24 58 +#define GPP_5_25 59 +#define GPP_5_26 61 +#define GPP_5_27 62 +#define GPP_5_28 63 + +/* Group 6 */ +#define GPP_6_0 64 +#define GPP_6_1 65 +#define GPP_6_2 66 +#define GPP_6_3 67 +#define GPP_6_4 68 +#define GPP_6_5 69 +#define GPP_6_6 70 +#define GPP_6_7 71 +#define GPP_6_8 72 +#define GPP_6_9 73 +#define GPP_6_10 74 +#define GPP_6_11 75 +#define GPP_6_12 76 + +/* NORTH */ +/* Group 7 */ +#define GPP_7_0 0 +#define GPP_7_1 1 +#define GPP_7_2 2 +#define GPP_7_3 3 +#define GPP_7_4 4 +#define GPP_7_5 5 +#define GPP_7_6 6 +#define GPP_7_7 7 +#define GPP_7_8 8 +#define GPP_7_9 9 +#define GPP_7_10 10 +#define GPP_7_11 11 +#define GPP_7_12 12 +#define GPP_7_13 13 +#define GPP_7_14 14 +#define GPP_7_15 15 +#define GPP_7_16 16 +#define GPP_7_17 17 +#define GPP_7_18 18 +#define GPP_7_19 19 +#define GPP_7_20 20 +#define GPP_7_21 21 +#define GPP_7_22 22 +#define GPP_7_23 23 +#define GPP_7_24 24 +#define GPP_7_25 25 +#define GPP_7_26 26 +#define GPP_7_27 27 +#define GPP_7_28 28 +#define GPP_7_29 29 +#define GPP_7_30 30 +#define GPP_7_31 31 + +/* Group 8 */ +#define GPP_8_0 32 +#define GPP_8_1 33 +#define GPP_8_2 34 +#define GPP_8_3 35 +#define GPP_8_4 36 +#define GPP_8_5 37 +#define GPP_8_6 38 +#define GPP_8_7 39 +#define GPP_8_8 40 +#define GPP_8_9 41 +#define GPP_8_10 42 +#define GPP_8_11 43 +#define GPP_8_12 44 +#define GPP_8_13 45 +#define GPP_8_14 46 +#define GPP_8_15 47 +#define GPP_8_16 48 +#define GPP_8_17 49 +#define GPP_8_18 50 +#define GPP_8_19 51 +#define GPP_8_20 52 +#define GPP_8_21 53 +#define GPP_8_22 54 +#define GPP_8_23 55 +#define GPP_8_24 56 +#define GPP_8_25 57 +#define GPP_8_26 58 +#define GPP_8_27 59 +#define GPP_8_28 60 +#define GPP_8_29 61 + +#define GPIO_MISCCFG 0x10 ///< Miscellaneous Configuration + +#define MISCCFG_GPE0_DW0_SHIFT 8 +#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) +#define MISCCFG_GPE0_DW1_SHIFT 12 +#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) +#define MISCCFG_GPE0_DW2_SHIFT 16 +#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) + #define PAD_CFG0_TX_STATE (1 << 0) #define PAD_CFG0_RX_STATE (1 << 1) #define PAD_CFG0_TX_DISABLE (1 << 8) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 3da7dd0..a3ed3b1 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -128,11 +128,18 @@ #define GEN_PMCON2 0x1024 # define RPS (1 << 2) #define GEN_PMCON3 0x1028 +#define GPIO_GPE_CFG 0x1050 + +#define GPE0_DWX_MASK 0xf +#define GPE0_DW0_SHIFT 0 +#define GPE0_DW1_SHIFT 4 +#define GPE0_DW2_SHIFT 8 +#define GPE0_DW3_SHIFT 12 + #define ETR 0x1048 # define CF9_LOCK (1 << 31) # define CF9_GLB_RST (1 << 20) - /* Generic sleep state types */ #define SLEEP_STATE_S0 0 #define SLEEP_STATE_S3 3

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Patch set updated for coreboot: soc/intel/apollolake: Add GPE routing code
by Shaunak Saha 28 Jun '16

28 Jun '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15324 -gerrit commit 1e643e541cbec7a6616752a9e5177063e9ff3337 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jun 7 02:06:28 2016 -0700 soc/intel/apollolake: Add GPE routing code This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/chip.c | 6 +- src/soc/intel/apollolake/chip.h | 7 + src/soc/intel/apollolake/gpio.c | 86 +++++++++ src/soc/intel/apollolake/include/soc/gpio.h | 14 ++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 236 +++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pm.h | 9 +- 6 files changed, 355 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 821570b..fc0025a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -33,6 +33,7 @@ #include <soc/pci_devs.h> #include <spi-generic.h> #include <soc/pm.h> +#include <soc/gpio.h> #include "chip.h" @@ -274,7 +275,6 @@ struct chip_operations soc_intel_apollolake_ops = { static void fsp_notify_dummy(void *arg) { - enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; enum fsp_status ret; @@ -284,8 +284,10 @@ static void fsp_notify_dummy(void *arg) fsp_handle_reset(ret); } /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ - if (ph == READY_TO_BOOT) + if (ph == READY_TO_BOOT){ + pmc_gpe_init(); fsp_notify_dummy((void *)END_OF_FIRMWARE); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ef82c53..7599d4e 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -18,6 +18,8 @@ #ifndef _SOC_APOLLOLAKE_CHIP_H_ #define _SOC_APOLLOLAKE_CHIP_H_ +#include <soc/gpio_defs.h> + #define CLKREQ_DISABLED 0xf /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ @@ -79,6 +81,11 @@ struct soc_intel_apollolake_config { /* Integrated Sensor Hub */ uint8_t integrated_sensor_hub_enable; + + uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index d0ef648..fe009fb 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -19,6 +19,15 @@ #include <gpio.h> #include <soc/gpio.h> #include <soc/iosf.h> +#include <soc/pm.h> +#include <soc/iomap.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <soc/pci_devs.h> +#include <reg_script.h> +#include <device/pci.h> +#include "chip.h" + /* This list must be in order, from highest pad numbers, to lowest pad numbers*/ static const struct pad_community { @@ -132,3 +141,80 @@ const char *gpio_acpi_path(gpio_t gpio_num) return NULL; } + +#if ENV_RAMSTAGE + +void pmc_gpe_init(void) +{ + uint32_t gpio_cfg = 0; + uint32_t gpio_cfg_reg; + struct soc_intel_apollolake_config *config; + + struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN); + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + + uintptr_t pmc_bar = get_pmc_mmio_bar(); + + const uint32_t gpio_cfg_mask = + (GPE0_DWX_MASK << GPE0_DW0_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW2_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW3_SHIFT); + + /* Route the GPIOs to the GPE0 block. Determine that all values + * are different, and if they aren't use the reset values. + * DW0 is reserved/unused */ + if (config->gpe0_dw1 == config->gpe0_dw2 || + config->gpe0_dw2 == config->gpe0_dw3) { + printk(BIOS_INFO, "PMC: Using default GPE route.\n"); + gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG); + } else { + gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw3 << GPE0_DW3_SHIFT; + } + + gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; + gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; + + write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg); + + /* Set the routes in the GPIO communities as well. */ + gpio_route_gpe(); +} + +void gpio_route_gpe(void) +{ + int i; + uint32_t misccfg_mask; + uint32_t misccfg_value; + uint32_t gpe0_dw0; + uint32_t gpe0_dw1; + uint32_t gpe0_dw2; + + /* Set the group here for community specific MISCCFG register */ + gpe0_dw0 = GPP_7; /* GPE0b */ + gpe0_dw1 = GPP_0; /* GPE0c */ + gpe0_dw2 = GPP_0; /* GPE0d */ + + /*Program GPIO_MISCCFG */ + misccfg_mask = (uint32_t) ~(MISCCFG_GPE0_DW2_MASK | + MISCCFG_GPE0_DW1_MASK | + MISCCFG_GPE0_DW0_MASK); + misccfg_value = (uint32_t)((gpe0_dw2 << MISCCFG_GPE0_DW2_SHIFT) | + (gpe0_dw1 << MISCCFG_GPE0_DW1_SHIFT) | + (gpe0_dw0 << MISCCFG_GPE0_DW0_SHIFT)); + + for (i = 0; i < ARRAY_SIZE(gpio_communities); i++) { + const struct pad_community *comm = &gpio_communities[i]; + + iosf_write( comm->port,GPIO_MISCCFG,((iosf_read( comm->port, + GPIO_MISCCFG)& misccfg_mask) | misccfg_value)); + } +} + +#endif diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index c9d32cc..9bed198 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -22,6 +22,7 @@ /* __ACPI__ guard is needed to ignore below code in ACPI/ASL compilation */ #ifndef __ACPI__ #include <types.h> +#include <soc/gpio_defs.h> typedef uint32_t gpio_t; @@ -99,5 +100,18 @@ struct pad_config { void gpio_configure_pad(const struct pad_config *cfg); void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); +void pmc_gpe_init(void); + +/* + * Set the GPIO groups for the GPE blocks. The gpe0_route is interpreted + * as the packed configuration for GPE0_DW[2:0]. This basically sets the + * MISCCFG register bits: + * dw0 = gpe0_route[11:8] + * dw1 = gpe0_route[15:12] + * dw2 = gpe0_route[19:16]. + */ +void gpio_route_gpe(void); + #endif /* __ACPI__ */ + #endif /* _SOC_APOLLOLAKE_GPIO_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 30c4bdb..d96ffba 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -23,6 +23,242 @@ #ifndef _SOC_APOLLOLAKE_GPIO_DEFS_H_ #define _SOC_APOLLOLAKE_GPIO_DEFS_H_ +/* + * There are 8 GPIO groups. GPP_0 -> GPP_8 (Group 3 is not present) + */ +#define GPP_0 0 /* SOUTHWEST GPIO # 0 ~ 31 belong to GROUP0 */ +#define GPP_1 1 /* SOUTHWEST GPIO # 32 ~ 42 belong to GROUP1 */ +#define GPP_2 2 /* WEST GPIO # 0 ~ 25 belong to GROUP2 */ +#define GPP_4 4 /* NORTHWEST GPIO # 0 ~ 17 belong to GROUP4 */ +#define GPP_5 5 /* NORTHWEST GPIO # 32 ~ 63 belong to GROUP5, except # 52 and 60 */ +#define GPP_6 6 /* NORTHWEST GPIO # 64 ~ 76 belong to GROUP6 */ +#define GPP_7 7 /* NORTH GPIO # 0 ~ 31 belong to GROUP7 */ +#define GPP_8 8 /* NORTH GPIO # 32 ~ 61 belong to GROUP8 */ + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* SOUTHWEST */ +/* Group 0 */ +#define GPP_0_0 0 +#define GPP_0_1 1 +#define GPP_0_2 2 +#define GPP_0_3 3 +#define GPP_0_4 4 +#define GPP_0_5 5 +#define GPP_0_6 6 +#define GPP_0_7 7 +#define GPP_0_8 8 +#define GPP_0_9 9 +#define GPP_0_10 10 +#define GPP_0_11 11 +#define GPP_0_12 12 +#define GPP_0_13 13 +#define GPP_0_14 14 +#define GPP_0_15 15 +#define GPP_0_16 16 +#define GPP_0_17 17 +#define GPP_0_18 18 +#define GPP_0_19 19 +#define GPP_0_20 20 +#define GPP_0_21 21 +#define GPP_0_22 22 +#define GPP_0_23 23 +#define GPP_0_24 24 +#define GPP_0_25 25 +#define GPP_0_26 26 +#define GPP_0_27 27 +#define GPP_0_28 28 +#define GPP_0_29 29 +#define GPP_0_30 30 +#define GPP_0_31 31 + +/* Group 1 */ +#define GPP_1_0 32 +#define GPP_1_1 33 +#define GPP_1_2 34 +#define GPP_1_3 35 +#define GPP_1_4 36 +#define GPP_1_5 37 +#define GPP_1_6 38 +#define GPP_1_7 39 +#define GPP_1_8 40 +#define GPP_1_9 41 +#define GPP_1_10 42 + +/* WEST */ +/* Group 2 */ +#define GPP_2_0 0 +#define GPP_2_1 1 +#define GPP_2_2 2 +#define GPP_2_3 3 +#define GPP_2_4 4 +#define GPP_2_5 5 +#define GPP_2_6 6 +#define GPP_2_7 7 +#define GPP_2_8 8 +#define GPP_2_9 9 +#define GPP_2_10 10 +#define GPP_2_11 11 +#define GPP_2_12 12 +#define GPP_2_13 13 +#define GPP_2_14 14 +#define GPP_2_15 15 +#define GPP_2_16 16 +#define GPP_2_17 17 +#define GPP_2_18 18 +#define GPP_2_19 19 +#define GPP_2_20 20 +#define GPP_2_21 21 +#define GPP_2_22 22 +#define GPP_2_23 23 +#define GPP_2_24 24 +#define GPP_2_25 25 + +/* NORTHWEST */ +/* Group 4 */ +#define GPP_4_0 0 +#define GPP_4_1 1 +#define GPP_4_2 2 +#define GPP_4_3 3 +#define GPP_4_4 4 +#define GPP_4_5 5 +#define GPP_4_6 6 +#define GPP_4_7 7 +#define GPP_4_8 8 +#define GPP_4_9 9 +#define GPP_4_10 10 +#define GPP_4_11 11 +#define GPP_4_12 12 +#define GPP_4_13 13 +#define GPP_4_14 14 +#define GPP_4_15 15 +#define GPP_4_16 16 +#define GPP_4_17 17 + +/* Group 5 */ +#define GPP_5_0 33 +#define GPP_5_1 34 +#define GPP_5_2 35 +#define GPP_5_3 36 +#define GPP_5_4 37 +#define GPP_5_5 38 +#define GPP_5_6 39 +#define GPP_5_7 40 +#define GPP_5_8 41 +#define GPP_5_9 42 +#define GPP_5_10 43 +#define GPP_5_11 44 +#define GPP_5_12 45 +#define GPP_5_13 46 +#define GPP_5_14 47 +#define GPP_5_15 48 +#define GPP_5_16 49 +#define GPP_5_17 50 +#define GPP_5_18 51 +#define GPP_5_19 53 +#define GPP_5_20 54 +#define GPP_5_21 55 +#define GPP_5_22 56 +#define GPP_5_23 57 +#define GPP_5_24 58 +#define GPP_5_25 59 +#define GPP_5_26 61 +#define GPP_5_27 62 +#define GPP_5_28 63 + +/* Group 6 */ +#define GPP_6_0 64 +#define GPP_6_1 65 +#define GPP_6_2 66 +#define GPP_6_3 67 +#define GPP_6_4 68 +#define GPP_6_5 69 +#define GPP_6_6 70 +#define GPP_6_7 71 +#define GPP_6_8 72 +#define GPP_6_9 73 +#define GPP_6_10 74 +#define GPP_6_11 75 +#define GPP_6_12 76 + +/* NORTH */ +/* Group 7 */ +#define GPP_7_0 0 +#define GPP_7_1 1 +#define GPP_7_2 2 +#define GPP_7_3 3 +#define GPP_7_4 4 +#define GPP_7_5 5 +#define GPP_7_6 6 +#define GPP_7_7 7 +#define GPP_7_8 8 +#define GPP_7_9 9 +#define GPP_7_10 10 +#define GPP_7_11 11 +#define GPP_7_12 12 +#define GPP_7_13 13 +#define GPP_7_14 14 +#define GPP_7_15 15 +#define GPP_7_16 16 +#define GPP_7_17 17 +#define GPP_7_18 18 +#define GPP_7_19 19 +#define GPP_7_20 20 +#define GPP_7_21 21 +#define GPP_7_22 22 +#define GPP_7_23 23 +#define GPP_7_24 24 +#define GPP_7_25 25 +#define GPP_7_26 26 +#define GPP_7_27 27 +#define GPP_7_28 28 +#define GPP_7_29 29 +#define GPP_7_30 30 +#define GPP_7_31 31 + +/* Group 8 */ +#define GPP_8_0 32 +#define GPP_8_1 33 +#define GPP_8_2 34 +#define GPP_8_3 35 +#define GPP_8_4 36 +#define GPP_8_5 37 +#define GPP_8_6 38 +#define GPP_8_7 39 +#define GPP_8_8 40 +#define GPP_8_9 41 +#define GPP_8_10 42 +#define GPP_8_11 43 +#define GPP_8_12 44 +#define GPP_8_13 45 +#define GPP_8_14 46 +#define GPP_8_15 47 +#define GPP_8_16 48 +#define GPP_8_17 49 +#define GPP_8_18 50 +#define GPP_8_19 51 +#define GPP_8_20 52 +#define GPP_8_21 53 +#define GPP_8_22 54 +#define GPP_8_23 55 +#define GPP_8_24 56 +#define GPP_8_25 57 +#define GPP_8_26 58 +#define GPP_8_27 59 +#define GPP_8_28 60 +#define GPP_8_29 61 + +#define GPIO_MISCCFG 0x10 ///< Miscellaneous Configuration + +#define MISCCFG_GPE0_DW0_SHIFT 8 +#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) +#define MISCCFG_GPE0_DW1_SHIFT 12 +#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) +#define MISCCFG_GPE0_DW2_SHIFT 16 +#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) + #define PAD_CFG0_TX_STATE (1 << 0) #define PAD_CFG0_RX_STATE (1 << 1) #define PAD_CFG0_TX_DISABLE (1 << 8) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 3da7dd0..a3ed3b1 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -128,11 +128,18 @@ #define GEN_PMCON2 0x1024 # define RPS (1 << 2) #define GEN_PMCON3 0x1028 +#define GPIO_GPE_CFG 0x1050 + +#define GPE0_DWX_MASK 0xf +#define GPE0_DW0_SHIFT 0 +#define GPE0_DW1_SHIFT 4 +#define GPE0_DW2_SHIFT 8 +#define GPE0_DW3_SHIFT 12 + #define ETR 0x1048 # define CF9_LOCK (1 << 31) # define CF9_GLB_RST (1 << 20) - /* Generic sleep state types */ #define SLEEP_STATE_S0 0 #define SLEEP_STATE_S3 3

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New patch to review for coreboot: intel post-car: Consolidate choose_top_of_stack()
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15463 -gerrit commit 896cf09b4440fbbc996dd5e7f72effd0fff7a660 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 14:50:27 2016 +0300 intel post-car: Consolidate choose_top_of_stack() Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/Kconfig | 4 +++ src/cpu/intel/haswell/romstage.c | 16 +---------- src/drivers/intel/fsp1_1/Kconfig | 4 --- src/drivers/intel/fsp1_1/stack.c | 20 ++------------ src/include/program_loading.h | 4 +++ src/lib/Makefile.inc | 1 + src/lib/romstage_stack.c | 44 ++++++++++++++++++++++++++++++ src/soc/intel/baytrail/romstage/romstage.c | 16 +---------- src/soc/intel/broadwell/romstage/stack.c | 17 ++---------- 9 files changed, 59 insertions(+), 67 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index a026b28..37d6513 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -25,6 +25,10 @@ config DCACHE_BSP_STACK_SLUSH config DCACHE_AP_STACK_SIZE hex +config ROMSTAGE_RAM_STACK_SIZE + hex "Size of the romstage RAM stack in bytes" + default 0x5000 + config SMP bool default y if MAX_CPUS != 1 diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index cde9441..8354aeb 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -65,20 +65,6 @@ static inline u32 *stack_push(u32 *stack, u32 value) return stack; } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - ROMSTAGE_RAM_STACK_SIZE); - stack_top += ROMSTAGE_RAM_STACK_SIZE; - return stack_top; -} - /* setup_romstage_stack_after_car() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ static void *setup_romstage_stack_after_car(void) @@ -90,7 +76,7 @@ static void *setup_romstage_stack_after_car(void) u32 top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; + top_of_stack = romstage_ram_stack() & ~3; slot = (void *)top_of_stack; num_mtrrs = 0; diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 86f6c7b..59b4797 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -99,10 +99,6 @@ config GOP_SUPPORT bool "Enable GOP support" default n -config ROMSTAGE_RAM_STACK_SIZE - hex "Size of the romstage RAM stack in bytes" - default 0x5000 - config USE_GENERIC_FSP_CAR_INC bool default n diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index 65ba235..b0e4992 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -21,23 +21,7 @@ #include <fsp/romstage.h> #include <fsp/stack.h> #include <stdlib.h> - -const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE; - -/* - * Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. - */ -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; -} +#include <program_loading.h> /* * setup_stack_and_mtrrs() determines the stack to use after @@ -57,7 +41,7 @@ void *setup_stack_and_mtrrs(void) soc_display_mtrrs(); /* Top of stack needs to be aligned to a 8-byte boundary. */ - top_of_stack = choose_top_of_stack(); + top_of_stack = romstage_ram_stack(); slot = (void *)top_of_stack; num_mtrrs = 0; max_mtrrs = soc_get_variable_mtrr_count(NULL); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 42addb8..f87082d 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -170,6 +170,10 @@ void run_ramstage(void); /* Called when the stage cache couldn't load ramstage on resume. */ void ramstage_cache_invalid(void); +/* Determine where stack for ramstage loader is located. */ +unsigned long romstage_ram_stack_maybe_low(int no_cbmem); +unsigned long romstage_ram_stack(void); + /*********************** * PAYLOAD LOADING * ***********************/ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1028917..0c34b75 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -78,6 +78,7 @@ romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c +romstage-y += romstage_stack.c romstage-y += stack.c ramstage-y += rtc.c diff --git a/src/lib/romstage_stack.c b/src/lib/romstage_stack.c new file mode 100644 index 0000000..319d354 --- /dev/null +++ b/src/lib/romstage_stack.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <program_loading.h> +#include <cbmem.h> + +const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE; + +/* + * Romstage needs quite a bit of stack for decompressing images since the lzma + * lib keeps its state on the stack during romstage. + */ +unsigned long romstage_ram_stack_maybe_low(int no_cbmem) +{ + unsigned long stack_top; + + if (no_cbmem) + return CONFIG_RAMTOP; + + /* cbmem_add() does a find() before add(). */ + stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, + romstage_ram_stack_size); + stack_top += romstage_ram_stack_size; + return stack_top; +} + +unsigned long romstage_ram_stack(void) +{ + int no_cbmem = IS_ENABLED(CONFIG_LATE_CBMEM_INIT); + return romstage_ram_stack_maybe_low(no_cbmem); +} diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index a167c90..6cf13bc 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -258,20 +258,6 @@ static inline uint32_t *stack_push(u32 *stack, u32 value) return stack; } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - const unsigned long romstage_ram_stack_size = 0x5000; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; -} - /* setup_stack_and_mttrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ static void *setup_stack_and_mttrs(void) @@ -283,7 +269,7 @@ static void *setup_stack_and_mttrs(void) uint32_t top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; + top_of_stack = romstage_ram_stack() & ~3; slot = (void *)top_of_stack; num_mtrrs = 0; diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c index 6c602a8..87f56ad 100644 --- a/src/soc/intel/broadwell/romstage/stack.c +++ b/src/soc/intel/broadwell/romstage/stack.c @@ -21,6 +21,7 @@ #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <soc/romstage.h> +#include <program_loading.h> static inline uint32_t *stack_push(u32 *stack, u32 value) { @@ -29,20 +30,6 @@ static inline uint32_t *stack_push(u32 *stack, u32 value) return stack; } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - const unsigned long romstage_ram_stack_size = 0x5000; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; -} - /* setup_stack_and_mttrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mttrs(void) @@ -54,7 +41,7 @@ void *setup_stack_and_mttrs(void) uint32_t top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; + top_of_stack = romstage_ram_stack() & ~3; slot = (void *)top_of_stack; num_mtrrs = 0;

1 0

New patch to review for coreboot: intel/haswell: No need for ACPI S3 resume backup
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15462 -gerrit commit e59bdcfb22ac506cb50885f2c7792823c27a4418 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 26 14:03:55 2016 +0300 intel/haswell: No need for ACPI S3 resume backup Platform is with RELOCATABLE_RAMSTAGE so nothing to backup. Change-Id: I2397db8affb084e34ca89dac4840f966b994e636 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/haswell/romstage.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 9cd4ae0..cde9441 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -275,13 +275,6 @@ void romstage_common(const struct romstage_params *params) void romstage_after_car(void) { - struct romstage_handoff *handoff; - - handoff = romstage_handoff_find_or_add(); - - if (handoff != NULL && handoff->s3_resume) - acpi_prepare_for_resume(); - /* Load the ramstage. */ run_ramstage(); }

1 0

New patch to review for coreboot: intel romstage: Use run_ramstage()
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15461 -gerrit commit cb9bc8a4596c955f2ee21c84677f8619064b0739 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 11:27:56 2016 +0300 intel romstage: Use run_ramstage() Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/haswell/romstage.c | 4 ++-- src/drivers/intel/fsp1_1/romstage.c | 4 ++-- src/mainboard/intel/cougar_canyon2/romstage.c | 4 ++-- src/soc/intel/baytrail/romstage/romstage.c | 4 ++-- src/soc/intel/broadwell/romstage/romstage.c | 4 ++-- src/soc/intel/fsp_baytrail/romstage/romstage.c | 4 ++-- src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 4 ++-- src/southbridge/intel/fsp_i89xx/romstage.c | 4 ++-- src/southbridge/intel/fsp_rangeley/romstage.c | 4 ++-- 9 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 11d449c..9cd4ae0 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -26,10 +26,10 @@ #include <timestamp.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/stages.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> #include <cbmem.h> +#include <program_loading.h> #include <romstage_handoff.h> #include <reset.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -283,7 +283,7 @@ void romstage_after_car(void) acpi_prepare_for_resume(); /* Load the ramstage. */ - copy_and_run(); + run_ramstage(); } diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index c380ff7..f99c87a 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -17,7 +17,6 @@ #include <stddef.h> #include <arch/io.h> #include <arch/cbfs.h> -#include <arch/stages.h> #include <arch/early_variables.h> #include <boardid.h> #include <console/console.h> @@ -29,6 +28,7 @@ #include <elog.h> #include <fsp/romstage.h> #include <reset.h> +#include <program_loading.h> #include <romstage_handoff.h> #include <smbios.h> #include <soc/intel/common/mrc_cache.h> @@ -187,7 +187,7 @@ void romstage_common(struct romstage_params *params) void after_cache_as_ram_stage(void) { /* Load the ramstage. */ - copy_and_run(); + run_ramstage(); die("ERROR - Failed to load ramstage!"); } diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 094ba32..998528d 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -28,6 +28,7 @@ #include <cbmem.h> #include <console/console.h> #include <halt.h> +#include <program_loading.h> #include <reset.h> #include <superio/smsc/sio1007/chip.h> #include <fsp_util.h> @@ -39,7 +40,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include "gpio.h" -#include <arch/stages.h> #define SIO_PORT 0x164e @@ -303,7 +303,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { post_code(0x4f); /* Load the ramstage. */ - copy_and_run(); + run_ramstage(); while (1); } diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index d3eea26..a167c90 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -16,7 +16,6 @@ #include <stddef.h> #include <arch/cpu.h> #include <arch/io.h> -#include <arch/stages.h> #include <arch/early_variables.h> #include <console/console.h> #include <cbfs.h> @@ -26,6 +25,7 @@ #include <ec/google/chromeec/ec.h> #endif #include <elog.h> +#include <program_loading.h> #include <romstage_handoff.h> #include <stage_cache.h> #include <timestamp.h> @@ -247,7 +247,7 @@ void romstage_common(struct romstage_params *params) void asmlinkage romstage_after_car(void) { /* Load the ramstage. */ - copy_and_run(); + run_ramstage(); while (1); } diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 762758d..c6ffe7a 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -18,7 +18,6 @@ #include <arch/cpu.h> #include <arch/io.h> #include <arch/cbfs.h> -#include <arch/stages.h> #include <arch/early_variables.h> #include <console/console.h> #include <cbfs.h> @@ -26,6 +25,7 @@ #include <cpu/x86/mtrr.h> #include <elog.h> #include <tpm.h> +#include <program_loading.h> #include <romstage_handoff.h> #include <stage_cache.h> #include <timestamp.h> @@ -129,7 +129,7 @@ void romstage_common(struct romstage_params *params) void asmlinkage romstage_after_car(void) { /* Load the ramstage. */ - copy_and_run(); + run_ramstage(); while (1); } diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 385b3e4..4de98d3 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -19,11 +19,11 @@ #include <lib.h> #include <arch/io.h> #include <arch/cbfs.h> -#include <arch/stages.h> #include <arch/early_variables.h> #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> +#include <program_loading.h> #include <romstage_handoff.h> #include <timestamp.h> #include <soc/gpio.h> @@ -267,7 +267,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) post_code(0x4f); /* Load the ramstage. */ - copy_and_run(); + run_ramstage(); while (1); } diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index dc883a4..91c2532 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -19,9 +19,9 @@ #include <lib.h> #include <arch/io.h> #include <arch/cbfs.h> -#include <arch/stages.h> #include <console/console.h> #include <cpu/x86/mtrr.h> +#include <program_loading.h> #include <romstage_handoff.h> #include <timestamp.h> #include <version.h> @@ -110,7 +110,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) /* Load the ramstage. */ post_code(0x4e); - copy_and_run(); + run_ramstage(); while (1); } diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index f14dd5b..5bcc8fa 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -21,7 +21,6 @@ #include <timestamp.h> #include <arch/cpu.h> #include <arch/io.h> -#include <arch/stages.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> @@ -31,6 +30,7 @@ #include <console/console.h> #include <console/usb.h> #include <halt.h> +#include <program_loading.h> #include <reset.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <northbridge/intel/fsp_sandybridge/northbridge.h> @@ -214,7 +214,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { timestamp_add_now(TS_END_ROMSTAGE); - copy_and_run(); + run_ramstage(); } uint64_t get_initial_timestamp(void) diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 2fe7b2e..042aaf9 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -26,12 +26,12 @@ #include <cbmem.h> #include <console/console.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <program_loading.h> #include "northbridge/intel/fsp_rangeley/northbridge.h" #include "southbridge/intel/fsp_rangeley/soc.h" #include "southbridge/intel/fsp_rangeley/gpio.h" #include "southbridge/intel/fsp_rangeley/romstage.h" #include <arch/cpu.h> -#include <arch/stages.h> #include <cpu/x86/msr.h> #include "gpio.h" @@ -129,7 +129,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { post_code(0x4f); /* Load the ramstage. */ - copy_and_run(); + run_ramstage(); while (1); }

1 0

Patch set updated for coreboot: AMD binaryPI: Use common ACPI S3 recovery
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15254 -gerrit commit 94a2b77b0c4312f4ec11fab8678bce4e968e123d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 18 17:55:08 2016 +0300 AMD binaryPI: Use common ACPI S3 recovery Note that no binaryPI board has HAVE_ACPI_RESUME. Change-Id: Ic7d87aa81c75374dd1570cef412a3ca245285d58 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/s3_resume.c | 31 ++++++------------------------- 1 file changed, 6 insertions(+), 25 deletions(-) diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index b6d3633..576a208 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -28,6 +28,7 @@ #include <string.h> #include "Porting.h" #include <northbridge/amd/pi/BiosCallOuts.h> +#include <halt.h> #include "s3_resume.h" /* The size needs to be 4k aligned, which is the sector size of most flashes. */ @@ -134,24 +135,6 @@ void restore_mtrr(void) } #ifdef __PRE_RAM__ -static void *backup_resume(void) -{ - void *resume_backup_memory; - - if (cbmem_recovery(1)) - return NULL; - - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (((u32) resume_backup_memory == 0) - || ((u32) resume_backup_memory == -1)) { - printk(BIOS_ERR, "Error: resume_backup_memory: %x\n", - (u32) resume_backup_memory); - for (;;) ; - } - - return resume_backup_memory; -} - static void move_stack_high_mem(void) { void *high_stack; @@ -289,13 +272,14 @@ static void set_resume_cache(void) void prepare_for_resume(void) { - printk(BIOS_DEBUG, "Find resume memory location\n"); - void *resume_backup_memory = backup_resume(); + if (cbmem_recovery(1)) { + printk(BIOS_EMERG, "Unable to recover CBMEM\n"); + halt(); + } post_code(0x62); printk(BIOS_DEBUG, "Move CAR stack.\n"); move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); post_code(0x63); disable_cache_as_ram(); @@ -306,9 +290,6 @@ void prepare_for_resume(void) * Copy the system memory that is in the ramstage area to the * reserved area. */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + acpi_prepare_for_resume(); } #endif

1 0

Patch set updated for coreboot: AGESA: Use common ACPI S3 recovery
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15253 -gerrit commit 089d8215b6f57f9cafad04e765cdef258ff21e17 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 18 16:55:51 2016 +0300 AGESA: Use common ACPI S3 recovery Previous behaviour was to halt() on S3 wakeup in case resume backup memory was missing. In this odd case we now continue to normal boot. Change-Id: I8ce91088c5fa1a2d2abc53b23e423939fe759117 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 32 +++++++------------------------- 1 file changed, 7 insertions(+), 25 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 3a60b8d..54e41c1 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -25,29 +25,11 @@ #include <halt.h> #include "s3_resume.h" -static void *backup_resume(void) -{ - void *resume_backup_memory; - - printk(BIOS_DEBUG, "Find resume memory location\n"); - - if (cbmem_recovery(1)) { - printk(BIOS_EMERG, "Unable to recover CBMEM\n"); - halt(); - } - - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory == NULL) { - printk(BIOS_EMERG, "No storage for low-memory backup\n"); - halt(); - } - - return resume_backup_memory; -} - static void move_stack_high_mem(void) { void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK); + if (high_stack == NULL) + halt(); /* TODO: Make the switch with empty stack instead. */ memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); @@ -93,7 +75,10 @@ static void set_resume_cache(void) void prepare_for_resume(void) { - void *resume_backup_memory = backup_resume(); + if (cbmem_recovery(1)) { + printk(BIOS_EMERG, "Unable to recover CBMEM\n"); + halt(); + } post_code(0x62); printk(BIOS_DEBUG, "Move CAR stack.\n"); @@ -108,8 +93,5 @@ void prepare_for_resume(void) * Copy the system memory that is in the ramstage area to the * reserved area. */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + acpi_prepare_for_resume(); }

1 0

New patch to review for coreboot: soc/apollolake: Expose a function to read pmc bar
by Shaunak Saha 28 Jun '16

28 Jun '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15460 -gerrit commit bb446f7568346a6a73c5ca34dd66c01b336227b7 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Mon Jun 27 23:00:15 2016 -0700 soc/apollolake: Expose a function to read pmc bar This patch exposes a function to read pmc bar. PMC bar is read in function read_pmc_mmio_bar which is defined static in file pmutil.c. This patch exposes that functionality to call it from other files. BUG=chrome-os-partner:53438 TEST= Read the PMC bar value properly from outside pmutil file. Change-Id: I26ee13e6ab95d3a8991c7f8ea4b3856ceb015d10 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/include/soc/pm.h | 1 + src/soc/intel/apollolake/pmutil.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 8838d1c..3da7dd0 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -171,6 +171,7 @@ void disable_pm1_control(uint32_t mask); void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); +uintptr_t get_pmc_mmio_bar(void); void global_reset_enable(bool enable); void global_reset_lock(void); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index f8b2fdf..f25adfb 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -34,6 +34,11 @@ static uintptr_t read_pmc_mmio_bar(void) return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } +uintptr_t get_pmc_mmio_bar(void) +{ + return read_pmc_mmio_bar(); +} + static void print_num_status_bits(int num_bits, uint32_t status, const char * const bit_names[]) {

1 0

Patch set updated for coreboot: mainboard/google/reef: Use common NHLT
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15440 -gerrit commit c0d21376c025a251dfb52192f88b614b8cabd6dd Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Sun Jun 26 18:25:34 2016 -0700 mainboard/google/reef: Use common NHLT Add ACPI NHLT table generation that the current hardware supports. Reef supports two audio codecs, Dialog 7219 for headsets and Maxim 98357 for speakers. Change-Id: Ie39947960c86b8f65140834e31f9ed9f1b578485 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/google/reef/Kconfig | 6 +++++ src/mainboard/google/reef/dsdt.asl | 1 + src/mainboard/google/reef/mainboard.c | 47 +++++++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index d64598d..e2109e9 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -45,4 +45,10 @@ config UART_FOR_CONSOLE int default 2 +config INCLUDE_AUDIO_BLOBS + bool "Include blobs for audio." + select NHLT_DMIC_2CH_16B + select NHLT_DA7219 + select NHLT_MAX98357 + endif # BOARD_GOOGLE_REEF diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index e48db4b..7a88fb6 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -33,6 +33,7 @@ DefinitionBlock( { #include <soc/intel/apollolake/acpi/northbridge.asl> #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> } } diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 31bf9c8..888accb 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -14,7 +14,11 @@ */ #include <device/device.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <nhlt.h> #include <soc/gpio.h> +#include <soc/nhlt.h> #include "ec.h" #include "gpio.h" @@ -24,6 +28,49 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (!nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Added 2CH DMIC array.\n"); + + /* Dialog for Headset codec. + * Headset codec is bi-directional but uses the same configuration + * settings for render and capture endpoints. + */ + if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; +} + struct chip_operations mainboard_ops = { .init = mainboard_init, + .enable_dev = mainboard_enable, };

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coreboot-gerrit June 2016