coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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1491 discussions

New patch to review for coreboot: intel post-car: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15469 -gerrit commit 31a10b3207b8759c2aeb5ffc91230ca2ec35acde Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:13:48 2016 +0300 intel post-car: Delay ACPI S3 backup until ramstage loader Change-Id: If0060b9ad8703a3d6524004fb69cb2171f8d89a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/t400/romstage.c | 1 - src/mainboard/lenovo/x200/romstage.c | 1 - src/mainboard/lenovo/x201/romstage.c | 1 - src/mainboard/packardbell/ms2290/romstage.c | 1 - src/mainboard/roda/rk9/romstage.c | 1 - src/northbridge/intel/i945/early_init.c | 1 - src/northbridge/intel/sandybridge/early_init.c | 1 - 7 files changed, 7 deletions(-) diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index f518775..0e7309d 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -179,7 +179,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 1deab65..db1d62f 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -179,7 +179,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 2bfa19c..7b8d7f9 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -282,7 +282,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 92ee021..04c9513 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -272,7 +272,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index fc0c8d3..e8bd1e2 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -192,7 +192,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index ade120f..3164f25 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -900,7 +900,6 @@ static void i945_prepare_resume(int s3resume) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_was_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index a013ec3..86d1c00 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -234,7 +234,6 @@ void northbridge_romstage_finalize(int s3resume) */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);

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New patch to review for coreboot: intel post-car: Separate romstage ramstack (WIP)
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15468 -gerrit commit cce68820dd9278de8a225b658621910c8b649b9a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 13:24:11 2016 +0300 intel post-car: Separate romstage ramstack (WIP) TODO: Need to fix MTRRs before placing stack high. Change-Id: I221e207bcd0031048876f29100a1770a444d435b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/romstage.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index c6df446..4892750 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -1,7 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include <cpu/intel/romstage.h> +#include <program_loading.h> void * asmlinkage romstage_main(unsigned long bist) { mainboard_romstage_entry(bist); - return (void*)CONFIG_RAMTOP; + return (void*)romstage_ram_stack(); }

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New patch to review for coreboot: AMD binaryPI: Split romstage ram stack
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15467 -gerrit commit e4af2e47036c891c3de6f4d260500f4d37961a00 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 15:25:14 2016 +0300 AMD binaryPI: Split romstage ram stack Change-Id: Ibbff1fdb1af247550815532ef12f078229f12321 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/heapmanager.c | 10 +++------- src/cpu/amd/pi/s3_resume.c | 9 +++++---- src/cpu/amd/pi/s3_resume.h | 8 ++++++++ 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c index c5e4202..d4a79b8 100644 --- a/src/cpu/amd/pi/heapmanager.c +++ b/src/cpu/amd/pi/heapmanager.c @@ -25,13 +25,9 @@ UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader) { UINT32 heap = BIOS_HEAP_START_ADDRESS; -#if CONFIG_HAVE_ACPI_RESUME - /* Both romstage and ramstage has this S3 detect. */ - if (acpi_get_sleep_type() == 3) - heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) + - (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); - /* himem_heap_base + high_stack_size */ -#endif + if (acpi_is_wakeup_s3()) + heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH); + return heap; } diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index 576a208..830d174 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -137,11 +137,12 @@ void restore_mtrr(void) #ifdef __PRE_RAM__ static void move_stack_high_mem(void) { - void *high_stack; + void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK); + if (high_stack == NULL) + halt(); - high_stack = cbmem_find(CBMEM_ID_RESUME_SCRATCH); - memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, - (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE)); + /* TODO: Make the switch with empty stack instead. */ + memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); #ifdef __x86_64__ __asm__ diff --git a/src/cpu/amd/pi/s3_resume.h b/src/cpu/amd/pi/s3_resume.h index f952055..3b6ecfa 100644 --- a/src/cpu/amd/pi/s3_resume.h +++ b/src/cpu/amd/pi/s3_resume.h @@ -31,4 +31,12 @@ void OemAgesaSaveMtrr (void); void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len); +#if 1 +/* This covers node 0 only. */ +#define HIGH_ROMSTAGE_STACK_SIZE (0x48000 - BSP_STACK_BASE_ADDR) +#else +/* This covers total of 8 nodes. */ +#define HIGH_ROMSTAGE_STACK_SIZE (0xA0000 - BSP_STACK_BASE_ADDR) +#endif + #endif

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New patch to review for coreboot: AGESA: Use common romstage ram stack
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15466 -gerrit commit 23e293f2ea14dea275097dde7bf225aecb2e03d9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 16:15:02 2016 +0300 AGESA: Use common romstage ram stack Change-Id: Ie120360fa79aa0f6f6d82606838404bb0b0d9681 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/acpi_s3.c | 3 +++ src/cpu/amd/agesa/Kconfig | 4 ++++ src/cpu/amd/agesa/s3_resume.c | 3 ++- src/cpu/amd/agesa/s3_resume.h | 4 ++++ src/lib/Makefile.inc | 1 + src/northbridge/amd/agesa/oem_s3.c | 3 --- 6 files changed, 14 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 7855a2f..bb52313 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -19,6 +19,7 @@ #include <cbmem.h> #include <cpu/cpu.h> #include <timestamp.h> +#include <program_loading.h> #include <romstage_handoff.h> #include <rules.h> @@ -100,6 +101,8 @@ void acpi_prepare_resume_backup(void) * it being there during reboot time. We don't need the pointer, nor * the result right now. If it fails, ACPI resume will be disabled. */ + if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) + romstage_ram_stack_maybe_low(0); if (HIGH_MEMORY_SAVE) cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index ae5e854..e41b2c9 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -69,6 +69,10 @@ config S3_DATA_SIZE int default 32768 +config ROMSTAGE_RAM_STACK_SIZE + hex "Size of the romstage RAM stack in bytes" + default 0x18000 + endif # CPU_AMD_AGESA source src/cpu/amd/agesa/family10/Kconfig diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 54e41c1..f74374a 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -21,13 +21,14 @@ #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> #include <cbmem.h> +#include <program_loading.h> #include <string.h> #include <halt.h> #include "s3_resume.h" static void move_stack_high_mem(void) { - void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK); + void *high_stack = (void*)romstage_ram_stack_maybe_low(0); if (high_stack == NULL) halt(); diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index ff23966..f47c8ba 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -38,4 +38,8 @@ void ResumeHeap(void **heap, size_t *len); #define HIGH_MEMORY_SCRATCH 0x30000 +#if (CONFIG_ROMSTAGE_RAM_STACK_SIZE < HIGH_ROMSTAGE_STACK_SIZE) +#error +#endif + #endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 0c34b75..9012321 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -79,6 +79,7 @@ ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c romstage-y += romstage_stack.c +ramstage-y += romstage_stack.c romstage-y += stack.c ramstage-y += rtc.c diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index 8cce0e7..da78c31 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -119,9 +119,6 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) u32 MTRRStorageSize = 0; uintptr_t pos, size; - if (HIGH_ROMSTAGE_STACK_SIZE) - cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE); - /* To be consumed in AmdInitResume. */ get_s3nv_data(S3DataTypeNonVolatile, &pos, &size); if (size && dataBlock->NvStorageSize)

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New patch to review for coreboot: AMD k8 fam10: Refactor S3 recovery
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15465 -gerrit commit d12f2e6f8fa5358c1b984d661ebe1fe893916747 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 28 07:38:03 2016 +0300 AMD k8 fam10: Refactor S3 recovery Change-Id: I09c218ca05391e8d80880be0aa5bdfd5079acf85 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 36 ++++++++++++++++-------------------- 1 file changed, 16 insertions(+), 20 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 1880ccb..15b2642 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -63,27 +63,32 @@ static int memcmp_(void *d, const void *s, size_t len) return memcmp(d, s, len); } -static void prepare_romstage_ramstack(void *resume_backup_memory) +static void prepare_romstage_ramstack(int s3resume) { size_t backup_top = backup_size(); print_car_debug("Prepare CAR migration and stack regions..."); - if (resume_backup_memory) { - memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, - (void *)(CONFIG_RAMTOP - backup_top), backup_top); + if (s3resume) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (resume_backup_memory) + memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, + (void *)(CONFIG_RAMTOP - backup_top), backup_top); } memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top); print_car_debug(" Done\n"); } -static void prepare_ramstage_region(void *resume_backup_memory) +static void prepare_ramstage_region(int s3resume) { size_t backup_top = backup_size(); print_car_debug("Prepare ramstage memory region..."); - if (resume_backup_memory) { - memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, HIGH_MEMORY_SAVE - backup_top); + if (s3resume) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (resume_backup_memory) + memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, + HIGH_MEMORY_SAVE - backup_top); memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE - backup_top); } else { memset_((void*)0, 0, CONFIG_RAMTOP - backup_top); @@ -115,7 +120,6 @@ static void vErrata343(void) void post_cache_as_ram(void) { - void *resume_backup_memory = NULL; uint32_t family = amd_fam1x_cpu_family(); /* Verify that the BSP didn't overrun the lower stack @@ -134,11 +138,10 @@ void post_cache_as_ram(void) printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); int s3resume = acpi_is_wakeup_s3(); - if (s3resume) { + if (s3resume) cbmem_recovery(s3resume); - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - } - prepare_romstage_ramstack(resume_backup_memory); + + prepare_romstage_ramstack(s3resume); /* from here don't store more data in CAR */ if (family >= 0x1f && family <= 0x3f) { @@ -168,9 +171,6 @@ void post_cache_as_ram(void) void cache_as_ram_new_stack (void) { - void *resume_backup_memory = NULL; - - print_car_debug("Top about %08x ... Done\n", (uint32_t) &resume_backup_memory); print_car_debug("Disabling cache as ram now\n"); disable_cache_as_ram_bsp(); @@ -179,11 +179,7 @@ void cache_as_ram_new_stack (void) set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - if (acpi_is_wakeup_s3()) { - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - print_car_debug("Resume backup memory location: %p\n", resume_backup_memory); - } - prepare_ramstage_region(resume_backup_memory); + prepare_ramstage_region(acpi_is_wakeup_s3()); set_sysinfo_in_ram(1); // So other core0 could start to train mem

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Patch set updated for coreboot: intel/sandybridge: Use common ACPI S3 recovery
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15248 -gerrit commit 5b4541bbf19eb098babd6b5680c4a0badb883029 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 17 22:54:22 2016 +0300 intel/sandybridge: Use common ACPI S3 recovery There is some 20ms delay with ACPI S3 wakeup time due to MTRR setup being done after the backup copy. Change-Id: Ib72ff914f5dfef8611f5f6cf9687495779013b02 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_206ax/cache_as_ram.inc | 21 --------------------- src/northbridge/intel/sandybridge/early_init.c | 10 ++-------- src/northbridge/intel/sandybridge/sandybridge.h | 6 ------ 3 files changed, 2 insertions(+), 35 deletions(-) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index a1f5cc9..e31d42a 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -281,27 +281,6 @@ before_romstage: /* Invalidate the cache again. */ invd - post_code(0x3c) - -#if CONFIG_HAVE_ACPI_RESUME - movl CBMEM_BOOT_MODE, %eax - cmpl $0x2, %eax // Resume? - jne __acpi_resume_backup_done - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high - * tables memory completely, but that's a wonderful clean up task for - * another day. - */ - cld - movl $CONFIG_RAMBASE, %esi - movl CBMEM_RESUME_BACKUP, %edi - movl $HIGH_MEMORY_SAVE >> 2, %ecx - rep movsl - -__acpi_resume_backup_done: -#endif - post_code(0x3d) __main: diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 779f29b..a013ec3 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -233,15 +233,9 @@ void northbridge_romstage_finalize(int s3resume) * this is not a resume. In that case we just create the cbmem toc. */ - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = 2; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } + acpi_prepare_for_resume(); + /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); } else { diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 7b0efd1..af5bd48 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -196,12 +196,6 @@ #define DMIDRCCFG 0xeb4 /* 32bit */ -/* Delegation of resume backup memory so we don't have to - * (slowly) handle backing up OS memory in romstage.c - */ -#define CBMEM_BOOT_MODE 0x610 -#define CBMEM_RESUME_BACKUP 0x614 - #ifndef __ASSEMBLER__ static inline void barrier(void) { asm("" ::: "memory"); }

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Patch set updated for coreboot: intel post-car: Consolidate choose_top_of_stack()
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15463 -gerrit commit da85ad95f13f3a15dcc2c9a2cce35be85a72b2d6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 14:50:27 2016 +0300 intel post-car: Consolidate choose_top_of_stack() Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/Kconfig | 4 +++ src/cpu/intel/haswell/romstage.c | 16 +---------- src/drivers/intel/fsp1_1/Kconfig | 4 --- src/drivers/intel/fsp1_1/stack.c | 20 ++------------ src/include/program_loading.h | 5 ++++ src/lib/Makefile.inc | 1 + src/lib/romstage_stack.c | 44 ++++++++++++++++++++++++++++++ src/soc/intel/baytrail/romstage/romstage.c | 16 +---------- src/soc/intel/broadwell/romstage/stack.c | 17 ++---------- 9 files changed, 60 insertions(+), 67 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index a026b28..37d6513 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -25,6 +25,10 @@ config DCACHE_BSP_STACK_SLUSH config DCACHE_AP_STACK_SIZE hex +config ROMSTAGE_RAM_STACK_SIZE + hex "Size of the romstage RAM stack in bytes" + default 0x5000 + config SMP bool default y if MAX_CPUS != 1 diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index cde9441..8354aeb 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -65,20 +65,6 @@ static inline u32 *stack_push(u32 *stack, u32 value) return stack; } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - ROMSTAGE_RAM_STACK_SIZE); - stack_top += ROMSTAGE_RAM_STACK_SIZE; - return stack_top; -} - /* setup_romstage_stack_after_car() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ static void *setup_romstage_stack_after_car(void) @@ -90,7 +76,7 @@ static void *setup_romstage_stack_after_car(void) u32 top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; + top_of_stack = romstage_ram_stack() & ~3; slot = (void *)top_of_stack; num_mtrrs = 0; diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 86f6c7b..59b4797 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -99,10 +99,6 @@ config GOP_SUPPORT bool "Enable GOP support" default n -config ROMSTAGE_RAM_STACK_SIZE - hex "Size of the romstage RAM stack in bytes" - default 0x5000 - config USE_GENERIC_FSP_CAR_INC bool default n diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index 65ba235..b0e4992 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -21,23 +21,7 @@ #include <fsp/romstage.h> #include <fsp/stack.h> #include <stdlib.h> - -const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE; - -/* - * Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. - */ -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; -} +#include <program_loading.h> /* * setup_stack_and_mtrrs() determines the stack to use after @@ -57,7 +41,7 @@ void *setup_stack_and_mtrrs(void) soc_display_mtrrs(); /* Top of stack needs to be aligned to a 8-byte boundary. */ - top_of_stack = choose_top_of_stack(); + top_of_stack = romstage_ram_stack(); slot = (void *)top_of_stack; num_mtrrs = 0; max_mtrrs = soc_get_variable_mtrr_count(NULL); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 42addb8..929d60c 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -170,6 +170,11 @@ void run_ramstage(void); /* Called when the stage cache couldn't load ramstage on resume. */ void ramstage_cache_invalid(void); +/* Determine where stack for ramstage loader is located. */ +unsigned long romstage_ram_stack_maybe_low(int no_cbmem); +unsigned long romstage_ram_stack(void); +extern const unsigned long romstage_ram_stack_size; + /*********************** * PAYLOAD LOADING * ***********************/ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1028917..0c34b75 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -78,6 +78,7 @@ romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c +romstage-y += romstage_stack.c romstage-y += stack.c ramstage-y += rtc.c diff --git a/src/lib/romstage_stack.c b/src/lib/romstage_stack.c new file mode 100644 index 0000000..319d354 --- /dev/null +++ b/src/lib/romstage_stack.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <program_loading.h> +#include <cbmem.h> + +const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE; + +/* + * Romstage needs quite a bit of stack for decompressing images since the lzma + * lib keeps its state on the stack during romstage. + */ +unsigned long romstage_ram_stack_maybe_low(int no_cbmem) +{ + unsigned long stack_top; + + if (no_cbmem) + return CONFIG_RAMTOP; + + /* cbmem_add() does a find() before add(). */ + stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, + romstage_ram_stack_size); + stack_top += romstage_ram_stack_size; + return stack_top; +} + +unsigned long romstage_ram_stack(void) +{ + int no_cbmem = IS_ENABLED(CONFIG_LATE_CBMEM_INIT); + return romstage_ram_stack_maybe_low(no_cbmem); +} diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index a167c90..6cf13bc 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -258,20 +258,6 @@ static inline uint32_t *stack_push(u32 *stack, u32 value) return stack; } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - const unsigned long romstage_ram_stack_size = 0x5000; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; -} - /* setup_stack_and_mttrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ static void *setup_stack_and_mttrs(void) @@ -283,7 +269,7 @@ static void *setup_stack_and_mttrs(void) uint32_t top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; + top_of_stack = romstage_ram_stack() & ~3; slot = (void *)top_of_stack; num_mtrrs = 0; diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c index 6c602a8..87f56ad 100644 --- a/src/soc/intel/broadwell/romstage/stack.c +++ b/src/soc/intel/broadwell/romstage/stack.c @@ -21,6 +21,7 @@ #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <soc/romstage.h> +#include <program_loading.h> static inline uint32_t *stack_push(u32 *stack, u32 value) { @@ -29,20 +30,6 @@ static inline uint32_t *stack_push(u32 *stack, u32 value) return stack; } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - const unsigned long romstage_ram_stack_size = 0x5000; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; -} - /* setup_stack_and_mttrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mttrs(void) @@ -54,7 +41,7 @@ void *setup_stack_and_mttrs(void) uint32_t top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; + top_of_stack = romstage_ram_stack() & ~3; slot = (void *)top_of_stack; num_mtrrs = 0;

1 0

Patch set updated for coreboot: ACPI S3: Remove HIGH_MEMORY_SAVE where possible
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15255 -gerrit commit a8bf8d583feb801724edfa9dcdc33ba9493e38d9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 28 07:38:46 2016 +0300 ACPI S3: Remove HIGH_MEMORY_SAVE where possible Use actual requirement of ramstage size for S3 resume backup in CBMEM, unless ACPI_HUGE_LOWMEM_BACKUP is selected. Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 4 + src/arch/x86/acpi_s3.c | 126 +++++++++++++++++++++++++----- src/arch/x86/include/arch/acpi.h | 8 +- src/cpu/amd/car/post_cache_as_ram.c | 7 +- src/cpu/amd/family_10h-family_15h/Kconfig | 1 + src/cpu/amd/model_fxx/Kconfig | 1 + src/include/cbfs.h | 3 + src/include/program_loading.h | 4 + src/lib/cbfs.c | 12 +++ src/lib/prog_loaders.c | 14 +++- 10 files changed, 151 insertions(+), 29 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7043851..b4c3cbe 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -516,6 +516,10 @@ config HAVE_ACPI_RESUME bool default n +config ACPI_HUGE_LOWMEM_BACKUP + bool + default n + config RESUME_PATH_SAME_AS_BOOT bool default y if ARCH_X86 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index bb52313..9d56c82 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -80,32 +80,114 @@ void acpi_fail_wakeup(void) } #endif /* ENV_RAMSTAGE */ -void acpi_prepare_for_resume(void) + +struct resume_backup { + u32 magic; + u32 base; + u32 size; + u8 buf[0]; +}; + +#define RESUME_BACKUP_MAGIC 0xCAFEBABE + +void backup_ramstage_section(u32 base, u32 size) { - if (!HIGH_MEMORY_SAVE) + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem == NULL) + return; + + if (backup_mem->magic == RESUME_BACKUP_MAGIC) return; + size = ALIGN_UP(size, 4); + if (!size) { + base = backup_mem->base; + size = backup_mem->size; + } + + if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { + base = CONFIG_RAMBASE; + size = HIGH_MEMORY_SAVE; + } + + /* FIXME: Sanity check CBMEM. */ + /* Back up the OS-controlled memory where ramstage will be loaded. */ - void *src = (void *)CONFIG_RAMBASE; - void *dest = cbmem_find(CBMEM_ID_RESUME); - if (dest != NULL) - memcpy(dest, src, HIGH_MEMORY_SAVE); + memcpy(&backup_mem->buf, (void*)base, size); + backup_mem->base = base; + backup_mem->size = size; + backup_mem->magic = RESUME_BACKUP_MAGIC; } +/* Make backup of low-memory region, relying on the base and size + * of the ramstage that was loaded before entry to ACPI S3. + * + * DEPRECATED + */ +void acpi_prepare_for_resume(void) +{ + backup_ramstage_section(0, 0); +} + +void *acpi_backup_container(void) +{ + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem == NULL) + return NULL; + + backup_mem->magic = 0; + return (void*)&backup_mem->buf; +} + +void acpi_backup_validate(u32 base, u32 size) +{ + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem == NULL) + return; + + backup_mem->base = base; + backup_mem->size = size; + backup_mem->magic = RESUME_BACKUP_MAGIC; +} + +extern unsigned char _program, _eprogram; + void acpi_prepare_resume_backup(void) { + size_t size = (u32)(&_eprogram - &_program); + u32 base = (u32) &_program; + struct resume_backup *backup_mem; + + if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) + return; + if (!acpi_s3_resume_allowed()) return; /* Let's prepare the ACPI S3 Resume area now already, so we can rely on - * it being there during reboot time. We don't need the pointer, nor - * the result right now. If it fails, ACPI resume will be disabled. + * it being there during reboot time. If this fails, ACPI resume will + * be disabled. We assume that ramstage does not change while in suspend, + * so base and size of the currently running ramstage will match the one + * we will load on resume path. */ if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) romstage_ram_stack_maybe_low(0); - if (HIGH_MEMORY_SAVE) - cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); + if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { + base = CONFIG_RAMBASE; + size = HIGH_MEMORY_SAVE; + } + + size = ALIGN_UP(size, 4); + + size_t reserve = ALIGN_UP(sizeof(*backup_mem) + size, 1024); + backup_mem = cbmem_add(CBMEM_ID_RESUME, reserve); + if (backup_mem == NULL) + return; + + backup_mem->magic = 0; + backup_mem->base = base; + backup_mem->size = size; } #define WAKEUP_BASE 0x600 @@ -118,21 +200,24 @@ extern unsigned int __wakeup_size; static void acpi_jump_to_wakeup(void *vector) { - uintptr_t acpi_backup_memory = 0; + struct resume_backup *backup_mem; + u32 source = 0, target = 0, size = 0; if (!acpi_s3_resume_allowed()) { printk(BIOS_WARNING, "ACPI: S3 resume not allowed.\n"); return; } - if (HIGH_MEMORY_SAVE) { - acpi_backup_memory = (uintptr_t)cbmem_find(CBMEM_ID_RESUME); - - if (!acpi_backup_memory) { - printk(BIOS_WARNING, "ACPI: Backup memory missing. " - "No S3 resume.\n"); - return; - } + backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem && backup_mem->magic == RESUME_BACKUP_MAGIC) { + backup_mem->magic = 0; + source = (u32) &backup_mem->buf; + target = backup_mem->base; + size = backup_mem->size; + } else if (!IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { + printk(BIOS_WARNING, "ACPI: Backup memory missing. " + "No S3 resume.\n"); + return; } /* Copy wakeup trampoline in place. */ @@ -140,8 +225,7 @@ static void acpi_jump_to_wakeup(void *vector) timestamp_add_now(TS_ACPI_WAKE_JUMP); - acpi_do_wakeup((uintptr_t)vector, acpi_backup_memory, CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); + acpi_do_wakeup((uintptr_t)vector, source, target, size); } void __attribute__((weak)) mainboard_suspend_resume(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 7434000..6bb1a8c 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -24,12 +24,7 @@ #ifndef __ASM_ACPI_H #define __ASM_ACPI_H -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ - ! IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) #define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) -#else -#define HIGH_MEMORY_SAVE 0 -#endif #ifndef __ASSEMBLER__ #include <stdint.h> @@ -623,6 +618,9 @@ static inline int acpi_s3_resume_allowed(void) return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME); } +void *acpi_backup_container(void); +void acpi_backup_validate(u32 base, u32 size); + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) extern int acpi_slp_type; diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 15b2642..ce1f930 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -69,7 +69,7 @@ static void prepare_romstage_ramstack(int s3resume) print_car_debug("Prepare CAR migration and stack regions..."); if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + void *resume_backup_memory = acpi_backup_container(); if (resume_backup_memory) memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, (void *)(CONFIG_RAMTOP - backup_top), backup_top); @@ -85,7 +85,7 @@ static void prepare_ramstage_region(int s3resume) print_car_debug("Prepare ramstage memory region..."); if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + void *resume_backup_memory = acpi_backup_container(); if (resume_backup_memory) memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, HIGH_MEMORY_SAVE - backup_top); @@ -102,6 +102,9 @@ static void prepare_ramstage_region(int s3resume) #endif print_car_debug(" Done\n"); + + if (s3resume) + acpi_backup_validate(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); } /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index fda7fc8..30c7dee 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -10,6 +10,7 @@ config CPU_AMD_MODEL_10XXX select TSC_SYNC_LFENCE select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER + select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index c8bae33..3eb5b94 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -9,6 +9,7 @@ config CPU_AMD_MODEL_FXX select SSE2 select TSC_SYNC_LFENCE select UDELAY_LAPIC + select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_FXX diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 2d19218..6a9e054 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -43,6 +43,9 @@ void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size); size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, size_t in_size, void *buffer, size_t buffer_size, uint32_t compression); +/* Fill base and size of the memory pstage will occupy when loaded. */ +void cbfs_prog_stage_section(struct prog *pstage, uint32_t *base, uint32_t *size); + /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 929d60c..269f812 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -175,6 +175,10 @@ unsigned long romstage_ram_stack_maybe_low(int no_cbmem); unsigned long romstage_ram_stack(void); extern const unsigned long romstage_ram_stack_size; +/* Backup OS memory to CBMEM_ID_RESUME on ACPI S3 resume path, + * if ramstage overwrites low memory. */ +void backup_ramstage_section(u32 base, u32 size); + /*********************** * PAYLOAD LOADING * ***********************/ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index aa652c2..c00e6aa 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -166,6 +166,18 @@ void *cbfs_boot_load_stage_by_name(const char *name) return prog_entry(&stage); } +void cbfs_prog_stage_section(struct prog *pstage, uint32_t *base, uint32_t *size) +{ + struct cbfs_stage stage; + const struct region_device *fh = prog_rdev(pstage); + + if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) + return; + + *base = stage.load; + *size = stage.memlen; +} + int cbfs_prog_stage_load(struct prog *pstage) { struct cbfs_stage stage; diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ecbc679..d659abe 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -101,6 +101,18 @@ static int load_relocatable_ramstage(struct prog *ramstage) return rmodule_stage_load(&rmod_ram); } +static int load_nonrelocatable_ramstage(struct prog *ramstage) +{ + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + uint32_t base = 0, size = 0; + cbfs_prog_stage_section(ramstage, &base, &size); + if (size) + backup_ramstage_section(base, size); + } + + return cbfs_prog_stage_load(ramstage); +} + void run_ramstage(void) { struct prog ramstage = @@ -126,7 +138,7 @@ void run_ramstage(void) if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { if (load_relocatable_ramstage(&ramstage)) goto fail; - } else if (cbfs_prog_stage_load(&ramstage)) + } else if (load_nonrelocatable_ramstage(&ramstage)) goto fail; stage_cache_add(STAGE_RAMSTAGE, &ramstage);

1 0

New patch to review for coreboot: lib/nhlt: Extend NHLT function library
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15464 -gerrit commit dc55345849936db925696bbb01b9a5ce4fa54ea1 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Jun 28 00:35:14 2016 -0700 lib/nhlt: Extend NHLT function library Add NHLT library function defintions to lib/nhlt.c. This adds nhlt_soc_add_endpoint(), nhlt_soc_serialiaze() and nhlt_soc_serialize_oem_overrides(). These functions are used by NHLT helper functions to add dmic and different audio codecs for an SoC/mainboard. Change-Id: I96b7369eb7ca2ac2edacf3d942a201b92a5363f4 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/lib/nhlt.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index e31803d..348c08e 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -524,3 +524,69 @@ int nhlt_add_codec_on_ssp(struct nhlt *nhlt, int hwlink, return 0; } + +struct nhlt_endpoint *nhlt_soc_add_endpoint(struct nhlt *nhlt, int soc_hwintf, + int soc_devtype, int dir) +{ + int nhlt_link_type; + int nhlt_dev_type; + uint16_t did; + struct nhlt_endpoint *endp; + + nhlt_link_type = nhlt_soc_get_link_type(soc_hwintf, soc_devtype); + + if (nhlt_link_type == -1) + return NULL; + + switch (soc_devtype) { + case AUDIO_DEV_I2S: + nhlt_dev_type = NHLT_SSP_DEV_I2S; + did = NHLT_DID_SSP; + break; + case AUDIO_DEV_DMIC: + nhlt_dev_type = NHLT_PDM_DEV; + did = NHLT_DID_DMIC; + break; + case AUDIO_DEV_BT: + nhlt_dev_type = NHLT_SSP_DEV_BT; + did = NHLT_DID_BT; + break; + default: + return NULL; + } + + endp = nhlt_add_endpoint(nhlt, nhlt_link_type, nhlt_dev_type, dir, + NHLT_VID, did); + + if (endp == NULL) + return NULL; + + /* Virtual bus id of SSP link is the hardware port id. */ + if (nhlt_link_type == NHLT_LINK_SSP) + endp->virtual_bus_id = soc_hwintf; + + return endp; +} + +uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) +{ + return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); +} + +uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, + uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs == NULL) + return acpi_addr; + + /* Update NHLT GNVS Data */ + gnvs->nhla = (uintptr_t)acpi_addr; + gnvs->nhll = nhlt_current_size(nhlt); + + return nhlt_serialize_oem_overrides(nhlt, acpi_addr, oem_id, + oem_table_id); +}

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Patch set updated for coreboot: soc/intel/apollolake: Add NHLT add codec APIs and device/vendor ids
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15311 -gerrit commit ffb230acfb2527dc7ef1fd3b69f02b93dc534baa Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Jun 21 14:22:16 2016 -0700 soc/intel/apollolake: Add NHLT add codec APIs and device/vendor ids nhlt_add_<codec>_on_ssp uses codec configs, tdm configs and add the particular codec on a SSP port specified by mainboard. get_nhlt_link_type() returns a corresponding NHLT link type based on audio soc hardware interface passed as an argument. Also define vendor id for NHLT and device ids for NHLT Bluetooth, DMIC & SSPs. These ids are used to add NHLT endpoints for different audio codecs. These ids are platform dependent. Change-Id: Ic9bd26ebe8d6df60af23733e122fd8f3c0432e1f Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/nhlt.h | 39 +++++++++ src/soc/intel/apollolake/nhlt.c | 130 ++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index a82dacd..556abbb 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -55,6 +55,7 @@ ramstage-y += pmutil.c ramstage-y += pmc.c ramstage-y += smi.c ramstage-y += reset.c +ramstage-y += nhlt.c # DSP firmware settings files. NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs diff --git a/src/soc/intel/apollolake/include/soc/nhlt.h b/src/soc/intel/apollolake/include/soc/nhlt.h new file mode 100644 index 0000000..cc6486b --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/nhlt.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_NHLT_H_ +#define _SOC_APOLLOLAKE_NHLT_H_ + +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + +enum { + AUDIO_LINK_SSP0, + AUDIO_LINK_SSP1, + AUDIO_LINK_SSP2, + AUDIO_LINK_SSP3, + AUDIO_LINK_SSP4, + AUDIO_LINK_SSP5, + AUDIO_LINK_DMIC, +}; + +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels); +int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink); +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink); + +#endif diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c new file mode 100644 index 0000000..87fc65a --- /dev/null +++ b/src/soc/intel/apollolake/nhlt.c @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +static const struct nhlt_format_config dmic_2ch_cfg[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_format_config da7219_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "dialog-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_tdm_config tdm_cfg = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_format_config max98357_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "max98357-render-2ch-48khz-24b.bin", + }, +}; + +int nhlt_soc_get_link_type(int hwlink, int soc_devtype) +{ + int nhlt_link_type; + + switch (hwlink) { + case AUDIO_LINK_SSP0: + case AUDIO_LINK_SSP1: + case AUDIO_LINK_SSP3: + case AUDIO_LINK_SSP4: + case AUDIO_LINK_SSP5: + /* Only I2S devices. */ + if (soc_devtype != AUDIO_DEV_I2S) + return -1; + nhlt_link_type = NHLT_LINK_SSP; + break; + case AUDIO_LINK_SSP2: + /* Only Bluetooth devices on SSP2. */ + if (soc_devtype != AUDIO_DEV_BT) + return -1; + nhlt_link_type = NHLT_LINK_SSP; + break; + case AUDIO_LINK_DMIC: + // Only DMIC devices on DMIC links. + if (soc_devtype != AUDIO_DEV_DMIC) + return -1; + nhlt_link_type = NHLT_LINK_PDM; + break; + default: + return -1; + } + + return nhlt_link_type; +} + +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) +{ + if (num_channels != 2) { + printk(BIOS_ERR, "APL only supports 2CH DMIC array.\n"); + return -1; + } + + if (nhlt_add_dmic_array(nhlt, num_channels, dmic_2ch_cfg, + ARRAY_SIZE(dmic_2ch_cfg))) { + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + return -1; + } + + return 0; +} + +int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink) +{ + if (nhlt_add_codec_on_ssp(nhlt, hwlink, max98357_cfg, + ARRAY_SIZE(max98357_cfg), NULL, 0, NULL, 0)) { + printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n"); + return -1; + } + + return 0; +} + +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink) +{ + if (nhlt_add_codec_on_ssp(nhlt, hwlink, da7219_cfg, + ARRAY_SIZE(da7219_cfg), da7219_cfg, ARRAY_SIZE(da7219_cfg), &tdm_cfg, + sizeof(tdm_cfg))) { + printk(BIOS_ERR, "Couldn't add Dialog_7219 codec.\n"); + return -1; + } + + return 0; +}

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coreboot-gerrit June 2016