coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: tegra124: Actually align the framebuffer's bytes-per-line to 32
by Paul Kocialkowski 28 Jun '16

28 Jun '16

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14816 -gerrit commit 0f8dc2a6e06d76248a85ce89a23d42f16beb4d15 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Sat May 14 15:25:51 2016 +0200 tegra124: Actually align the framebuffer's bytes-per-line to 32 The previous change with that intent aligned the framebuffer's bytes-per-line to 64 instead of 32: commit 8957dd6b52919ed634aa502dfd5b6316a6e6e055 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Sun May 1 18:38:04 2016 +0200 tegra124: Align the framebuffer's bytes-per-line to 32 Change-Id: I88bba2ff355a51d42cab6a869ec1e9c534160b9c Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/soc/nvidia/tegra124/display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 0fc15cb..9ec34d4 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -334,6 +334,6 @@ void display_startup(device_t dev) edid.mode.va = config->yres; edid.mode.ha = config->xres; edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel, 64); + config->framebuffer_bits_per_pixel, 32); set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); }

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Patch set updated for coreboot: tegra124: Build verstage when CHROMEOS is selected
by Paul Kocialkowski 28 Jun '16

28 Jun '16

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15451 -gerrit commit 78ebe17af3be5a41bbe0eeeb4586662daceb2a55 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Jun 27 19:08:59 2016 +0200 tegra124: Build verstage when CHROMEOS is selected This includes the proper Kconfig options (based on the chromium os coreboot configuration) for setting up verstage on tegra124 devices. Change-Id: I4a1976ff684a417cae6fa718ef53cad763cee47d Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/soc/nvidia/tegra124/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 49929ad..227efca 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -18,6 +18,9 @@ if SOC_NVIDIA_TEGRA124 config CHROMEOS select VBOOT_OPROM_MATTERS + select VBOOT_STARTS_IN_BOOTBLOCK + select SEPARATE_VERSTAGE + select CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL config TEGRA124_MODEL_TD570D bool "TD570D"

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Patch set updated for coreboot: nyan: Avoid running early_mainboard_init twice in vboot context
by Paul Kocialkowski 28 Jun '16

28 Jun '16

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15450 -gerrit commit 7d69fe0ed193c1de7dd9923b4aa075cef11e5241 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Jun 27 18:17:14 2016 +0200 nyan: Avoid running early_mainboard_init twice in vboot context A call to early_mainboard_init is already present in verstage, thus it is only necessary to call it from romstage when not in vboot context. Change-Id: I2e0b5a369c5fb24efae4ac40d83a31f5cf4a078d Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/mainboard/google/nyan/romstage.c | 4 +++- src/mainboard/google/nyan_big/romstage.c | 4 +++- src/mainboard/google/nyan_blaze/romstage.c | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index d09bf5e..2388f95 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -82,7 +82,9 @@ static void __attribute__((noinline)) romstage(void) /* FIXME: this may require coordination with moving timestamps */ cbmem_initialize_empty(); - early_mainboard_init(); + /* This was already called from verstage in vboot context. */ + if (!IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)) + early_mainboard_init(); run_ramstage(); } diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index d09bf5e..2388f95 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -82,7 +82,9 @@ static void __attribute__((noinline)) romstage(void) /* FIXME: this may require coordination with moving timestamps */ cbmem_initialize_empty(); - early_mainboard_init(); + /* This was already called from verstage in vboot context. */ + if (!IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)) + early_mainboard_init(); run_ramstage(); } diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 373d43b..e91fa33 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -86,7 +86,9 @@ static void __attribute__((noinline)) romstage(void) /* FIXME: this may require coordination with moving timestamps */ cbmem_initialize_empty(); - early_mainboard_init(); + /* This was already called from verstage in vboot context. */ + if (!IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)) + early_mainboard_init(); run_ramstage(); }

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Patch set updated for coreboot: buildgcc: Never set GMP CFLAGS manually in order to get the right flags
by Paul Kocialkowski 28 Jun '16

28 Jun '16

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15452 -gerrit commit 2c90672c66cc115c846c09f5f8bd9192fd992165 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Fri Jun 17 21:41:00 2016 -0700 buildgcc: Never set GMP CFLAGS manually in order to get the right flags When no CFLAGS are explicitly provided to it, the GMP configure script will figure out the best optimization flags to use on its own. In particular, it will setup the march, mfpu and mtune flags based on hardware detection. However, when CFLAGS are provided, they are used as-is and such detection doesn't happen. When the march, mfpu and mtune flags are not provided (which happens when GMP wasn't built already), not only will related optimizations be disabled, but some code might not build because of missing support. This happens with NEON instructions on ARMv7 hosts. Thus, it is better not to set CFLAGS and leave it up to the GMP configure script to get them right and still reuse those later. Change-Id: I6ffcbac1298523d1b8ddf29a8bca1b00298828a7 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- util/crossgcc/buildgcc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 1e761da..a4d83f0 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -416,8 +416,7 @@ set_hostcflags_from_gmp() { } build_GMP() { - CC="$CC" CFLAGS="$HOSTCFLAGS" \ - ../${GMP_DIR}/configure --disable-shared --enable-fat \ + CC="$CC" ../${GMP_DIR}/configure --disable-shared --enable-fat \ --prefix=$TARGETDIR $OPTIONS \ || touch .failed $MAKE $JOBS || touch .failed

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New patch to review for coreboot: AMD binaryPI: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15471 -gerrit commit 9237e347c6a8249c332fc4aa905c37c5d97979f6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:14:49 2016 +0300 AMD binaryPI: Delay ACPI S3 backup until ramstage loader Change-Id: I482cf93fe5dfab95817c87c32aad33df2e0a6439 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/s3_resume.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index 830d174..b6e1e92 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -287,10 +287,5 @@ void prepare_for_resume(void) printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - acpi_prepare_for_resume(); } #endif

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Patch set updated for coreboot: ACPI S3: Remove HIGH_MEMORY_SAVE where possible
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15255 -gerrit commit a5c2e3efa245f5f5800aac48f1fe8e7ab9b1345a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 28 07:38:46 2016 +0300 ACPI S3: Remove HIGH_MEMORY_SAVE where possible Use actual requirement of ramstage size for S3 resume backup in CBMEM, unless ACPI_HUGE_LOWMEM_BACKUP is selected. Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 4 + src/arch/x86/acpi_s3.c | 126 +++++++++++++++++++++++++----- src/arch/x86/include/arch/acpi.h | 8 +- src/cpu/amd/car/post_cache_as_ram.c | 7 +- src/cpu/amd/family_10h-family_15h/Kconfig | 1 + src/cpu/amd/model_fxx/Kconfig | 1 + src/include/cbfs.h | 3 + src/include/program_loading.h | 4 + src/lib/cbfs.c | 12 +++ src/lib/prog_loaders.c | 14 +++- 10 files changed, 151 insertions(+), 29 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7043851..b4c3cbe 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -516,6 +516,10 @@ config HAVE_ACPI_RESUME bool default n +config ACPI_HUGE_LOWMEM_BACKUP + bool + default n + config RESUME_PATH_SAME_AS_BOOT bool default y if ARCH_X86 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index bb52313..9d56c82 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -80,32 +80,114 @@ void acpi_fail_wakeup(void) } #endif /* ENV_RAMSTAGE */ -void acpi_prepare_for_resume(void) + +struct resume_backup { + u32 magic; + u32 base; + u32 size; + u8 buf[0]; +}; + +#define RESUME_BACKUP_MAGIC 0xCAFEBABE + +void backup_ramstage_section(u32 base, u32 size) { - if (!HIGH_MEMORY_SAVE) + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem == NULL) + return; + + if (backup_mem->magic == RESUME_BACKUP_MAGIC) return; + size = ALIGN_UP(size, 4); + if (!size) { + base = backup_mem->base; + size = backup_mem->size; + } + + if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { + base = CONFIG_RAMBASE; + size = HIGH_MEMORY_SAVE; + } + + /* FIXME: Sanity check CBMEM. */ + /* Back up the OS-controlled memory where ramstage will be loaded. */ - void *src = (void *)CONFIG_RAMBASE; - void *dest = cbmem_find(CBMEM_ID_RESUME); - if (dest != NULL) - memcpy(dest, src, HIGH_MEMORY_SAVE); + memcpy(&backup_mem->buf, (void*)base, size); + backup_mem->base = base; + backup_mem->size = size; + backup_mem->magic = RESUME_BACKUP_MAGIC; } +/* Make backup of low-memory region, relying on the base and size + * of the ramstage that was loaded before entry to ACPI S3. + * + * DEPRECATED + */ +void acpi_prepare_for_resume(void) +{ + backup_ramstage_section(0, 0); +} + +void *acpi_backup_container(void) +{ + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem == NULL) + return NULL; + + backup_mem->magic = 0; + return (void*)&backup_mem->buf; +} + +void acpi_backup_validate(u32 base, u32 size) +{ + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem == NULL) + return; + + backup_mem->base = base; + backup_mem->size = size; + backup_mem->magic = RESUME_BACKUP_MAGIC; +} + +extern unsigned char _program, _eprogram; + void acpi_prepare_resume_backup(void) { + size_t size = (u32)(&_eprogram - &_program); + u32 base = (u32) &_program; + struct resume_backup *backup_mem; + + if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) + return; + if (!acpi_s3_resume_allowed()) return; /* Let's prepare the ACPI S3 Resume area now already, so we can rely on - * it being there during reboot time. We don't need the pointer, nor - * the result right now. If it fails, ACPI resume will be disabled. + * it being there during reboot time. If this fails, ACPI resume will + * be disabled. We assume that ramstage does not change while in suspend, + * so base and size of the currently running ramstage will match the one + * we will load on resume path. */ if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) romstage_ram_stack_maybe_low(0); - if (HIGH_MEMORY_SAVE) - cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); + if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { + base = CONFIG_RAMBASE; + size = HIGH_MEMORY_SAVE; + } + + size = ALIGN_UP(size, 4); + + size_t reserve = ALIGN_UP(sizeof(*backup_mem) + size, 1024); + backup_mem = cbmem_add(CBMEM_ID_RESUME, reserve); + if (backup_mem == NULL) + return; + + backup_mem->magic = 0; + backup_mem->base = base; + backup_mem->size = size; } #define WAKEUP_BASE 0x600 @@ -118,21 +200,24 @@ extern unsigned int __wakeup_size; static void acpi_jump_to_wakeup(void *vector) { - uintptr_t acpi_backup_memory = 0; + struct resume_backup *backup_mem; + u32 source = 0, target = 0, size = 0; if (!acpi_s3_resume_allowed()) { printk(BIOS_WARNING, "ACPI: S3 resume not allowed.\n"); return; } - if (HIGH_MEMORY_SAVE) { - acpi_backup_memory = (uintptr_t)cbmem_find(CBMEM_ID_RESUME); - - if (!acpi_backup_memory) { - printk(BIOS_WARNING, "ACPI: Backup memory missing. " - "No S3 resume.\n"); - return; - } + backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem && backup_mem->magic == RESUME_BACKUP_MAGIC) { + backup_mem->magic = 0; + source = (u32) &backup_mem->buf; + target = backup_mem->base; + size = backup_mem->size; + } else if (!IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { + printk(BIOS_WARNING, "ACPI: Backup memory missing. " + "No S3 resume.\n"); + return; } /* Copy wakeup trampoline in place. */ @@ -140,8 +225,7 @@ static void acpi_jump_to_wakeup(void *vector) timestamp_add_now(TS_ACPI_WAKE_JUMP); - acpi_do_wakeup((uintptr_t)vector, acpi_backup_memory, CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); + acpi_do_wakeup((uintptr_t)vector, source, target, size); } void __attribute__((weak)) mainboard_suspend_resume(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 7434000..6bb1a8c 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -24,12 +24,7 @@ #ifndef __ASM_ACPI_H #define __ASM_ACPI_H -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ - ! IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) #define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) -#else -#define HIGH_MEMORY_SAVE 0 -#endif #ifndef __ASSEMBLER__ #include <stdint.h> @@ -623,6 +618,9 @@ static inline int acpi_s3_resume_allowed(void) return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME); } +void *acpi_backup_container(void); +void acpi_backup_validate(u32 base, u32 size); + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) extern int acpi_slp_type; diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 15b2642..ce1f930 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -69,7 +69,7 @@ static void prepare_romstage_ramstack(int s3resume) print_car_debug("Prepare CAR migration and stack regions..."); if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + void *resume_backup_memory = acpi_backup_container(); if (resume_backup_memory) memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, (void *)(CONFIG_RAMTOP - backup_top), backup_top); @@ -85,7 +85,7 @@ static void prepare_ramstage_region(int s3resume) print_car_debug("Prepare ramstage memory region..."); if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + void *resume_backup_memory = acpi_backup_container(); if (resume_backup_memory) memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, HIGH_MEMORY_SAVE - backup_top); @@ -102,6 +102,9 @@ static void prepare_ramstage_region(int s3resume) #endif print_car_debug(" Done\n"); + + if (s3resume) + acpi_backup_validate(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); } /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index fda7fc8..30c7dee 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -10,6 +10,7 @@ config CPU_AMD_MODEL_10XXX select TSC_SYNC_LFENCE select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER + select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index c8bae33..3eb5b94 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -9,6 +9,7 @@ config CPU_AMD_MODEL_FXX select SSE2 select TSC_SYNC_LFENCE select UDELAY_LAPIC + select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_FXX diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 2d19218..6a9e054 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -43,6 +43,9 @@ void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size); size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, size_t in_size, void *buffer, size_t buffer_size, uint32_t compression); +/* Fill base and size of the memory pstage will occupy when loaded. */ +void cbfs_prog_stage_section(struct prog *pstage, uint32_t *base, uint32_t *size); + /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 929d60c..269f812 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -175,6 +175,10 @@ unsigned long romstage_ram_stack_maybe_low(int no_cbmem); unsigned long romstage_ram_stack(void); extern const unsigned long romstage_ram_stack_size; +/* Backup OS memory to CBMEM_ID_RESUME on ACPI S3 resume path, + * if ramstage overwrites low memory. */ +void backup_ramstage_section(u32 base, u32 size); + /*********************** * PAYLOAD LOADING * ***********************/ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index aa652c2..c00e6aa 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -166,6 +166,18 @@ void *cbfs_boot_load_stage_by_name(const char *name) return prog_entry(&stage); } +void cbfs_prog_stage_section(struct prog *pstage, uint32_t *base, uint32_t *size) +{ + struct cbfs_stage stage; + const struct region_device *fh = prog_rdev(pstage); + + if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) + return; + + *base = stage.load; + *size = stage.memlen; +} + int cbfs_prog_stage_load(struct prog *pstage) { struct cbfs_stage stage; diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ecbc679..d659abe 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -101,6 +101,18 @@ static int load_relocatable_ramstage(struct prog *ramstage) return rmodule_stage_load(&rmod_ram); } +static int load_nonrelocatable_ramstage(struct prog *ramstage) +{ + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + uint32_t base = 0, size = 0; + cbfs_prog_stage_section(ramstage, &base, &size); + if (size) + backup_ramstage_section(base, size); + } + + return cbfs_prog_stage_load(ramstage); +} + void run_ramstage(void) { struct prog ramstage = @@ -126,7 +138,7 @@ void run_ramstage(void) if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { if (load_relocatable_ramstage(&ramstage)) goto fail; - } else if (cbfs_prog_stage_load(&ramstage)) + } else if (load_nonrelocatable_ramstage(&ramstage)) goto fail; stage_cache_add(STAGE_RAMSTAGE, &ramstage);

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Patch set updated for coreboot: AGESA: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15470 -gerrit commit 7b5e537e7139a6d9b66b0dfea7f23c910dd28fac Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:14:39 2016 +0300 AGESA: Delay ACPI S3 backup until ramstage loader Change-Id: I59773161f22c1ec6a52050245f9ad3e6cc74a934 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index f74374a..9a8899e 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -90,9 +90,4 @@ void prepare_for_resume(void) printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - acpi_prepare_for_resume(); }

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Patch set updated for coreboot: intel post-car: Separate romstage ramstack (WIP)
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15468 -gerrit commit 608fa5fa416ff590645fb7632f3a8db6d0a86fdc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 13:24:11 2016 +0300 intel post-car: Separate romstage ramstack (WIP) TODO: Need to fix MTRRs before placing stack high. Change-Id: I221e207bcd0031048876f29100a1770a444d435b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/romstage.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index c6df446..18c453c 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -1,7 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include <cpu/intel/romstage.h> +#include <program_loading.h> void * asmlinkage romstage_main(unsigned long bist) { mainboard_romstage_entry(bist); - return (void*)CONFIG_RAMTOP; + return (void*)romstage_ram_stack(); }

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Patch set updated for coreboot: intel post-car: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15469 -gerrit commit c6256c69cb6f5ba982cd14c51175223b9f574824 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:13:48 2016 +0300 intel post-car: Delay ACPI S3 backup until ramstage loader Change-Id: If0060b9ad8703a3d6524004fb69cb2171f8d89a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/t400/romstage.c | 1 - src/mainboard/lenovo/x200/romstage.c | 1 - src/mainboard/lenovo/x201/romstage.c | 1 - src/mainboard/packardbell/ms2290/romstage.c | 1 - src/mainboard/roda/rk9/romstage.c | 1 - src/northbridge/intel/i945/early_init.c | 1 - src/northbridge/intel/sandybridge/early_init.c | 1 - 7 files changed, 7 deletions(-) diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index f518775..0e7309d 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -179,7 +179,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 1deab65..db1d62f 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -179,7 +179,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 2bfa19c..7b8d7f9 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -282,7 +282,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 92ee021..04c9513 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -272,7 +272,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index fc0c8d3..e8bd1e2 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -192,7 +192,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index ade120f..3164f25 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -900,7 +900,6 @@ static void i945_prepare_resume(int s3resume) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_was_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index a013ec3..86d1c00 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -234,7 +234,6 @@ void northbridge_romstage_finalize(int s3resume) */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);

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New patch to review for coreboot: AGESA: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15470 -gerrit commit e0191fdd5cff7b5b04d5195954d7f77b58f0b6e1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:14:39 2016 +0300 AGESA: Delay ACPI S3 backup until ramstage loader Change-Id: I59773161f22c1ec6a52050245f9ad3e6cc74a934 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index f74374a..9a8899e 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -90,9 +90,4 @@ void prepare_for_resume(void) printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - acpi_prepare_for_resume(); }

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coreboot-gerrit June 2016