coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

1 participants
1491 discussions

New patch to review for coreboot: vendorcode/siemens: Add extended info block support to hwilib
by Werner Zeh 28 Jun '16

28 Jun '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15478 -gerrit commit 3dfe877506a19a2809f1a8f933adfa0a61385220 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Jun 28 14:31:30 2016 +0200 vendorcode/siemens: Add extended info block support to hwilib Add support for a fourth info block type to hwilib. This block provides new values and is now variable in length. Change-Id: Ia928b4a98b806ba3e80fb576b78f60bb8f2ea3fc Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/vendorcode/siemens/hwilib/hwilib.c | 228 ++++++++++++++++++++++++++++++++- src/vendorcode/siemens/hwilib/hwilib.h | 74 ++++++++++- 2 files changed, 293 insertions(+), 9 deletions(-) diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index 5d47881..6f7f831 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -21,13 +21,15 @@ #include "hwilib.h" -#define MAX_BLOCK_NUM 3 +#define MAX_BLOCK_NUM 4 #define LEN_HIB 0x1fd #define LEN_SIB 0x121 #define LEN_EIB 0x0b5 +#define LEN_XIB 0x200 #define NEXT_OFFSET_HIB 0x1dc #define NEXT_OFFSET_SIB 0x104 #define NEXT_OFFSET_EIB 0x0b0 +#define NEXT_OFFSET_XIB 0x014 #define LEN_UNIQUEL_NUM 0x010 #define LEN_HW_REV 0x002 #define LEN_MAC_ADDRESS 0x006 @@ -43,6 +45,7 @@ enum { BLK_HIB, BLK_SIB, BLK_EIB, + BLK_XIB }; /* This structure holds a valid position for a given field @@ -71,6 +74,12 @@ struct param_info { */ static uint8_t *all_blocks[MAX_BLOCK_NUM] CAR_GLOBAL; +/* As the length of extended block is variable, save all length to a global + * variable so that they can be used later to check boundaries. + */ +static uint16_t all_blk_size[MAX_BLOCK_NUM] CAR_GLOBAL; + + static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst, uint32_t maxlen); @@ -89,6 +98,9 @@ static const struct param_info params[] = { [EIB_VerID] = { .pos[0] = {.blk_type = BLK_EIB, .offset = 0x8, .len = 4}, .get_field = hwilib_read_bytes }, + [XIB_VerID] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x8, .len = 4}, + .get_field = hwilib_read_bytes }, [HIB_HwRev] = { .pos[0] = {.blk_type = BLK_HIB, .offset = 0xbe, .len = 2}, .get_field = hwilib_read_bytes }, @@ -151,6 +163,9 @@ static const struct param_info params[] = { [MacMapping4] = { .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1d8, .len = 4}, .get_field = hwilib_read_bytes }, + [RTCType] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1e8, .len = 1}, + .get_field = hwilib_read_bytes }, [PF_Color_Depth] = { .pos[0] = {.blk_type = BLK_SIB, .offset = 0xea, .len = 1}, .mask = 0x03, @@ -168,6 +183,196 @@ static const struct param_info params[] = { [VddRef] = { .pos[0] = {.blk_type = BLK_EIB, .offset = 0x90, .len = 2}, .get_field = hwilib_read_bytes }, + [XMac1] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0xfc, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac1Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x102, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac2] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x114, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac2Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x11a, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac3] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x12c, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac3Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x132, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac4] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x144, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac4Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x14a, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac5] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x15c, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac5Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x162, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac6] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x174, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac6Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x17a, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac7] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x18c, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac7Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x192, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac8] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1a4, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac8Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1aa, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac9] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1bc, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac9Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1c2, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac10] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1d4, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac10Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1da, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac1Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0xec, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac2Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x104, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac3Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x11c, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac4Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x134, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac5Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x14c, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac6Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x164, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac7Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x17c, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac8Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x194, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac9Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1ac, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac10Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1c4, .len = 16}, + .get_field = hwilib_read_bytes }, + [netKind1] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x103, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind2] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x11b, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind3] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x133, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind4] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x14b, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind5] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x163, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind6] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x17b, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind7] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x193, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind8] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1ab, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind9] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1c3, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind10] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1db, .len = 1}, + .get_field = hwilib_read_bytes }, + [T_Warn] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x18, .len = 4}, + .get_field = hwilib_read_bytes }, + [T_Crit] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1c, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANSamplingTime] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x20, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANSetPoint] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x24, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANKp] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x28, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANKi] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x2c, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANKd] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x30, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANHystVal] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x34, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANHystThreshold] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x38, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANHystCtrl] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x3c, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANMaxSpeed] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x40, .len = 2}, + .get_field = hwilib_read_bytes }, + [FANStartpeed] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x42, .len = 2}, + .get_field = hwilib_read_bytes }, + [FANSensorDelay] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x44, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANSensorNum] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x48, .len = 1}, + .get_field = hwilib_read_bytes }, + [FANSensorSelect] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x49, .len = 1}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg0] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x4c, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg1] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x60, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg2] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x74, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg3] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x88, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg4] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x9c, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg5] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0xb0, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg6] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0xc4, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg7] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0xd8, .len = 20}, + .get_field = hwilib_read_bytes }, + }; /** \brief This functions reads the given field from the first valid hwinfo @@ -181,8 +386,7 @@ static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst, { uint8_t i = 0, *blk = NULL; uint8_t **blk_ptr = car_get_var_ptr(&all_blocks[0]); - static const uint16_t all_blk_size[MAX_BLOCK_NUM] = - {LEN_HIB, LEN_SIB, LEN_EIB}; + uint16_t *all_blk_size_ptr = car_get_var_ptr(&all_blk_size[0]); if (!param || !dst) return 0; @@ -200,7 +404,7 @@ static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst, */ if ((!blk) || (param->pos[i].len > maxlen) || (param->pos[i].len + param->pos[i].offset > - all_blk_size[param->pos[i].blk_type])) + all_blk_size_ptr[param->pos[i].blk_type])) return 0; /* We can now copy the wanted data. */ memcpy(dst, (blk + param->pos[i].offset), param->pos[i].len); @@ -248,6 +452,7 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename) uint8_t *ptr = NULL, *base = NULL; uint32_t next_offset = 1; uint8_t **blk_ptr = car_get_var_ptr(&all_blocks[0]); + uint16_t *all_blk_size_ptr = car_get_var_ptr(&all_blk_size[0]); size_t filesize = 0; /* Check for a valid parameter */ @@ -271,6 +476,12 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename) memset(blk_ptr, 0, (MAX_BLOCK_NUM * sizeof (uint8_t *))); /* Check which blocks are available by examining the length field. */ base = ptr; + /* Fill in sizes of all fixed length blocks. */ + all_blk_size_ptr[BLK_HIB] = LEN_HIB; + all_blk_size_ptr[BLK_SIB] = LEN_SIB; + all_blk_size_ptr[BLK_EIB] = LEN_EIB; + /* Length of BLK_XIB is variable and will be filled if block is found */ + all_blk_size_ptr[BLK_XIB] = 0; while(!(strncmp((char *)ptr, BLOCK_MAGIC, LEN_MAGIC_NUM)) && next_offset) { uint16_t len = read16(ptr + LEN_OFFSET); @@ -294,12 +505,19 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename) next_offset = read32(ptr + NEXT_OFFSET_EIB); if (next_offset) ptr = base + next_offset; + } else if (len > LEN_XIB) { + blk_ptr[BLK_XIB] = ptr; + next_offset = read32(ptr + NEXT_OFFSET_XIB); + all_blk_size_ptr[BLK_XIB] = len; + if (next_offset) + ptr = base + next_offset; } else { next_offset = 0; } } /* We should have found at least one valid block */ - if (blk_ptr[BLK_HIB] || blk_ptr[BLK_SIB] || blk_ptr[BLK_EIB]) + if (blk_ptr[BLK_HIB] || blk_ptr[BLK_SIB] || blk_ptr[BLK_EIB] || + blk_ptr[BLK_XIB]) return CB_SUCCESS; else return CB_ERR; diff --git a/src/vendorcode/siemens/hwilib/hwilib.h b/src/vendorcode/siemens/hwilib/hwilib.h index c66a99c..d858091 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.h +++ b/src/vendorcode/siemens/hwilib/hwilib.h @@ -24,16 +24,17 @@ typedef enum { HIB_VerID = 0, SIB_VerID, EIB_VerID, + XIB_VerID, HIB_HwRev, SIB_HwRev, UniqueNum, Mac1, - Mac1Aux, Mac2, - Mac2Aux, Mac3, - Mac3Aux, Mac4, + Mac1Aux, + Mac2Aux, + Mac3Aux, Mac4Aux, SPD, FF_FreezeDis, @@ -43,11 +44,76 @@ typedef enum { MacMapping2, MacMapping3, MacMapping4, + RTCType, PF_Color_Depth, PF_DisplType, PF_DisplCon, Edid, - VddRef + VddRef, + T_Warn, + T_Crit, + FANSamplingTime, + FANSetPoint, + FANKp, + FANKi, + FANKd, + FANHystVal, + FANHystThreshold, + FANHystCtrl, + FANMaxSpeed, + FANStartpeed, + FANSensorDelay, + FANSensorNum, + FANSensorSelect, + FANSensorCfg0, + FANSensorCfg1, + FANSensorCfg2, + FANSensorCfg3, + FANSensorCfg4, + FANSensorCfg5, + FANSensorCfg6, + FANSensorCfg7, + XMac1, + XMac2, + XMac3, + XMac4, + XMac5, + XMac6, + XMac7, + XMac8, + XMac9, + XMac10, + XMac1Aux, + XMac2Aux, + XMac3Aux, + XMac4Aux, + XMac5Aux, + XMac6Aux, + XMac7Aux, + XMac8Aux, + XMac9Aux, + XMac10Aux, + XMac1Mapping, + XMac2Mapping, + XMac3Mapping, + XMac4Mapping, + XMac5Mapping, + XMac6Mapping, + XMac7Mapping, + XMac8Mapping, + XMac9Mapping, + XMac10Mapping, + netKind1, + netKind2, + netKind3, + netKind4, + netKind5, + netKind6, + netKind7, + netKind8, + netKind9, + netKind10 + } hwinfo_field_t; /* Define used values in supported fields */

1 0

Patch set updated for coreboot: console/serialice: Add SerialICE
by Patrick Rudolph 28 Jun '16

28 Jun '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14504 -gerrit commit 5828db30f6cdc3699f0ce52352af6fd3b16aa000 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Apr 25 11:00:17 2016 +0200 console/serialice: Add SerialICE Add Kconfig Option to build SerialICE shell into coreboot stages. You can select between romstage and ramstage. The SerialICE shell will be launched instead of coreboot console. As minimal system initialization is already done in coreboot, it should work on all boards. Tested with EHCI Debug on Lenovo T520. Needs tests: * Ramstage * Serial cable * On other boards Change-Id: I1fa6eb4f40e0f625c8c8302d1580bcd2664d670b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/Kconfig | 32 +++ src/arch/x86/c_start.S | 2 +- src/arch/x86/exception.c | 7 +- src/console/Makefile.inc | 2 + src/console/console.c | 22 -- src/console/init.c | 3 + src/console/serialice.c | 430 ++++++++++++++++++++++++++++++++++++++++ src/console/serialice_priv.h | 103 ++++++++++ src/include/console/serialice.h | 30 +++ src/include/console/streams.h | 6 - src/include/console/uart.h | 10 +- src/include/console/usb.h | 11 +- src/include/serial-com.h | 24 +++ src/lib/Makefile.inc | 6 + src/lib/gdb.c | 64 ++++++ src/lib/serial.c | 57 ++++++ 16 files changed, 760 insertions(+), 49 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 1cb55c9..0ab91de 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1078,6 +1078,38 @@ config DEBUG_COVERAGE If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped. +config DEBUG_SERIALICE + bool "Enable SerialICE instead normal boot" + default n + depends on ARCH_X86 + depends on CONSOLE_SERIAL || CONSOLE_USB + help + If enabled, SerialICE will be run instead of normal boot. + You need to connect a serial cable or EHCI debug dongle to + communicate with SerialICE shell. + +if DEBUG_SERIALICE + +choice + prompt "SerialICE bootstage" + default DEBUG_SERIALICE_ROMSTAGE + help + Choose the stage SerialICE to start. You can choose between + ROMSTAGE and RAMSTAGE. + +config DEBUG_SERIALICE_ROMSTAGE + bool "Start SerialICE instead of Romstage" + depends on CONSOLE_SERIAL || USBDEBUG_IN_ROMSTAGE + help + Start SerialICE in romstage, right after minimal system initialization. + +config DEBUG_SERIALICE_RAMSTAGE + bool "Start SerialICE instead of Ramstage" + help + Start SerialICE in ramstage. +endchoice + +endif endmenu # These probably belong somewhere else, but they are needed somewhere. diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 6bda64f..ed6025c 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -111,7 +111,7 @@ _start: post_code(POST_PRE_HARDWAREMAIN) /* post fe */ #if CONFIG_GDB_WAIT - call gdb_hw_init + call serial_hw_init call gdb_stub_breakpoint #endif call main diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index b6e6ffb..c8f474f 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -14,6 +14,7 @@ #include <console/console.h> #include <console/streams.h> #include <string.h> +#include <serial-com.h> #if CONFIG_GDB_STUB @@ -231,17 +232,17 @@ static char out_buffer[BUFMAX]; static inline void stub_putc(int ch) { - gdb_tx_byte(ch); + serial_tx_byte(ch); } static inline void stub_flush(void) { - gdb_tx_flush(); + serial_tx_flush(); } static inline int stub_getc(void) { - return gdb_rx_byte(); + return serial_rx_byte(); } static int hex(char ch) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 0fee12a..e3015fe 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += vtxprintf.c printk.c vsprintf.c ramstage-y += init.c console.c ramstage-y += post.c ramstage-y += die.c +ramstage-$(CONFIG_DEBUG_SERIALICE_RAMSTAGE) += serialice.c smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c @@ -17,6 +18,7 @@ romstage-y += vtxprintf.c printk.c romstage-y += init.c console.c romstage-y += post.c romstage-y += die.c +romstage-$(CONFIG_DEBUG_SERIALICE_ROMSTAGE) += serialice.c postcar-y += vtxprintf.c printk.c postcar-y += init.c console.c diff --git a/src/console/console.c b/src/console/console.c index c4365f3..231b245 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -62,25 +62,3 @@ void console_tx_flush(void) __usb_tx_flush(); } - -#if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) -void gdb_hw_init(void) -{ - __gdb_hw_init(); -} - -void gdb_tx_byte(unsigned char byte) -{ - __gdb_tx_byte(byte); -} - -void gdb_tx_flush(void) -{ - __gdb_tx_flush(); -} - -unsigned char gdb_rx_byte(void) -{ - return __gdb_rx_byte(); -} -#endif diff --git a/src/console/init.c b/src/console/init.c index 8f40abb..66b751c 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <console/uart.h> +#include <console/serialice.h> #include <console/streams.h> #include <device/pci.h> #include <option.h> @@ -43,6 +44,8 @@ void console_init(void) console_hw_init(); + serialice_main(); + printk(BIOS_INFO, "\n\ncoreboot-%s%s %s " ENV_STRING " starting...\n", coreboot_version, coreboot_extra_version, coreboot_build); } diff --git a/src/console/serialice.c b/src/console/serialice.c new file mode 100644 index 0000000..dc57edb --- /dev/null +++ b/src/console/serialice.c @@ -0,0 +1,430 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <console/serialice.h> +#include <arch/io.h> +#include <serial-com.h> +#include "serialice_priv.h" + +#define VERSION "1.6" + +/* Uart wrapper functions */ + +static void sio_flush(void) +{ + serial_tx_flush(); +} + +static void sio_putc(u8 byte) +{ + serial_tx_byte(byte); +} + +static u8 sio_getc(void) +{ + u8 val = 0; + + val = serial_rx_byte(); + if (val) { +#if ECHO_MODE + sio_putc(val); +#endif + return val; + } + + return 0; +} + +/* String functions */ + +static void sio_putstring(const char *string) +{ + /* Very simple, no %d, %x etc. */ + while (*string) { + if (*string == '\n') + sio_putc('\r'); + sio_putc(*string); + string++; + } + sio_flush(); +} + +static void sio_put8(u8 data) +{ + u8 c; + + c = (data >> 4) & 0xf; + sio_put_nibble(c); + + c = data & 0xf; + sio_put_nibble(c); + sio_flush(); +} + +static void sio_put16(u16 data) +{ + int i; + u8 c; + + for (i = 12; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static void sio_put32(u32 data) +{ + int i; + u8 c; + + for (i = 28; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static u8 sio_get_nibble(void) +{ + u8 ret = 0; + u8 nibble = sio_getc(); + + if (nibble >= '0' && nibble <= '9') { + ret = (nibble - '0'); + } else if (nibble >= 'a' && nibble <= 'f') { + ret = (nibble - 'a') + 0xa; + } else if (nibble >= 'A' && nibble <= 'F') { + ret = (nibble - 'A') + 0xa; + } else { + sio_putstring("ERROR: parsing number\n"); + } + return ret; +} + +static u8 sio_get8(void) +{ + u8 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + return data; +} + +static u16 sio_get16(void) +{ + u16 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +static u32 sio_get32(void) +{ + u32 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +/* SerialICE interface functions */ + +static void serialice_read_memory(void) +{ + u8 width; + u32 *addr; + + // Format: + // *rm00000000.w + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(read8(addr)); + break; + case 'w': + sio_put16(read16(addr)); + break; + case 'l': + sio_put32(read32(addr)); + break; + } +} + +static void serialice_write_memory(void) +{ + u8 width; + u32 *addr; + u32 data; + + // Format: + // *wm00000000.w=0000 + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + write8(addr, (u8)data); + break; + case 'w': + data = sio_get16(); + write16(addr, (u16)data); + break; + case 'l': + data = sio_get32(); + write32(addr, (u32)data); + break; + } +} + +static void serialice_read_io(void) +{ + u8 width; + u16 port; + + // Format: + // *ri0000.w + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(inb(port)); + break; + case 'w': + sio_put16(inw(port)); + break; + case 'l': + sio_put32(inl(port)); + break; + } +} + +static void serialice_write_io(void) +{ + u8 width; + u16 port; + u32 data; + + // Format: + // *wi0000.w=0000 + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + outb((u8)data, port); + break; + case 'w': + data = sio_get16(); + outw((u16)data, port); + break; + case 'l': + data = sio_get32(); + outl((u32)data, port); + break; + } +} + +static void serialice_read_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *rc00000000.9c5a203a + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // key in %edi + + sio_putc('\r'); sio_putc('\n'); + + msr = rdmsr(addr, key); + sio_put32(msr.hi); + sio_putc('.'); + sio_put32(msr.lo); +} + +static void serialice_write_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *wc00000000.9c5a203a=00000000.00000000 + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // read key in %edi + sio_getc(); // skip = + msr.hi = sio_get32(); + sio_getc(); // skip . + msr.lo = sio_get32(); + +#ifdef __ROMCC__ + /* Cheat to avoid register outage */ + wrmsr(addr, msr, 0x9c5a203a); +#else + wrmsr(addr, msr, key); +#endif +} + +static void serialice_cpuinfo(void) +{ + u32 eax, ecx; + u32 reg32; + + // Format: + // --EAX--- --ECX--- + // *ci00000000.00000000 + eax = sio_get32(); + sio_getc(); // skip . + ecx = sio_get32(); + + sio_putc('\r'); sio_putc('\n'); + + /* This code looks quite crappy but this way we don't + * have to worry about running out of registers if we + * occupy eax, ebx, ecx, edx at the same time + */ + reg32 = cpuid_eax(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ebx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ecx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_edx(eax, ecx); + sio_put32(reg32); +} + +static void serialice_mainboard(void) +{ + int i = 0; + const char mb_string[] = CONFIG_MAINBOARD_VENDOR" " + CONFIG_MAINBOARD_PART_NUMBER; + + sio_putc('\r'); sio_putc('\n'); + + while (i < 32 && mb_string[i] > 0) { + sio_putc(mb_string[i]); + i++; + } + while (i < 32) { + sio_putc(' '); + i++; + } + + sio_flush(); +} + +static void serialice_version(void) +{ + sio_putstring("\nSerialICE v" VERSION "\n"); +} + +void serialice_main(void) +{ + u16 c; + + serialice_version(); + + while (1) { + sio_putstring("\n> "); + + c = sio_getc(); + if (c != '*') + continue; + + c = sio_getc() << 8; + c |= sio_getc(); + + switch (c) { + case (('r' << 8)|'m'): // Read Memory *rm + serialice_read_memory(); + break; + case (('w' << 8)|'m'): // Write Memory *wm + serialice_write_memory(); + break; + case (('r' << 8)|'i'): // Read IO *ri + serialice_read_io(); + break; + case (('w' << 8)|'i'): // Write IO *wi + serialice_write_io(); + break; + case (('r' << 8)|'c'): // Read CPU MSR *rc + serialice_read_msr(); + break; + case (('w' << 8)|'c'): // Write CPU MSR *wc + serialice_write_msr(); + break; + case (('c' << 8)|'i'): // Read CPUID *ci + serialice_cpuinfo(); + break; + case (('m' << 8)|'b'): // Read mainboard type *mb + serialice_mainboard(); + break; + case (('v' << 8)|'i'): // Read version info *vi + serialice_version(); + break; + default: + sio_putstring("ERROR\n"); + break; + } + } +} diff --git a/src/console/serialice_priv.h b/src/console/serialice_priv.h new file mode 100644 index 0000000..078ef04 --- /dev/null +++ b/src/console/serialice_priv.h @@ -0,0 +1,103 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_PRIV_H +#define CONSOLE_SERIALICE_PRIV_H + +/* String functions */ + +#define sio_put_nibble(nibble) \ + do { \ + if (nibble > 9) \ + nibble += ('a' - 10); \ + else \ + nibble += '0'; \ + sio_putc(nibble); \ + } while (0) + +/* MSR functions */ + +typedef struct { u32 lo, hi; } msr_t; + +static inline msr_t rdmsr(u32 index, u32 key) +{ + msr_t result; + + __asm__ __volatile__ ( + "rdmsr" + : "=a" (result.lo), "=d" (result.hi) + : "c" (index), "D" (key) + ); + return result; +} + +static inline void wrmsr(u32 index, msr_t msr, u32 key) +{ + __asm__ __volatile__ ( + "wrmsr" + : /* No outputs */ + : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (key) + ); +} + +/* CPUID functions */ + +static inline u32 cpuid_eax(u32 op, u32 op2) +{ + u32 eax; + + __asm__("cpuid" + : "=a" (eax) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return eax; +} + +static inline u32 cpuid_ebx(u32 op, u32 op2) +{ + u32 ebx; + + __asm__("cpuid" + : "=b" (ebx) + : "a" (op), "c" (op2) + : "edx"); + return ebx; +} + +static inline u32 cpuid_ecx(u32 op, u32 op2) +{ + u32 ecx; + + __asm__("cpuid" + : "=c" (ecx) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return ecx; +} + +static inline u32 cpuid_edx(u32 op, u32 op2) +{ + u32 edx; + + __asm__("cpuid" + : "=d" (edx) + : "a" (op), "c" (op2) + : "ebx"); + return edx; +} + +#endif diff --git a/src/include/console/serialice.h b/src/include/console/serialice.h new file mode 100644 index 0000000..a2b27e7 --- /dev/null +++ b/src/include/console/serialice.h @@ -0,0 +1,30 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_H +#define CONSOLE_SERIALICE_H + +#define ECHO_MODE 1 + +#if (ENV_RAMSTAGE && CONFIG_DEBUG_SERIALICE_RAMSTAGE) || \ + (ENV_ROMSTAGE && CONFIG_DEBUG_SERIALICE_ROMSTAGE) +void serialice_main(void); +#else +static inline void serialice_main(void) { } +#endif + +#endif diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 35f7999..53bd12d 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -18,10 +18,4 @@ void console_hw_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void); -/* For remote GDB debugging. */ -void gdb_hw_init(void); -void gdb_tx_byte(unsigned char byte); -void gdb_tx_flush(void); -unsigned char gdb_rx_byte(void); - #endif /* _CONSOLE_STREAMS_H_ */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index a3d650b..05df8d8 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -63,18 +63,12 @@ void oxford_remap(unsigned int new_base); static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); } static inline void __uart_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } +static inline u8 __uart_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_CONSOLE); } #else static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} -#endif - -#if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) -#define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE -static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); } -static inline void __gdb_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } -static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); } -static inline u8 __gdb_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_GDB); } +static inline u8 __uart_rx_byte(void) { return 0; } #endif #endif /* __ROMCC__ */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index b758c03..65e1dee 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -37,19 +37,12 @@ int usb_can_rx_byte(int idx); static inline void __usbdebug_init(void) { usbdebug_init(); } static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); } static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); } +static inline u8 __usb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_CONSOLE); } #else static inline void __usbdebug_init(void) {} static inline void __usb_tx_byte(u8 data) {} static inline void __usb_tx_flush(void) {} -#endif - -/* */ -#if 0 && CONFIG_GDB_STUB && \ - ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) -static inline void __gdb_hw_init(void) { usbdebug_init(); } -static inline void __gdb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_GDB, data); } -static inline void __gdb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_GDB); } -static inline u8 __gdb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_GDB); } +static inline u8 __usb_rx_byte(void) { return 0; } #endif #endif /* _CONSOLE_USB_H_ */ diff --git a/src/include/serial-com.h b/src/include/serial-com.h new file mode 100644 index 0000000..baf75ce --- /dev/null +++ b/src/include/serial-com.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SERIAL_H_ +#define _SERIAL_H_ + +#include <stdint.h> + +void serial_hw_init(void); +void serial_tx_byte(unsigned char byte); +void serial_tx_flush(void); +unsigned char serial_rx_byte(void); + +#endif /* _SERIAL_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 49720a7..9f54cff 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -221,6 +221,12 @@ postcar-y += prog_ops.c postcar-y += rmodule.c postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c +romstage-$(CONFIG_GDB_STUB) += gdb.c +ramstage-$(CONFIG_GDB_STUB) += gdb.c + +romstage-$(CONFIG_DEBUG_SERIALICE_ROMSTAGE) += serial.c +ramstage-$(CONFIG_DEBUG_SERIALICE_RAMSTAGE) += serial.c + # Use program.ld for all the platforms which use C fo the bootblock. bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += program.ld diff --git a/src/lib/gdb.c b/src/lib/gdb.c new file mode 100644 index 0000000..66eb2cb --- /dev/null +++ b/src/lib/gdb.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <rules.h> +#include <stdint.h> +#include <console/uart.h> +#include <console/usb.h> +#include <serial-com.h> + +#define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE +#define USB_PIPE_FOR_GDB 0 + +/* Configure GDB to use EHCI debug or UART functions */ +#if __CONSOLE_USB_ENABLE__ && \ + ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) +static inline void __gdb_hw_init(void) { usbdebug_init(); } +static inline void __gdb_tx_byte(u8 data) + { usb_tx_byte(USB_PIPE_FOR_GDB, data); } +static inline void __gdb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_GDB); } +#elif __CONSOLE_SERIAL_ENABLE__ && (ENV_ROMSTAGE || ENV_RAMSTAGE) +static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); } +static inline void __gdb_tx_byte(u8 data) + { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } +static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) + { return uart_rx_byte(CONFIG_UART_FOR_GDB); } +#else +static inline void __gdb_hw_init(void) {} +static inline void __gdb_tx_byte(u8 data) {} +static inline void __gdb_tx_flush(void) {} +static inline u8 __gdb_rx_byte(void) { return 0; } +#endif + + +void serial_hw_init(void) +{ + __gdb_hw_init(); +} + +void serial_tx_byte(unsigned char byte) +{ + __gdb_tx_byte(byte); +} + +void serial_tx_flush(void) +{ + __gdb_tx_flush(); +} + +unsigned char serial_rx_byte(void) +{ + return __gdb_rx_byte(); +} diff --git a/src/lib/serial.c b/src/lib/serial.c new file mode 100644 index 0000000..2d89e56 --- /dev/null +++ b/src/lib/serial.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <rules.h> +#include <stdint.h> +#include <console/uart.h> +#include <console/usb.h> +#include <serial-com.h> + +#if defined(__CONSOLE_SERIAL_ENABLE__) +static inline void __serial_init(void) { __uart_init(); } +static inline void __serial_tx_byte(u8 data) { __uart_tx_byte(data); } +static inline void __serial_tx_flush(void) { __uart_tx_flush(); } +static inline u8 __serial_rx_byte(void) { return __uart_rx_byte(); } +#elif defined(__CONSOLE_USB_ENABLE__) +static inline void __serial_init(void) { __usbdebug_init(); } +static inline void __serial_tx_byte(u8 data) { __usb_tx_byte(data); } +static inline void __serial_tx_flush(void) { __usb_tx_flush(); } +static inline u8 __serial_rx_byte(void) { return __usb_rx_byte(); } +#else +static inline void __serial_init(void) {} +static inline void __serial_tx_byte(u8 data) {} +static inline void __serial_tx_flush(void) {} +static inline u8 __serial_rx_byte(void) { return 0; } +#endif + + +void serial_hw_init(void) +{ + __serial_init(); +} + +void serial_tx_byte(unsigned char byte) +{ + __serial_tx_byte(byte); +} + +void serial_tx_flush(void) +{ + __serial_tx_flush(); +} + +unsigned char serial_rx_byte(void) +{ + return __serial_rx_byte(); +} +

1 0

New patch to review for coreboot: ACPI S3: Drop early resume backup
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15477 -gerrit commit 114b87bffdce9430a7d4707943da6df638502831 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 13:09:56 2016 +0300 ACPI S3: Drop early resume backup No longer needed as low memory backup is implemented as part of the ramstage loader, after MTRRs are set to write-back cache for better performance. Change-Id: I5f5ad94bae2afef915927b9737c79431b6f75f22 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/acpi_s3.c | 21 +-------------------- src/arch/x86/include/arch/acpi.h | 2 -- 2 files changed, 1 insertion(+), 22 deletions(-) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index af833cb..10212ac 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -100,10 +100,6 @@ void backup_ramstage_section(u32 base, u32 size) return; size = ALIGN_UP(size, 4); - if (!size) { - base = backup_mem->base; - size = backup_mem->size; - } /* FIXME: Sanity check CBMEM. */ @@ -114,22 +110,11 @@ void backup_ramstage_section(u32 base, u32 size) backup_mem->magic = RESUME_BACKUP_MAGIC; } -/* Make backup of low-memory region, relying on the base and size - * of the ramstage that was loaded before entry to ACPI S3. - * - * DEPRECATED - */ -void acpi_prepare_for_resume(void) -{ - backup_ramstage_section(0, 0); -} - extern unsigned char _program, _eprogram; void acpi_prepare_resume_backup(void) { size_t size = (u32)(&_eprogram - &_program); - u32 base = (u32) &_program; struct resume_backup *backup_mem; if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) @@ -140,9 +125,7 @@ void acpi_prepare_resume_backup(void) /* Let's prepare the ACPI S3 Resume area now already, so we can rely on * it being there during reboot time. If this fails, ACPI resume will - * be disabled. We assume that ramstage does not change while in suspend, - * so base and size of the currently running ramstage will match the one - * we will load on resume path. + * be disabled. */ if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) romstage_ram_stack_maybe_low(0); @@ -155,8 +138,6 @@ void acpi_prepare_resume_backup(void) return; backup_mem->magic = 0; - backup_mem->base = base; - backup_mem->size = size; } #define WAKEUP_BASE 0x600 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 3bda1c6..66cb1c9 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -629,14 +629,12 @@ int acpi_is_wakeup(void); int acpi_is_wakeup_s3(void); int acpi_is_wakeup_s4(void); #endif -void acpi_prepare_for_resume(void); #else #define acpi_slp_type 0 static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } static inline int acpi_is_wakeup_s4(void) { return 0; } -static inline void acpi_prepare_for_resume(void) { } #endif static inline uintptr_t acpi_align_current(uintptr_t current)

1 0

New patch to review for coreboot: ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15476 -gerrit commit a02194eb31bf87f6d5b82b4392e3732b200fafe9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 28 07:50:48 2016 +0300 ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP Change-Id: Ifae41b51b359010ec02269c674936a87bd15623b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 4 ---- src/arch/x86/acpi_s3.c | 10 ---------- src/arch/x86/include/arch/acpi.h | 2 -- 3 files changed, 16 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index b4c3cbe..7043851 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -516,10 +516,6 @@ config HAVE_ACPI_RESUME bool default n -config ACPI_HUGE_LOWMEM_BACKUP - bool - default n - config RESUME_PATH_SAME_AS_BOOT bool default y if ARCH_X86 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index b804c6c..af833cb 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -105,11 +105,6 @@ void backup_ramstage_section(u32 base, u32 size) size = backup_mem->size; } - if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { - base = CONFIG_RAMBASE; - size = HIGH_MEMORY_SAVE; - } - /* FIXME: Sanity check CBMEM. */ /* Back up the OS-controlled memory where ramstage will be loaded. */ @@ -152,11 +147,6 @@ void acpi_prepare_resume_backup(void) if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) romstage_ram_stack_maybe_low(0); - if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { - base = CONFIG_RAMBASE; - size = HIGH_MEMORY_SAVE; - } - size = ALIGN_UP(size, 4); size_t reserve = ALIGN_UP(sizeof(*backup_mem) + size, 1024); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index babb50b..3bda1c6 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -24,8 +24,6 @@ #ifndef __ASM_ACPI_H #define __ASM_ACPI_H -#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) - #ifndef __ASSEMBLER__ #include <stdint.h> #include <rules.h>

1 0

New patch to review for coreboot: AMD k8 fam10: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15475 -gerrit commit 8246ecba1233f4a52104930e89e2ec869a773752 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:14:57 2016 +0300 AMD k8 fam10: Delay ACPI S3 backup until ramstage loader Change-Id: I6d5d3e1ccd2dab727c9eba6c6175d47955719b54 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index db10071..d9137a5 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -131,9 +131,6 @@ void cache_as_ram_new_stack (void) set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - if (acpi_is_wakeup_s3()) - acpi_prepare_for_resume(); - #if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) initialize_romstage_console_lock(); #endif

1 0

New patch to review for coreboot: AMD k8 fam10: Use common ACPI S3 recovery
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15474 -gerrit commit 996e2edb9f34d1615312f2362102d0f9419a7ad6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:53:00 2016 +0300 AMD k8 fam10: Use common ACPI S3 recovery Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/acpi_s3.c | 21 --------------- src/arch/x86/include/arch/acpi.h | 3 --- src/cpu/amd/car/post_cache_as_ram.c | 43 +++++++------------------------ src/cpu/amd/family_10h-family_15h/Kconfig | 1 - src/cpu/amd/model_fxx/Kconfig | 1 - 5 files changed, 9 insertions(+), 60 deletions(-) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 9d56c82..b804c6c 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -129,27 +129,6 @@ void acpi_prepare_for_resume(void) backup_ramstage_section(0, 0); } -void *acpi_backup_container(void) -{ - struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); - if (backup_mem == NULL) - return NULL; - - backup_mem->magic = 0; - return (void*)&backup_mem->buf; -} - -void acpi_backup_validate(u32 base, u32 size) -{ - struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); - if (backup_mem == NULL) - return; - - backup_mem->base = base; - backup_mem->size = size; - backup_mem->magic = RESUME_BACKUP_MAGIC; -} - extern unsigned char _program, _eprogram; void acpi_prepare_resume_backup(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 6bb1a8c..babb50b 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -618,9 +618,6 @@ static inline int acpi_s3_resume_allowed(void) return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME); } -void *acpi_backup_container(void); -void acpi_backup_validate(u32 base, u32 size); - #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) extern int acpi_slp_type; diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 0ec58cd..db10071 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -45,12 +45,6 @@ static void memcpy_(void *d, const void *s, size_t len) memcpy(d, s, len); } -static void memset_(void *d, int val, size_t len) -{ - print_car_debug(" Fill [%08x-%08x] ...", (uint32_t) d, (uint32_t) (d + len - 1)); - memset(d, val, len); -} - static int memcmp_(void *d, const void *s, size_t len) { print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...", @@ -58,33 +52,6 @@ static int memcmp_(void *d, const void *s, size_t len) return memcmp(d, s, len); } -static void prepare_ramstage_region(int s3resume) -{ - print_car_debug("Prepare ramstage memory region..."); - - if (s3resume) { - void *resume_backup_memory = acpi_backup_container(); - if (resume_backup_memory) - memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); - memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE); - } else { - memset_((void*)0, 0, CONFIG_RAMTOP); - } - -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) - initialize_romstage_console_lock(); -#endif -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) - initialize_romstage_nvram_cbfs_lock(); -#endif - - print_car_debug(" Done\n"); - - if (s3resume) - acpi_backup_validate(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); -} - /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 * and RevGuide for Fam12h, Pub#44739 Rev 3.10 */ @@ -164,7 +131,15 @@ void cache_as_ram_new_stack (void) set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - prepare_ramstage_region(acpi_is_wakeup_s3()); + if (acpi_is_wakeup_s3()) + acpi_prepare_for_resume(); + +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) + initialize_romstage_console_lock(); +#endif +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) + initialize_romstage_nvram_cbfs_lock(); +#endif set_sysinfo_in_ram(1); // So other core0 could start to train mem diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 30c7dee..fda7fc8 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -10,7 +10,6 @@ config CPU_AMD_MODEL_10XXX select TSC_SYNC_LFENCE select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER - select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 3eb5b94..c8bae33 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -9,7 +9,6 @@ config CPU_AMD_MODEL_FXX select SSE2 select TSC_SYNC_LFENCE select UDELAY_LAPIC - select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_FXX

1 0

New patch to review for coreboot: AMD k8 fam10: Separate romstage ramstack (WIP)
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15473 -gerrit commit 6ffef315076ed7841d71844d6d8f2d3f64b55e6f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 19:45:19 2016 +0300 AMD k8 fam10: Separate romstage ramstack (WIP) Romstage ram stack was placed below RAMTOP. This is vulnerable location as a large ramstage could overwrite it. Location also prevents optimizing S3 resume path since all low memory between RAMBASE..RAMTOP has to be backed to CBMEM. When possible, place ram stack high. Change-Id: I4106e91ed3256aca5d0d115d4aa7e46b75b27eec Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 35 +++++++---------------------------- 1 file changed, 7 insertions(+), 28 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index dba2a06..0ec58cd 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -23,6 +23,7 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> #include <arch/acpi.h> +#include <program_loading.h> #include <romstage_handoff.h> #include "cbmem.h" #include "cpu/amd/car/disable_cache_as_ram.c" @@ -37,12 +38,6 @@ #define print_car_debug(format, arg...) #endif -static size_t backup_size(void) -{ - size_t car_size = car_data_size(); - return ALIGN(car_size + 1024, 1024); -} - static void memcpy_(void *d, const void *s, size_t len) { print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...", @@ -63,35 +58,18 @@ static int memcmp_(void *d, const void *s, size_t len) return memcmp(d, s, len); } -static void prepare_romstage_ramstack(int s3resume) -{ - size_t backup_top = backup_size(); - print_car_debug("Prepare CAR migration and stack regions..."); - - if (s3resume) { - void *resume_backup_memory = acpi_backup_container(); - if (resume_backup_memory) - memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, - (void *)(CONFIG_RAMTOP - backup_top), backup_top); - } - memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top); - - print_car_debug(" Done\n"); -} - static void prepare_ramstage_region(int s3resume) { - size_t backup_top = backup_size(); print_car_debug("Prepare ramstage memory region..."); if (s3resume) { void *resume_backup_memory = acpi_backup_container(); if (resume_backup_memory) memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, - HIGH_MEMORY_SAVE - backup_top); - memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE - backup_top); + HIGH_MEMORY_SAVE); + memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE); } else { - memset_((void*)0, 0, CONFIG_RAMTOP - backup_top); + memset_((void*)0, 0, CONFIG_RAMTOP); } #if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) @@ -138,7 +116,8 @@ void post_cache_as_ram(void) if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) || s3resume) cbmem_recovery(s3resume); - prepare_romstage_ramstack(s3resume); + /* FIXME: CBMEM stack is not wb-cacheable yet. */ + uintptr_t ramtop = romstage_ram_stack_maybe_low(!s3resume); if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) { struct romstage_handoff *handoff; @@ -156,7 +135,7 @@ void post_cache_as_ram(void) } size_t car_size = car_data_size(); - void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); + void *migrated_car = (void *)(ramtop - car_size); print_car_debug("Copying data from cache to RAM..."); memcpy_(migrated_car, _car_relocatable_data_start, car_size);

1 0

New patch to review for coreboot: AMD k8 fam10: Fix romstage handoff
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15472 -gerrit commit 65537018621514028da93a98b5518991503e678f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 26 15:44:05 2016 +0300 AMD k8 fam10: Fix romstage handoff It is not possible for cbmem_add() to complete succesfully before cbmem_recovery() is called. Adding more tables on S3 resume path is also not possible. Change-Id: Ic14857eeef2932562acee4a36f59c22ff4ca1a84 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index ce1f930..dba2a06 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -133,19 +133,22 @@ void post_cache_as_ram(void) if ((*lower_stack_boundary) != 0xdeadbeef) printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); - struct romstage_handoff *handoff; - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = acpi_is_wakeup_s3(); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - int s3resume = acpi_is_wakeup_s3(); - if (s3resume) + + if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) || s3resume) cbmem_recovery(s3resume); prepare_romstage_ramstack(s3resume); + if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) { + struct romstage_handoff *handoff; + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = s3resume; + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + } + /* from here don't store more data in CAR */ if (family >= 0x1f && family <= 0x3f) { /* Family 10h and 12h, 11h until shown otherwise */

1 0

Patch set updated for coreboot: RELOCATABLE_RAMSTAGE obsoletes RAMBASE and RAMTOP
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15250 -gerrit commit 238b86bd507af6bb26bc898dce38918b1cff6a88 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 18 07:39:31 2016 +0300 RELOCATABLE_RAMSTAGE obsoletes RAMBASE and RAMTOP There is no fixed region of RAMBASE..RAMTOP where ramstage gets loaded. To have RELOCATABLE_RAMSTAGE is not a decision user could make in menuconfig, so hide it. Change-Id: Ie90611274fb011759661d5c46c8e35e5cca6533c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 2 +- src/arch/x86/Kconfig | 5 +++++ src/arch/x86/include/arch/memlayout.h | 9 +++++++-- src/arch/x86/memlayout.ld | 2 +- src/northbridge/amd/agesa/Kconfig | 4 ---- src/northbridge/amd/pi/Kconfig | 4 ---- 6 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7043851..b158d11 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -243,7 +243,7 @@ config RELOCATABLE_MODULES config RELOCATABLE_RAMSTAGE depends on EARLY_CBMEM_INIT - bool "Build the ramstage to be relocatable in 32-bit address space." + bool default n select RELOCATABLE_MODULES help diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index af73a58..e268661 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -79,15 +79,20 @@ config SIPI_VECTOR_IN_ROM default n depends on ARCH_X86 +if !RELOCATABLE_RAMSTAGE + config RAMBASE hex default 0x100000 + depends on ARCH_X86 config RAMTOP hex default 0x200000 depends on ARCH_X86 +endif + # Traditionally BIOS region on SPI flash boot media was memory mapped right below # 4G and it was the last region in the IFD. This way translation between CPU # address space to flash address was trivial. However some IFDs on newer SoCs diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 5f5cba6..2fa7943 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -24,8 +24,13 @@ #define ARCH_STAGE_HAS_BSS_SECTION 0 #endif -#if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP -# error "CONFIG_RAMTOP not configured" +#if IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) +# define MAX_RAMSTAGE_SIZE (8<<20) +#else +# if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP +# error "CONFIG_RAMTOP not configured" +# endif +# define MAX_RAMSTAGE_SIZE (CONFIG_RAMTOP - CONFIG_RAMBASE) #endif #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index e6db0b8..48c9394 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -26,7 +26,7 @@ SECTIONS * conditionalize with macros. */ #if ENV_RAMSTAGE - RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) + RAMSTAGE(CONFIG_RAMBASE, MAX_RAMSTAGE_SIZE) #elif ENV_ROMSTAGE /* The 1M size is not allocated. It's just for basic size checking. diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index d5cff80..37bf3c4 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -35,8 +35,4 @@ config HEAP_SIZE hex default 0xc0000 -config RAMTOP - hex - default 0x400000 - endif # NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index cb72416..eea2897 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -40,10 +40,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config RAMTOP - hex - default 0x1000000 - config HEAP_SIZE hex default 0xc0000

1 0

Patch set updated for coreboot: quick_ram_check: Remove reference to RAMBASE (WIP)
by Kyösti Mälkki 28 Jun '16

28 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15239 -gerrit commit 0574bff3499e4bef6413d5f5cdb698a3e8f69549 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 17 23:31:42 2016 +0300 quick_ram_check: Remove reference to RAMBASE (WIP) TODO: Test at address cbmem_top() instead? TODO: lib/ramtest.c builds for arch/x86-only Change-Id: Ieb8f11690fb0e9b287d866be56010bb9adefd21d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/ramtest.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index a29fa25..6d12060 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -181,32 +181,37 @@ int ram_check_noprint_nodie(unsigned long start, unsigned long stop) return failures; } -void quick_ram_check(void) +static void __quick_ram_check(uintptr_t dst) { int fail = 0; u32 backup; - backup = read_phys(CONFIG_RAMBASE); - write_phys(CONFIG_RAMBASE, 0x55555555); + backup = read_phys(dst); + write_phys(dst, 0x55555555); phys_memory_barrier(); - if (read_phys(CONFIG_RAMBASE) != 0x55555555) + if (read_phys(dst) != 0x55555555) fail=1; - write_phys(CONFIG_RAMBASE, 0xaaaaaaaa); + write_phys(dst, 0xaaaaaaaa); phys_memory_barrier(); - if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa) + if (read_phys(dst) != 0xaaaaaaaa) fail=1; - write_phys(CONFIG_RAMBASE, 0x00000000); + write_phys(dst, 0x00000000); phys_memory_barrier(); - if (read_phys(CONFIG_RAMBASE) != 0x00000000) + if (read_phys(dst) != 0x00000000) fail=1; - write_phys(CONFIG_RAMBASE, 0xffffffff); + write_phys(dst, 0xffffffff); phys_memory_barrier(); - if (read_phys(CONFIG_RAMBASE) != 0xffffffff) + if (read_phys(dst) != 0xffffffff) fail=1; - write_phys(CONFIG_RAMBASE, backup); + write_phys(dst, backup); if (fail) { post_code(0xea); die("RAM INIT FAILURE!\n"); } phys_memory_barrier(); } + +void quick_ram_check(void) +{ + __quick_ram_check(0x100000); +}

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2016