the following patch was just integrated into master:
commit fefc77afd0e739ec18129f8cd58781e15b9802e4
Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
Date: Tue Jun 21 19:37:03 2016 +0200
arch/riscv: Show fault PC and load address on load access faults
Change-Id: Ib0535bf25ce25550cc17f64177f804a70aa13fb3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
Reviewed-on: https://review.coreboot.org/15286
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See https://review.coreboot.org/15286 for details.
-gerrit
the following patch was just integrated into master:
commit 719f9b53898bffa52395a1e25b616432eef6ff57
Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
Date: Tue Jun 21 19:37:03 2016 +0200
arch/riscv: Move _start to the beginning of the bootblock
The different entry points (0x100, 0x140, ...), which were defined in
the RISC-V Privileged Specification 1.7, aren't used anymore. Instead
the Spike bootrom jumps at the start of our image, and traps are handled
through mtvec.
Change-Id: I865adec5e7a752a25bac93a45654ac06e27d5a8e
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
Reviewed-on: https://review.coreboot.org/15283
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See https://review.coreboot.org/15283 for details.
-gerrit
the following patch was just integrated into master:
commit 4f7d329caaa99814a2383872025ca1757cf4fbad
Author: Antonello Dettori <dettori.an(a)gmail.com>
Date: Fri May 27 23:44:47 2016 +0200
tint: Fix tint and add Kconfig option
Fix the compiler errors with tint, improves the Makefile,
adds Kconfig integration and secondary payload option.
Change-Id: Ia99e30f566d5ccf0d083e52bf174970535daefc5
Signed-off-by: Antonello Dettori <dettori.an(a)gmail.com>
Reviewed-on: https://review.coreboot.org/14989
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/14989 for details.
-gerrit
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15026
-gerrit
commit 8383342c7811e10097255cd3f2ed41d6faa6b5dd
Author: Saurabh Satija <saurabh.satija(a)intel.com>
Date: Tue Mar 8 17:33:29 2016 -0800
apollolake: Add ACPI device for audio controller
Add the audio controller device to ACPI and define the _DSM handler
to return the address of the NHLT table, if set in NVS.
Change-Id: I619dbfb562b94255e42a3e5d5a3926c28b14db3e
Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com>
---
src/soc/intel/apollolake/acpi/pch_hda.asl | 84 +++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/pch_hda.asl b/src/soc/intel/apollolake/acpi/pch_hda.asl
new file mode 100644
index 0000000..33cd771
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pch_hda.asl
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* Audio Controller - Device 14, Function 0 */
+
+Device (HDAS)
+{
+ Name (_ADR, 0x000E0000)
+ Name (_DDN, "Audio Controller")
+ Name (UUID, ToUUID("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
+
+ /* Device is D3 wake capable */
+ Name (_S0W, 3)
+
+ /* NHLT Table Address populated from GNVS values */
+ Name (NBUF, ResourceTemplate() {
+ QWordMemory (ResourceConsumer, PosDecode, MinFixed,
+ MaxFixed, Cacheable, ReadOnly,
+ 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)
+ }
+ )
+
+ /*
+ * Device Specific Method
+ * Arg0 - UUID
+ * Arg1 - Revision
+ * Arg2 - Function Index
+ */
+ Method (_DSM, 4) {
+ If (LEqual (Arg0, ^UUID)) {
+ /*
+ * Function 0: Function Support Query
+ * Returns a bitmask of functions supported.
+ */
+ If (LEqual (Arg2, Zero)) {
+ /*
+ * NHLT Query only supported for revision 1 and
+ * if NHLT address and length are set in NVS.
+ */
+ If (LAnd (LEqual (Arg1, One),
+ LAnd (LNotEqual (NHLA, Zero),
+ LNotEqual (NHLL, Zero)))) {
+ Return (Buffer (One) { 0x03 })
+ }
+ Else {
+ Return (Buffer (One) { 0x01 })
+ }
+ }
+
+ /*
+ * Function 1: Query NHLT memory address used by
+ * Intel Offload Engine Driver to discover any non-HDA
+ * devices that are supported by the DSP.
+ *
+ * Returns a pointer to NHLT table in memory.
+ */
+ If (LEqual (Arg2, One)) {
+ CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
+ CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
+ CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
+ Store (NHLA, NBAS)
+ Store (NHLA, NMAS)
+ Store (NHLL, NLEN)
+ Return (NBUF)
+ }
+ }
+
+ Return (Buffer (One) { 0x00 })
+ }
+}
the following patch was just integrated into master:
commit bc141debb54c0a4b3759dce655550b2937354163
Author: Paul Kocialkowski <contact(a)paulk.fr>
Date: Sat May 14 15:25:51 2016 +0200
tegra124: Actually align the framebuffer's bytes-per-line to 32
The previous change with that intent aligned the framebuffer's
bytes-per-line to 64 instead of 32:
commit 8957dd6b52919ed634aa502dfd5b6316a6e6e055
Author: Paul Kocialkowski <contact(a)paulk.fr>
Date: Sun May 1 18:38:04 2016 +0200
tegra124: Align the framebuffer's bytes-per-line to 32
Change-Id: I88bba2ff355a51d42cab6a869ec1e9c534160b9c
Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr>
Reviewed-on: https://review.coreboot.org/14816
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
See https://review.coreboot.org/14816 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15322
-gerrit
commit 6655f35abd46915d8d1f35ceb779976a323933ef
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Jun 22 15:49:42 2016 -0600
rebase.sh: Update to current cros branch
Change-Id: I04add4e6fc957cb9a0cdefe79ec9e97e3cebdf8e
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
util/gitconfig/rebase.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/gitconfig/rebase.sh b/util/gitconfig/rebase.sh
index 26cec55..4b098c1 100755
--- a/util/gitconfig/rebase.sh
+++ b/util/gitconfig/rebase.sh
@@ -13,7 +13,7 @@
#
# Adapt to your remote branch:
-BRANCH="cros/chromeos-2015.07"
+BRANCH="cros/chromeos-2016.05"
# When pulling in patches from another tree from a gerrit repository,
# do the following at the end of a larger cherry-pick series:
the following patch was just integrated into master:
commit 6dfe25dc8b737e8c66f690cd3676dc0f4b96934f
Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com>
Date: Thu Jun 23 12:50:01 2016 -0700
google/reef: disable unused devices
BRANCH=none
BUG=chrome-os-partner:54325, chrome-os-partner:54581
TEST=device off in devicetree should disable the device.
Change-Id: I5dada06cba0eea8a30f297e3a6940a36b2ff40ee
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com>
Reviewed-on: https://review.coreboot.org/15339
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/15339 for details.
-gerrit
the following patch was just integrated into master:
commit 651642203426661e4092dd0d5c3cbecb97486236
Author: Hannah Williams <hannah.williams(a)intel.com>
Date: Fri Jun 24 14:13:45 2016 -0700
soc/apollolake: Populate fields in FADT to enable\disable SCI
This will allow kernel to trigger a APM SMI to enable\disable SCI
Change-Id: I1be79b7a3082c23fbaf204eff55360c46458e325
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
Reviewed-on: https://review.coreboot.org/15347
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/15347 for details.
-gerrit