coreboot-gerrit June 2016

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New patch to review for coreboot: fmaptool: Accept hex values with uppercase letters
by Patrick Georgi 28 Jun '16

28 Jun '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15482 -gerrit commit a87e4591439004952f50f1cd99484357d04e32df Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 28 20:45:34 2016 +0200 fmaptool: Accept hex values with uppercase letters Due to a newer flex version with which the scanner was recreated, we also have to make the compiler less strict on the generated code. Change-Id: I3758c0dcb2f5661d072b54a30d6a4ebe094854e6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/cbfstool/Makefile.inc | 1 + util/cbfstool/fmd_scanner.c_shipped | 185 +++++++++++++++++++----------------- util/cbfstool/fmd_scanner.h_shipped | 23 +++-- util/cbfstool/fmd_scanner.l | 2 +- 4 files changed, 114 insertions(+), 97 deletions(-) diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 6c2b100..8c9a2c0 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -162,6 +162,7 @@ $(objutil)/cbfstool/fmd.o: $(objutil)/cbfstool/fmd_parser.h $(objutil)/cbfstool/fmd.o: $(objutil)/cbfstool/fmd_scanner.h $(objutil)/cbfstool/fmd_parser.o: $(objutil)/cbfstool/fmd.o $(objutil)/cbfstool/fmd_scanner.o: $(objutil)/cbfstool/fmd.o +$(objutil)/cbfstool/fmd_scanner.o: TOOLCFLAGS += -Wno-sign-compare $(objutil)/cbfstool/%: $(top)/util/cbfstool/%_shipped mkdir -p $(dir $@) diff --git a/util/cbfstool/fmd_scanner.c_shipped b/util/cbfstool/fmd_scanner.c_shipped index b22011d..61215cf 100644 --- a/util/cbfstool/fmd_scanner.c_shipped +++ b/util/cbfstool/fmd_scanner.c_shipped @@ -7,8 +7,8 @@ #define FLEX_SCANNER #define YY_FLEX_MAJOR_VERSION 2 -#define YY_FLEX_MINOR_VERSION 5 -#define YY_FLEX_SUBMINOR_VERSION 39 +#define YY_FLEX_MINOR_VERSION 6 +#define YY_FLEX_SUBMINOR_VERSION 0 #if YY_FLEX_SUBMINOR_VERSION > 0 #define FLEX_BETA #endif @@ -210,7 +210,7 @@ struct yy_buffer_state /* Number of characters read into yy_ch_buf, not including EOB * characters. */ - yy_size_t yy_n_chars; + int yy_n_chars; /* Whether we "own" the buffer - i.e., we know we created it, * and can realloc() it to grow it, and should free() it to @@ -280,7 +280,7 @@ static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */ /* yy_hold_char holds the character lost when yytext is formed. */ static char yy_hold_char; -static yy_size_t yy_n_chars; /* number of characters read into yy_ch_buf */ +static int yy_n_chars; /* number of characters read into yy_ch_buf */ yy_size_t yyleng; /* Points to current character in buffer. */ @@ -341,7 +341,7 @@ void yyfree (void * ); /* Begin user sect3 */ -#define yywrap() 1 +#define yywrap() (/*CONSTCOND*/1) #define YY_SKIP_YYWRAP typedef unsigned char YY_CHAR; @@ -355,11 +355,17 @@ extern int yylineno; int yylineno = 1; extern char *yytext; +#ifdef yytext_ptr +#undef yytext_ptr +#endif #define yytext_ptr yytext static yy_state_type yy_get_previous_state (void ); static yy_state_type yy_try_NUL_trans (yy_state_type current_state ); static int yy_get_next_buffer (void ); +#if defined(__GNUC__) && __GNUC__ >= 3 +__attribute__((__noreturn__)) +#endif static void yy_fatal_error (yyconst char msg[] ); /* Done after the current pattern has been matched and before the @@ -388,7 +394,7 @@ static yyconst flex_int16_t yy_accept[24] = 6, 6, 0 } ; -static yyconst flex_int32_t yy_ec[256] = +static yyconst YY_CHAR yy_ec[256] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, @@ -396,13 +402,13 @@ static yyconst flex_int32_t yy_ec[256] = 1, 2, 1, 1, 4, 1, 1, 1, 1, 5, 5, 1, 1, 1, 1, 1, 1, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, - 1, 1, 1, 5, 1, 1, 1, 1, 1, 1, - 8, 1, 1, 1, 8, 1, 8, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 9, 1, 1, - 1, 1, 1, 1, 1, 1, 10, 10, 10, 10, + 1, 1, 1, 5, 8, 8, 8, 8, 8, 8, + 9, 1, 1, 1, 9, 1, 9, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 10, 1, 1, + 1, 1, 1, 1, 1, 1, 8, 8, 8, 8, - 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 9, + 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 10, 1, 1, 5, 1, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, @@ -420,16 +426,16 @@ static yyconst flex_int32_t yy_ec[256] = 1, 1, 1, 1, 1 } ; -static yyconst flex_int32_t yy_meta[11] = +static yyconst YY_CHAR yy_meta[11] = { 0, 1, 2, 2, 3, 3, 1, 1, 1, 1, 1 } ; -static yyconst flex_int16_t yy_base[27] = +static yyconst flex_uint16_t yy_base[27] = { 0, - 0, 0, 29, 0, 0, 0, 25, 34, 10, 15, - 0, 0, 12, 34, 16, 0, 20, 0, 0, 0, - 6, 0, 34, 12, 10, 30 + 0, 0, 33, 0, 0, 0, 20, 34, 10, 15, + 0, 0, 12, 34, 16, 0, 21, 0, 0, 0, + 5, 0, 34, 12, 10, 29 } ; static yyconst flex_int16_t yy_def[27] = @@ -439,12 +445,12 @@ static yyconst flex_int16_t yy_def[27] = 17, 24, 0, 23, 23, 23 } ; -static yyconst flex_int16_t yy_nxt[45] = +static yyconst flex_uint16_t yy_nxt[45] = { 0, 4, 5, 6, 7, 8, 9, 10, 4, 4, 4, - 11, 12, 11, 22, 14, 15, 15, 16, 17, 11, - 18, 18, 19, 20, 11, 21, 21, 14, 23, 21, - 13, 13, 13, 3, 23, 23, 23, 23, 23, 23, + 11, 12, 11, 22, 14, 15, 15, 11, 16, 17, + 18, 18, 14, 19, 20, 11, 21, 21, 21, 13, + 13, 13, 23, 3, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23 } ; @@ -452,8 +458,8 @@ static yyconst flex_int16_t yy_chk[45] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 9, 25, 24, 21, 13, 9, 9, 9, 9, 9, - 10, 10, 10, 15, 15, 17, 17, 7, 3, 17, - 26, 26, 26, 23, 23, 23, 23, 23, 23, 23, + 10, 10, 7, 10, 15, 15, 17, 17, 17, 26, + 26, 26, 3, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23 } ; @@ -485,12 +491,8 @@ char *yytext; * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. */ -#line 21 "fmd_scanner.l" +#line 17 "fmd_scanner.l" #include "fmd_parser.h" #include <assert.h> @@ -498,7 +500,7 @@ char *yytext; int parse_integer(char *src, int base); int copy_string(const char *src); -#line 502 "<stdout>" +#line 504 "<stdout>" #define INITIAL 0 @@ -531,11 +533,11 @@ void yyset_extra (YY_EXTRA_TYPE user_defined ); FILE *yyget_in (void ); -void yyset_in (FILE * in_str ); +void yyset_in (FILE * _in_str ); FILE *yyget_out (void ); -void yyset_out (FILE * out_str ); +void yyset_out (FILE * _out_str ); yy_size_t yyget_leng (void ); @@ -543,7 +545,7 @@ char *yyget_text (void ); int yyget_lineno (void ); -void yyset_lineno (int line_number ); +void yyset_lineno (int _line_number ); /* Macros after this point can all be overridden by user definitions in * section 1. @@ -557,8 +559,12 @@ extern int yywrap (void ); #endif #endif +#ifndef YY_NO_UNPUT + static void yyunput (int c,char *buf_ptr ); +#endif + #ifndef yytext_ptr static void yy_flex_strncpy (char *,yyconst char *,int ); #endif @@ -671,7 +677,7 @@ extern int yylex (void); /* Code executed at the end of each rule. */ #ifndef YY_BREAK -#define YY_BREAK break; +#define YY_BREAK /*LINTED*/break; #endif #define YY_RULE_SETUP \ @@ -681,9 +687,9 @@ extern int yylex (void); */ YY_DECL { - register yy_state_type yy_current_state; - register char *yy_cp, *yy_bp; - register int yy_act; + yy_state_type yy_current_state; + char *yy_cp, *yy_bp; + int yy_act; if ( !(yy_init) ) { @@ -712,12 +718,12 @@ YY_DECL } { -#line 34 "fmd_scanner.l" +#line 30 "fmd_scanner.l" -#line 719 "<stdout>" +#line 725 "<stdout>" - while ( 1 ) /* loops until end-of-file is reached */ + while ( /*CONSTCOND*/1 ) /* loops until end-of-file is reached */ { yy_cp = (yy_c_buf_p); @@ -733,7 +739,7 @@ YY_DECL yy_match: do { - register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)] ; + YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)] ; if ( yy_accept[yy_current_state] ) { (yy_last_accepting_state) = yy_current_state; @@ -775,7 +781,7 @@ do_action: /* This label is used only to access EOF actions. */ case 1: /* rule 1 can match eol */ YY_RULE_SETUP -#line 36 "fmd_scanner.l" +#line 32 "fmd_scanner.l" /* Eat whitespace. */ YY_BREAK case 2: @@ -783,42 +789,42 @@ case 2: (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 37 "fmd_scanner.l" +#line 33 "fmd_scanner.l" /* Eat comments. */ YY_BREAK case 3: -#line 39 "fmd_scanner.l" +#line 35 "fmd_scanner.l" case 4: YY_RULE_SETUP -#line 39 "fmd_scanner.l" +#line 35 "fmd_scanner.l" return parse_integer(yytext, 10); YY_BREAK case 5: YY_RULE_SETUP -#line 40 "fmd_scanner.l" +#line 36 "fmd_scanner.l" return OCTAL; YY_BREAK case 6: YY_RULE_SETUP -#line 41 "fmd_scanner.l" +#line 37 "fmd_scanner.l" return parse_integer(yytext + 2, 16); YY_BREAK case 7: YY_RULE_SETUP -#line 42 "fmd_scanner.l" +#line 38 "fmd_scanner.l" return copy_string(yytext); YY_BREAK case 8: YY_RULE_SETUP -#line 43 "fmd_scanner.l" +#line 39 "fmd_scanner.l" return *yytext; YY_BREAK case 9: YY_RULE_SETUP -#line 45 "fmd_scanner.l" +#line 41 "fmd_scanner.l" ECHO; YY_BREAK -#line 822 "<stdout>" +#line 828 "<stdout>" case YY_STATE_EOF(INITIAL): yyterminate(); @@ -961,9 +967,9 @@ case YY_STATE_EOF(INITIAL): */ static int yy_get_next_buffer (void) { - register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; - register char *source = (yytext_ptr); - register int number_to_move, i; + char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; + char *source = (yytext_ptr); + yy_size_t number_to_move, i; int ret_val; if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] ) @@ -992,7 +998,7 @@ static int yy_get_next_buffer (void) /* Try to read more data. */ /* First move last chars to start of buffer. */ - number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1; + number_to_move = (yy_size_t) ((yy_c_buf_p) - (yytext_ptr)) - 1; for ( i = 0; i < number_to_move; ++i ) *(dest++) = *(source++); @@ -1074,9 +1080,9 @@ static int yy_get_next_buffer (void) else ret_val = EOB_ACT_CONTINUE_SCAN; - if ((yy_size_t) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { + if ((int) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { /* Extend the array by 50%, plus the number we really need. */ - yy_size_t new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); + int new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size ); if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" ); @@ -1095,14 +1101,14 @@ static int yy_get_next_buffer (void) static yy_state_type yy_get_previous_state (void) { - register yy_state_type yy_current_state; - register char *yy_cp; + yy_state_type yy_current_state; + char *yy_cp; yy_current_state = (yy_start); for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp ) { - register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1); + YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1); if ( yy_accept[yy_current_state] ) { (yy_last_accepting_state) = yy_current_state; @@ -1127,10 +1133,10 @@ static int yy_get_next_buffer (void) */ static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state ) { - register int yy_is_jam; - register char *yy_cp = (yy_c_buf_p); + int yy_is_jam; + char *yy_cp = (yy_c_buf_p); - register YY_CHAR yy_c = 1; + YY_CHAR yy_c = 1; if ( yy_accept[yy_current_state] ) { (yy_last_accepting_state) = yy_current_state; @@ -1148,9 +1154,11 @@ static int yy_get_next_buffer (void) return yy_is_jam ? 0 : yy_current_state; } - static void yyunput (int c, register char * yy_bp ) +#ifndef YY_NO_UNPUT + + static void yyunput (int c, char * yy_bp ) { - register char *yy_cp; + char *yy_cp; yy_cp = (yy_c_buf_p); @@ -1160,10 +1168,10 @@ static int yy_get_next_buffer (void) if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 ) { /* need to shift things up to make room */ /* +2 for EOB chars. */ - register yy_size_t number_to_move = (yy_n_chars) + 2; - register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[ + yy_size_t number_to_move = (yy_n_chars) + 2; + char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[ YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2]; - register char *source = + char *source = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]; while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) @@ -1185,6 +1193,8 @@ static int yy_get_next_buffer (void) (yy_c_buf_p) = yy_cp; } +#endif + #ifndef YY_NO_INPUT #ifdef __cplusplus static int yyinput (void) @@ -1334,7 +1344,7 @@ static void yy_load_buffer_state (void) if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); - b->yy_buf_size = size; + b->yy_buf_size = (yy_size_t)size; /* yy_ch_buf has to be 2 characters longer than the size given because * we need to put in 2 end-of-buffer characters. @@ -1489,7 +1499,7 @@ static void yyensure_buffer_stack (void) * scanner will even need a stack. We use 2 instead of 1 to avoid an * immediate realloc on the next call. */ - num_to_alloc = 1; + num_to_alloc = 1; /* After all that talk, this was set to 1 anyways... */ (yy_buffer_stack) = (struct yy_buffer_state**)yyalloc (num_to_alloc * sizeof(struct yy_buffer_state*) ); @@ -1506,7 +1516,7 @@ static void yyensure_buffer_stack (void) if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){ /* Increase the buffer to prepare for a possible push. */ - int grow_size = 8 /* arbitrary grow size */; + yy_size_t grow_size = 8 /* arbitrary grow size */; num_to_alloc = (yy_buffer_stack_max) + grow_size; (yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc @@ -1614,7 +1624,7 @@ YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, yy_size_t _yybytes_len static void yy_fatal_error (yyconst char* msg ) { - (void) fprintf( stderr, "%s\n", msg ); + (void) fprintf( stderr, "%s\n", msg ); exit( YY_EXIT_FAILURE ); } @@ -1680,29 +1690,29 @@ char *yyget_text (void) } /** Set the current line number. - * @param line_number + * @param _line_number line number * */ -void yyset_lineno (int line_number ) +void yyset_lineno (int _line_number ) { - yylineno = line_number; + yylineno = _line_number; } /** Set the input stream. This does not discard the current * input buffer. - * @param in_str A readable stream. + * @param _in_str A readable stream. * * @see yy_switch_to_buffer */ -void yyset_in (FILE * in_str ) +void yyset_in (FILE * _in_str ) { - yyin = in_str ; + yyin = _in_str ; } -void yyset_out (FILE * out_str ) +void yyset_out (FILE * _out_str ) { - yyout = out_str ; + yyout = _out_str ; } int yyget_debug (void) @@ -1710,9 +1720,9 @@ int yyget_debug (void) return yy_flex_debug; } -void yyset_debug (int bdebug ) +void yyset_debug (int _bdebug ) { - yy_flex_debug = bdebug ; + yy_flex_debug = _bdebug ; } static int yy_init_globals (void) @@ -1772,7 +1782,8 @@ int yylex_destroy (void) #ifndef yytext_ptr static void yy_flex_strncpy (char* s1, yyconst char * s2, int n ) { - register int i; + + int i; for ( i = 0; i < n; ++i ) s1[i] = s2[i]; } @@ -1781,7 +1792,7 @@ static void yy_flex_strncpy (char* s1, yyconst char * s2, int n ) #ifdef YY_NEED_STRLEN static int yy_flex_strlen (yyconst char * s ) { - register int n; + int n; for ( n = 0; s[n]; ++n ) ; @@ -1791,11 +1802,12 @@ static int yy_flex_strlen (yyconst char * s ) void *yyalloc (yy_size_t size ) { - return (void *) malloc( size ); + return (void *) malloc( size ); } void *yyrealloc (void * ptr, yy_size_t size ) { + /* The cast to (char *) in the following accommodates both * implementations that use char* generic pointers, and those * that use void* generic pointers. It works with the latter @@ -1808,12 +1820,12 @@ void *yyrealloc (void * ptr, yy_size_t size ) void yyfree (void * ptr ) { - free( (char *) ptr ); /* see yyrealloc() for (char *) cast */ + free( (char *) ptr ); /* see yyrealloc() for (char *) cast */ } #define YYTABLES_NAME "yytables" -#line 44 "fmd_scanner.l" +#line 41 "fmd_scanner.l" @@ -1849,3 +1861,4 @@ int copy_string(const char *src) yylval.strval = strdup(src); return STRING; } + diff --git a/util/cbfstool/fmd_scanner.h_shipped b/util/cbfstool/fmd_scanner.h_shipped index 595b530..0ac158d 100644 --- a/util/cbfstool/fmd_scanner.h_shipped +++ b/util/cbfstool/fmd_scanner.h_shipped @@ -2,7 +2,7 @@ #define yyHEADER_H 1 #define yyIN_HEADER 1 -#line 6 "fmd_scanner.h" +#line 6 "fmd_scanner.h_shipped" #define YY_INT_ALIGNED short int @@ -10,8 +10,8 @@ #define FLEX_SCANNER #define YY_FLEX_MAJOR_VERSION 2 -#define YY_FLEX_MINOR_VERSION 5 -#define YY_FLEX_SUBMINOR_VERSION 39 +#define YY_FLEX_MINOR_VERSION 6 +#define YY_FLEX_SUBMINOR_VERSION 0 #if YY_FLEX_SUBMINOR_VERSION > 0 #define FLEX_BETA #endif @@ -155,7 +155,7 @@ struct yy_buffer_state /* Number of characters read into yy_ch_buf, not including EOB * characters. */ - yy_size_t yy_n_chars; + int yy_n_chars; /* Whether we "own" the buffer - i.e., we know we created it, * and can realloc() it to grow it, and should free() it to @@ -207,12 +207,15 @@ void yyfree (void * ); /* Begin user sect3 */ -#define yywrap() 1 +#define yywrap() (/*CONSTCOND*/1) #define YY_SKIP_YYWRAP extern int yylineno; extern char *yytext; +#ifdef yytext_ptr +#undef yytext_ptr +#endif #define yytext_ptr yytext #ifdef YY_HEADER_EXPORT_START_CONDITIONS @@ -247,11 +250,11 @@ void yyset_extra (YY_EXTRA_TYPE user_defined ); FILE *yyget_in (void ); -void yyset_in (FILE * in_str ); +void yyset_in (FILE * _in_str ); FILE *yyget_out (void ); -void yyset_out (FILE * out_str ); +void yyset_out (FILE * _out_str ); yy_size_t yyget_leng (void ); @@ -259,7 +262,7 @@ char *yyget_text (void ); int yyget_lineno (void ); -void yyset_lineno (int line_number ); +void yyset_lineno (int _line_number ); /* Macros after this point can all be overridden by user definitions in * section 1. @@ -325,9 +328,9 @@ extern int yylex (void); #undef YY_DECL #endif -#line 44 "fmd_scanner.l" +#line 41 "fmd_scanner.l" -#line 332 "fmd_scanner.h" +#line 335 "fmd_scanner.h_shipped" #undef yyIN_HEADER #endif /* yyHEADER_H */ diff --git a/util/cbfstool/fmd_scanner.l b/util/cbfstool/fmd_scanner.l index efcd342..8296959 100644 --- a/util/cbfstool/fmd_scanner.l +++ b/util/cbfstool/fmd_scanner.l @@ -34,7 +34,7 @@ MULTIPLIER [KMG] 0{MULTIPLIER}? | [1-9][0-9]*{MULTIPLIER}? return parse_integer(yytext, 10); 0[0-9]+{MULTIPLIER}? return OCTAL; -0[xX][0-9a-f]+{MULTIPLIER}? return parse_integer(yytext + 2, 16); +0[xX][0-9a-fA-F]+{MULTIPLIER}? return parse_integer(yytext + 2, 16); [^#@{}()[:space:]]* return copy_string(yytext); . return *yytext;

1 0

Patch merged into coreboot/master: intel/amenia: Configure unused Pads
by gerrit＠coreboot.org 28 Jun '16

28 Jun '16

the following patch was just integrated into master: commit 2dd226a7134d953dfc6dd0b1f319519c2cb237e9 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Thu May 26 14:18:41 2016 -0700 intel/amenia: Configure unused Pads Configure unused Pads as NC and sort the pads according to the gpio community. Move the pad configurations from mainboard to gpio.h BUG=none TEST=Boot to OS and check all functionalities. Change-Id: I8e9eeebf5d75c71c521649c72612c06f3fa43701 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Reviewed-on: https://review.coreboot.org/15327 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15327 for details. -gerrit

1 0

Patch set updated for coreboot: skylake: Generate ACPI for I2C devices
by Duncan Laurie 28 Jun '16

28 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15291 -gerrit commit 2281ccb0919561d1a4539c78a48d4d3b6a12325e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 21 10:41:19 2016 -0700 skylake: Generate ACPI for I2C devices Have the Skylake SOC generate ACPI Devices for the enabled I2C controllers instead of passing it in the DSDT with static timings. The timing values are generated from the controller clock speed and are more accurate than the hardcoded values that were in the ASL which were originally copied from Broadwell where the controller is running at a different clock speed... Additionally it is now possible for a board to override the values using devicetree.cb. If zero is passed in for SCL HCNT or LCNT then the kernel will generate its own timing using the same formula, but if the SDA hold time value is zero the kernel will NOT generate a correct value and the SDA hold time may be incorrect. The logic in the SSDT generator is a bit more complicated than I wanted but the flexibility for board-level override is important as there may be extra load on an I2C bus and a board may need to tune these values to get stable I2C operation on that bus. This was tested on the Chell platform to ensure all the I2C devices on the board are still operational with these new timing values. Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/acpi/serialio.asl | 55 --------------------- src/soc/intel/skylake/chip.h | 3 ++ src/soc/intel/skylake/i2c.c | 84 +++++++++++++++++++++++++++++---- src/soc/intel/skylake/romstage/i2c.c | 14 +++++- 4 files changed, 90 insertions(+), 66 deletions(-) diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl index f274be8..4f74320 100644 --- a/src/soc/intel/skylake/acpi/serialio.asl +++ b/src/soc/intel/skylake/acpi/serialio.asl @@ -16,61 +16,6 @@ /* Intel Serial IO Devices */ -Device (I2C0) -{ - Name (_ADR, 0x00150000) - Name (_DDN, "Serial IO I2C Controller 0") - - Name (SSCN, Package () { 432, 507, 30 }) - Name (FMCN, Package () { 72, 160, 30 }) -} - -Device (I2C1) -{ - Name (_ADR, 0x00150001) - Name (_DDN, "Serial IO I2C Controller 1") - - Name (SSCN, Package () { 528, 640, 30 }) - Name (FMCN, Package () { 128, 160, 30 }) - Name (FPCN, Package () { 48, 64, 30}) -} - -Device (I2C2) -{ - Name (_ADR, 0x00150002) - Name (_DDN, "Serial IO I2C Controller 2") - - Name (SSCN, Package () { 432, 507, 30 }) - Name (FMCN, Package () { 72, 160, 30 }) -} - -Device (I2C3) -{ - Name (_ADR, 0x00150003) - Name (_DDN, "Serial IO I2C Controller 3") - - Name (SSCN, Package () { 432, 507, 30 }) - Name (FMCN, Package () { 72, 160, 30 }) -} - -Device (I2C4) -{ - Name (_ADR, 0x00190002) - Name (_DDN, "Serial IO I2C Controller 4") - - Name (SSCN, Package () { 432, 507, 30 }) - Name (FMCN, Package () { 72, 160, 30 }) -} - -Device (I2C5) -{ - Name (_ADR, 0x00190002) - Name (_DDN, "Serial IO I2C Controller 5") - - Name (SSCN, Package () { 432, 507, 30 }) - Name (FMCN, Package () { 72, 160, 30 }) -} - Device (SPI0) { Name (_ADR, 0x001E0002) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index fe03e59..eec6f1e 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -24,6 +24,7 @@ #include <stdint.h> #include <soc/gpio_defs.h> #include <soc/gpe.h> +#include <soc/intel/common/lpss_i2c.h> #include <soc/pci_devs.h> #include <soc/pmc.h> #include <soc/serialio.h> @@ -44,6 +45,8 @@ struct skylake_i2c_config { enum i2c_speed speed; /* Bus should be enabled prior to ramstage with temporary base */ int early_init; + /* Custom bus speed configuration { scl_lcnt, scl_hcnt, sda_hold } */ + struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT]; }; struct soc_intel_skylake_config { diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c index 64d39cd..8377b50 100644 --- a/src/soc/intel/skylake/i2c.c +++ b/src/soc/intel/skylake/i2c.c @@ -13,12 +13,15 @@ * GNU General Public License for more details. */ +#include <arch/acpigen.h> #include <device/device.h> #include <device/i2c.h> #include <device/pci.h> +#include <device/pci_def.h> #include <device/pci_ids.h> #include <soc/intel/common/lpss_i2c.h> #include <soc/ramstage.h> +#include <string.h> uintptr_t lpss_i2c_base_address(unsigned bus) { @@ -54,26 +57,87 @@ static int i2c_dev_to_bus(struct device *dev) static void i2c_dev_init(struct device *dev) { struct soc_intel_skylake_config *config = dev->chip_info; - int bus = i2c_dev_to_bus(dev); + const struct lpss_i2c_speed_config *sptr; + enum i2c_speed speed; + int i, bus = i2c_dev_to_bus(dev); if (!config || bus < 0) return; - lpss_i2c_init(bus, config->i2c[bus].speed ? : I2C_SPEED_FAST); + speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; + lpss_i2c_init(bus, speed); + + /* Apply custom speed config if it has been set by the board */ + for (i = 0; i < LPSS_I2C_SPEED_CONFIG_COUNT; i++) { + sptr = &config->i2c[bus].speed_config[i]; + if (sptr->speed == speed) { + lpss_i2c_set_speed_config(bus, sptr); + break; + } + } +} + +/* Generate ACPI I2C device objects */ +static void i2c_fill_ssdt(struct device *dev) +{ + struct soc_intel_skylake_config *config = dev->chip_info; + struct lpss_i2c_speed_config *sptr, sgen; + uint32_t pci_address; + int i, bus = i2c_dev_to_bus(dev); + enum i2c_speed speeds[LPSS_I2C_SPEED_CONFIG_COUNT] = { + I2C_SPEED_STANDARD, + I2C_SPEED_FAST, + I2C_SPEED_FAST_PLUS, + I2C_SPEED_HIGH, + }; + + if (!config || bus < 0) + return; + + acpigen_write_scope(acpi_device_scope(dev)); + acpigen_write_device(acpi_device_name(dev)); + + /* Build ACPI PCI address */ + pci_address = PCI_SLOT(dev->path.pci.devfn) << 16; + pci_address |= PCI_FUNC(dev->path.pci.devfn); + acpigen_write_name_dword("_ADR", pci_address); + + /* Report timing values for the OS driver */ + for (i = 0; i < LPSS_I2C_SPEED_CONFIG_COUNT; i++) { + /* Generate speed config for default case */ + if (lpss_i2c_gen_speed_config(speeds[i], &sgen) < 0) + continue; + + /* Apply board specific override for this speed if found */ + for (sptr = config->i2c[bus].speed_config; + sptr && sptr->speed; sptr++) { + if (sptr->speed == speeds[i]) { + memcpy(&sgen, sptr, sizeof(sgen)); + break; + } + } + + /* Generate ACPI based on selected speed config */ + lpss_i2c_acpi_write_speed_config(&sgen); + } + + acpigen_pop_len(); + acpigen_pop_len(); } static struct i2c_bus_operations i2c_bus_ops = { - .dev_to_bus = &i2c_dev_to_bus, + .dev_to_bus = &i2c_dev_to_bus, }; static struct device_operations i2c_dev_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_smbus, - .ops_pci = &soc_pci_ops, - .ops_i2c_bus = &i2c_bus_ops, - .init = &i2c_dev_init, + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .scan_bus = &scan_smbus, + .ops_pci = &soc_pci_ops, + .ops_i2c_bus = &i2c_bus_ops, + .init = &i2c_dev_init, + .acpi_fill_ssdt_generator = &i2c_fill_ssdt, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/skylake/romstage/i2c.c b/src/soc/intel/skylake/romstage/i2c.c index 64e6924..3d2e994 100644 --- a/src/soc/intel/skylake/romstage/i2c.c +++ b/src/soc/intel/skylake/romstage/i2c.c @@ -46,6 +46,8 @@ static void i2c_early_init_bus(unsigned bus) { ROMSTAGE_CONST struct soc_intel_skylake_config *config; ROMSTAGE_CONST struct device *tree_dev; + const struct lpss_i2c_speed_config *sptr; + enum i2c_speed speed; pci_devfn_t dev; unsigned devfn; uintptr_t base; @@ -84,7 +86,17 @@ static void i2c_early_init_bus(unsigned bus) write32(reg, value); /* Initialize the controller */ - lpss_i2c_init(bus, config->i2c[bus].speed ? : I2C_SPEED_FAST); + speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; + lpss_i2c_init(bus, speed); + + /* Apply custom speed config if it has been set by the board */ + for (value = 0; value < LPSS_I2C_SPEED_CONFIG_COUNT; value++) { + sptr = &config->i2c[bus].speed_config[value]; + if (sptr->speed == speed) { + lpss_i2c_set_speed_config(bus, sptr); + break; + } + } } void i2c_early_init(void)

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New patch to review for coreboot: google/reef: ACPI: Move trackpad to SSDT and remove TPM
by Duncan Laurie 28 Jun '16

28 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15481 -gerrit commit 10582027bace752c7943f62c2d258e9fc4fcc725 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 27 11:05:16 2016 -0700 google/reef: ACPI: Move trackpad to SSDT and remove TPM Instantiate the touchpad using the drivers/i2c/generic device driver to generate the ACPI object in the SSDT. There is not currently a separate wake pin for this device, this will be added in EVT hardware. This was tested on the reef board by ensuring that the touchpad device continues to work in the OS. Also remove the LPC TPM from the DSDT as it is not present. Change-Id: I3151a28f628e66f63033398d6fab9fd8f5dfc37b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 3 ++ src/mainboard/google/reef/acpi/mainboard.asl | 48 +--------------------------- src/mainboard/google/reef/devicetree.cb | 9 +++++- 3 files changed, 12 insertions(+), 48 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index d64598d..c271f78 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -25,6 +25,9 @@ config CHROMEOS select VBOOT_OPROM_MATTERS select VIRTUAL_DEV_SWITCH +config DRIVERS_I2C_GENERIC + default y + config MAINBOARD_DIR string default google/reef diff --git a/src/mainboard/google/reef/acpi/mainboard.asl b/src/mainboard/google/reef/acpi/mainboard.asl index 5471488..5b6e976 100644 --- a/src/mainboard/google/reef/acpi/mainboard.asl +++ b/src/mainboard/google/reef/acpi/mainboard.asl @@ -33,54 +33,8 @@ Scope (\_SB) } } -Scope (\_SB.PCI0.I2C4) -{ - /* Standard Mode: HCNT, LCNT, SDA Hold Register */ - /* SDA Hold register value of 40 indicates - * sda hold time of 0.3us for ic_clk of 133MHz - */ - Name (SSCN, Package () { 0, 0, 40 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Register */ - /* SDA Hold register value of 40 indicates - * sda hold time of 0.3us for ic_clk of 133MHz - */ - Name (FMCN, Package () { 0, 0, 40 }) - - Device (ETPA) - { - Name (_HID, "ELAN0000") - Name (_DDN, "Elan Touchpad") - Name (_UID, 1) - Name (ISTP, 1) /* Touchpad */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x15, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.PCI0.I2C4", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - TOUCHPAD_INT - } - }) - - Method (_STA) - { - Return (0xF) - } - } -} - -/* - * LPC Trusted Platform Module - */ Scope (\_SB.PCI0.LPCB) { - #include <drivers/pc80/tpm/acpi/tpm.asl> + /* Chrome OS Embedded Controller */ #include "ec.asl" } diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index d2b295f..e0831f4 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -61,7 +61,14 @@ chip soc/intel/apollolake device pci 16.1 on end # - I2C 1 device pci 16.2 on end # - I2C 2 device pci 16.3 on end # - I2C 3 - device pci 17.0 on end # - I2C 4 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + device i2c 15 on end + end + end # - I2C 4 device pci 17.1 on end # - I2C 5 device pci 17.2 on end # - I2C 6 device pci 17.3 on end # - I2C 7

1 0

New patch to review for coreboot: apollolake: Add support for LPSS I2C driver
by Duncan Laurie 28 Jun '16

28 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15480 -gerrit commit 0c5854b799c97a54f4369d51c3232e86af44fd77 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 27 10:57:13 2016 -0700 apollolake: Add support for LPSS I2C driver Support the I2C interfaces on this SOC using the intel common lpss_i2c driver. The controllers are supported in pre-ram environments by setting a temporary base address in bootblock and in ramstage using the natuarlly enumerated base address. The base speed of this controller is 133MHz and the SCL/SDA timing values that are reported to the OS are calculated using that clock. This was tested on a google/reef board doing I2C transactions to the trackpad both in verstage and in ramstage. Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/apollolake/Kconfig | 8 +- src/soc/intel/apollolake/Makefile.inc | 3 + src/soc/intel/apollolake/acpi/lpss.asl | 57 ++-------- src/soc/intel/apollolake/chip.h | 17 +++ src/soc/intel/apollolake/i2c.c | 161 +++++++++++++++++++++++++++ src/soc/intel/apollolake/i2c_early.c | 116 +++++++++++++++++++ src/soc/intel/apollolake/include/soc/i2c.h | 50 +++++++++ src/soc/intel/apollolake/include/soc/iomap.h | 5 +- 8 files changed, 367 insertions(+), 50 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 98ce7d8..749c15b 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -38,8 +38,9 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select SMM_TSEG select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_SMI select SOC_INTEL_COMMON_ACPI + select SOC_INTEL_COMMON_LPSS_I2C + select SOC_INTEL_COMMON_SMI select SPI_FLASH select UDELAY_TSC select TSC_CONSTANT_RATE @@ -93,6 +94,11 @@ config CPU_ADDR_BITS int default 36 +config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ + depends on SOC_INTEL_COMMON_LPSS_I2C + int + default 133 + config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL hex "MMIO base address for UART" diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 7326f14..c639eec 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -23,6 +23,7 @@ bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c +romstage-y += i2c_early.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += lpc_lib.c romstage-y += memmap.c @@ -45,6 +46,7 @@ ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += gpio.c ramstage-y += graphics.c +ramstage-y += i2c.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += lpc.c ramstage-y += lpc_lib.c @@ -68,6 +70,7 @@ postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c verstage-y += car.c +verstage-y += i2c_early.c verstage-y += memmap.c verstage-y += mmap_boot.c verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/acpi/lpss.asl b/src/soc/intel/apollolake/acpi/lpss.asl index ab97374..f6fd542 100644 --- a/src/soc/intel/apollolake/acpi/lpss.asl +++ b/src/soc/intel/apollolake/acpi/lpss.asl @@ -65,52 +65,13 @@ scope (\_SB.PCI0) { Name (_DDN, "Intel(R) SPI Controller #3") } - - /* LPIO2 I2C #0 */ - Device(I2C0) { - Name (_ADR, 0x00160000) - Name (_DDN, "Intel(R) I2C Controller #0") - } - - /* LPIO2 I2C #1 */ - Device(I2C1) { - Name (_ADR, 0x00160001) - Name (_DDN, "Intel(R) I2C Controller #1") - } - - /* LPIO2 I2C #2 */ - Device(I2C2) { - Name (_ADR, 0x00160002) - Name (_DDN, "Intel(R) I2C Controller #2") - } - - /* LPIO2 I2C #3 */ - Device(I2C3) { - Name (_ADR, 0x00160003) - Name (_DDN, "Intel(R) I2C Controller #3") - } - - /* LPIO2 I2C #4 */ - Device(I2C4) { - Name (_ADR, 0x00170000) - Name (_DDN, "Intel(R) I2C Controller #4") - } - - /* LPIO2 I2C #5 */ - Device(I2C5) { - Name (_ADR, 0x00170001) - Name (_DDN, "Intel(R) I2C Controller #5") - } - - /* LPIO2 I2C #6 */ - Device(I2C6) { - Name (_ADR, 0x00170002) - Name (_DDN, "Intel(R) I2C Controller #6") - } - - /* LPIO2 I2C #7 */ - Device(I2C7) { - Name (_ADR, 0x00170003) - Name (_DDN, "Intel(R) I2C Controller #7") - } + /* I2C Controllers are defined in the SSDT */ + External (I2C0, DeviceObj) + External (I2C1, DeviceObj) + External (I2C2, DeviceObj) + External (I2C3, DeviceObj) + External (I2C4, DeviceObj) + External (I2C5, DeviceObj) + External (I2C6, DeviceObj) + External (I2C7, DeviceObj) } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ef82c53..c83f973 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -18,7 +18,21 @@ #ifndef _SOC_APOLLOLAKE_CHIP_H_ #define _SOC_APOLLOLAKE_CHIP_H_ +#include <soc/gpio.h> +#include <soc/intel/common/lpss_i2c.h> +#include <device/i2c.h> + #define CLKREQ_DISABLED 0xf +#define APOLLOLAKE_I2C_DEV_MAX 8 + +struct apollolake_i2c_config { + /* Bus should be enabled prior to ramstage with temporary base */ + int early_init; + /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */ + enum i2c_speed speed; + /* Specific bus speed configuration */ + struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT]; +}; /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ enum serirq_mode { @@ -79,6 +93,9 @@ struct soc_intel_apollolake_config { /* Integrated Sensor Hub */ uint8_t integrated_sensor_hub_enable; + + /* I2C bus configuration */ + struct apollolake_i2c_config i2c[APOLLOLAKE_I2C_DEV_MAX]; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/i2c.c b/src/soc/intel/apollolake/i2c.c new file mode 100644 index 0000000..8eaa2b8 --- /dev/null +++ b/src/soc/intel/apollolake/i2c.c @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <device/device.h> +#include <device/i2c.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <soc/i2c.h> +#include <soc/intel/common/lpss_i2c.h> +#include <soc/pci_devs.h> +#include <soc/pci_ids.h> +#include <string.h> +#include "chip.h" + +uintptr_t lpss_i2c_base_address(unsigned bus) +{ + unsigned devfn; + struct device *dev; + struct resource *res; + + /* bus -> devfn */ + devfn = i2c_bus_to_devfn(bus); + if (devfn >= 0) { + /* devfn -> dev */ + dev = dev_find_slot(0, devfn); + if (dev) { + /* dev -> bar0 */ + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) + return res->base; + } + } + + return (uintptr_t)NULL; +} + +static int i2c_dev_to_bus(struct device *dev) +{ + return i2c_devfn_to_bus(dev->path.pci.devfn); +} + +/* + * The device should already be enabled and out of reset, + * either from early init in coreboot or FSP-S. + */ +static void i2c_dev_init(struct device *dev) +{ + struct soc_intel_apollolake_config *config = dev->chip_info; + const struct lpss_i2c_speed_config *sptr; + enum i2c_speed speed; + int i, bus = i2c_dev_to_bus(dev); + + if (!config || bus < 0) + return; + + speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; + lpss_i2c_init(bus, speed); + + /* Apply custom speed config if it has been set by the board */ + for (i = 0; i < LPSS_I2C_SPEED_CONFIG_COUNT; i++) { + sptr = &config->i2c[bus].speed_config[i]; + if (sptr->speed == speed) { + lpss_i2c_set_speed_config(bus, sptr); + break; + } + } +} + +static void i2c_fill_ssdt(struct device *dev) +{ + struct soc_intel_apollolake_config *config = dev->chip_info; + struct lpss_i2c_speed_config *sptr, sgen; + uint32_t pci_address; + int i, bus = i2c_dev_to_bus(dev); + enum i2c_speed speeds[LPSS_I2C_SPEED_CONFIG_COUNT] = { + I2C_SPEED_STANDARD, + I2C_SPEED_FAST, + I2C_SPEED_FAST_PLUS, + I2C_SPEED_HIGH, + }; + + if (!config || bus < 0) + return; + + acpigen_write_scope(acpi_device_scope(dev)); + acpigen_write_device(acpi_device_name(dev)); + + /* Build ACPI PCI address */ + pci_address = PCI_SLOT(dev->path.pci.devfn) << 16; + pci_address |= PCI_FUNC(dev->path.pci.devfn); + acpigen_write_name_dword("_ADR", pci_address); + + /* Report timing values for the OS driver */ + for (i = 0; i < LPSS_I2C_SPEED_CONFIG_COUNT; i++) { + /* Generate speed config for default case */ + if (lpss_i2c_gen_speed_config(speeds[i], &sgen) < 0) + continue; + + /* Apply board specific override for this speed if found */ + for (sptr = config->i2c[bus].speed_config; + sptr && sptr->speed; sptr++) { + if (sptr->speed == speeds[i]) { + memcpy(&sgen, sptr, sizeof(sgen)); + break; + } + } + + /* Generate ACPI based on selected speed config */ + lpss_i2c_acpi_write_speed_config(&sgen); + } + + acpigen_pop_len(); + acpigen_pop_len(); +} + +static struct i2c_bus_operations i2c_bus_ops = { + .dev_to_bus = &i2c_dev_to_bus, +}; + +static struct device_operations i2c_dev_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .scan_bus = &scan_smbus, + .ops_i2c_bus = &i2c_bus_ops, + .init = &i2c_dev_init, + .acpi_fill_ssdt_generator = &i2c_fill_ssdt, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_APOLLOLAKE_I2C0, + PCI_DEVICE_ID_APOLLOLAKE_I2C1, + PCI_DEVICE_ID_APOLLOLAKE_I2C2, + PCI_DEVICE_ID_APOLLOLAKE_I2C3, + PCI_DEVICE_ID_APOLLOLAKE_I2C4, + PCI_DEVICE_ID_APOLLOLAKE_I2C5, + PCI_DEVICE_ID_APOLLOLAKE_I2C6, + PCI_DEVICE_ID_APOLLOLAKE_I2C7, + 0, +}; + +static const struct pci_driver pch_i2c __pci_driver = { + .ops = &i2c_dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/apollolake/i2c_early.c b/src/soc/intel/apollolake/i2c_early.c new file mode 100644 index 0000000..968e993 --- /dev/null +++ b/src/soc/intel/apollolake/i2c_early.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <device/device.h> +#include <device/i2c.h> +#include <device/pci_def.h> +#include <soc/intel/common/lpss_i2c.h> +#include <soc/i2c.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include "chip.h" + +static int i2c_early_init_bus(unsigned bus) +{ + ROMSTAGE_CONST struct soc_intel_apollolake_config *config; + ROMSTAGE_CONST struct device *tree_dev; + const struct lpss_i2c_speed_config *sptr; + enum i2c_speed speed; + pci_devfn_t dev; + unsigned devfn; + uintptr_t base; + uint32_t value; + void *reg; + + /* Find the PCI device for this bus controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) { + printk(BIOS_ERR, "I2C%u device not found\n", bus); + return -1; + } + + /* Look up the controller device in the devicetree */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + tree_dev = dev_find_slot(0, devfn); + if (!tree_dev || !tree_dev->enabled) { + printk(BIOS_ERR, "I2C%u device not enabled\n", bus); + return -1; + } + + /* Skip if not enabled for early init */ + config = tree_dev->chip_info; + if (!config || !config->i2c[bus].early_init) { + printk(BIOS_ERR, "I2C%u not enabled for early init\n", bus); + return -1; + } + + /* Prepare early base address for access before memory */ + base = PRERAM_I2C_BASE_ADDRESS(bus); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); + pci_write_config32(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Take device out of reset */ + reg = (void *)(base + I2C_LPSS_REG_RESET); + value = read32(reg); + value |= I2C_LPSS_RESET_RELEASE_HC; + write32(reg, value); + + /* Initialize the controller */ + speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; + if (lpss_i2c_init(bus, speed) < 0) { + printk(BIOS_ERR, "I2C%u failed to initialize\n", bus); + return -1; + } + + /* Apply custom speed config if it has been set by the board */ + for (value = 0; value < LPSS_I2C_SPEED_CONFIG_COUNT; value++) { + sptr = &config->i2c[bus].speed_config[value]; + if (sptr->speed == speed) { + lpss_i2c_set_speed_config(bus, sptr); + break; + } + } + + return 0; +} + +uintptr_t lpss_i2c_base_address(unsigned bus) +{ + unsigned devfn; + pci_devfn_t dev; + uintptr_t base; + + /* Find device+function for this controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) + return (uintptr_t)NULL; + + /* Form a PCI address for this device */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + + /* Read the first base address for this device */ + base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); + + /* Attempt to initialize bus if base is not set yet */ + if (!base && !i2c_early_init_bus(bus)) + base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), + 16); + + return base; +} diff --git a/src/soc/intel/apollolake/include/soc/i2c.h b/src/soc/intel/apollolake/include/soc/i2c.h new file mode 100644 index 0000000..7a42e1a --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/i2c.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_I2C_H_ +#define _SOC_APOLLOLAKE_I2C_H_ + +#include <device/pci_def.h> +#include <soc/pci_devs.h> + +/* I2C Controller Reset in MMIO private region */ +#define I2C_LPSS_REG_RESET 0x204 +#define I2C_LPSS_RESET_RELEASE_HC ((1 << 1) | (1 << 0)) +#define I2C_LPSS_RESET_RELEASE_IDMA (1 << 2) + +/* Convert I2C bus number to PCI device and function */ +static inline int i2c_bus_to_devfn(unsigned bus) +{ + if (bus >= 0 && bus <= 3) + return PCI_DEVFN(LPSS_DEV_SLOT_I2C_0123, bus); + else if (bus >= 4 && bus <= 7) + return PCI_DEVFN(LPSS_DEV_SLOT_I2C_4567, (bus - 4)); + else + return -1; +} + +/* Convert PCI device and function to I2C bus number */ +static inline int i2c_devfn_to_bus(unsigned devfn) +{ + if (PCI_SLOT(devfn) == LPSS_DEV_SLOT_I2C_0123) + return PCI_FUNC(devfn); + else if (PCI_SLOT(devfn) == LPSS_DEV_SLOT_I2C_4567) + return PCI_FUNC(devfn) + 4; + else + return -1; +} + +#endif /* _SOC_APOLLOLAKE_I2C_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 716c2a6..e9caeca 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -31,6 +31,9 @@ #define PMC_BAR1 0xfe044000 /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ -#define PRERAM_SPI_BASE_ADDRESS 0xfe010000 +#define PRERAM_SPI_BASE_ADDRESS 0xfe010000 + +/* Temporary BAR for early I2C bus access */ +#define PRERAM_I2C_BASE_ADDRESS(x) (0xfe020000 + (0x1000 * (x))) #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */

1 0

New patch to review for coreboot: apollolake: Add function to translate device into ACPI name
by Duncan Laurie 28 Jun '16

28 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15479 -gerrit commit e2f6dda724451687c0fe40477179a132f92073c4 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 27 10:51:17 2016 -0700 apollolake: Add function to translate device into ACPI name Add support for the soc_acpi_name() handler in the device operations structure to translate a device path into ACPI name. In order to make this more complete add some missing devices in include/soc/pci_devs.h. Change-Id: I517bc86d8d9fe70bfa0fc4eb3828681887239587 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/apollolake/chip.c | 58 +++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pci_devs.h | 18 ++++++++ 2 files changed, 76 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 821570b..79cde2e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -39,6 +39,63 @@ static void *vbt; static struct region_device vbt_rdev; +static const char *soc_acpi_name(struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + /* DSDT: acpi/northbridge.asl */ + case NB_DEVFN: + return "MCHC"; + case PCI_DEVFN(0x1f, 0): + /* DSDT: acpi/lpc.asl */ + return "LPCB"; + /* DSDT: acpi/xhci.asl */ + case PCI_DEVFN(0x15, 0): + return "XHCI"; + /* DSDT: acpi/lpss.asl */ + case PCI_DEVFN(LPSS_DEV_SLOT_UART, 0): + return "URT1"; + case PCI_DEVFN(LPSS_DEV_SLOT_UART, 1): + return "URT2"; + case PCI_DEVFN(LPSS_DEV_SLOT_UART, 2): + return "URT3"; + case PCI_DEVFN(LPSS_DEV_SLOT_UART, 3): + return "URT4"; + case PCI_DEVFN(LPSS_DEV_SLOT_SPI, 0): + return "SPI1"; + case PCI_DEVFN(LPSS_DEV_SLOT_SPI, 1): + return "SPI2"; + case PCI_DEVFN(LPSS_DEV_SLOT_SPI, 2): + return "SPI3"; + case PCI_DEVFN(LPSS_DEV_SLOT_PWM, 0): + return "PWM"; + /* SSDT: i2c.c */ + case PCI_DEVFN(LPSS_DEV_SLOT_I2C_0123, 0): + return "I2C0"; + case PCI_DEVFN(LPSS_DEV_SLOT_I2C_0123, 1): + return "I2C1"; + case PCI_DEVFN(LPSS_DEV_SLOT_I2C_0123, 2): + return "I2C2"; + case PCI_DEVFN(LPSS_DEV_SLOT_I2C_0123, 3): + return "I2C3"; + case PCI_DEVFN(LPSS_DEV_SLOT_I2C_4567, 0): + return "I2C4"; + case PCI_DEVFN(LPSS_DEV_SLOT_I2C_4567, 1): + return "I2C5"; + case PCI_DEVFN(LPSS_DEV_SLOT_I2C_4567, 2): + return "I2C6"; + case PCI_DEVFN(LPSS_DEV_SLOT_I2C_4567, 3): + return "I2C7"; + } + + return NULL; +} + static void pci_domain_set_resources(device_t dev) { assign_resources(dev->link_list); @@ -51,6 +108,7 @@ static struct device_operations pci_domain_ops = { .init = NULL, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, + .acpi_name = &soc_acpi_name, }; static struct device_operations cpu_bus_ops = { diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index fc046d1..ec2674d 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -39,12 +39,30 @@ #define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2) #define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3) +/* LPSS I2C */ +#define LPSS_DEV_SLOT_I2C_0123 0x16 /* I2C bus 0-3 */ +#define LPSS_DEV_SLOT_I2C_4567 0x17 /* I2C bus 4-7 */ + +/* LPSS SPI */ +#define LPSS_DEV_SLOT_SPI 0x19 + +/* LPSS PWM */ +#define LPSS_DEV_SLOT_PWM 0x1a + #define NB_BUS 0 #define NB_DEVFN PCI_DEVFN(0, 0) #define NB_DEV_ROOT PCI_DEV(NB_BUS, 0x0, 0) + +#define P2SB_DEVFN PCI_DEVFN(0xd, 0) #define P2SB_DEV PCI_DEV(0, 0xd, 0) + +#define PMC_DEVFN PCI_DEVFN(0xd, 1) #define PMC_DEV PCI_DEV(0, 0xd, 1) + +#define SPI_DEVFN PCI_DEVFN(0xd, 2) #define SPI_DEV PCI_DEV(0, 0xd, 2) + +#define LPC_DEVFN PCI_DEVFN(0x1f, 0) #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define ISH_DEVFN PCI_DEVFN(0x11, 0)

1 0

Patch set updated for coreboot: console/serialice: Add SerialICE
by Antonello Dettori 28 Jun '16

28 Jun '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14504 -gerrit commit 300e7ba06f61b3d902598f679542d068e0f29958 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Apr 25 11:00:17 2016 +0200 console/serialice: Add SerialICE Add Kconfig Option to build SerialICE shell into coreboot stages. You can select between romstage and ramstage. The SerialICE shell will be launched instead of coreboot console. As minimal system initialization is already done in coreboot, it should work on all boards. Tested with EHCI Debug on Lenovo T520 and Lenovo X60. Needs tests: * Ramstage * On other boards Change-Id: I1fa6eb4f40e0f625c8c8302d1580bcd2664d670b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/Kconfig | 33 +++ src/arch/x86/c_start.S | 2 +- src/arch/x86/exception.c | 7 +- src/console/Makefile.inc | 2 + src/console/console.c | 22 -- src/console/init.c | 3 + src/console/serialice.c | 430 ++++++++++++++++++++++++++++++++++++++++ src/console/serialice_priv.h | 103 ++++++++++ src/include/console/serialice.h | 30 +++ src/include/console/streams.h | 6 - src/include/console/uart.h | 10 +- src/include/console/usb.h | 11 +- src/include/serial-com.h | 24 +++ src/lib/Makefile.inc | 5 + src/lib/serial-com.c | 80 ++++++++ 15 files changed, 719 insertions(+), 49 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 1cb55c9..c13189d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1078,6 +1078,39 @@ config DEBUG_COVERAGE If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped. +config DEBUG_SERIALICE + bool "Enable SerialICE instead normal boot" + default n + depends on ARCH_X86 + depends on CONSOLE_SERIAL || CONSOLE_USB + depends on !GDB_STUB + help + If enabled, SerialICE will be run instead of normal boot. + You need to connect a serial cable or EHCI debug dongle to + communicate with SerialICE shell. + +if DEBUG_SERIALICE + +choice + prompt "SerialICE bootstage" + default DEBUG_SERIALICE_ROMSTAGE + help + Choose the stage SerialICE to start. You can choose between + ROMSTAGE and RAMSTAGE. + +config DEBUG_SERIALICE_ROMSTAGE + bool "Start SerialICE instead of Romstage" + depends on CONSOLE_SERIAL || USBDEBUG_IN_ROMSTAGE + help + Start SerialICE in romstage, right after minimal system initialization. + +config DEBUG_SERIALICE_RAMSTAGE + bool "Start SerialICE instead of Ramstage" + help + Start SerialICE in ramstage. +endchoice + +endif endmenu # These probably belong somewhere else, but they are needed somewhere. diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 6bda64f..ed6025c 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -111,7 +111,7 @@ _start: post_code(POST_PRE_HARDWAREMAIN) /* post fe */ #if CONFIG_GDB_WAIT - call gdb_hw_init + call serial_hw_init call gdb_stub_breakpoint #endif call main diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index b6e6ffb..c8f474f 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -14,6 +14,7 @@ #include <console/console.h> #include <console/streams.h> #include <string.h> +#include <serial-com.h> #if CONFIG_GDB_STUB @@ -231,17 +232,17 @@ static char out_buffer[BUFMAX]; static inline void stub_putc(int ch) { - gdb_tx_byte(ch); + serial_tx_byte(ch); } static inline void stub_flush(void) { - gdb_tx_flush(); + serial_tx_flush(); } static inline int stub_getc(void) { - return gdb_rx_byte(); + return serial_rx_byte(); } static int hex(char ch) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 0fee12a..e3015fe 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += vtxprintf.c printk.c vsprintf.c ramstage-y += init.c console.c ramstage-y += post.c ramstage-y += die.c +ramstage-$(CONFIG_DEBUG_SERIALICE_RAMSTAGE) += serialice.c smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c @@ -17,6 +18,7 @@ romstage-y += vtxprintf.c printk.c romstage-y += init.c console.c romstage-y += post.c romstage-y += die.c +romstage-$(CONFIG_DEBUG_SERIALICE_ROMSTAGE) += serialice.c postcar-y += vtxprintf.c printk.c postcar-y += init.c console.c diff --git a/src/console/console.c b/src/console/console.c index c4365f3..231b245 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -62,25 +62,3 @@ void console_tx_flush(void) __usb_tx_flush(); } - -#if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) -void gdb_hw_init(void) -{ - __gdb_hw_init(); -} - -void gdb_tx_byte(unsigned char byte) -{ - __gdb_tx_byte(byte); -} - -void gdb_tx_flush(void) -{ - __gdb_tx_flush(); -} - -unsigned char gdb_rx_byte(void) -{ - return __gdb_rx_byte(); -} -#endif diff --git a/src/console/init.c b/src/console/init.c index 8f40abb..66b751c 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <console/uart.h> +#include <console/serialice.h> #include <console/streams.h> #include <device/pci.h> #include <option.h> @@ -43,6 +44,8 @@ void console_init(void) console_hw_init(); + serialice_main(); + printk(BIOS_INFO, "\n\ncoreboot-%s%s %s " ENV_STRING " starting...\n", coreboot_version, coreboot_extra_version, coreboot_build); } diff --git a/src/console/serialice.c b/src/console/serialice.c new file mode 100644 index 0000000..dc57edb --- /dev/null +++ b/src/console/serialice.c @@ -0,0 +1,430 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <console/serialice.h> +#include <arch/io.h> +#include <serial-com.h> +#include "serialice_priv.h" + +#define VERSION "1.6" + +/* Uart wrapper functions */ + +static void sio_flush(void) +{ + serial_tx_flush(); +} + +static void sio_putc(u8 byte) +{ + serial_tx_byte(byte); +} + +static u8 sio_getc(void) +{ + u8 val = 0; + + val = serial_rx_byte(); + if (val) { +#if ECHO_MODE + sio_putc(val); +#endif + return val; + } + + return 0; +} + +/* String functions */ + +static void sio_putstring(const char *string) +{ + /* Very simple, no %d, %x etc. */ + while (*string) { + if (*string == '\n') + sio_putc('\r'); + sio_putc(*string); + string++; + } + sio_flush(); +} + +static void sio_put8(u8 data) +{ + u8 c; + + c = (data >> 4) & 0xf; + sio_put_nibble(c); + + c = data & 0xf; + sio_put_nibble(c); + sio_flush(); +} + +static void sio_put16(u16 data) +{ + int i; + u8 c; + + for (i = 12; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static void sio_put32(u32 data) +{ + int i; + u8 c; + + for (i = 28; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static u8 sio_get_nibble(void) +{ + u8 ret = 0; + u8 nibble = sio_getc(); + + if (nibble >= '0' && nibble <= '9') { + ret = (nibble - '0'); + } else if (nibble >= 'a' && nibble <= 'f') { + ret = (nibble - 'a') + 0xa; + } else if (nibble >= 'A' && nibble <= 'F') { + ret = (nibble - 'A') + 0xa; + } else { + sio_putstring("ERROR: parsing number\n"); + } + return ret; +} + +static u8 sio_get8(void) +{ + u8 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + return data; +} + +static u16 sio_get16(void) +{ + u16 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +static u32 sio_get32(void) +{ + u32 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +/* SerialICE interface functions */ + +static void serialice_read_memory(void) +{ + u8 width; + u32 *addr; + + // Format: + // *rm00000000.w + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(read8(addr)); + break; + case 'w': + sio_put16(read16(addr)); + break; + case 'l': + sio_put32(read32(addr)); + break; + } +} + +static void serialice_write_memory(void) +{ + u8 width; + u32 *addr; + u32 data; + + // Format: + // *wm00000000.w=0000 + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + write8(addr, (u8)data); + break; + case 'w': + data = sio_get16(); + write16(addr, (u16)data); + break; + case 'l': + data = sio_get32(); + write32(addr, (u32)data); + break; + } +} + +static void serialice_read_io(void) +{ + u8 width; + u16 port; + + // Format: + // *ri0000.w + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(inb(port)); + break; + case 'w': + sio_put16(inw(port)); + break; + case 'l': + sio_put32(inl(port)); + break; + } +} + +static void serialice_write_io(void) +{ + u8 width; + u16 port; + u32 data; + + // Format: + // *wi0000.w=0000 + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + outb((u8)data, port); + break; + case 'w': + data = sio_get16(); + outw((u16)data, port); + break; + case 'l': + data = sio_get32(); + outl((u32)data, port); + break; + } +} + +static void serialice_read_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *rc00000000.9c5a203a + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // key in %edi + + sio_putc('\r'); sio_putc('\n'); + + msr = rdmsr(addr, key); + sio_put32(msr.hi); + sio_putc('.'); + sio_put32(msr.lo); +} + +static void serialice_write_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *wc00000000.9c5a203a=00000000.00000000 + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // read key in %edi + sio_getc(); // skip = + msr.hi = sio_get32(); + sio_getc(); // skip . + msr.lo = sio_get32(); + +#ifdef __ROMCC__ + /* Cheat to avoid register outage */ + wrmsr(addr, msr, 0x9c5a203a); +#else + wrmsr(addr, msr, key); +#endif +} + +static void serialice_cpuinfo(void) +{ + u32 eax, ecx; + u32 reg32; + + // Format: + // --EAX--- --ECX--- + // *ci00000000.00000000 + eax = sio_get32(); + sio_getc(); // skip . + ecx = sio_get32(); + + sio_putc('\r'); sio_putc('\n'); + + /* This code looks quite crappy but this way we don't + * have to worry about running out of registers if we + * occupy eax, ebx, ecx, edx at the same time + */ + reg32 = cpuid_eax(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ebx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ecx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_edx(eax, ecx); + sio_put32(reg32); +} + +static void serialice_mainboard(void) +{ + int i = 0; + const char mb_string[] = CONFIG_MAINBOARD_VENDOR" " + CONFIG_MAINBOARD_PART_NUMBER; + + sio_putc('\r'); sio_putc('\n'); + + while (i < 32 && mb_string[i] > 0) { + sio_putc(mb_string[i]); + i++; + } + while (i < 32) { + sio_putc(' '); + i++; + } + + sio_flush(); +} + +static void serialice_version(void) +{ + sio_putstring("\nSerialICE v" VERSION "\n"); +} + +void serialice_main(void) +{ + u16 c; + + serialice_version(); + + while (1) { + sio_putstring("\n> "); + + c = sio_getc(); + if (c != '*') + continue; + + c = sio_getc() << 8; + c |= sio_getc(); + + switch (c) { + case (('r' << 8)|'m'): // Read Memory *rm + serialice_read_memory(); + break; + case (('w' << 8)|'m'): // Write Memory *wm + serialice_write_memory(); + break; + case (('r' << 8)|'i'): // Read IO *ri + serialice_read_io(); + break; + case (('w' << 8)|'i'): // Write IO *wi + serialice_write_io(); + break; + case (('r' << 8)|'c'): // Read CPU MSR *rc + serialice_read_msr(); + break; + case (('w' << 8)|'c'): // Write CPU MSR *wc + serialice_write_msr(); + break; + case (('c' << 8)|'i'): // Read CPUID *ci + serialice_cpuinfo(); + break; + case (('m' << 8)|'b'): // Read mainboard type *mb + serialice_mainboard(); + break; + case (('v' << 8)|'i'): // Read version info *vi + serialice_version(); + break; + default: + sio_putstring("ERROR\n"); + break; + } + } +} diff --git a/src/console/serialice_priv.h b/src/console/serialice_priv.h new file mode 100644 index 0000000..078ef04 --- /dev/null +++ b/src/console/serialice_priv.h @@ -0,0 +1,103 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_PRIV_H +#define CONSOLE_SERIALICE_PRIV_H + +/* String functions */ + +#define sio_put_nibble(nibble) \ + do { \ + if (nibble > 9) \ + nibble += ('a' - 10); \ + else \ + nibble += '0'; \ + sio_putc(nibble); \ + } while (0) + +/* MSR functions */ + +typedef struct { u32 lo, hi; } msr_t; + +static inline msr_t rdmsr(u32 index, u32 key) +{ + msr_t result; + + __asm__ __volatile__ ( + "rdmsr" + : "=a" (result.lo), "=d" (result.hi) + : "c" (index), "D" (key) + ); + return result; +} + +static inline void wrmsr(u32 index, msr_t msr, u32 key) +{ + __asm__ __volatile__ ( + "wrmsr" + : /* No outputs */ + : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (key) + ); +} + +/* CPUID functions */ + +static inline u32 cpuid_eax(u32 op, u32 op2) +{ + u32 eax; + + __asm__("cpuid" + : "=a" (eax) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return eax; +} + +static inline u32 cpuid_ebx(u32 op, u32 op2) +{ + u32 ebx; + + __asm__("cpuid" + : "=b" (ebx) + : "a" (op), "c" (op2) + : "edx"); + return ebx; +} + +static inline u32 cpuid_ecx(u32 op, u32 op2) +{ + u32 ecx; + + __asm__("cpuid" + : "=c" (ecx) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return ecx; +} + +static inline u32 cpuid_edx(u32 op, u32 op2) +{ + u32 edx; + + __asm__("cpuid" + : "=d" (edx) + : "a" (op), "c" (op2) + : "ebx"); + return edx; +} + +#endif diff --git a/src/include/console/serialice.h b/src/include/console/serialice.h new file mode 100644 index 0000000..a2b27e7 --- /dev/null +++ b/src/include/console/serialice.h @@ -0,0 +1,30 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_H +#define CONSOLE_SERIALICE_H + +#define ECHO_MODE 1 + +#if (ENV_RAMSTAGE && CONFIG_DEBUG_SERIALICE_RAMSTAGE) || \ + (ENV_ROMSTAGE && CONFIG_DEBUG_SERIALICE_ROMSTAGE) +void serialice_main(void); +#else +static inline void serialice_main(void) { } +#endif + +#endif diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 35f7999..53bd12d 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -18,10 +18,4 @@ void console_hw_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void); -/* For remote GDB debugging. */ -void gdb_hw_init(void); -void gdb_tx_byte(unsigned char byte); -void gdb_tx_flush(void); -unsigned char gdb_rx_byte(void); - #endif /* _CONSOLE_STREAMS_H_ */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index a3d650b..05df8d8 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -63,18 +63,12 @@ void oxford_remap(unsigned int new_base); static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); } static inline void __uart_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } +static inline u8 __uart_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_CONSOLE); } #else static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} -#endif - -#if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) -#define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE -static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); } -static inline void __gdb_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } -static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); } -static inline u8 __gdb_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_GDB); } +static inline u8 __uart_rx_byte(void) { return 0; } #endif #endif /* __ROMCC__ */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index b758c03..65e1dee 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -37,19 +37,12 @@ int usb_can_rx_byte(int idx); static inline void __usbdebug_init(void) { usbdebug_init(); } static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); } static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); } +static inline u8 __usb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_CONSOLE); } #else static inline void __usbdebug_init(void) {} static inline void __usb_tx_byte(u8 data) {} static inline void __usb_tx_flush(void) {} -#endif - -/* */ -#if 0 && CONFIG_GDB_STUB && \ - ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) -static inline void __gdb_hw_init(void) { usbdebug_init(); } -static inline void __gdb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_GDB, data); } -static inline void __gdb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_GDB); } -static inline u8 __gdb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_GDB); } +static inline u8 __usb_rx_byte(void) { return 0; } #endif #endif /* _CONSOLE_USB_H_ */ diff --git a/src/include/serial-com.h b/src/include/serial-com.h new file mode 100644 index 0000000..baf75ce --- /dev/null +++ b/src/include/serial-com.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SERIAL_H_ +#define _SERIAL_H_ + +#include <stdint.h> + +void serial_hw_init(void); +void serial_tx_byte(unsigned char byte); +void serial_tx_flush(void); +unsigned char serial_rx_byte(void); + +#endif /* _SERIAL_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 49720a7..989cef4 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -221,6 +221,11 @@ postcar-y += prog_ops.c postcar-y += rmodule.c postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c +romstage-$(CONFIG_DEBUG_SERIALICE_ROMSTAGE) += serial-com.c +ramstage-$(CONFIG_DEBUG_SERIALICE_RAMSTAGE) += serial-com.c +romstage-$(CONFIG_GDB_STUB) += serial-com.c +ramstage-$(CONFIG_GDB_STUB) += serial-com.c + # Use program.ld for all the platforms which use C fo the bootblock. bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += program.ld diff --git a/src/lib/serial-com.c b/src/lib/serial-com.c new file mode 100644 index 0000000..2354237 --- /dev/null +++ b/src/lib/serial-com.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <rules.h> +#include <stdint.h> +#include <console/uart.h> +#include <console/usb.h> +#include <serial-com.h> + +#define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE +#define USB_PIPE_FOR_GDB 0 + +#if __CONSOLE_SERIAL_ENABLE__ && !CONFIG_GDB_STUB +static inline void __serial_hw_init(void) { __uart_init(); } +static inline void __serial_tx_byte(u8 data) { __uart_tx_byte(data); } +static inline void __serial_tx_flush(void) { __uart_tx_flush(); } +static inline u8 __serial_rx_byte(void) { return __uart_rx_byte(); } +#elif __CONSOLE_USB_ENABLE__ && !CONFIG_GDB_STUB +static inline void __serial_hw_init(void) { __usbdebug_init(); } +static inline void __serial_tx_byte(u8 data) { __usb_tx_byte(data); } +static inline void __serial_tx_flush(void) { __usb_tx_flush(); } +static inline u8 __serial_rx_byte(void) { return __usb_rx_byte(); } +/* Configure functions to use GDB arguments */ +#elif __CONSOLE_USB_ENABLE__ && CONFIG_GDB_STUB && \ + ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) +static inline void __serial_hw_init(void) { usbdebug_init(); } +static inline void __serial_tx_byte(u8 data) + { usb_tx_byte(USB_PIPE_FOR_GDB, data); } +static inline void __serial_tx_flush(void) + { usb_tx_flush(USB_PIPE_FOR_GDB); } +static inline u8 __serial_rx_byte(void) + { return usb_rx_byte(USB_PIPE_FOR_GDB); } +#elif __CONSOLE_SERIAL_ENABLE__ && CONFIG_GDB_STUB && \ + (ENV_ROMSTAGE || ENV_RAMSTAGE) +static inline void __serial_hw_init(void) + { uart_init(CONFIG_UART_FOR_GDB); } +static inline void __serial_tx_byte(u8 data) + { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } +static inline void __serial_tx_flush(void) + { uart_tx_flush(CONFIG_UART_FOR_GDB); } +static inline u8 __serial_rx_byte(void) + { return uart_rx_byte(CONFIG_UART_FOR_GDB); } +#else +static inline void __serial_hw_init(void) {} +static inline void __serial_tx_byte(u8 data) {} +static inline void __serial_tx_flush(void) {} +static inline u8 __serial_rx_byte(void) { return 0; } +#endif + + +void serial_hw_init(void) +{ + __serial_hw_init(); +} + +void serial_tx_byte(unsigned char byte) +{ + __serial_tx_byte(byte); +} + +void serial_tx_flush(void) +{ + __serial_tx_flush(); +} + +unsigned char serial_rx_byte(void) +{ + return __serial_rx_byte(); +} +

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Patch set updated for coreboot: nvramcui: Update Makefile
by Martin Roth 28 Jun '16

28 Jun '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14482 -gerrit commit 50eab490dd094ea4333626de7651e27a70f97793 Author: Martin Roth <martinroth(a)google.com> Date: Sat Apr 23 17:19:41 2016 -0600 nvramcui: Update Makefile - Add all, clean and distclean to .PHONY - Rebuild nvramcui.elf when the makefile changes. - Update libpayload target to $(LIBPAYLOAD_DIR) target - these are the same thing, but by using the variable it makes it more obvious. - Remove .config.old as well as .config when running distclean. - Add CFLAGS to the LPGCC command line: -- Enable all warnings, set warnings as errors. -- Optimize for size -- Enable '-ffreestanding -nostdinc -nostdlib' to keep from building in system functions and to fix the warning: libpayload.h: warning: conflicting types for built-in function 'log2' static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } Change-Id: Icc6c70b259cd7c22dc960cdb732927f9c0c93ee8 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/nvramcui/Makefile | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/payloads/nvramcui/Makefile b/payloads/nvramcui/Makefile index 0f27ff8..c6a9cd0 100644 --- a/payloads/nvramcui/Makefile +++ b/payloads/nvramcui/Makefile @@ -3,10 +3,11 @@ XCOMPILE=$(LIBPAYLOAD_DIR)/libpayload.xcompile # build libpayload and put .config file in $(CURDIR) instead of ../libpayload # to avoid pollute the libpayload source directory and possible conflicts LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config" +CFLAGS += -Wall -Werror -Os -ffreestanding -nostdinc -nostdlib all: nvramcui.elf -libpayload: +$(LIBPAYLOAD_DIR): $(MAKE) -C ../libpayload $(LPOPTS) defconfig $(MAKE) -C ../libpayload $(LPOPTS) $(MAKE) -C ../libpayload $(LPOPTS) install @@ -14,19 +15,20 @@ libpayload: ifneq ($(strip $(wildcard libpayload)),) include $(XCOMPILE) LPGCC = CC="$(GCC_CC_x86_32)" "$(LIBPAYLOAD_DIR)/bin/lpgcc" -%.elf: %.c - $(LPGCC) -o $*.elf $*.c +%.elf: %.c Makefile + $(LPGCC) $(CFLAGS) -o $*.elf $*.c else # If libpayload is not found, first build libpayload, # then do the make, this time it'll find libpayload # and generate the nvramcui.elf target -%.elf: libpayload +%.elf: $(LIBPAYLOAD_DIR) $(MAKE) all endif -.PHONY: clean: rm -f nvramcui.elf distclean: clean - rm -rf build libpayload .config + rm -rf build libpayload .config .config.old + +.PHONY: all clean distclean

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Patch set updated for coreboot: google/reef: Update gpio config for audio
by HARSHAPRIYA N 28 Jun '16

28 Jun '16

HARSHAPRIYA N (harshapriya.n(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15433 -gerrit commit e54db15cb332b0c419e31eda85c84e2e538de08e Author: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Date: Thu Jun 16 14:34:30 2016 -0700 google/reef: Update gpio config for audio This changelist updates gpio config for speaker SDMODE pin and headset interrupt. 1. Disables speaker by default and audio kernel is expected to enable this when audio rendering starts. 2. Headset codec (Dialog) is level LOW triggered interrupt. Updating the gpio as "INVERT" to get level LOW interrupt configuration. Change-Id: Id33ad29e637bf1fe6b02e8a4b0fd9e220e8983e7 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- src/mainboard/google/reef/gpio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 23628eb..eeaf806 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -211,7 +211,7 @@ static const struct pad_config gpio_table[] = { /* I2S1 -- largely unused */ PAD_CFG_GPI(GPIO_74, UP_20K, DEEP), /* I2S1_MCLK */ PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ - PAD_CFG_GPI(GPIO_76, UP_20K, DEEP), /* I2S1_WS_SYNC */ + PAD_CFG_GPO(GPIO_76, 0, DEEP), /* I2S1_WS_SYNC -- SPK_PA_EN */ PAD_CFG_GPI(GPIO_77, UP_20K, DEEP), /* I2S1_SDI */ PAD_CFG_GPI(GPIO_78, UP_20K, DEEP), /* I2S1_SDO */ @@ -256,7 +256,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_112, UP_20K, DEEP), /* SIO_SPI_1_FS0 */ PAD_CFG_GPI(GPIO_113, UP_20K, DEEP), /* SIO_SPI_1_FS1 */ /* Headset interrupt */ - PAD_CFG_GPI_APIC(GPIO_116, NONE, DEEP, LEVEL, NONE), /* SIO_SPI_1_RXD */ + PAD_CFG_GPI_APIC(GPIO_116, NONE, DEEP, LEVEL, INVERT), /* SIO_SPI_1_RXD */ PAD_CFG_GPI(GPIO_117, UP_20K, DEEP), /* SIO_SPI_1_TXD */ /* SIO_SPI_2 -- unused */

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Patch merged into coreboot/master: riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handler
by gerrit＠coreboot.org 28 Jun '16

28 Jun '16

the following patch was just integrated into master: commit 9d0cce2087139a2eab447aea3fdebfe44e97c280 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Tue Jun 21 19:37:03 2016 +0200 riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handler Change-Id: Ic42d8490cc02a3907e2989435aab786f7c0f39c9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/15287 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See https://review.coreboot.org/15287 for details. -gerrit

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