coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: mainboard/intel/amenia: Select NHLT audio blobs
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15485 -gerrit commit a5ae9592fcf14754f4693d81eaf8f5fadf054226 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Jun 28 12:39:20 2016 -0700 mainboard/intel/amenia: Select NHLT audio blobs Select the following NHLT audio blobs: NHLT_DMIC_2CH_16B, this adds 2 channel dmic array, NHLT_DA7219, this adds Dialog 7219 for headset codec, and NHLT_MAX98357, this adds Maxim 98357 for speaker codec. Change-Id: I5b16f7c2ecde7ffabab2fbc1c17b7fd72c23c8e9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index 6dd171c..abea9e6 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -52,4 +52,10 @@ config MAX_CPUS int default 8 +config INCLUDE_AUDIO_BLOBS + bool "Include blobs for audio." + select NHLT_DMIC_2CH_16B + select NHLT_DA7219 + select NHLT_MAX98357 + endif # BOARD_INTEL_AMENIA

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New patch to review for coreboot: soc/intel/apollolake: Add NHLT blobs configuration settings
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15484 -gerrit commit 1200d122a62b63828003b99430aaadde63cf8329 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Jun 28 12:32:39 2016 -0700 soc/intel/apollolake: Add NHLT blobs configuration settings Select ACPI_NHLT and add configuration settings for NHLT audio blobs for Intel Apollolake SoC. These configs are set in mainboard for including NHLT audio blobs in cbfs. The following audio blobs configs are added: NHLT_DMIC_2CH_16B NHLT_MAX98357 NHLT_DA7219 Change-Id: Ieebf535b584919d6551bde0f2ee691a93eb9e57e Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d830a9f..9bc199d 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -17,6 +17,8 @@ config CPU_SPECIFIC_OPTIONS select SMP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS + # Audio options + select ACPI_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS @@ -184,4 +186,25 @@ config IFWI_FILE_NAME help Name of file to store in the IFWI region. +config NHLT_DMIC_2CH_16B + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for 2 channel 16B DMIC array. + +config NHLT_MAX98357 + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for headset codec. + +config NHLT_DA7219 + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for headset codec. + endif

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Patch set updated for coreboot: apollolake: Add ACPI device for audio controller
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15026 -gerrit commit 2b52ee0d1e37fc75e521256504a4f33b435903f3 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Mar 8 17:33:29 2016 -0800 apollolake: Add ACPI device for audio controller Add the audio controller device to ACPI and define the _DSM handler to return the address of the NHLT table, if set in NVS. Change-Id: I619dbfb562b94255e42a3e5d5a3926c28b14db3e Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/acpi/pch_hda.asl | 84 +++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pch_hda.asl b/src/soc/intel/apollolake/acpi/pch_hda.asl new file mode 100644 index 0000000..33cd771 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pch_hda.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* Audio Controller - Device 14, Function 0 */ + +Device (HDAS) +{ + Name (_ADR, 0x000E0000) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate() { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, Cacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + } + ) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (LEqual (Arg2, Zero)) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If (LAnd (LEqual (Arg1, One), + LAnd (LNotEqual (NHLA, Zero), + LNotEqual (NHLL, Zero)))) { + Return (Buffer (One) { 0x03 }) + } + Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (LEqual (Arg2, One)) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + Store (NHLA, NBAS) + Store (NHLA, NMAS) + Store (NHLL, NLEN) + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +}

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Patch set updated for coreboot: mainboard/intel/amenia: Use common NHLT
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15024 -gerrit commit b84ab5ef11e96670273d140d46b348bda3b19b4f Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 16:08:45 2016 -0700 mainboard/intel/amenia: Use common NHLT Add ACPI NHLT table generation that the current hardware supports. Amenia has support for two audio codecs, Dialog for headsets and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/dsdt.asl | 11 ++++---- src/mainboard/intel/amenia/mainboard.c | 50 +++++++++++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 4a64f87..46404ed 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2016 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -33,15 +33,16 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include <soc/intel/apollolake/acpi/northbridge.asl> - #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> } } /* Mainboard Specific devices */ #include "acpi/mainboard.asl" - /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> #include "acpi/superio.asl" } diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 22304f8..07e896e 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -16,8 +16,14 @@ */ #include <device/device.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <nhlt.h> #include <soc/gpio.h> +#include <soc/nhlt.h> #include <soc/pci_devs.h> +#include <stdlib.h> +#include <string.h> #include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ @@ -129,7 +135,6 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ PAD_CFG_NF(PMC_SPI_FS1, NATIVE, DEEP, NF2), /* HV_DDI2_HPD */ - }; static void mainboard_init(void *chip_info) @@ -138,6 +143,49 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (!nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Added 2CH DMIC array.\n"); + + /* Dialog for Headset codec. + * Headset codec is bi-directional but uses the same configuration + * settings for render and capture endpoints. + */ + if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; +} + struct chip_operations mainboard_ops = { .init = mainboard_init, + .enable_dev = mainboard_enable, };

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Patch set updated for coreboot: soc/intel/apollolake: Add NHLT table region to ACPI global nvs
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15025 -gerrit commit 24c7ff91c5b86e73107019aa3925a55d648674cb Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Mar 31 15:41:30 2016 -0700 soc/intel/apollolake: Add NHLT table region to ACPI global nvs Add address and length of NHLT table in ACPI. Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/acpi/globalnvs.asl | 2 ++ src/soc/intel/apollolake/include/soc/nvs.h | 14 ++++++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 3597788..3f9683f 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -34,6 +34,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PWRS, 8, // 0x03 - AC Power State DPTE, 8, // 0x04 - Enable DPTF CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console + NHLA, 64, // 0x09 - NHLT Address + NHLL, 32, // 0x11 - NHLT Length /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index fda3556..1ff5f23 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,13 +28,15 @@ struct global_nvs_t { /* Miscellaneous */ - uint8_t pcnt; /* 0x00 - Processor Count */ - uint8_t ppcm; /* 0x01 - Max PPC State */ - uint8_t lids; /* 0x02 - LID State */ - uint8_t pwrs; /* 0x03 - AC Power State */ - uint8_t dpte; /* 0x04 - Enable DPTF */ + uint8_t pcnt; /* 0x00 - Processor Count */ + uint8_t ppcm; /* 0x01 - Max PPC State */ + uint8_t lids; /* 0x02 - LID State */ + uint8_t pwrs; /* 0x03 - AC Power State */ + uint8_t dpte; /* 0x04 - Enable DPTF */ uint32_t cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */ - uint8_t unused[247]; + uint64_t nhla; /* 0x09 - NHLT Address */ + uint32_t nhll; /* 0x11 - NHLT Length */ + uint8_t unused[235]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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Patch set updated for coreboot: soc/intel/apollolake: Add NHLT add codec APIs and device/vendor ids
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15311 -gerrit commit 3090705e872827b2726f71dc0c954400a6267289 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Jun 21 14:22:16 2016 -0700 soc/intel/apollolake: Add NHLT add codec APIs and device/vendor ids nhlt_add_<codec>_on_ssp uses codec configs, tdm configs and add the particular codec on a SSP port specified by mainboard. get_nhlt_link_type() returns a corresponding NHLT link type based on audio soc hardware interface passed as an argument. Also define vendor id for NHLT and device ids for NHLT Bluetooth, DMIC & SSPs. These ids are used to add NHLT endpoints for different audio codecs. These ids are platform dependent. Change-Id: Ic9bd26ebe8d6df60af23733e122fd8f3c0432e1f Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/nhlt.h | 39 +++++++++ src/soc/intel/apollolake/nhlt.c | 130 ++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 38ed07d..c335e39 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -55,6 +55,7 @@ ramstage-y += pmutil.c ramstage-y += pmc.c ramstage-y += smi.c ramstage-y += reset.c +ramstage-y += nhlt.c postcar-y += exit_car.S postcar-y += memmap.c diff --git a/src/soc/intel/apollolake/include/soc/nhlt.h b/src/soc/intel/apollolake/include/soc/nhlt.h new file mode 100644 index 0000000..cc6486b --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/nhlt.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_NHLT_H_ +#define _SOC_APOLLOLAKE_NHLT_H_ + +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + +enum { + AUDIO_LINK_SSP0, + AUDIO_LINK_SSP1, + AUDIO_LINK_SSP2, + AUDIO_LINK_SSP3, + AUDIO_LINK_SSP4, + AUDIO_LINK_SSP5, + AUDIO_LINK_DMIC, +}; + +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels); +int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink); +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink); + +#endif diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c new file mode 100644 index 0000000..87fc65a --- /dev/null +++ b/src/soc/intel/apollolake/nhlt.c @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +static const struct nhlt_format_config dmic_2ch_cfg[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_format_config da7219_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "dialog-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_tdm_config tdm_cfg = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_format_config max98357_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "max98357-render-2ch-48khz-24b.bin", + }, +}; + +int nhlt_soc_get_link_type(int hwlink, int soc_devtype) +{ + int nhlt_link_type; + + switch (hwlink) { + case AUDIO_LINK_SSP0: + case AUDIO_LINK_SSP1: + case AUDIO_LINK_SSP3: + case AUDIO_LINK_SSP4: + case AUDIO_LINK_SSP5: + /* Only I2S devices. */ + if (soc_devtype != AUDIO_DEV_I2S) + return -1; + nhlt_link_type = NHLT_LINK_SSP; + break; + case AUDIO_LINK_SSP2: + /* Only Bluetooth devices on SSP2. */ + if (soc_devtype != AUDIO_DEV_BT) + return -1; + nhlt_link_type = NHLT_LINK_SSP; + break; + case AUDIO_LINK_DMIC: + // Only DMIC devices on DMIC links. + if (soc_devtype != AUDIO_DEV_DMIC) + return -1; + nhlt_link_type = NHLT_LINK_PDM; + break; + default: + return -1; + } + + return nhlt_link_type; +} + +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) +{ + if (num_channels != 2) { + printk(BIOS_ERR, "APL only supports 2CH DMIC array.\n"); + return -1; + } + + if (nhlt_add_dmic_array(nhlt, num_channels, dmic_2ch_cfg, + ARRAY_SIZE(dmic_2ch_cfg))) { + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + return -1; + } + + return 0; +} + +int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink) +{ + if (nhlt_add_codec_on_ssp(nhlt, hwlink, max98357_cfg, + ARRAY_SIZE(max98357_cfg), NULL, 0, NULL, 0)) { + printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n"); + return -1; + } + + return 0; +} + +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink) +{ + if (nhlt_add_codec_on_ssp(nhlt, hwlink, da7219_cfg, + ARRAY_SIZE(da7219_cfg), da7219_cfg, ARRAY_SIZE(da7219_cfg), &tdm_cfg, + sizeof(tdm_cfg))) { + printk(BIOS_ERR, "Couldn't add Dialog_7219 codec.\n"); + return -1; + } + + return 0; +}

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Patch set updated for coreboot: soc/intel/apollolake: Use common NHLT
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15326 -gerrit commit 5f4b0f28a6fe5a825b58bdc6ba686dc43c4c4016 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Wed Jun 22 17:38:12 2016 -0700 soc/intel/apollolake: Use common NHLT This makes use of common NHLT implmentation for audio on Intel's apollolake platform. Change-Id: I3ff87efc83bc243d51a8ddea896ae60f7bb7aec9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index c335e39..556abbb 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -57,6 +57,24 @@ ramstage-y += smi.c ramstage-y += reset.c ramstage-y += nhlt.c +# DSP firmware settings files. +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs +DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin +MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin +DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin + +cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER) +$(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER) +$(MAX98357_RENDER)-type := raw + +cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE) +$(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE) +$(DA7219_RENDER_CAPTURE)-type := raw + postcar-y += exit_car.S postcar-y += memmap.c postcar-y += mmap_boot.c

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Patch set updated for coreboot: lib/nhlt: Extend NHLT function library
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15464 -gerrit commit 7888e0df0524c7b978ed1acb8f3c5a09a6c478e7 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Jun 28 00:35:14 2016 -0700 lib/nhlt: Extend NHLT function library Add NHLT library function defintions to lib/nhlt.c. This adds nhlt_soc_add_endpoint(), nhlt_soc_serialiaze() and nhlt_soc_serialize_oem_overrides(). These functions are used by NHLT helper functions to add dmic and different audio codecs for an SoC/mainboard. Change-Id: I96b7369eb7ca2ac2edacf3d942a201b92a5363f4 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/lib/nhlt.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index 11a397c..d9107ee 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -437,3 +437,69 @@ uintptr_t nhlt_serialize_oem_overrides(struct nhlt *nhlt, return acpi_addr; } + +struct nhlt_endpoint *nhlt_soc_add_endpoint(struct nhlt *nhlt, int soc_hwintf, + int soc_devtype, int dir) +{ + int nhlt_link_type; + int nhlt_dev_type; + uint16_t did; + struct nhlt_endpoint *endp; + + nhlt_link_type = nhlt_soc_get_link_type(soc_hwintf, soc_devtype); + + if (nhlt_link_type == -1) + return NULL; + + switch (soc_devtype) { + case AUDIO_DEV_I2S: + nhlt_dev_type = NHLT_SSP_DEV_I2S; + did = NHLT_DID_SSP; + break; + case AUDIO_DEV_DMIC: + nhlt_dev_type = NHLT_PDM_DEV; + did = NHLT_DID_DMIC; + break; + case AUDIO_DEV_BT: + nhlt_dev_type = NHLT_SSP_DEV_BT; + did = NHLT_DID_BT; + break; + default: + return NULL; + } + + endp = nhlt_add_endpoint(nhlt, nhlt_link_type, nhlt_dev_type, dir, + NHLT_VID, did); + + if (endp == NULL) + return NULL; + + /* Virtual bus id of SSP link is the hardware port id. */ + if (nhlt_link_type == NHLT_LINK_SSP) + endp->virtual_bus_id = soc_hwintf; + + return endp; +} + +uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) +{ + return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); +} + +uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, + uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs == NULL) + return acpi_addr; + + /* Update NHLT GNVS Data */ + gnvs->nhla = (uintptr_t)acpi_addr; + gnvs->nhll = nhlt_current_size(nhlt); + + return nhlt_serialize_oem_overrides(nhlt, acpi_addr, oem_id, + oem_table_id); +}

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Patch set updated for coreboot: lib/nhlt: Add common NHLT audio for Intel platforms
by Saurabh Satija 28 Jun '16

28 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15023 -gerrit commit 21b049a404969f9b0d00cf19d75655b043b83b25 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Jun 23 14:46:27 2016 -0700 lib/nhlt: Add common NHLT audio for Intel platforms The use of a NHLT table is required to make audio work on the Intel SoCs employing the internal DSP. The table describes the audio endpoints (render vs capture) along with their supported formats. These formats are not only dependent on the audio peripheral but also hardware interfaces. As such each format has an associated blob of DSP settings to make the peripheral work. Lastly, each of these settings are provided by Intel and need to be generated for each device's hardware connection plus mode/format it supports. This patch does not include the DSP setting blobs. Change-Id: I3c75d3537288c47d29e8949ca253ea8c5c1a387d Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/include/nhlt.h | 45 +++++++++++++++++++++++++++ src/lib/nhlt.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 134 insertions(+), 2 deletions(-) diff --git a/src/include/nhlt.h b/src/include/nhlt.h index f0b3b6f..20d20ed 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -23,6 +23,51 @@ struct nhlt; struct nhlt_endpoint; struct nhlt_format; struct nhlt_format_config; +struct nhlt_tdm_config; + +/* + * NHLT device types. These values are used with nhlt_soc_add_endpoint(). + */ +enum { + AUDIO_DEV_I2S, + AUDIO_DEV_DMIC, + AUDIO_DEV_BT, +}; + +/* + * Returns corresponding nhlt link type based on hardware link number. + * Hardware link number is the SSP port number on which the particular + * is present, which is mainboard specfic. + * nhlt_soc_get_link_type() is SoC specific. + */ +int nhlt_soc_get_link_type(int hwlink, int soc_devtype); + +/* + * Add a dmic array composed of the provided number of channels. + * Returns 0 on success, < 0 on error. + */ +int nhlt_add_dmic_array(struct nhlt *nhlt, int num_channels, + const struct nhlt_format_config *dmic_ch_config, int num_fmt); + +/* + * Add audio codec on provided SSP link. Return 0 on succes, < 0 on error. + * + * The same DSP firmware settings can be used for both the capture and render + * endpoints in some cases. Most of the smart amps use different DSP firmware + * settings for capture and render endpoints. + * + * render_cfg, capture_cfg: These are the audio codec configuration defined + * in mainboard souce code. + * cfg_size: This is the number of configurations defined in codec config. + * Each configuration is added as an endpoint. + * tdm_config: This is also board specific and defined in mainboard.c + * hwlink: This is the SSP hardware port number. + * direction: This can be Render only, Capture only or Bi-directional. + */ +int nhlt_add_codec_on_ssp(struct nhlt *nhlt, int hwlink, + const struct nhlt_format_config *render_cfg, int r_num_fmt, + const struct nhlt_format_config *capture_cfg, int c_num_fmt, + const struct nhlt_tdm_config *tdm_config, size_t tdm_size); /* * Non HD Audio ACPI support. This table is typically used for Intel Smart diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index d9107ee..3883b32 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -15,9 +15,12 @@ #include <arch/acpi.h> #include <cbfs.h> +#include <cbmem.h> #include <commonlib/endian.h> #include <console/console.h> #include <nhlt.h> +#include <soc/nvs.h> +#include <soc/nhlt.h> #include <stdlib.h> #include <string.h> @@ -47,8 +50,7 @@ struct nhlt *nhlt_init(void) } struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type, - int device_type, int dir, - uint16_t vid, uint16_t did) + int device_type, int dir, uint16_t vid, uint16_t did) { struct nhlt_endpoint *endp; @@ -503,3 +505,88 @@ uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, return nhlt_serialize_oem_overrides(nhlt, acpi_addr, oem_id, oem_table_id); } + +int nhlt_add_dmic_array(struct nhlt *nhlt, int num_channels, + const struct nhlt_format_config *dmic_ch_cfg, int num_fmt) +{ + struct nhlt_endpoint *endp; + struct nhlt_dmic_array_config mic_config; + + if (num_channels != 2 && num_channels != 4) + return -1; + + endp = nhlt_soc_add_endpoint(nhlt, AUDIO_LINK_DMIC, AUDIO_DEV_DMIC, + NHLT_DIR_CAPTURE); + + if (endp == NULL) + return -1; + + memset(&mic_config, 0, sizeof(mic_config)); + mic_config.tdm_config.config_type = NHLT_TDM_MIC_ARRAY; + + switch (num_channels) { + case 2: + mic_config.array_type = NHLT_MIC_ARRAY_2CH_SMALL; + break; + case 4: + mic_config.array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED; + break; + } + + if (nhlt_endpoint_append_config(endp, &mic_config, sizeof(mic_config))) + return -1; + + return nhlt_endpoint_add_formats(endp, dmic_ch_cfg, num_fmt); +} + +int nhlt_add_codec_on_ssp(struct nhlt *nhlt, int hwlink, + const struct nhlt_format_config *render_cfg, int r_num_fmt, + const struct nhlt_format_config *capture_cfg, int c_num_fmt, + const struct nhlt_tdm_config *tdm_config, size_t tdm_size) +{ + struct nhlt_endpoint *endp; + + /* For Bi-directional amplifiers, both capture and render + * configuratoins are needed. + */ + if (render_cfg == NULL && capture_cfg == NULL) + return -1; + + /* Render Endpoint */ + if (render_cfg != NULL) { + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_RENDER); + if (endp == NULL) + return -1; + + if (tdm_config != NULL) { + if (nhlt_endpoint_append_config(endp, tdm_config, + tdm_size)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, render_cfg, r_num_fmt)) + return -1; + } + + /* Capture Endpoint */ + if (capture_cfg != NULL) { + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_CAPTURE); + if (endp == NULL) + return -1; + + if (tdm_config != NULL) { + if (nhlt_endpoint_append_config(endp, tdm_config, + tdm_size)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, capture_cfg, c_num_fmt)) + return -1; + } + + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return 0; +}

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New patch to review for coreboot: soc/intel/apollolake: Change PCI macros to match Skylake
by Andrey Petrov 28 Jun '16

28 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15483 -gerrit commit 6bc009656ec8b1113a3df3b260e15dff9724fee0 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Jun 28 12:14:33 2016 -0700 soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/chip.c | 35 ++++----- src/soc/intel/apollolake/include/soc/pci_devs.h | 95 +++++++++++++++---------- 2 files changed, 76 insertions(+), 54 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 821570b..af3310e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -134,49 +134,49 @@ static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) { case XDCI_DEVFN: silconfig->UsbOtg = 0; break; - case I2C0_DEVFN: + case LPSS_DEVFN_I2C0: silconfig->I2c0Enable = 0; break; - case I2C1_DEVFN: + case LPSS_DEVFN_I2C1: silconfig->I2c1Enable = 0; break; - case I2C2_DEVFN: + case LPSS_DEVFN_I2C2: silconfig->I2c2Enable = 0; break; - case I2C3_DEVFN: + case LPSS_DEVFN_I2C3: silconfig->I2c3Enable = 0; break; - case I2C4_DEVFN: + case LPSS_DEVFN_I2C4: silconfig->I2c4Enable = 0; break; - case I2C5_DEVFN: + case LPSS_DEVFN_I2C5: silconfig->I2c5Enable = 0; break; - case I2C6_DEVFN: + case LPSS_DEVFN_I2C6: silconfig->I2c6Enable = 0; break; - case I2C7_DEVFN: + case LPSS_DEVFN_I2C7: silconfig->I2c7Enable = 0; break; - case UART0_DEVFN: + case LPSS_DEVFN_UART0: silconfig->Hsuart0Enable = 0; break; - case UART1_DEVFN: + case LPSS_DEVFN_UART1: silconfig->Hsuart1Enable = 0; break; - case UART2_DEVFN: + case LPSS_DEVFN_UART2: silconfig->Hsuart2Enable = 0; break; - case UART3_DEVFN: + case LPSS_DEVFN_UART3: silconfig->Hsuart3Enable = 0; break; - case SPI0_DEVFN: + case LPSS_DEVFN_SPI0: silconfig->Spi0Enable = 0; break; - case SPI1_DEVFN: + case LPSS_DEVFN_SPI1: silconfig->Spi1Enable = 0; break; - case SPI2_DEVFN: + case LPSS_DEVFN_SPI2: silconfig->Spi2Enable = 0; break; case SDCARD_DEVFN: @@ -201,7 +201,7 @@ static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) { static void parse_devicetree(struct FSP_S_CONFIG *silconfig) { - struct device *dev = dev_find_slot(0, NB_DEVFN); + struct device *dev = NB_DEV_ROOT; if (!dev) { printk(BIOS_ERR, "Could not find root device\n"); @@ -222,7 +222,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) /* Load VBT before devicetree-specific config. */ silconfig->GraphicsConfigPtr = (uintptr_t)vbt; - struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN); + struct device *dev = NB_DEV_ROOT; + if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index fc046d1..1a97621 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -18,14 +18,17 @@ #include <rules.h> #define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func) +#define _PCI_DEVFN(slot, func) PCI_DEVFN(slot, func) #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> #include <device/pci_def.h> #define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func)) +#define _PCI_DEV(slot, func) dev_find_slot(0, PCI_DEVFN(slot, func)) #else #include <arch/io.h> #define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func) +#define _PCI_DEV(slot, func) PCI_DEV(0, slot, func) #endif /* LPSS UART */ @@ -39,41 +42,59 @@ #define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2) #define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3) -#define NB_BUS 0 -#define NB_DEVFN PCI_DEVFN(0, 0) -#define NB_DEV_ROOT PCI_DEV(NB_BUS, 0x0, 0) -#define P2SB_DEV PCI_DEV(0, 0xd, 0) -#define PMC_DEV PCI_DEV(0, 0xd, 1) -#define SPI_DEV PCI_DEV(0, 0xd, 2) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) - -#define ISH_DEVFN PCI_DEVFN(0x11, 0) -#define SATA_DEVFN PCI_DEVFN(0x12, 0) -#define PCIEA0_DEVFN PCI_DEVFN(0x13, 0) -#define PCIEA1_DEVFN PCI_DEVFN(0x13, 1) -#define PCIEA2_DEVFN PCI_DEVFN(0x13, 2) -#define PCIEA3_DEVFN PCI_DEVFN(0x13, 3) -#define PCIEB0_DEVFN PCI_DEVFN(0x14, 0) -#define PCIEB1_DEVFN PCI_DEVFN(0x14, 1) -#define XHCI_DEVFN PCI_DEVFN(0x15, 0) -#define XDCI_DEVFN PCI_DEVFN(0x15, 1) -#define I2C0_DEVFN PCI_DEVFN(0x16, 0) -#define I2C1_DEVFN PCI_DEVFN(0x16, 1) -#define I2C2_DEVFN PCI_DEVFN(0x16, 2) -#define I2C3_DEVFN PCI_DEVFN(0x16, 3) -#define I2C4_DEVFN PCI_DEVFN(0x17, 0) -#define I2C5_DEVFN PCI_DEVFN(0x17, 1) -#define I2C6_DEVFN PCI_DEVFN(0x17, 2) -#define I2C7_DEVFN PCI_DEVFN(0x17, 3) -#define UART0_DEVFN PCI_DEVFN(0x18, 0) -#define UART1_DEVFN PCI_DEVFN(0x18, 1) -#define UART2_DEVFN PCI_DEVFN(0x18, 2) -#define UART3_DEVFN PCI_DEVFN(0x18, 3) -#define SPI0_DEVFN PCI_DEVFN(0x19, 0) -#define SPI1_DEVFN PCI_DEVFN(0x19, 1) -#define SPI2_DEVFN PCI_DEVFN(0x19, 2) -#define SDCARD_DEVFN PCI_DEVFN(0x1b, 0) -#define EMMC_DEVFN PCI_DEVFN(0x1c, 0) -#define SDIO_DEVFN PCI_DEVFN(0x1e, 0) -#define SMBUS_DEVFN PCI_DEVFN(0x1f, 1) +/* LPSS I2C */ +#define LPSS_DEV_SLOT_I2C_D0 0x16 +#define LPSS_DEV_SLOT_I2C_D1 0x17 +#define LPSS_DEVFN_I2C0 _LPSS_PCI_DEVFN(I2C_D0, 0) +#define LPSS_DEVFN_I2C1 _LPSS_PCI_DEVFN(I2C_D0, 1) +#define LPSS_DEVFN_I2C2 _LPSS_PCI_DEVFN(I2C_D0, 2) +#define LPSS_DEVFN_I2C3 _LPSS_PCI_DEVFN(I2C_D0, 3) +#define LPSS_DEVFN_I2C4 _LPSS_PCI_DEVFN(I2C_D1, 0) +#define LPSS_DEVFN_I2C5 _LPSS_PCI_DEVFN(I2C_D1, 1) +#define LPSS_DEVFN_I2C6 _LPSS_PCI_DEVFN(I2C_D1, 2) +#define LPSS_DEVFN_I2C7 _LPSS_PCI_DEVFN(I2C_D1, 3) + +/* LPSS SPI */ +#define LPSS_DEV_SLOT_SPI 0x19 +#define LPSS_DEVFN_SPI0 _LPSS_PCI_DEVFN(SPI, 0) +#define LPSS_DEVFN_SPI1 _LPSS_PCI_DEVFN(SPI, 1) +#define LPSS_DEVFN_SPI2 _LPSS_PCI_DEVFN(SPI, 2) + +#define NB_DEVFN _PCI_DEVFN(0, 0) +#define NB_DEV_ROOT _PCI_DEV(0x0, 0) +#define P2SB_DEV _PCI_DEV(0xd, 0) +#define PMC_DEV _PCI_DEV(0xd, 1) +#define SPI_DEV _PCI_DEV(0xd, 2) +#define LPC_DEV _PCI_DEV(0x1f, 0) + +#define ISH_DEVFN _PCI_DEVFN(0x11, 0) +#define ISH_DEV _PCI_DEV(0x11, 0) + +#define SATA_DEVFN _PCI_DEVFN(0x12, 0) +#define SATA_DEV _PCI_DEV(0x12, 0) + +#define PCIEA0_DEVFN _PCI_DEVFN(0x13, 0) +#define PCIEA1_DEVFN _PCI_DEVFN(0x13, 1) +#define PCIEA2_DEVFN _PCI_DEVFN(0x13, 2) +#define PCIEA3_DEVFN _PCI_DEVFN(0x13, 3) +#define PCIEB0_DEVFN _PCI_DEVFN(0x14, 0) +#define PCIEB1_DEVFN _PCI_DEVFN(0x14, 1) + +#define XHCI_DEVFN _PCI_DEVFN(0x15, 0) +#define XHCI_DEV _PCI_DEV(0x15, 0) + +#define XDCI_DEVFN _PCI_DEVFN(0x15, 1) +#define XDCI_DEV _PCI_DEV(0x15, 1) + +#define SDCARD_DEVFN _PCI_DEVFN(0x1b, 0) +#define SDCARD_DEV _PCI_DEV(0x1b, 0) + +#define EMMC_DEVFN _PCI_DEVFN(0x1c, 0) +#define EMMC_DEV _PCI_DEV(0x1c, 0) + +#define SDIO_DEVFN _PCI_DEVFN(0x1e, 0) +#define SDIO_DEV _PCI_DEV(0x1e, 0) + +#define SMBUS_DEVFN _PCI_DEVFN(0x1f, 1) +#define SMBUS_DEV _PCI_DEV(0x1f, 1) #endif

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coreboot-gerrit June 2016