coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

1 participants
1491 discussions

Patch set updated for coreboot: soc/intel/apollolake: Update Upd header files for FSP Label 143_10
by Hannah Williams 29 Jun '16

29 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15459 -gerrit commit 07968685ba3b6f45151bb83b68a0d6226a86ed3d Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Jun 24 10:41:39 2016 -0700 soc/intel/apollolake: Update Upd header files for FSP Label 143_10 New UPDs added to header files as well as many comment fixes. Memory infor is now defined in FspmUpd.h and added ability to skip CSE RBP for coreboot. Removes some UPDs that are no longer available from source. BUG=chrome-os-partner:54677 BRANCH=none TEST=built and tested with FSP 143_10 version Change-Id: I7e1f531ebbe343b45151a265ac715ae74aeffcad Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/chip.c | 6 -- src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 47 +++++++++++- src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 83 +++++++++++----------- 3 files changed, 85 insertions(+), 51 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 821570b..044ef91 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -253,12 +253,6 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) if (cfg->emmc_rx_cmd_data_cntl2 != 0) silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; - /* Our defaults may not match FSP defaults, so set them explicitly */ - silconfig->AcpiBase = ACPI_PMIO_BASE; - /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ - silconfig->PmcBase = PMC_BAR0 + 0x1000; - silconfig->P2sbBase = P2SB_BAR; - silconfig->IshEnable = cfg->integrated_sensor_hub_enable; /* Disable setting of EISS bit in FSP. */ diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index 5f5f367..3712fd7 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -36,6 +36,42 @@ are permitted provided that the following conditions are met: #include "FspUpd.h" #include <fsp/upd.h> +#define MAX_CHANNELS_NUM 4 +#define MAX_DIMMS_NUM 1 + +struct DIMM_INFO { + uint8_t DimmId; + uint32_t SizeInMb; + uint16_t MfgId; + /** Module part number for DRR3 is 18 bytes + but DRR4 is 20 bytes as per JEDEC Spec, so + reserving 20 bytes **/ + uint8_t ModulePartNum[20]; +} __attribute__((packed)); + +struct CHANNEL_INFO { + uint8_t ChannelId; + uint8_t DimmCount; + struct DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} __attribute__((packed)); + +struct FSP_SMBIOS_MEMORY_INFO { + uint8_t Revision; + uint8_t DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + uint16_t MemoryType; + uint16_t MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + uint8_t ErrorCorrectionType; + uint8_t ChannelCount; + struct CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} __attribute__((packed)); + + /** Fsp M Configuration **/ struct FSP_M_CONFIG { @@ -528,9 +564,16 @@ struct FSP_M_CONFIG { **/ void* MrcBootDataPtr; -/** Offset 0x0135 +/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB + Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of + CSE. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + uint8_t SkipCseRbp; + +/** Offset 0x0136 **/ - uint8_t ReservedFspmUpd[27]; + uint8_t ReservedFspmUpd[26]; } __attribute__((packed)); /** Fsp M Test Configuration diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h index d4ecd36..8dd824b 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h @@ -587,10 +587,9 @@ struct FSP_S_CONFIG { **/ uint8_t HpetFunctionNumber; -/** Offset 0x00AF - Hpet Base Address - Hpet Base Address. 0xFED00000(Default). +/** Offset 0x00AF **/ - uint32_t HpetBase; + uint32_t UnusedUpdSpace1; /** Offset 0x00B3 - IoApic Valid BDF Value Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. @@ -635,7 +634,7 @@ struct FSP_S_CONFIG { **/ uint8_t IshEnable; -/** Offset 0x00BB - ISH Controller +/** Offset 0x00BB - BIOS Interface Lock Down Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. 0:Disable, 1:Enable(Default). $EN_DIS @@ -663,7 +662,7 @@ struct FSP_S_CONFIG { Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t S0ixEnable; + uint8_t LPSS_S0ixEnable; /** Offset 0x00C0 - LPSS I2C Clock Gating Configuration Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). @@ -770,8 +769,8 @@ struct FSP_S_CONFIG { **/ uint8_t Spi2Enable; -/** Offset 0x00DE - UART Debug Bass Address - UART Debug Bass Address. 0x00000000(Default). +/** Offset 0x00DE - UART Debug Base Address + UART Debug Base Address. 0x00000000(Default). **/ uint32_t Uart2KernelDebugBaseAddress; @@ -810,7 +809,7 @@ struct FSP_S_CONFIG { **/ uint8_t PcieRootPortPeerMemoryWriteEnable; -/** Offset 0x00E8 - PCIE SWSMI Nubmer +/** Offset 0x00E8 - PCIE SWSMI Number This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). **/ uint8_t PcieAspmSwSmiNumber; @@ -932,7 +931,7 @@ struct FSP_S_CONFIG { uint8_t PcieRpCompletionTimeout[6]; /** Offset 0x0173 - PTM Support - Enable/Diable PTM Support. 0:Disable(Default), 1:Enable. + Enable/Disable PTM Support. 0:Disable(Default), 1:Enable. **/ uint8_t PtmEnable[6]; @@ -957,7 +956,7 @@ struct FSP_S_CONFIG { **/ uint8_t PcieRpLtrConfigLock[6]; -/** Offset 0x0191 - PME_B0_S5 Diable bit +/** Offset 0x0191 - PME_B0_S5 Disable bit PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. $EN_DIS **/ @@ -1029,8 +1028,8 @@ struct FSP_S_CONFIG { uint8_t SataPortsHotPlug[2]; /** Offset 0x01A0 - Mechanical Presence Switch - Controls reporting if this port has an Mechanical Presence Switch.\nNote:Requires - hardware support. 0:Disable, 1:Enable(Default). + Controls reporting if this port has an Mechanical Presence Switch.\n + Note:Requires hardware support. 0:Disable, 1:Enable(Default). **/ uint8_t SataPortsInterlockSw[2]; @@ -1075,20 +1074,9 @@ struct FSP_S_CONFIG { **/ uint16_t SubSystemId; -/** Offset 0x01B4 - PM Base Address - PM Base Address. 0x400(Default). +/** Offset 0x01B4 **/ - uint16_t AcpiBase; - -/** Offset 0x01B6 - PMC Base Address - PMC Base Address. 0xD10010000(Default). -**/ - uint32_t PmcBase; - -/** Offset 0x01BA - P2SB Base Address - P2SB Base Address. 0xD0000000(Default). -**/ - uint32_t P2sbBase; + uint8_t UnusedUpdSpace2[10]; /** Offset 0x01BE - CRIDSettings PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. @@ -1150,7 +1138,7 @@ struct FSP_S_CONFIG { /** Offset 0x01C8 - Start Frame Pulse Width Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. - $EN_DIS + 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk **/ uint8_t StartFramePulse; @@ -1166,10 +1154,9 @@ struct FSP_S_CONFIG { **/ uint8_t ArpEnable; -/** Offset 0x01CB - SMBus Base Address (IO space) - SMBUS Base Address (IO space). 0xEFA0(Default). +/** Offset 0x01CB **/ - uint16_t SmbusIoBase; + uint16_t UnusedUpdSpace3; /** Offset 0x01CD - SMBus Table Elements The number of elements in the Reserved SMBus Address Table. 0x0080(Default). @@ -1189,14 +1176,14 @@ struct FSP_S_CONFIG { uint8_t DisableComplianceMode; /** Offset 0x0250 - USB Per-Port Control - Control each of the USB ports (0~3) enable/disable. 0:Disable(Default), 1:Enable. + Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t UsbPerPortCtl; /** Offset 0x0251 - xHCI Mode - Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default), 3:SmartAuto. - $EN_DIS + Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default) + 0:Disable, 1:Enable, 2:Auto **/ uint8_t Usb30Mode; @@ -1224,7 +1211,7 @@ struct FSP_S_CONFIG { /** Offset 0x026E - XDCI Support Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. - $EN_DIS + 0:Disable, 1:PCI_Mode, 2:ACPI_mode **/ uint8_t UsbOtg; @@ -1293,8 +1280,10 @@ struct FSP_S_CONFIG { uint16_t PcieRpLtrMaxSnoopLatency[6]; /** Offset 0x028A - Snoop Latency Override - Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually - enter override values.\nAuto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). + Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). **/ uint8_t PcieRpSnoopLatencyOverrideMode[6]; @@ -1315,9 +1304,10 @@ struct FSP_S_CONFIG { uint16_t PcieRpLtrMaxNonSnoopLatency[6]; /** Offset 0x02AE - Non Snoop Latency Override - Non Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually - enter override values.\nAuto: Maintain default BIOS flow. 0:Disable, 1:Enable, - 2:Auto(Default). + Non Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). **/ uint8_t PcieRpNonSnoopLatencyOverrideMode[6]; @@ -1361,7 +1351,7 @@ struct FSP_S_CONFIG { **/ uint8_t TcoTimerHaltLock; -/** Offset 0x02D5 - Power Button Override Peroid +/** Offset 0x02D5 - Power Button Override Period specifies how long will PMC wait before initiating a global reset. 000b-4s(default), 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.) 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s @@ -1369,7 +1359,7 @@ struct FSP_S_CONFIG { uint8_t PwrBtnOverridePeriod; /** Offset 0x02D6 - Power Button Native Mode Disable - Diable power button native mode, when 1, this will result in the PMC logic constantly + Disable power button native mode, when 1, this will result in the PMC logic constantly seeing the power button as de-asserted. 0 (default)) $EN_DIS **/ @@ -1479,13 +1469,20 @@ struct FSP_S_CONFIG { /** Offset 0x0326 - Os Selection Mode Select OS mode. 0:Windows(default), 1:Android, 2:Win7 - $EN_DIS + 0:Windows, 1:Android, 2:Win7 **/ uint8_t OsSelection; -/** Offset 0x0327 +/** Offset 0x0327 - Monitor Mwait Enable + Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux + based OS, this should be Disabled. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t MonitorMwaitEnable; + +/** Offset 0x0328 **/ - uint8_t ReservedFspsUpd[9]; + uint8_t ReservedFspsUpd[8]; } __attribute__((packed)); /** Fsp S Test Configuration

1 0

Patch set updated for coreboot: soc/apollolake: Allow enable\disable of LPSS S0ix from devicetree
by Hannah Williams 29 Jun '16

29 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15055 -gerrit commit 4c6101625f0d544b65c55514adf2987e5c6f049a Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue May 3 15:15:31 2016 -0700 soc/apollolake: Allow enable\disable of LPSS S0ix from devicetree Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/chip.c | 2 ++ src/soc/intel/apollolake/chip.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 044ef91..edf4a56 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -255,6 +255,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->IshEnable = cfg->integrated_sensor_hub_enable; + silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; + /* Disable setting of EISS bit in FSP. */ silconfig->SpiEiss = 0; } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ef82c53..49e0be4 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -79,6 +79,8 @@ struct soc_intel_apollolake_config { /* Integrated Sensor Hub */ uint8_t integrated_sensor_hub_enable; + /* Configure LPSS S0ix Enable */ + uint8_t lpss_s0ix_enable; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */

1 0

Patch set updated for coreboot: soc/intel/apollolake: Update Upd header files for FSP Label 143_10
by Brandon Breitenstein 29 Jun '16

29 Jun '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15459 -gerrit commit c743fbf81c21f07baea59bf27172b2f7343ee70f Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Jun 24 10:41:39 2016 -0700 soc/intel/apollolake: Update Upd header files for FSP Label 143_10 New UPDs added to header files as well as many comment fixes. Memory infor is now defined in FspmUpd.h and added ability to skip CSE RBP for coreboot. Removes some UPDs that are no longer available from source. BUG=chrome-os-partner:54677 BRANCH=none TEST=built and tested with FSP 143_10 version Change-Id: I7e1f531ebbe343b45151a265ac715ae74aeffcad Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/chip.c | 6 -- src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 47 +++++++++++- src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 83 +++++++++++----------- 3 files changed, 85 insertions(+), 51 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 821570b..044ef91 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -253,12 +253,6 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) if (cfg->emmc_rx_cmd_data_cntl2 != 0) silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; - /* Our defaults may not match FSP defaults, so set them explicitly */ - silconfig->AcpiBase = ACPI_PMIO_BASE; - /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ - silconfig->PmcBase = PMC_BAR0 + 0x1000; - silconfig->P2sbBase = P2SB_BAR; - silconfig->IshEnable = cfg->integrated_sensor_hub_enable; /* Disable setting of EISS bit in FSP. */ diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index 5f5f367..3712fd7 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -36,6 +36,42 @@ are permitted provided that the following conditions are met: #include "FspUpd.h" #include <fsp/upd.h> +#define MAX_CHANNELS_NUM 4 +#define MAX_DIMMS_NUM 1 + +struct DIMM_INFO { + uint8_t DimmId; + uint32_t SizeInMb; + uint16_t MfgId; + /** Module part number for DRR3 is 18 bytes + but DRR4 is 20 bytes as per JEDEC Spec, so + reserving 20 bytes **/ + uint8_t ModulePartNum[20]; +} __attribute__((packed)); + +struct CHANNEL_INFO { + uint8_t ChannelId; + uint8_t DimmCount; + struct DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} __attribute__((packed)); + +struct FSP_SMBIOS_MEMORY_INFO { + uint8_t Revision; + uint8_t DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + uint16_t MemoryType; + uint16_t MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + uint8_t ErrorCorrectionType; + uint8_t ChannelCount; + struct CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} __attribute__((packed)); + + /** Fsp M Configuration **/ struct FSP_M_CONFIG { @@ -528,9 +564,16 @@ struct FSP_M_CONFIG { **/ void* MrcBootDataPtr; -/** Offset 0x0135 +/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB + Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of + CSE. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + uint8_t SkipCseRbp; + +/** Offset 0x0136 **/ - uint8_t ReservedFspmUpd[27]; + uint8_t ReservedFspmUpd[26]; } __attribute__((packed)); /** Fsp M Test Configuration diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h index d4ecd36..8dd824b 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h @@ -587,10 +587,9 @@ struct FSP_S_CONFIG { **/ uint8_t HpetFunctionNumber; -/** Offset 0x00AF - Hpet Base Address - Hpet Base Address. 0xFED00000(Default). +/** Offset 0x00AF **/ - uint32_t HpetBase; + uint32_t UnusedUpdSpace1; /** Offset 0x00B3 - IoApic Valid BDF Value Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. @@ -635,7 +634,7 @@ struct FSP_S_CONFIG { **/ uint8_t IshEnable; -/** Offset 0x00BB - ISH Controller +/** Offset 0x00BB - BIOS Interface Lock Down Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. 0:Disable, 1:Enable(Default). $EN_DIS @@ -663,7 +662,7 @@ struct FSP_S_CONFIG { Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t S0ixEnable; + uint8_t LPSS_S0ixEnable; /** Offset 0x00C0 - LPSS I2C Clock Gating Configuration Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). @@ -770,8 +769,8 @@ struct FSP_S_CONFIG { **/ uint8_t Spi2Enable; -/** Offset 0x00DE - UART Debug Bass Address - UART Debug Bass Address. 0x00000000(Default). +/** Offset 0x00DE - UART Debug Base Address + UART Debug Base Address. 0x00000000(Default). **/ uint32_t Uart2KernelDebugBaseAddress; @@ -810,7 +809,7 @@ struct FSP_S_CONFIG { **/ uint8_t PcieRootPortPeerMemoryWriteEnable; -/** Offset 0x00E8 - PCIE SWSMI Nubmer +/** Offset 0x00E8 - PCIE SWSMI Number This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). **/ uint8_t PcieAspmSwSmiNumber; @@ -932,7 +931,7 @@ struct FSP_S_CONFIG { uint8_t PcieRpCompletionTimeout[6]; /** Offset 0x0173 - PTM Support - Enable/Diable PTM Support. 0:Disable(Default), 1:Enable. + Enable/Disable PTM Support. 0:Disable(Default), 1:Enable. **/ uint8_t PtmEnable[6]; @@ -957,7 +956,7 @@ struct FSP_S_CONFIG { **/ uint8_t PcieRpLtrConfigLock[6]; -/** Offset 0x0191 - PME_B0_S5 Diable bit +/** Offset 0x0191 - PME_B0_S5 Disable bit PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. $EN_DIS **/ @@ -1029,8 +1028,8 @@ struct FSP_S_CONFIG { uint8_t SataPortsHotPlug[2]; /** Offset 0x01A0 - Mechanical Presence Switch - Controls reporting if this port has an Mechanical Presence Switch.\nNote:Requires - hardware support. 0:Disable, 1:Enable(Default). + Controls reporting if this port has an Mechanical Presence Switch.\n + Note:Requires hardware support. 0:Disable, 1:Enable(Default). **/ uint8_t SataPortsInterlockSw[2]; @@ -1075,20 +1074,9 @@ struct FSP_S_CONFIG { **/ uint16_t SubSystemId; -/** Offset 0x01B4 - PM Base Address - PM Base Address. 0x400(Default). +/** Offset 0x01B4 **/ - uint16_t AcpiBase; - -/** Offset 0x01B6 - PMC Base Address - PMC Base Address. 0xD10010000(Default). -**/ - uint32_t PmcBase; - -/** Offset 0x01BA - P2SB Base Address - P2SB Base Address. 0xD0000000(Default). -**/ - uint32_t P2sbBase; + uint8_t UnusedUpdSpace2[10]; /** Offset 0x01BE - CRIDSettings PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. @@ -1150,7 +1138,7 @@ struct FSP_S_CONFIG { /** Offset 0x01C8 - Start Frame Pulse Width Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. - $EN_DIS + 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk **/ uint8_t StartFramePulse; @@ -1166,10 +1154,9 @@ struct FSP_S_CONFIG { **/ uint8_t ArpEnable; -/** Offset 0x01CB - SMBus Base Address (IO space) - SMBUS Base Address (IO space). 0xEFA0(Default). +/** Offset 0x01CB **/ - uint16_t SmbusIoBase; + uint16_t UnusedUpdSpace3; /** Offset 0x01CD - SMBus Table Elements The number of elements in the Reserved SMBus Address Table. 0x0080(Default). @@ -1189,14 +1176,14 @@ struct FSP_S_CONFIG { uint8_t DisableComplianceMode; /** Offset 0x0250 - USB Per-Port Control - Control each of the USB ports (0~3) enable/disable. 0:Disable(Default), 1:Enable. + Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t UsbPerPortCtl; /** Offset 0x0251 - xHCI Mode - Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default), 3:SmartAuto. - $EN_DIS + Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default) + 0:Disable, 1:Enable, 2:Auto **/ uint8_t Usb30Mode; @@ -1224,7 +1211,7 @@ struct FSP_S_CONFIG { /** Offset 0x026E - XDCI Support Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. - $EN_DIS + 0:Disable, 1:PCI_Mode, 2:ACPI_mode **/ uint8_t UsbOtg; @@ -1293,8 +1280,10 @@ struct FSP_S_CONFIG { uint16_t PcieRpLtrMaxSnoopLatency[6]; /** Offset 0x028A - Snoop Latency Override - Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually - enter override values.\nAuto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). + Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). **/ uint8_t PcieRpSnoopLatencyOverrideMode[6]; @@ -1315,9 +1304,10 @@ struct FSP_S_CONFIG { uint16_t PcieRpLtrMaxNonSnoopLatency[6]; /** Offset 0x02AE - Non Snoop Latency Override - Non Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually - enter override values.\nAuto: Maintain default BIOS flow. 0:Disable, 1:Enable, - 2:Auto(Default). + Non Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). **/ uint8_t PcieRpNonSnoopLatencyOverrideMode[6]; @@ -1361,7 +1351,7 @@ struct FSP_S_CONFIG { **/ uint8_t TcoTimerHaltLock; -/** Offset 0x02D5 - Power Button Override Peroid +/** Offset 0x02D5 - Power Button Override Period specifies how long will PMC wait before initiating a global reset. 000b-4s(default), 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.) 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s @@ -1369,7 +1359,7 @@ struct FSP_S_CONFIG { uint8_t PwrBtnOverridePeriod; /** Offset 0x02D6 - Power Button Native Mode Disable - Diable power button native mode, when 1, this will result in the PMC logic constantly + Disable power button native mode, when 1, this will result in the PMC logic constantly seeing the power button as de-asserted. 0 (default)) $EN_DIS **/ @@ -1479,13 +1469,20 @@ struct FSP_S_CONFIG { /** Offset 0x0326 - Os Selection Mode Select OS mode. 0:Windows(default), 1:Android, 2:Win7 - $EN_DIS + 0:Windows, 1:Android, 2:Win7 **/ uint8_t OsSelection; -/** Offset 0x0327 +/** Offset 0x0327 - Monitor Mwait Enable + Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux + based OS, this should be Disabled. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t MonitorMwaitEnable; + +/** Offset 0x0328 **/ - uint8_t ReservedFspsUpd[9]; + uint8_t ReservedFspsUpd[8]; } __attribute__((packed)); /** Fsp S Test Configuration

1 0

New patch to review for coreboot: ga-g41m-es2l: add cmos.layout
by Arthur Heymans 28 Jun '16

28 Jun '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15493 -gerrit commit a81768ecee815cd9c764951571a27b75e6f1f44d Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jun 18 23:26:46 2016 +0200 ga-g41m-es2l: add cmos.layout This adds a cmos.layout and a cmos.default to ga-g41m-es2l. This allows to set things like baud_rate, debug_level, etc. from cmos. Change-Id: I25df7a1f3a0ce486b96cfe05bda628f604b0baec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 2 + src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 5 + src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout | 119 +++++++++++++++++++++++ 3 files changed, 126 insertions(+) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 7dec921..6452f4d 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE select REALTEK_8168_RESET + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default new file mode 100644 index 0000000..c20ba94 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable \ No newline at end of file diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout new file mode 100644 index 0000000..f92de11 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -0,0 +1,119 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: cpu +#424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size +#435 549 r 0 unused + + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984

1 0

New patch to review for coreboot: x4x: make preallocated IGD memory a cmos option
by Arthur Heymans 28 Jun '16

28 Jun '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15492 -gerrit commit c94e51ae02e859e700be6640eea74791f1a5f2bd Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jun 18 21:52:30 2016 +0200 x4x: make preallocated IGD memory a cmos option This allows to set the preallocated memory for the IGD on x4x using a cmos option. If no cmos option is found a default value of 64M is used. Change-Id: I9051d080be82f6dfab37d353252e29b2ed1fca7f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/early_init.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index b522293..a430538 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include "iomap.h" #include <southbridge/intel/i82801gx/i82801gx.h> /* DEFAULT_PMBASE */ +#include <pc80/mc146818rtc.h> #include "x4x.h" void x4x_early_init(void) @@ -51,5 +52,12 @@ void x4x_early_init(void) /* Enable internal GFX */ pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); - pci_write_config16(d0f0, D0F0_GGC, 0x0170); + /* Set preallocated IGD size from cmos */ + u8 gfxsize; + + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { + /* 6 for 64MB, default if not set in cmos */ + gfxsize = 6; + } + pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4)); }

1 0

New patch to review for coreboot: x4x: add non documented vram sizes
by Arthur Heymans 28 Jun '16

28 Jun '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15491 -gerrit commit 233e9de0c9e0fc81cd0a03bd9fb42bf7ec09bc91 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jun 18 21:08:58 2016 +0200 x4x: add non documented vram sizes The Intel documtentation, "Intel ® 4 Series Chipset Family" mentions the possibility of 1, 4, 8 and 16M of preallocated memory for the IGD, but does not document this. This allows to set those undocumented values. Change-Id: I92beb8d78907d4514a5aaf69248dd607dcf227c0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/ram_calc.c | 2 +- src/northbridge/intel/x4x/raminit_ddr2.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 27562ea..5a6a767 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -28,7 +28,7 @@ /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) { - static const u16 ggc2uma[] = { 0, 0, 0, 0, 0, + static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; if (gms > ARRAY_SIZE(ggc2uma)) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 5acb127..cc5624f 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -1626,7 +1626,8 @@ static void mmap_ddr2(struct sysinfo *s) u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud; u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit; u16 ggc; - u16 ggc2uma[] = { 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; + u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, + 160, 224, 352 }; u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; ggc = pci_read_config16(PCI_DEV(0,0,0), 0x52);

1 0

Patch merged into coreboot/master: soc/intel/apollolake: Add NHLT table region to ACPI global nvs
by gerrit＠coreboot.org 28 Jun '16

28 Jun '16

the following patch was just integrated into master: commit 3d0e2871cbf6d0c639ed1c4864c919318c3a8e28 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Mar 31 15:41:30 2016 -0700 soc/intel/apollolake: Add NHLT table region to ACPI global nvs Add address and length of NHLT table in ACPI. Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> Reviewed-on: https://review.coreboot.org/15025 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/15025 for details. -gerrit

1 0

Patch set updated for coreboot: lib/nhlt: drop nhlt_soc_add_endpoint()
by Aaron Durbin 28 Jun '16

28 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15489 -gerrit commit bc286472571b1ea6136094c6023b0896bbb04da1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 28 15:36:01 2016 -0500 lib/nhlt: drop nhlt_soc_add_endpoint() The nhlt_soc_add_endpoint() is no longer used. Drop its declaration. Change-Id: I3b68471650a43c5faae44bde523abca7ba250a34 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/nhlt.h | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/include/nhlt.h b/src/include/nhlt.h index 3300d43..17b7d11 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -45,7 +45,7 @@ struct nhlt_format_config; * An example sequence: * * nhlt = nhlt_init() - * ep = nhlt_soc_add_endpoint() + * ep = nhlt_add_endpoint() * nhlt_endpoint_append_config(ep) * nhlt_endpoint_add_formats(ep) * nhlt_soc_serialize() @@ -97,19 +97,13 @@ int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id, /* * Add endpoint to NHLT object. Returns NULL on error. * - * Note that the SoC variant uses SoC-specifc types for the hardware interface - * and device types. This is to allow the SoC code to validate its particular - * device support for specific hardware interfaces. - * - * The more generic nhlt_add_endpoint() is called by the SoC code to provide + * generic nhlt_add_endpoint() is called by the SoC code to provide * the specific assumptions/uses for NHLT for that platform. All fields * are the NHLT enumerations found within this header file. */ struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type, int device_type, int dir, uint16_t vid, uint16_t did); -struct nhlt_endpoint *nhlt_soc_add_endpoint(struct nhlt *nhlt, int soc_hwintf, - int soc_devtype, int dir); /* * Append blob of configuration to the endpoint proper. Returns 0 on

1 0

Patch set updated for coreboot: soc/intel/{common, skylake}: provide common NHLT SoC support
by Aaron Durbin 28 Jun '16

28 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15490 -gerrit commit 8f55d9f7d54ea5aa1d85c6aaae62c6bc33a5c76e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 28 15:41:07 2016 -0500 soc/intel/{common,skylake}: provide common NHLT SoC support The nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides() functions should be able to be levearaged on all Intel SoCs which support NHLT. Therefore provide that functionality and make skylake use it. Change-Id: Ib5535cc874f2680ec22554cecaf97b09753cacd0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/common/Kconfig | 4 ++++ src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/nhlt.c | 41 +++++++++++++++++++++++++++++++++ src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/nhlt/Makefile.inc | 1 - src/soc/intel/skylake/nhlt/nhlt.c | 41 --------------------------------- 6 files changed, 47 insertions(+), 42 deletions(-) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index fdd8f04..776004b 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -99,4 +99,8 @@ config SOC_INTEL_COMMON_ACPI bool default n +config SOC_INTEL_COMMON_NHLT + bool + default n + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 88d5fd2..e9ad508 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -20,6 +20,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c new file mode 100644 index 0000000..d498152 --- /dev/null +++ b/src/soc/intel/common/nhlt.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <nhlt.h> +#include <soc/acpi.h> + +uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) +{ + return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); +} + +uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, + uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs == NULL) + return acpi_addr; + + /* Update NHLT GNVS Data */ + gnvs->nhla = (uintptr_t)acpi_addr; + gnvs->nhll = nhlt_current_size(nhlt); + + return nhlt_serialize_oem_overrides(nhlt, acpi_addr, + oem_id, oem_table_id); +} diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index a134d1c..6843cef 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -38,6 +38,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_LPSS_I2C + select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SMM_TSEG select SMP diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index aff182c..e022482 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -1,4 +1,3 @@ -ramstage-y += nhlt.c ramstage-y += dmic.c ramstage-y += nau88l25.c ramstage-y += max98357.c diff --git a/src/soc/intel/skylake/nhlt/nhlt.c b/src/soc/intel/skylake/nhlt/nhlt.c deleted file mode 100644 index d498152..0000000 --- a/src/soc/intel/skylake/nhlt/nhlt.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <nhlt.h> -#include <soc/acpi.h> - -uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) -{ - return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); -} - -uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, - uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) -{ - global_nvs_t *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - if (gnvs == NULL) - return acpi_addr; - - /* Update NHLT GNVS Data */ - gnvs->nhla = (uintptr_t)acpi_addr; - gnvs->nhll = nhlt_current_size(nhlt); - - return nhlt_serialize_oem_overrides(nhlt, acpi_addr, - oem_id, oem_table_id); -}

1 0

Patch set updated for coreboot: soc/intel/skylake: refactor nhlt support
by Aaron Durbin 28 Jun '16

28 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15488 -gerrit commit 4406e88ba365322121f4f78fd6f67a919d690ab4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 28 15:00:30 2016 -0500 soc/intel/skylake: refactor nhlt support Utilize the new NHLT helper functions by driving the NHLT endpoints through data descriptors. Change-Id: I80838214d3615b83d4939ec2d96a4fd7050d5920 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/include/soc/nhlt.h | 15 +++--- src/soc/intel/skylake/nhlt/dmic.c | 81 +++++++++++++++++++------------- src/soc/intel/skylake/nhlt/max98357.c | 33 +++++++------ src/soc/intel/skylake/nhlt/nau88l25.c | 74 ++++++++++++++--------------- src/soc/intel/skylake/nhlt/nhlt.c | 70 +-------------------------- src/soc/intel/skylake/nhlt/ssm4567.c | 57 +++++++++++----------- 6 files changed, 136 insertions(+), 194 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index 3800bb9..008dd0d 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -18,9 +18,14 @@ #include <nhlt.h> +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + /* - * Skylake NHLT device and hardware link types. These values are to be used - * with nhlt_soc_add_endpoint(). + * Skylake NHLT link types. These values are to be used for the hwlink + * fields in the functions below to specify which link a device is on. */ enum { @@ -30,12 +35,6 @@ enum { AUDIO_LINK_DMIC, }; -enum { - AUDIO_DEV_I2S, - AUDIO_DEV_DMIC, - AUDIO_DEV_BT, -}; - /* * Add a dmic array composed of the provided number of channels. The skylake * SoC currently only supports dmic arrays on the dmic signals. Either 2 diff --git a/src/soc/intel/skylake/nhlt/dmic.c b/src/soc/intel/skylake/nhlt/dmic.c index 6e14891..a7684bd 100644 --- a/src/soc/intel/skylake/nhlt/dmic.c +++ b/src/soc/intel/skylake/nhlt/dmic.c @@ -14,9 +14,8 @@ */ #include <soc/nhlt.h> -#include <string.h> -static const struct nhlt_format_config dmic_2ch_cfg[] = { +static const struct nhlt_format_config dmic_2ch_formats[] = { /* 48 KHz 16-bits per sample. */ { .num_channels = 2, @@ -37,7 +36,28 @@ static const struct nhlt_format_config dmic_2ch_cfg[] = { }, }; -static const struct nhlt_format_config dmic_4ch_cfg[] = { +static const struct nhlt_dmic_array_config dmic_2ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_MIC_ARRAY, + }, + .array_type = NHLT_MIC_ARRAY_2CH_SMALL, +}; + +static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_2ch_mic_config, + .cfg_size = sizeof(dmic_2ch_mic_config), + .formats = dmic_2ch_formats, + .num_formats = ARRAY_SIZE(dmic_2ch_formats), + }, +}; + +static const struct nhlt_format_config dmic_4ch_formats[] = { /* 48 KHz 16-bits per sample. */ { .num_channels = 4, @@ -60,42 +80,37 @@ static const struct nhlt_format_config dmic_4ch_cfg[] = { }, }; -int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) -{ - struct nhlt_endpoint *endp; - struct nhlt_dmic_array_config mic_config; - const struct nhlt_format_config *formats; - size_t num_formats; - - if (num_channels != 2 && num_channels != 4) - return -1; - - endp = nhlt_soc_add_endpoint(nhlt, AUDIO_LINK_DMIC, AUDIO_DEV_DMIC, - NHLT_DIR_CAPTURE); - - if (endp == NULL) - return -1; +static const struct nhlt_dmic_array_config dmic_4ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_MIC_ARRAY, + }, + .array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED, +}; - memset(&mic_config, 0, sizeof(mic_config)); - mic_config.tdm_config.config_type = NHLT_TDM_MIC_ARRAY; +static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_4ch_mic_config, + .cfg_size = sizeof(dmic_4ch_mic_config), + .formats = dmic_4ch_formats, + .num_formats = ARRAY_SIZE(dmic_4ch_formats), + }, +}; +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) +{ switch (num_channels) { case 2: - formats = dmic_2ch_cfg; - num_formats = ARRAY_SIZE(dmic_2ch_cfg); - mic_config.array_type = NHLT_MIC_ARRAY_2CH_SMALL; - break; + return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors, + ARRAY_SIZE(dmic_2ch_descriptors)); case 4: - formats = dmic_4ch_cfg; - num_formats = ARRAY_SIZE(dmic_4ch_cfg); - mic_config.array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED; - break; + return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors, + ARRAY_SIZE(dmic_4ch_descriptors)); default: return -1; } - - if (nhlt_endpoint_append_config(endp, &mic_config, sizeof(mic_config))) - return -1; - - return nhlt_endpoint_add_formats(endp, formats, num_formats); } diff --git a/src/soc/intel/skylake/nhlt/max98357.c b/src/soc/intel/skylake/nhlt/max98357.c index fa14dd2..b2abc26 100644 --- a/src/soc/intel/skylake/nhlt/max98357.c +++ b/src/soc/intel/skylake/nhlt/max98357.c @@ -15,7 +15,7 @@ #include <soc/nhlt.h> -static const struct nhlt_format_config max98357_render_cfg[] = { +static const struct nhlt_format_config max98357_render_formats[] = { /* 48 KHz 24-bits per sample. */ { .num_channels = 2, @@ -27,22 +27,21 @@ static const struct nhlt_format_config max98357_render_cfg[] = { }, }; +static const struct nhlt_endp_descriptor max98357_descriptors[] = { + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = max98357_render_formats, + .num_formats = ARRAY_SIZE(max98357_render_formats), + }, +}; + int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink) { - struct nhlt_endpoint *endp; - - /* Render Endpoint */ - endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, - NHLT_DIR_RENDER); - - if (endp == NULL) - return -1; - - if (nhlt_endpoint_add_formats(endp, max98357_render_cfg, - ARRAY_SIZE(max98357_render_cfg))) - return -1; - - nhlt_next_instance(nhlt, NHLT_LINK_SSP); - - return 0; + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, max98357_descriptors, + ARRAY_SIZE(max98357_descriptors)); } diff --git a/src/soc/intel/skylake/nhlt/nau88l25.c b/src/soc/intel/skylake/nhlt/nau88l25.c index 0a6dd1b..dd91435 100644 --- a/src/soc/intel/skylake/nhlt/nau88l25.c +++ b/src/soc/intel/skylake/nhlt/nau88l25.c @@ -17,7 +17,7 @@ /* The same DSP firmware settings are used for both the capture and * render endpoints. */ -static const struct nhlt_format_config nau88l25_cfg[] = { +static const struct nhlt_format_config nau88l25_formats[] = { /* 48 KHz 24-bits per sample. */ { .num_channels = 2, @@ -29,45 +29,43 @@ static const struct nhlt_format_config nau88l25_cfg[] = { }, }; -int nhlt_soc_add_nau88l25(struct nhlt *nhlt, int hwlink) -{ - struct nhlt_endpoint *endp; - /* The nau88l25 just has headphones and a mic. Both the capture and - * render endpoints occupy the same virtual slot. */ - struct nhlt_tdm_config tdm_config = { - .virtual_slot = 0, - .config_type = NHLT_TDM_BASIC, - }; - const void *fmt_cfg = nau88l25_cfg; - size_t fmt_sz = ARRAY_SIZE(nau88l25_cfg); +/* The nau88l25 just has headphones and a mic. Both the capture and render + * endpoints occupy the same virtual slot. */ +static const struct nhlt_tdm_config tdm_config = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; +static const struct nhlt_endp_descriptor nau88l25_descriptors[] = { /* Render Endpoint */ - endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, - NHLT_DIR_RENDER); - - if (endp == NULL) - return -1; - - if (nhlt_endpoint_append_config(endp, &tdm_config, sizeof(tdm_config))) - return -1; - - if (nhlt_endpoint_add_formats(endp, fmt_cfg, fmt_sz)) - return -1; - + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = nau88l25_formats, + .num_formats = ARRAY_SIZE(nau88l25_formats), + }, /* Capture Endpoint */ - endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, - NHLT_DIR_CAPTURE); - - if (endp == NULL) - return -1; - - if (nhlt_endpoint_append_config(endp, &tdm_config, sizeof(tdm_config))) - return -1; - - if (nhlt_endpoint_add_formats(endp, fmt_cfg, fmt_sz)) - return -1; - - nhlt_next_instance(nhlt, NHLT_LINK_SSP); + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = nau88l25_formats, + .num_formats = ARRAY_SIZE(nau88l25_formats), + }, +}; - return 0; +int nhlt_soc_add_nau88l25(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, nau88l25_descriptors, + ARRAY_SIZE(nau88l25_descriptors)); } diff --git a/src/soc/intel/skylake/nhlt/nhlt.c b/src/soc/intel/skylake/nhlt/nhlt.c index 6ef906a..d498152 100644 --- a/src/soc/intel/skylake/nhlt/nhlt.c +++ b/src/soc/intel/skylake/nhlt/nhlt.c @@ -14,76 +14,8 @@ */ #include <cbmem.h> +#include <nhlt.h> #include <soc/acpi.h> -#include <soc/nhlt.h> - -#define NHLT_VID 0x8086 -#define NHLT_DID_DMIC 0xae20 -#define NHLT_DID_BT 0xae30 -#define NHLT_DID_SSP 0xae34 - -struct nhlt_endpoint *nhlt_soc_add_endpoint(struct nhlt *nhlt, int soc_hwintf, - int soc_devtype, int dir) -{ - int nhlt_link_type; - int nhlt_dev_type; - uint16_t did; - struct nhlt_endpoint *endp; - - /* Check link type and device type. */ - switch (soc_hwintf) { - case AUDIO_LINK_SSP0: - case AUDIO_LINK_SSP1: - /* Only I2S devices on SSP0 and SSP1. */ - if (soc_devtype != AUDIO_DEV_I2S) - return NULL; - nhlt_link_type = NHLT_LINK_SSP; - break; - case AUDIO_LINK_SSP2: - /* Only Bluetooth devices on SSP2. */ - if (soc_devtype != AUDIO_DEV_BT) - return NULL; - nhlt_link_type = NHLT_LINK_SSP; - break; - case AUDIO_LINK_DMIC: - /* Only DMIC devices on DMIC links. */ - if (soc_devtype != AUDIO_DEV_DMIC) - return NULL; - nhlt_link_type = NHLT_LINK_PDM; - break; - default: - return NULL; - } - - switch (soc_devtype) { - case AUDIO_DEV_I2S: - nhlt_dev_type = NHLT_SSP_DEV_I2S; - did = NHLT_DID_SSP; - break; - case AUDIO_DEV_DMIC: - nhlt_dev_type = NHLT_PDM_DEV; - did = NHLT_DID_DMIC; - break; - case AUDIO_DEV_BT: - nhlt_dev_type = NHLT_SSP_DEV_BT; - did = NHLT_DID_BT; - break; - default: - return NULL; - } - - endp = nhlt_add_endpoint(nhlt, nhlt_link_type, nhlt_dev_type, dir, - NHLT_VID, did); - - if (endp == NULL) - return NULL; - - /* Virtual bus id of SSP links are the hardware port ids proper. */ - if (nhlt_link_type == NHLT_LINK_SSP) - endp->virtual_bus_id = soc_hwintf; - - return endp; -} uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) { diff --git a/src/soc/intel/skylake/nhlt/ssm4567.c b/src/soc/intel/skylake/nhlt/ssm4567.c index 55d9481..6808bff 100644 --- a/src/soc/intel/skylake/nhlt/ssm4567.c +++ b/src/soc/intel/skylake/nhlt/ssm4567.c @@ -15,7 +15,7 @@ #include <soc/nhlt.h> -static const struct nhlt_format_config ssm4567_render_cfg[] = { +static const struct nhlt_format_config ssm4567_render_formats[] = { /* 48 KHz 24-bits per sample. */ { .num_channels = 2, @@ -28,7 +28,7 @@ static const struct nhlt_format_config ssm4567_render_cfg[] = { }; /* Capture Blob used for IV feedback for Speaker Protection Algorithm */ -static const struct nhlt_format_config ssm4567_capture_cfg[] = { +static const struct nhlt_format_config ssm4567_capture_formats[] = { /* 48 KHz 32-bits per sample. */ { .num_channels = 4, @@ -39,33 +39,32 @@ static const struct nhlt_format_config ssm4567_capture_cfg[] = { }, }; -int nhlt_soc_add_ssm4567(struct nhlt *nhlt, int hwlink) -{ - struct nhlt_endpoint *endp; - +static const struct nhlt_endp_descriptor ssm4567_descriptors[] = { /* Render Endpoint */ - endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, - NHLT_DIR_RENDER); - - if (endp == NULL) - return -1; - - if (nhlt_endpoint_add_formats(endp, ssm4567_render_cfg, - ARRAY_SIZE(ssm4567_render_cfg))) - return -1; - - /* Capture Endpoint for IV Feedback */ - endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, - NHLT_DIR_CAPTURE); - - if (endp == NULL) - return -1; - - if (nhlt_endpoint_add_formats(endp, ssm4567_capture_cfg, - ARRAY_SIZE(ssm4567_capture_cfg))) - return -1; - - nhlt_next_instance(nhlt, NHLT_LINK_SSP); + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = ssm4567_render_formats, + .num_formats = ARRAY_SIZE(ssm4567_render_formats), + }, + /* Capture Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = ssm4567_capture_formats, + .num_formats = ARRAY_SIZE(ssm4567_capture_formats), + }, +}; - return 0; +int nhlt_soc_add_ssm4567(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, ssm4567_descriptors, + ARRAY_SIZE(ssm4567_descriptors)); }

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2016