coreboot-gerrit May 2016

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Patch set updated for coreboot: WIP: Add ifwitool for managing IFWI images
by Furquan Shaikh 24 May '16

24 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14896 -gerrit commit faa997a4c964c100c3c5ffcfee0a3dd6cc28a960 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu May 19 16:12:16 2016 -0700 WIP: Add ifwitool for managing IFWI images Still needs work to support subdir management. Change-Id: I683a0ab13cc50eb60eecca34db4a8ffefc8dccbd Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- util/cbfstool/Makefile | 2 + util/cbfstool/Makefile.inc | 8 + util/cbfstool/ifwitool.c | 1590 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1600 insertions(+) diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index 61a1a63..f49da3e 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -10,6 +10,7 @@ OBJCOPY ?= objcopy all: $(objutil)/cbfstool/cbfstool \ $(objutil)/cbfstool/fmaptool \ $(objutil)/cbfstool/rmodtool \ + $(objutil)/cbfstool/ifwitool \ .PHONY: clean clean: @@ -17,6 +18,7 @@ clean: $(RM) $(objutil)/cbfstool/cbfstool $(cbfsobj) $(RM) $(objutil)/cbfstool/fmaptool $(fmapobj) $(RM) $(objutil)/cbfstool/rmodtool $(rmodobj) + $(RM) $(objutil)/cbfstool/ifwitool $(ifwiobj) linux_trampoline.c: linux_trampoline.S rm -f linux_trampoline.c diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index aa42f01..6c2b100 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -58,6 +58,10 @@ rmodobj += common.o rmodobj += elfheaders.o rmodobj += xdr.o +ifwiobj := +ifwiobj += ifwitool.o +ifwiobj += common.o + TOOLCFLAGS ?= -Werror -Wall -Wextra TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings @@ -132,6 +136,10 @@ $(objutil)/cbfstool/rmodtool: $(addprefix $(objutil)/cbfstool/,$(rmodobj)) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(rmodobj)) +$(objutil)/cbfstool/ifwitool: $(addprefix $(objutil)/cbfstool/,$(ifwiobj)) + printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" + $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(ifwiobj)) + # Yacc source is superset of header $(objutil)/cbfstool/fmd.o: TOOLCFLAGS += -Wno-redundant-decls $(objutil)/cbfstool/fmd_parser.o: TOOLCFLAGS += -Wno-redundant-decls diff --git a/util/cbfstool/ifwitool.c b/util/cbfstool/ifwitool.c new file mode 100644 index 0000000..a38bf76 --- /dev/null +++ b/util/cbfstool/ifwitool.c @@ -0,0 +1,1590 @@ +/* + * ifwitool, CLI utility for IFWI manipulation + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <commonlib/endian.h> +#include <getopt.h> +#include <stdlib.h> + +#include "common.h" + +#define BPDT_SIGNATURE (0x000055AA) +#define KiB 1024 + +/* Parameters passed in by caller. */ +static struct param { + const char *file_name; + const char *comp_name; + const char *image_name; + bool subpart_ops; +} param; + +struct bpdt_header { + uint32_t signature; + uint16_t descriptor_count; + uint16_t bpdt_version; + uint32_t xor_redundant_block; + uint32_t ifwi_version; + uint64_t fit_tool_version; +}; +#define BPDT_HEADER_SIZE (sizeof(struct bpdt_header)) + +struct bpdt_entry { + uint16_t type; + uint16_t flags; + uint32_t offset; + uint32_t size; +}; +#define BPDT_ENTRY_SIZE (sizeof(struct bpdt_entry)) + +#define BPDT_SIZE(c) (BPDT_HEADER_SIZE + (c) * \ + BPDT_ENTRY_SIZE) + +struct subpart_header { + uint32_t marker; + uint32_t num_entries; + uint8_t header_version; + uint8_t entry_version; + uint8_t header_length; + uint8_t checksum; + uint8_t name[4]; +}; +#define SUBPART_HEADER_SIZE (sizeof(struct subpart_header)) +#define SUBPART_MARKER 0x44504324 +#define SUBPART_HEADER_VERSION_SUPPORTED 1 +#define SUBPART_ENTRY_VERSION_SUPPORTED 1 + +struct subpart_entry { + uint8_t name[12]; + uint32_t offset; + uint32_t length; + uint32_t rsvd; +}; +#define SUBPART_ENTRY_SIZE (sizeof(struct subpart_entry)) + +struct subpart { + struct subpart_header h; + struct subpart_entry e[1]; +}; +#define SUBPART_SIZE(c) (SUBPART_HEADER_SIZE + (c) * \ + SUBPART_ENTRY_SIZE) + +/* + * Attributes for various IFWI components. + * LIES_WITHIN_BPDT_4K = Component should lie within the same 4K block as BPDT. + * NON_CRITICAL_COMP = Component entry should be present in S-BPDT. + * CONTAINS_SUBPART = Component might require subpart operation (TODO(furquan)) + * AUTO_GENERATED = Component is generated by the tool. + * MANDATORY_BPDT_ENTRY = Even if component is deleted, BPDT should contain an + * entry for it with size 0 and offset 0. + */ +enum comp_attributes { + LIES_WITHIN_BPDT_4K = (1 << 0), + NON_CRITICAL_COMP = (1 << 1), + CONTAINS_SUBPART = (1 << 2), + AUTO_GENERATED = (1 << 3), + MANDATORY_BPDT_ENTRY = (1 << 4), +}; + +/* Type value for various IFWI components. */ +enum bpdt_entry_type { + SMIP_TYPE = 0, + CSE_RBE_TYPE = 1, + CSE_BUP_TYPE = 2, + UCODE_TYPE = 3, + IBB_TYPE = 4, + S_BPDT_TYPE = 5, + OBB_TYPE = 6, + CSE_MAIN_TYPE = 7, + ISH_TYPE = 8, + CSE_IDLM_TYPE = 9, + IFP_OVERRIDE_TYPE = 10, + DEBUG_TOKENS_TYPE = 11, + UFS_PHY_TYPE = 12, + UFS_GPP_TYPE = 13, + PMC_TYPE = 14, + IUNIT_TYPE = 15, + NVM_CONFIG_TYPE = 16, + UEP_TYPE = 17, + UFS_RATE_B_TYPE = 18, + MAX_COMPS = 19, +}; + +/* + * There are two order requirements for an IFWI image: + * 1. Order in which the entries lie within the BPDT. + * 2. Order in which the components lie within the image. + * + * header_order defines #1 i.e. the order in which the entries should appear in + * the BPDT. pack_order defines #2 i.e. the order in which components appear in + * the IFWI image. pack_order controls the offset and thus components would have + * increasing offsets as we loop over pack_order. + */ +enum bpdt_entry_type bpdt_header_order[MAX_COMPS] = { + CSE_IDLM_TYPE, + IFP_OVERRIDE_TYPE, + S_BPDT_TYPE, + CSE_RBE_TYPE, + UFS_PHY_TYPE, + UFS_GPP_TYPE, + CSE_BUP_TYPE, + UEP_TYPE, + NVM_CONFIG_TYPE, + SMIP_TYPE, + PMC_TYPE, + UCODE_TYPE, + IBB_TYPE, + DEBUG_TOKENS_TYPE, + UFS_RATE_B_TYPE, + ISH_TYPE, + CSE_MAIN_TYPE, + OBB_TYPE, + IUNIT_TYPE, +}; + +enum bpdt_entry_type bpdt_pack_order[MAX_COMPS] = { + CSE_IDLM_TYPE, + UFS_PHY_TYPE, + UFS_GPP_TYPE, + IFP_OVERRIDE_TYPE, + UEP_TYPE, + IBB_TYPE, + NVM_CONFIG_TYPE, + SMIP_TYPE, + CSE_RBE_TYPE, + PMC_TYPE, + CSE_BUP_TYPE, + UCODE_TYPE, + DEBUG_TOKENS_TYPE, + UFS_RATE_B_TYPE, + S_BPDT_TYPE, + ISH_TYPE, + CSE_MAIN_TYPE, + OBB_TYPE, + IUNIT_TYPE, +}; + +/* Utility functions. */ +enum ifwi_ret { + COMM_ERR = -1, + NO_ACTION_REQUIRED = 0, + REPACK_REQUIRED = 1, +}; + +struct cbp_ops { + enum ifwi_ret (*cbp_add)(int); +}; + +struct bpdt_comp { + const char *name; + uint32_t attr; + const char *subpart_name; + struct cbp_ops cbp_ops; +} comp[MAX_COMPS] = { + /* OEM SMIP */ + [SMIP_TYPE] = {"SMIP", CONTAINS_SUBPART, "SMIP", {NULL}}, + /* CSE RBE */ + [CSE_RBE_TYPE] = {"CSE_RBE", CONTAINS_SUBPART | MANDATORY_BPDT_ENTRY, + "RBEP", {NULL}}, + /* CSE BUP */ + [CSE_BUP_TYPE] = {"CSE_BUP", CONTAINS_SUBPART | MANDATORY_BPDT_ENTRY, + "FTPR", {NULL}}, + /* uCode */ + [UCODE_TYPE] = {"uCODE", CONTAINS_SUBPART, "UCOD", {NULL}}, + /* IBB */ + [IBB_TYPE] = {"bootblock", CONTAINS_SUBPART, "IBBP", {NULL}}, + /* S-BPDT */ + [S_BPDT_TYPE] = {"S_BPDT", AUTO_GENERATED | MANDATORY_BPDT_ENTRY, + NULL, {NULL}}, + /* OBB */ + [OBB_TYPE] = {"OBB", CONTAINS_SUBPART | NON_CRITICAL_COMP, "OBBP", + {NULL}}, + /* CSE Main */ + [CSE_MAIN_TYPE] = {"CSE_MAIN", NON_CRITICAL_COMP, "NFTP", {NULL}}, + /* ISH */ + [ISH_TYPE] = {"ISH", NON_CRITICAL_COMP, "ISHP", {NULL}}, + /* CSE IDLM */ + [CSE_IDLM_TYPE] = {"CSE_IDLM", CONTAINS_SUBPART | MANDATORY_BPDT_ENTRY, + "DLMP", {NULL}}, + /* IFP Override */ + [IFP_OVERRIDE_TYPE] = {"IFP_OVERRIDE", LIES_WITHIN_BPDT_4K | + MANDATORY_BPDT_ENTRY, NULL, {NULL}}, + /* Debug Tokens */ + [DEBUG_TOKENS_TYPE] = {"DEBUG_TOKENS", 0, NULL, {NULL}}, + /* UFS Phy Configuration */ + [UFS_PHY_TYPE] = {"UFS_PHY", LIES_WITHIN_BPDT_4K | MANDATORY_BPDT_ENTRY, + NULL, {NULL}}, + /* UFS GPP LUN ID */ + [UFS_GPP_TYPE] = {"UFS_GPP", LIES_WITHIN_BPDT_4K | MANDATORY_BPDT_ENTRY, + NULL, {NULL}}, + /* PMC */ + [PMC_TYPE] = {"PMC", CONTAINS_SUBPART, "PMCP", {NULL}}, + /* IUNIT */ + [IUNIT_TYPE] = {"IUNIT", NON_CRITICAL_COMP, "IUNP", {NULL}}, + /* NVM Config */ + [NVM_CONFIG_TYPE] = {"NVM_CONFIG", 0, NULL, {NULL}}, + /* UEP */ + [UEP_TYPE] = {"UEP", LIES_WITHIN_BPDT_4K | MANDATORY_BPDT_ENTRY, NULL, + {NULL}}, + /* UFS Rate B Config */ + [UFS_RATE_B_TYPE] = {"UFS_RATE_B", 0, NULL, {NULL}}, +}; + +/* + * Stores information about various components read from the input file. + * Also need to save any non-IFWI prefix and suffix in the image so that they + * can be restored when output image is created. + */ +struct ifwi_image { + struct buffer bpdt; + + struct buffer non_ifwi_prefix; + struct buffer non_ifwi_suffix; + + struct buffer subpart; + + struct buffer comp_buf[MAX_COMPS]; +} ifwi_image; + +static void alloc_buffer(struct buffer *b, size_t s, const char *n) +{ + if (buffer_create(b, s, n) == 0) + return; + + ERROR("Buffer allocation failure for %s (size = %zx).\n", n, s); + exit(-1); +} + +/* Read header/entry members in little-endian format. */ +static void read_member(void *src, size_t *offset, size_t size_bytes, void *dst) +{ + switch (size_bytes) { + case 1: + *(uint8_t *)dst = read_at_le8(src, *offset); + break; + case 2: + *(uint16_t *)dst = read_at_le16(src, *offset); + break; + case 4: + *(uint32_t *)dst = read_at_le32(src, *offset); + break; + case 8: + *(uint64_t *)dst = read_at_le64(src, *offset); + break; + default: + ERROR("Read size not supported %zd\n", size_bytes); + exit(-1); + } + + *offset += size_bytes; +} + +#define READ_MEMBER(m) read_member(data, &offset, sizeof(m), &m) + +/* Convert to little endian format. */ +static void fix_member(void *data, size_t *offset, size_t size_bytes) +{ + uint8_t *src = (uint8_t *)data + *offset; + + switch (size_bytes) { + case 1: + write_at_le8(data, *(uint8_t *)src, *offset); + break; + case 2: + write_at_le16(data, *(uint16_t *)src, *offset); + break; + case 4: + write_at_le32(data, *(uint32_t *)src, *offset); + break; + case 8: + write_at_le64(data, *(uint64_t *)src, *offset); + break; + default: + ERROR("Write size not supported %zd\n", size_bytes); + exit(-1); + } + *offset += size_bytes; +} + +#define FIX_MEMBER(m) fix_member(&m, &offset, sizeof(m)) + +static void print_subpart(const char *name) +{ + if (verbose == 0) + return; + + size_t i; + struct subpart *s = buffer_get(&ifwi_image.subpart); + + printf("\n%-25s %-25s\n", "Subpart Header", name); + printf("%-25s 0x%-23.8x\n", "Marker", s->h.marker); + printf("%-25s %-25d\n", "Num entries", s->h.num_entries); + printf("%-25s %-25d\n", "Header Version", s->h.header_version); + printf("%-25s %-25d\n", "Entry Version", s->h.entry_version); + printf("%-25s 0x%-23x\n", "Header Length", s->h.header_length); + printf("%-25s 0x%-23x\n", "Checksum", s->h.checksum); + printf("%-25s ", "Name"); + for (i = 0; i < sizeof(s->h.name); i++) + printf("%c", s->h.name[i]); + + printf("\n%s entries\n", name); + + printf("%-25s%-25s%-25s%-25s%-25s\n", "Entry #", "Name", "Offset", + "Length", "Rsvd"); + + printf("==============================================================" + "===========================================================\n"); + + for (i = 0; i < s->h.num_entries; i++) { + printf("%-25zd%-25.12s0x%-23x0x%-23x0x%-23x\n", i+1, + s->e[i].name, s->e[i].offset, s->e[i].length, + s->e[i].rsvd); + } + + printf("==============================================================" + "===========================================================\n"); +} + +static void bpdt_print_header(struct bpdt_header *h, const char *name) +{ + if (verbose == 0) + return; + + printf("%-25s %-25s\n", "Header", name); + printf("%-25s 0x%-23.8x\n", "Signature", h->signature); + printf("%-25s %-25d\n", "Descriptor count", h->descriptor_count); + printf("%-25s %-25d\n", "BPDT Version", h->bpdt_version); + printf("%-25s 0x%-23x\n", "XOR checksum", h->xor_redundant_block); + printf("%-25s 0x%-23x\n", "IFWI Version", h->ifwi_version); + printf("%-25s 0x%-23lx\n", "FIT Tool Version", h->fit_tool_version); +} + +static void bpdt_print_entries(struct bpdt_entry *e, size_t count, + const char *name) +{ + if (verbose == 0) + return; + + printf("%s entries\n", name); + + printf("%-25s%-25s%-25s%-25s%-25s%-25s\n", "Entry #", "Name", "Type", + "Flags", "Offset", "Size"); + + printf("==============================================================" + "==============================================================" + "=======================\n"); + + size_t i; + for (i = 0; i < count; i++) { + printf("%-25zd%-25s%-25d0x%-23.08x0x%-23x0x%-23x\n", i+1, + comp[e[i].type].name, e[i].type, e[i].flags, + e[i].offset, e[i].size); + } + + printf("==============================================================" + "==============================================================" + "=======================\n"); + +} + +static void bpdt_validate_header(struct bpdt_header *h, const char *name) +{ + assert (h->signature == BPDT_SIGNATURE); + + if (h->bpdt_version != 1) { + ERROR("Invalid header : %s\n", name); + exit(-1); + } + + DEBUG("Validated header : %s\n", name); +} + +static void bpdt_read_header(void *data, struct bpdt_header *h, + const char *name) +{ + size_t offset = 0; + + READ_MEMBER(h->signature); + READ_MEMBER(h->descriptor_count); + READ_MEMBER(h->bpdt_version); + READ_MEMBER(h->xor_redundant_block); + READ_MEMBER(h->ifwi_version); + READ_MEMBER(h->fit_tool_version); + + bpdt_validate_header(h, name); + bpdt_print_header(h, name); +} + +static void bpdt_read_entries(void *h, struct bpdt_entry *e, size_t count, + const char *name) +{ + size_t i, offset = 0; + void *data = (struct bpdt_header *)h + 1; + + for (i = 0; i < count; i++) { + READ_MEMBER(e[i].type); + READ_MEMBER(e[i].flags); + READ_MEMBER(e[i].offset); + READ_MEMBER(e[i].size); + } + + bpdt_print_entries(e, count, name); +} + +struct bpdt { + struct bpdt_header h; + struct bpdt_entry e[1]; +}; + +/* + * Given type of component, identify BPDT entry for it. + * Component could lie either within BPDT or S-BPDT. + */ +static struct bpdt_entry *__find_entry_by_type(struct bpdt_entry *e, + size_t count, int type) +{ + size_t i; + for (i = 0; i < count; i++) { + if (e[i].type == type) + break; + } + + if (i == count) + return NULL; + + return &e[i]; +} + +static struct bpdt_entry *find_entry_by_type(int type) +{ + struct bpdt *b = buffer_get(&ifwi_image.bpdt); + assert(b); + + struct bpdt_entry *curr = __find_entry_by_type(&b->e[0], + b->h.descriptor_count, + type); + + if (curr) + return curr; + + b = buffer_get(&ifwi_image.comp_buf[S_BPDT_TYPE]); + assert(b); + + return __find_entry_by_type(&b->e[0], b->h.descriptor_count, type); +} + +/* + * Find component type given its name. If the name does not exist, returns -1. + */ +static int find_type_by_name(const char *name) +{ + int i; + + for (i = 0; i < MAX_COMPS; i++) { + if ((strlen(comp[i].name) == strlen(name)) && + (!strcmp(comp[i].name, name))) + break; + } + + if (i == MAX_COMPS) { + ERROR("Invalid component name %s.\n", name); + return -1; + } + + return i; +} + +/* + * Read the content of a component from input file and store it in + * ifwi_image.comp_buf[COMPONENT_TYPE]. + * + * Returns the maximum offset occupied by the components. + */ +static size_t read_comp_buf(void *data, size_t size, struct bpdt_entry *e, + size_t count) +{ + size_t i, type; + struct buffer *buf; + size_t max_offset = 0; + + for (i = 0; i < count; i++) { + type = e[i].type; + + if (type >= MAX_COMPS) { + ERROR("Invalid component type %zd.\n", type); + exit(-1); + } + + if (buffer_size(&ifwi_image.comp_buf[type])) { + ERROR("Multiple components of type %zd(%s).\n", type, + comp[type].name); + exit(-1); + } + + if (e[i].size == 0) { + INFO("Dummy component %zd(%s). Skipping.\n", type, + comp[type].name); + continue; + } + + assert((e[i].offset + e[i].size) <= size); + + if ((e[i].offset + e[i].size) > max_offset) + max_offset = e[i].offset + e[i].size; + + /* Needs special handling for S-BPDT component. */ + if (type == S_BPDT_TYPE) + continue; + + buf = &ifwi_image.comp_buf[type]; + + alloc_buffer(buf, e[i].size, comp[type].name); + memcpy(buffer_get(buf), (uint8_t *)data + e[i].offset, + e[i].size); + } + + assert(max_offset); + return max_offset; +} + +/* + * Allocate buffer for bpdt header, entries and all component content. + * Returns offset in data where BPDT ends. + */ +static size_t alloc_bpdt_buffer(void *data, size_t size, size_t offset, + struct buffer *b, const char *name) +{ + struct bpdt_header bpdt_header; + assert((offset + BPDT_HEADER_SIZE) < size); + bpdt_read_header((uint8_t *)data + offset, &bpdt_header, name); + + /* Buffer to read BPDT header and entries. */ + alloc_buffer(b, BPDT_SIZE(bpdt_header.descriptor_count), name); + + struct bpdt *bpdt = buffer_get(b); + memcpy(&bpdt->h, &bpdt_header, BPDT_HEADER_SIZE); + + /* + * If no entries are present, maximum offset occupied is (offset + + * BPDT_HEADER_SIZE). + */ + if (bpdt->h.descriptor_count == 0) + return (offset + BPDT_HEADER_SIZE); + + /* Read all entries. */ + assert((offset + BPDT_SIZE(bpdt->h.descriptor_count)) < size); + bpdt_read_entries((uint8_t *)data + offset, &bpdt->e[0], + bpdt->h.descriptor_count, name); + + /* Read all component content in comp_buf. */ + return read_comp_buf(data, size, &bpdt->e[0], bpdt->h.descriptor_count); +} + +static void parse_sbpdt(void *data, size_t size) +{ + struct bpdt_entry *s; + s = find_entry_by_type(S_BPDT_TYPE); + if (!s) + return; + + assert(size > s->offset); + + alloc_bpdt_buffer(data, size, s->offset, + &ifwi_image.comp_buf[S_BPDT_TYPE], + "S-BPDT"); +} + +static void validate_subpart(const char *name) +{ + struct subpart *s = buffer_get(&ifwi_image.subpart); + + if ((s->h.marker != SUBPART_MARKER) || + (s->h.header_version != SUBPART_HEADER_VERSION_SUPPORTED) || + (s->h.entry_version != SUBPART_ENTRY_VERSION_SUPPORTED) || + (s->h.header_length != SUBPART_HEADER_SIZE)) { + ERROR("Invalid subpart for %s.\n", name); + exit(-1); + } +} + +static void parse_subpart(struct buffer *b, const char *name) +{ + struct buffer *s = &ifwi_image.subpart; + buffer_delete(s); + + struct subpart_header hdr; + size_t offset = 0; + uint8_t *data = buffer_get(b); + size_t size = buffer_size(b); + + /* Read Subpart header. */ + assert(size >= SUBPART_HEADER_SIZE); + READ_MEMBER(hdr.marker); + READ_MEMBER(hdr.num_entries); + READ_MEMBER(hdr.header_version); + READ_MEMBER(hdr.entry_version); + READ_MEMBER(hdr.header_length); + READ_MEMBER(hdr.checksum); + memcpy(hdr.name, data + offset, sizeof(hdr.name)); + offset += sizeof(hdr.name); + + assert(size > SUBPART_SIZE(hdr.num_entries)); + alloc_buffer(s, SUBPART_SIZE(hdr.num_entries), "Subpart"); + memcpy(buffer_get(s), &hdr, SUBPART_HEADER_SIZE); + + /* Read Subpart entries. */ + struct subpart *subpart = buffer_get(s); + struct subpart_entry *e = &subpart->e[0]; + uint32_t i; + for (i = 0; i < hdr.num_entries; i++) { + memcpy(e[i].name, data + offset, sizeof(e[i].name)); + offset += sizeof(e[i].name); + READ_MEMBER(e[i].offset); + READ_MEMBER(e[i].length); + READ_MEMBER(e[i].rsvd); + } + + validate_subpart(name); + print_subpart(name); +} + +/* Parse input image file to identify different components. */ +static int ifwi_parse(void) +{ + DEBUG("Parsing IFWI image...\n"); + const char *image_name = param.image_name; + + /* Read input file. */ + struct buffer buff; + if (buffer_from_file(&buff, image_name)) { + ERROR("Failed to read input file %s.\n", image_name); + return -1; + } + + INFO("Buffer %p size 0x%zx\n", buff.data, buff.size); + + /* Look for BPDT signature at 4K intervals. */ + size_t offset = 0; + void *data = buffer_get(&buff); + + while (offset < buffer_size(&buff)) { + if (read_at_le32(data, offset) == BPDT_SIGNATURE) + break; + offset += 4 * KiB; + } + + if (offset >= buffer_size(&buff)) { + ERROR("Image does not contain BPDT!!\n"); + return -1; + } + + /* Read non-IFWI prefix, if present. */ + if (offset) { + INFO("File contains non-IFWI prefix (size=0x%zx)\n", offset); + alloc_buffer(&ifwi_image.non_ifwi_prefix, offset, + "Non-IFWI Prefix"); + memcpy(buffer_get(&ifwi_image.non_ifwi_prefix), data, offset); + } + + data = (uint8_t *)data + offset; + size_t ifwi_size = buffer_size(&buff) - offset; + + /* Read BPDT and components. */ + uintptr_t end_offset = alloc_bpdt_buffer(data, ifwi_size, 0, + &ifwi_image.bpdt, "BPDT"); + + /* Parse S-BPDT, if any. */ + parse_sbpdt(data, ifwi_size); + + /* + * Check if there is any non-IFWI suffix. + * Assumption: non-IFWI suffix always starts on 4k boundary. + */ + end_offset = ALIGN(end_offset, 4 * KiB); + + if (end_offset >= ifwi_size) + return 0; + + size_t size = ifwi_size - end_offset; + + INFO("File contains non-IFWI suffix (offset = 0x%zx, size=0x%zx)\n", + end_offset, size); + alloc_buffer(&ifwi_image.non_ifwi_suffix, size, + "Non-IFWI Suffix"); + memcpy(buffer_get(&ifwi_image.non_ifwi_suffix), + (uint8_t *)data + end_offset, size); + + buffer_delete(&buff); + + DEBUG("Parsing done\n"); + + return 0; +} + +/* + * This function is used by repack to count the number of BPDT and S-BPDT + * entries that are present. It frees the current buffers used by the entries + * and allocates fresh buffers that can be used for repacking. Returns BPDT + * entries which are empty and need to be filled in. + */ +static void __bpdt_reset(struct buffer *b, size_t count) +{ + struct bpdt *bpdt = buffer_get(b); + + /* If count has not changed, just zero out BPDT entries. */ + if (bpdt->h.descriptor_count == count) { + memset(&bpdt->e[0], 0, BPDT_ENTRY_SIZE * count); + return; + } + + /* Else, re-allocate buffer of new size and then zero out entries. */ + char *name = strdup(b->name); + assert(name); + + struct bpdt_header temp; + bpdt->h.descriptor_count = count; + memcpy(&temp, &bpdt->h, BPDT_HEADER_SIZE); + + buffer_delete(b); + alloc_buffer(b, BPDT_SIZE(count), name); + + bpdt = buffer_get(b); + + memcpy(&bpdt->h, &temp, BPDT_HEADER_SIZE); + if (count == 0) + return; + + memset(&bpdt->e[0], 0, BPDT_ENTRY_SIZE * count); +} + +static void bpdt_reset(void) +{ + size_t i; + size_t bpdt_count = 0, sbpdt_count = 0, dummy_bpdt_count = 0; + + /* Count number of BPDT and S-BPDT entries. */ + for (i = 0; i < MAX_COMPS; i++) { + if (buffer_size(&ifwi_image.comp_buf[i]) == 0) { + if (comp[i].attr & MANDATORY_BPDT_ENTRY) { + bpdt_count++; + dummy_bpdt_count++; + } + continue; + } + + if (comp[i].attr & NON_CRITICAL_COMP) + sbpdt_count++; + else + bpdt_count++; + } + + DEBUG("Count: BPDT = %zd, Dummy BPDT = %zd, S-BPDT = %zd\n", bpdt_count, + dummy_bpdt_count, sbpdt_count); + + /* Update BPDT if required. */ + __bpdt_reset(&ifwi_image.bpdt, bpdt_count); + + /* Update S-BPDT if required. */ + __bpdt_reset(&ifwi_image.comp_buf[S_BPDT_TYPE], sbpdt_count); +} + +/* Initialize BPDT entries in header order. */ +static void bpdt_entries_init_header_order(void) +{ + int i, type; + size_t size; + + struct bpdt *bpdt, *sbpdt, *curr; + size_t bpdt_curr = 0, sbpdt_curr = 0, *count_ptr; + + bpdt = buffer_get(&ifwi_image.bpdt); + sbpdt = buffer_get(&ifwi_image.comp_buf[S_BPDT_TYPE]); + + for (i = 0; i < MAX_COMPS; i++) { + type = bpdt_header_order[i]; + size = buffer_size(&ifwi_image.comp_buf[type]); + + if ((size == 0) && !(comp[type].attr & MANDATORY_BPDT_ENTRY)) + continue; + + if (comp[type].attr & NON_CRITICAL_COMP) { + curr = sbpdt; + count_ptr = &sbpdt_curr; + } else { + curr = bpdt; + count_ptr = &bpdt_curr; + } + + assert(*count_ptr < curr->h.descriptor_count); + curr->e[*count_ptr].type = type; + curr->e[*count_ptr].flags = 0; + curr->e[*count_ptr].offset = 0; + curr->e[*count_ptr].size = size; + + (*count_ptr)++; + } +} + +/* Initialize offsets of entries using pack order. */ +static void bpdt_entries_init_pack_order(void) +{ + int i, type; + struct bpdt_entry *curr; + uint32_t alignment; + size_t curr_offset; + size_t max_offset = 0; + + curr_offset = MAX(512, buffer_size(&ifwi_image.bpdt)); + + for (i = 0; i < MAX_COMPS; i++) { + type = bpdt_pack_order[i]; + curr = find_entry_by_type(type); + + if ((curr == NULL) || (curr->size == 0)) + continue; + + if (comp[type].attr & LIES_WITHIN_BPDT_4K) + alignment = 1; + else + alignment = 4 * KiB; + + curr->offset = ALIGN(curr_offset, alignment); + curr_offset = curr->offset + curr->size; + + if (max_offset < curr_offset) + max_offset = curr_offset; + } + + /* + * Update size of S-BPDT to include size of all non-critical + * components. + * + * Assumption: S-BPDT always lies at the end of IFWI image. + */ + curr = find_entry_by_type(S_BPDT_TYPE); + assert(curr); + + curr->size = max_offset - curr->offset; +} + +/* + * Copy data from src to dst. + * curr_offset identifies the offset upto which data is written to in dst. + * write_offset identifies the offset at which data from src is to be written to + * dst. + * + * This function fills up FF in any hole present between end of last + * write(curr_offset) and offset for current src(write_offset). + * + * IMPORTANT: data_copy needs to be called in ascending order of write_offset to + * properly fill up holes with FF. + */ +static void data_copy(struct buffer *dst, size_t *curr_offset, + size_t write_offset, struct buffer *src) +{ + uint8_t *data_dst = buffer_get(dst); + uint8_t *data_src = buffer_get(src); + + assert(data_dst); + + if (buffer_size(src) == 0) + return; + + if (*curr_offset < write_offset) + memset(data_dst + *curr_offset, 0xFF, + write_offset - *curr_offset); + + memcpy(data_dst + write_offset, data_src, buffer_size(src)); + + *curr_offset = write_offset + buffer_size(src); +} + +/* + * Identify the next entry that lies immediately above or at the passed in + * offset. Component could lie either within BPDT or S-BPDT. + * + * entries = Entries in BPDT or S-BPDT + * count = Total number of entries in BPDT or S-BPDT + * offset = Offset at or above which the next component lies at + */ +static struct bpdt_entry *__get_next_entry(struct bpdt *bpdt, size_t offset) +{ + uint32_t i; + size_t lowest_offset = SIZE_MAX; + struct bpdt_entry *next = NULL; + + for (i = 0; i < bpdt->h.descriptor_count; i++) { + if (bpdt->e[i].offset == offset) { + next = &bpdt->e[i]; + break; + } + + if ((bpdt->e[i].offset > offset) && + (bpdt->e[i].offset < lowest_offset)) { + lowest_offset = bpdt->e[i].offset; + next = &bpdt->e[i]; + } + } + + return next; +} + +static struct bpdt_entry *get_next_entry(size_t offset) +{ + struct bpdt_entry *next; + next = __get_next_entry(buffer_get(&ifwi_image.bpdt), offset); + + if (next) + return next; + + return __get_next_entry(buffer_get(&ifwi_image.comp_buf[S_BPDT_TYPE]), + offset); +} + +/* Convert all members of BPDT to little-endian format. */ +static void bpdt_fixup_write_buffer(struct buffer *buf) +{ + struct bpdt *s = buffer_get(buf); + + struct bpdt_header *h = &s->h; + struct bpdt_entry *e = &s->e[0]; + + size_t count = h->descriptor_count; + + size_t offset = 0; + + FIX_MEMBER(h->signature); + FIX_MEMBER(h->descriptor_count); + FIX_MEMBER(h->bpdt_version); + FIX_MEMBER(h->xor_redundant_block); + FIX_MEMBER(h->ifwi_version); + FIX_MEMBER(h->fit_tool_version); + + uint32_t i; + for (i = 0; i < count; i++) { + FIX_MEMBER(e[i].type); + FIX_MEMBER(e[i].flags); + FIX_MEMBER(e[i].offset); + FIX_MEMBER(e[i].size); + } +} + +/* Write BPDT to output buffer after fixup. */ +static void bpdt_write(struct buffer *dst, size_t offset, struct buffer *src) +{ + bpdt_fixup_write_buffer(src); + memcpy(buffer_get(dst) + offset, buffer_get(src), buffer_size(src)); +} + +/* + * Follows these steps to re-create image: + * 1. Write any non-IFWI prefix. + * 2. Write out BPDT header and entries. + * 3. Write component buffers to respective offsets. + * 4. Write any non-IFWI suffix. + * + * While performing the above steps, make sure that any empty holes are filled + * with FF. + */ +static void ifwi_write(const char *image_name) +{ + struct bpdt_entry *s = find_entry_by_type(S_BPDT_TYPE); + assert(s); + + size_t bpdt_offset = buffer_size(&ifwi_image.non_ifwi_prefix); + size_t non_ifwi_suffix_offset = s->offset + s->size; + size_t non_ifwi_suffix_size = buffer_size(&ifwi_image.non_ifwi_suffix); + + if (non_ifwi_suffix_size) + non_ifwi_suffix_offset = ALIGN(s->offset + s->size, 4096); + + size_t total_size = bpdt_offset + non_ifwi_suffix_offset + + non_ifwi_suffix_size; + + struct buffer b; + size_t curr_offset = 0; + + alloc_buffer(&b, total_size, "Final-IFWI"); + + /* Copy non-IFWI prefix, if any. */ + data_copy(&b, &curr_offset, 0, &ifwi_image.non_ifwi_prefix); + + struct buffer bpdt; + buffer_splice(&bpdt, &b, curr_offset, buffer_size(&b) - curr_offset); + + curr_offset = buffer_size(&ifwi_image.bpdt);; + + /* Copy components. */ + struct bpdt_entry *curr; + while (1) { + curr = get_next_entry(curr_offset); + if (curr == NULL) + break; + + assert(curr->size != 0); + data_copy(&bpdt, &curr_offset, curr->offset, + &ifwi_image.comp_buf[curr->type]); + } + + assert (curr_offset == (s->offset + s->size)); + + /* + * Copy non-IFWI suffix, if any. + * Assumption: Non-IFWI suffix starts on 4k boundary. + */ + if (non_ifwi_suffix_size == 0) { + buffer_delete(&b); + return; + } + + data_copy(&bpdt, &curr_offset, non_ifwi_suffix_offset, + &ifwi_image.non_ifwi_suffix); + + /* + * Convert BPDT to little-endian format and write it to output buffer. + * S-BPDT is written first and then BPDT. + */ + bpdt_write(&bpdt, s->offset, &ifwi_image.comp_buf[S_BPDT_TYPE]); + bpdt_write(&bpdt, 0, &ifwi_image.bpdt); + + if (buffer_write_file(&b, image_name)) { + ERROR("File write error\n"); + exit(-1); + } + + buffer_delete(&b); +} + +/* + * Calculate size and offset of each component again since it might have changed + * because of add/delete operation. Also, re-create BPDT and S-BPDT entries and + * write back the new IFWI image to file. + */ +static void ifwi_repack(void) +{ + bpdt_reset(); + bpdt_entries_init_header_order(); + bpdt_entries_init_pack_order(); + + struct bpdt *b = buffer_get(&ifwi_image.bpdt); + bpdt_print_entries(&b->e[0], b->h.descriptor_count, "BPDT"); + + b = buffer_get(&ifwi_image.comp_buf[S_BPDT_TYPE]); + bpdt_print_entries(&b->e[0], b->h.descriptor_count, "S-BPDT"); + + ifwi_write(param.image_name); +} + +static enum ifwi_ret ifwi_raw_add(int type) +{ + if (buffer_from_file(&ifwi_image.comp_buf[type], param.file_name)) + return COMM_ERR; + + return REPACK_REQUIRED; +} + +static enum ifwi_ret ifwi_cbp_add(int type) +{ + if (!(comp[type].attr & CONTAINS_SUBPART) || + (comp[type].cbp_ops.cbp_add == NULL)) { + ERROR("Component %s(%d) does not support cbp ops.\n", + comp[type].name, type); + return COMM_ERR; + } + + parse_subpart(&ifwi_image.comp_buf[type], comp[type].name); + return comp[type].cbp_ops.cbp_add(type); +} + +static enum ifwi_ret ifwi_add(void) +{ + if (!param.file_name) { + ERROR("%s: -f option required\n", __func__); + return COMM_ERR; + } + + if (!param.comp_name) { + ERROR("%s: -n option required\n", __func__); + return COMM_ERR; + } + + int type = find_type_by_name(param.comp_name); + if (type == -1) + return COMM_ERR; + + struct bpdt_comp *curr_comp = &comp[type]; + + if (curr_comp->attr & AUTO_GENERATED) { + ERROR("Cannot delete auto-generated components.\n"); + return COMM_ERR; + } + + if (buffer_size(&ifwi_image.comp_buf[type])) { + ERROR("Image already contains component %s(%d).\n", + param.comp_name, type); + return COMM_ERR; + } + + if (param.subpart_ops) + return ifwi_cbp_add(type); + + return ifwi_raw_add(type); +} + +static enum ifwi_ret ifwi_delete(void) +{ + if (!param.comp_name) { + ERROR("%s: -n option required\n", __func__); + return COMM_ERR; + } + + int type = find_type_by_name(param.comp_name); + if (type == -1) + return COMM_ERR; + + struct bpdt_comp *curr_comp = &comp[type]; + + if (curr_comp->attr & AUTO_GENERATED) { + ERROR("Cannot delete auto-generated components.\n"); + return COMM_ERR; + } + + if (buffer_size(&ifwi_image.comp_buf[type]) == 0) { + ERROR("Image does not contain component %s(%d).\n", + param.comp_name, type); + return COMM_ERR; + } + + buffer_delete(&ifwi_image.comp_buf[type]); + + INFO("Component %s(%d) deleted.\n", comp[type].name, type); + + return REPACK_REQUIRED; +} + +static enum ifwi_ret ifwi_cbp_extract(int type) +{ + if (!(comp[type].attr & CONTAINS_SUBPART)) { + ERROR("Component %s(%d) does not support cbp ops.\n", + comp[type].name, type); + return COMM_ERR; + } + + parse_subpart(&ifwi_image.comp_buf[type], comp[type].name); + + uint32_t i; + struct subpart *s = buffer_get(&ifwi_image.subpart); + + for (i = 0; i < s->h.num_entries; i++) { + if (!strcmp((char *)s->e[i].name, param.file_name)) + break; + } + + if (i == s->h.num_entries) { + ERROR("File %s not found in subpartition for %s.\n", + param.file_name, param.comp_name); + exit(-1); + } + + struct buffer dst; + + buffer_splice(&dst, &ifwi_image.subpart, s->e[i].offset, + s->e[i].length); + + if (buffer_write_file(&dst, param.file_name)) + return COMM_ERR; + + INFO("Component %s(%d) stored in %s.\n", param.comp_name, type, + param.file_name); + + return NO_ACTION_REQUIRED; +} + +static enum ifwi_ret ifwi_raw_extract(int type) +{ + if (buffer_write_file(&ifwi_image.comp_buf[type], param.file_name)) + return COMM_ERR; + + INFO("Component %s(%d) stored in %s.\n", param.comp_name, type, + param.file_name); + + return NO_ACTION_REQUIRED; +} + +static enum ifwi_ret ifwi_extract(void) +{ + if (!param.file_name) { + ERROR("%s: -f option required\n", __func__); + return COMM_ERR; + } + + if (!param.comp_name) { + ERROR("%s: -n option required\n", __func__); + return COMM_ERR; + } + + int type = find_type_by_name(param.comp_name); + if (type == -1) + return COMM_ERR; + + if (type == S_BPDT_TYPE) { + ERROR("Nothing to extract.\n"); + return NO_ACTION_REQUIRED; + } + + if (buffer_size(&ifwi_image.comp_buf[type]) == 0) { + ERROR("Image does not contain component %s(%d).\n", + param.comp_name, type); + return COMM_ERR; + } + + INFO("Extracting component %s(%d).\n", param.comp_name, type); + if (param.subpart_ops) + return ifwi_cbp_extract(type); + + return ifwi_raw_extract(type); +} + +static enum ifwi_ret ifwi_print(void) +{ + verbose += 2; + + struct bpdt *b = buffer_get(&ifwi_image.bpdt); + + bpdt_print_header(&b->h, "BPDT"); + bpdt_print_entries(&b->e[0], b->h.descriptor_count, "BPDT"); + + b = buffer_get(&ifwi_image.comp_buf[S_BPDT_TYPE]); + bpdt_print_header(&b->h, "S-BPDT"); + bpdt_print_entries(&b->e[0], b->h.descriptor_count, "S-BPDT"); + + int i; + for (i = 0; i < MAX_COMPS ; i++) { + if (!(comp[i].attr & CONTAINS_SUBPART) || + (buffer_size(&ifwi_image.comp_buf[i]) == 0)) + continue; + + parse_subpart(&ifwi_image.comp_buf[i], comp[i].name); + } + + verbose -= 2; + + return NO_ACTION_REQUIRED; +} + +static enum ifwi_ret ifwi_raw_replace(int type) +{ + if (buffer_size(&ifwi_image.comp_buf[type]) == 0) { + INFO("Image does not contain component %s(%d).\n", + param.comp_name, type); + } else + buffer_delete(&ifwi_image.comp_buf[type]); + + return ifwi_raw_add(type); +} + +static void subpart_fixup_write_buffer(struct buffer *buf) +{ + struct subpart *s = buffer_get(buf); + struct subpart_header *h = &s->h; + struct subpart_entry *e = &s->e[0]; + + size_t count = h->num_entries; + size_t offset = 0; + + FIX_MEMBER(h->marker); + FIX_MEMBER(h->num_entries); + FIX_MEMBER(h->header_version); + FIX_MEMBER(h->entry_version); + FIX_MEMBER(h->header_length); + FIX_MEMBER(h->checksum); + offset += sizeof(h->name); + + uint32_t i; + for (i = 0; i < count; i++) { + offset += sizeof(e[i].name); + FIX_MEMBER(e[i].offset); + FIX_MEMBER(e[i].length); + FIX_MEMBER(e[i].rsvd); + } +} + +static void recalc_checksum(struct subpart *s) +{ + size_t size = SUBPART_SIZE(s->h.num_entries); + uint8_t *data = (uint8_t *)s; + uint8_t checksum = 0; + size_t i; + + s->h.checksum = 0; + + for (i = 0; i < size; i++) { + checksum ^= data[i]; + } + + s->h.checksum = checksum; +} + +static enum ifwi_ret ifwi_cbp_replace(int type) +{ + if (buffer_size(&ifwi_image.comp_buf[type]) == 0) { + ERROR("Image does not contain component %s(%d).\n", + param.comp_name, type); + return COMM_ERR; + } + + if (!(comp[type].attr & CONTAINS_SUBPART)) { + ERROR("Component %s(%d) does not support cbp ops.\n", + comp[type].name, type); + return COMM_ERR; + } + + parse_subpart(&ifwi_image.comp_buf[type], comp[type].name); + + uint32_t i; + struct subpart *s = buffer_get(&ifwi_image.subpart); + + for (i = 0; i < s->h.num_entries; i++) { + if (!strcmp((char *)s->e[i].name, param.file_name)) + break; + } + + if (i == s->h.num_entries) { + ERROR("File %s not found in subpartition for %s.\n", + param.file_name, param.comp_name); + exit(-1); + } + + struct buffer b; + if (buffer_from_file(&b, param.file_name)) { + ERROR("Failed to read %s\n", param.file_name); + exit(-1); + } + + struct buffer dst; + size_t dst_size = buffer_size(&ifwi_image.comp_buf[type] + + buffer_size(&b) - s->e[i].length); + size_t comp_start = s->e[i].offset; + size_t comp_end = s->e[i].offset + s->e[i].length; + + alloc_buffer(&dst, dst_size, ifwi_image.comp_buf[type].name); + + uint8_t *src_data = buffer_get(&ifwi_image.comp_buf[type]); + uint8_t *dst_data = buffer_get(&dst); + size_t curr_offset = 0; + + /* Copy data before the sub-partition entry. */ + memcpy(dst_data + curr_offset, src_data, comp_start); + curr_offset += comp_start; + + /* Copy sub-partition entry. */ + memcpy(dst_data + curr_offset, buffer_get(&b), buffer_size(&b)); + curr_offset += buffer_size(&b); + + /* Copy remaining data. */ + memcpy(dst_data + curr_offset, src_data + comp_end, + buffer_size(&ifwi_image.comp_buf[type]) - comp_end); + + /* Update component buffer. */ + int offset = s->e[i].offset; + buffer_delete(&ifwi_image.comp_buf[type]); + ifwi_image.comp_buf[type] = dst; + + /* Update length of entry in the subpartition. */ + s->e[i].length = buffer_size(&b); + buffer_delete(&b); + + /* Adjust offsets of affected entries in subpartition. */ + offset = s->e[i].offset - offset; + for (; i < s->h.num_entries; i++) { + s->e[i].offset += offset; + } + + /* Re-calculate checksum. */ + recalc_checksum(s); + + /* Convert members to litte-endian. */ + subpart_fixup_write_buffer(&ifwi_image.subpart); + + memcpy(dst_data, buffer_get(&ifwi_image.subpart), + buffer_size(&ifwi_image.subpart)); + + buffer_delete(&ifwi_image.subpart); + + return REPACK_REQUIRED; +} + +static enum ifwi_ret ifwi_replace(void) +{ + if (!param.file_name) { + ERROR("%s: -f option required\n", __func__); + return COMM_ERR; + } + + if (!param.comp_name) { + ERROR("%s: -n option required\n", __func__); + return COMM_ERR; + } + + int type = find_type_by_name(param.comp_name); + if (type == -1) + return COMM_ERR; + + struct bpdt_comp *curr_comp = &comp[type]; + + if (curr_comp->attr & AUTO_GENERATED) { + ERROR("Cannot replace auto-generated components.\n"); + return COMM_ERR; + } + + if (param.subpart_ops) + return ifwi_cbp_replace(type); + + return ifwi_raw_replace(type); +} + +static enum ifwi_ret ifwi_create(void) +{ + if (!param.file_name) { + ERROR("%s: -f option required\n", __func__); + return COMM_ERR; + } + + buffer_delete(&ifwi_image.non_ifwi_prefix); + buffer_delete(&ifwi_image.non_ifwi_suffix); + + param.image_name = param.file_name; + + return REPACK_REQUIRED; +} + +struct command { + const char *name; + const char *optstring; + enum ifwi_ret (*function)(void); +}; + +static const struct command commands[] = { + {"add", "f:n:svh?", ifwi_add}, + {"create", "f:vh?", ifwi_create}, + {"delete", "f:n:vh?", ifwi_delete}, + {"extract", "f:n:svh?", ifwi_extract}, + {"print", "h?", ifwi_print}, + {"replace", "f:n:svh?", ifwi_replace}, +}; + +static struct option long_options[] = { + {"file", required_argument, 0, 'f'}, + {"help", required_argument, 0, 'h'}, + {"name", required_argument, 0, 'n'}, + {"subpart_ops", no_argument, 0, 's'}, + {"verbose", no_argument, 0, 'v'}, + {NULL, 0, 0, 0 } +}; + +static void usage(const char *name) +{ + printf("ifwitool: Utility for IFWI manipulation\n\n" + "USAGE:\n" + " %s [-h]\n" + " %s FILE COMMAND [PARAMETERS]\n\n" + "COMMANDs:\n" + " add -f FILE -n NAME\n" + " create -f FILE\n" + " delete -n NAME\n" + " extract -f FILE -n NAME\n" + " print\n" + " replace -f FILE -n NAME\n", + name, name + ); +} + +int main(int argc, char **argv) +{ + if (argc < 3) { + usage(argv[0]); + return 1; + } + + param.image_name = argv[1]; + char *cmd = argv[2]; + optind += 2; + + uint32_t i; + + for (i = 0; i < ARRAY_SIZE(commands); i++) { + if (strcmp(cmd, commands[i].name) != 0) + continue; + + int c; + + while (1) { + int option_index; + + c = getopt_long(argc, argv, commands[i].optstring, + long_options, &option_index); + + if (c == -1) + break; + + /* Filter out illegal long options. */ + if (strchr(commands[i].optstring, c) == NULL) { + ERROR("%s: invalid option -- '%c'\n", argv[0], + c); + c = '?'; + } + + switch(c) { + case 'n': + param.comp_name = optarg; + break; + case 'f': + param.file_name = optarg; + break; + case 's': + param.subpart_ops = 1; + break; + case 'v': + verbose++; + break; + case 'h': + case '?': + usage(argv[0]); + return 1; + default: + break; + } + } + + if (ifwi_parse()) { + ERROR("%s: ifwi parsing failed\n", argv[0]); + return 1; + } + + enum ifwi_ret ret = commands[i].function(); + + if (ret == COMM_ERR) { + ERROR("%s: failed execution\n", argv[0]); + return 1; + } + + if (ret == REPACK_REQUIRED) + ifwi_repack(); + + return 0; + } + + ERROR("%s: invalid command\n", argv[0]); + return 1; +}

1 0

Patch set updated for coreboot: WIP: Add ifwitool for managing IFWI images
by Furquan Shaikh 24 May '16

24 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14896 -gerrit commit 31975cd28d3571a290b221acb233959509e6f3f8 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu May 19 16:12:16 2016 -0700 WIP: Add ifwitool for managing IFWI images Still needs work to support subdir management. Change-Id: I683a0ab13cc50eb60eecca34db4a8ffefc8dccbd Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- util/cbfstool/Makefile | 2 + util/cbfstool/Makefile.inc | 8 + util/cbfstool/ifwitool.c | 1571 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1581 insertions(+) diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index 61a1a63..f49da3e 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -10,6 +10,7 @@ OBJCOPY ?= objcopy all: $(objutil)/cbfstool/cbfstool \ $(objutil)/cbfstool/fmaptool \ $(objutil)/cbfstool/rmodtool \ + $(objutil)/cbfstool/ifwitool \ .PHONY: clean clean: @@ -17,6 +18,7 @@ clean: $(RM) $(objutil)/cbfstool/cbfstool $(cbfsobj) $(RM) $(objutil)/cbfstool/fmaptool $(fmapobj) $(RM) $(objutil)/cbfstool/rmodtool $(rmodobj) + $(RM) $(objutil)/cbfstool/ifwitool $(ifwiobj) linux_trampoline.c: linux_trampoline.S rm -f linux_trampoline.c diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index aa42f01..6c2b100 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -58,6 +58,10 @@ rmodobj += common.o rmodobj += elfheaders.o rmodobj += xdr.o +ifwiobj := +ifwiobj += ifwitool.o +ifwiobj += common.o + TOOLCFLAGS ?= -Werror -Wall -Wextra TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings @@ -132,6 +136,10 @@ $(objutil)/cbfstool/rmodtool: $(addprefix $(objutil)/cbfstool/,$(rmodobj)) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(rmodobj)) +$(objutil)/cbfstool/ifwitool: $(addprefix $(objutil)/cbfstool/,$(ifwiobj)) + printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" + $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(ifwiobj)) + # Yacc source is superset of header $(objutil)/cbfstool/fmd.o: TOOLCFLAGS += -Wno-redundant-decls $(objutil)/cbfstool/fmd_parser.o: TOOLCFLAGS += -Wno-redundant-decls diff --git a/util/cbfstool/ifwitool.c b/util/cbfstool/ifwitool.c new file mode 100644 index 0000000..408cb8a --- /dev/null +++ b/util/cbfstool/ifwitool.c @@ -0,0 +1,1571 @@ +/* + * ifwitool, CLI utility for IFWI manipulation + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <commonlib/endian.h> +#include <getopt.h> +#include <stdlib.h> + +#include "common.h" + +#define BPDT_SIGNATURE (0x000055AA) +#define KiB 1024 + +/* Parameters passed in by caller. */ +static struct param { + const char *file_name; + const char *comp_name; + const char *image_name; + bool subpart_ops; +} param; + +struct bpdt_header { + uint32_t signature; + uint16_t descriptor_count; + uint16_t bpdt_version; + uint32_t xor_redundant_block; + uint32_t ifwi_version; + uint64_t fit_tool_version; +}; +#define BPDT_HEADER_SIZE (sizeof(struct bpdt_header)) + +struct bpdt_entry { + uint16_t type; + uint16_t flags; + uint32_t offset; + uint32_t size; +}; +#define BPDT_ENTRY_SIZE (sizeof(struct bpdt_entry)) + +#define BPDT_SIZE(c) (BPDT_HEADER_SIZE + (c) * \ + BPDT_ENTRY_SIZE) + +struct subpart_header { + uint32_t marker; + uint32_t num_entries; + uint8_t header_version; + uint8_t entry_version; + uint8_t header_length; + uint8_t checksum; + uint8_t name[4]; +}; +#define SUBPART_HEADER_SIZE (sizeof(struct subpart_header)) +#define SUBPART_MARKER 0x44504324 +#define SUBPART_HEADER_VERSION_SUPPORTED 1 +#define SUBPART_ENTRY_VERSION_SUPPORTED 1 + +struct subpart_entry { + uint8_t name[12]; + uint32_t offset; + uint32_t length; + uint32_t rsvd; +}; +#define SUBPART_ENTRY_SIZE (sizeof(struct subpart_entry)) + +struct subpart { + struct subpart_header h; + struct subpart_entry e[1]; +}; +#define SUBPART_SIZE(c) (SUBPART_HEADER_SIZE + (c) * \ + SUBPART_ENTRY_SIZE) + +/* + * Attributes for various IFWI components. + * LIES_WITHIN_BPDT_4K = Component should lie within the same 4K block as BPDT. + * NON_CRITICAL_COMP = Component entry should be present in S-BPDT. + * CONTAINS_SUBPART = Component might require subpart operation (TODO(furquan)) + * AUTO_GENERATED = Component is generated by the tool. + * MANDATORY_BPDT_ENTRY = Even if component is deleted, BPDT should contain an + * entry for it with size 0 and offset 0. + */ +enum comp_attributes { + LIES_WITHIN_BPDT_4K = (1 << 0), + NON_CRITICAL_COMP = (1 << 1), + CONTAINS_SUBPART = (1 << 2), + AUTO_GENERATED = (1 << 3), + MANDATORY_BPDT_ENTRY = (1 << 4), +}; + +/* Type value for various IFWI components. */ +enum bpdt_entry_type { + SMIP_TYPE = 0, + CSE_RBE_TYPE = 1, + CSE_BUP_TYPE = 2, + UCODE_TYPE = 3, + IBB_TYPE = 4, + S_BPDT_TYPE = 5, + OBB_TYPE = 6, + CSE_MAIN_TYPE = 7, + ISH_TYPE = 8, + CSE_IDLM_TYPE = 9, + IFP_OVERRIDE_TYPE = 10, + DEBUG_TOKENS_TYPE = 11, + UFS_PHY_TYPE = 12, + UFS_GPP_TYPE = 13, + PMC_TYPE = 14, + IUNIT_TYPE = 15, + NVM_CONFIG_TYPE = 16, + UEP_TYPE = 17, + UFS_RATE_B_TYPE = 18, + MAX_COMPS = 19, +}; + +/* + * There are two order requirements for an IFWI image: + * 1. Order in which the entries lie within the BPDT. + * 2. Order in which the components lie within the image. + * + * header_order defines #1 i.e. the order in which the entries should appear in + * the BPDT. pack_order defines #2 i.e. the order in which components appear in + * the IFWI image. pack_order controls the offset and thus components would have + * increasing offsets as we loop over pack_order. + */ +enum bpdt_entry_type bpdt_header_order[MAX_COMPS] = { + CSE_IDLM_TYPE, + IFP_OVERRIDE_TYPE, + S_BPDT_TYPE, + CSE_RBE_TYPE, + UFS_PHY_TYPE, + UFS_GPP_TYPE, + CSE_BUP_TYPE, + UEP_TYPE, + NVM_CONFIG_TYPE, + SMIP_TYPE, + PMC_TYPE, + UCODE_TYPE, + IBB_TYPE, + DEBUG_TOKENS_TYPE, + UFS_RATE_B_TYPE, + ISH_TYPE, + CSE_MAIN_TYPE, + OBB_TYPE, + IUNIT_TYPE, +}; + +enum bpdt_entry_type bpdt_pack_order[MAX_COMPS] = { + CSE_IDLM_TYPE, + UFS_PHY_TYPE, + UFS_GPP_TYPE, + IFP_OVERRIDE_TYPE, + UEP_TYPE, + IBB_TYPE, + NVM_CONFIG_TYPE, + SMIP_TYPE, + CSE_RBE_TYPE, + PMC_TYPE, + CSE_BUP_TYPE, + UCODE_TYPE, + DEBUG_TOKENS_TYPE, + UFS_RATE_B_TYPE, + S_BPDT_TYPE, + ISH_TYPE, + CSE_MAIN_TYPE, + OBB_TYPE, + IUNIT_TYPE, +}; + +/* Utility functions. */ +enum ifwi_ret { + COMM_ERR = -1, + NO_ACTION_REQUIRED = 0, + REPACK_REQUIRED = 1, +}; + +struct cbp_ops { + enum ifwi_ret (*cbp_add)(int); +}; + +struct bpdt_comp { + const char *name; + uint32_t attr; + const char *subpart_name; + struct cbp_ops cbp_ops; +} comp[MAX_COMPS] = { + /* OEM SMIP */ + [SMIP_TYPE] = {"SMIP", CONTAINS_SUBPART, "SMIP", {NULL}}, + /* CSE RBE */ + [CSE_RBE_TYPE] = {"CSE_RBE", CONTAINS_SUBPART | MANDATORY_BPDT_ENTRY, + "RBEP", {NULL}}, + /* CSE BUP */ + [CSE_BUP_TYPE] = {"CSE_BUP", CONTAINS_SUBPART | MANDATORY_BPDT_ENTRY, + "FTPR", {NULL}}, + /* uCode */ + [UCODE_TYPE] = {"uCODE", CONTAINS_SUBPART, "UCOD", {NULL}}, + /* IBB */ + [IBB_TYPE] = {"bootblock", CONTAINS_SUBPART, "IBBP", {NULL}}, + /* S-BPDT */ + [S_BPDT_TYPE] = {"S_BPDT", AUTO_GENERATED | MANDATORY_BPDT_ENTRY, + NULL, {NULL}}, + /* OBB */ + [OBB_TYPE] = {"OBB", CONTAINS_SUBPART | NON_CRITICAL_COMP, "OBBP", + {NULL}}, + /* CSE Main */ + [CSE_MAIN_TYPE] = {"CSE_MAIN", NON_CRITICAL_COMP, "NFTP", {NULL}}, + /* ISH */ + [ISH_TYPE] = {"ISH", NON_CRITICAL_COMP, "ISHP", {NULL}}, + /* CSE IDLM */ + [CSE_IDLM_TYPE] = {"CSE_IDLM", CONTAINS_SUBPART | MANDATORY_BPDT_ENTRY, + "DLMP", {NULL}}, + /* IFP Override */ + [IFP_OVERRIDE_TYPE] = {"IFP_OVERRIDE", LIES_WITHIN_BPDT_4K | + MANDATORY_BPDT_ENTRY, NULL, {NULL}}, + /* Debug Tokens */ + [DEBUG_TOKENS_TYPE] = {"DEBUG_TOKENS", 0, NULL, {NULL}}, + /* UFS Phy Configuration */ + [UFS_PHY_TYPE] = {"UFS_PHY", LIES_WITHIN_BPDT_4K | MANDATORY_BPDT_ENTRY, + NULL, {NULL}}, + /* UFS GPP LUN ID */ + [UFS_GPP_TYPE] = {"UFS_GPP", LIES_WITHIN_BPDT_4K | MANDATORY_BPDT_ENTRY, + NULL, {NULL}}, + /* PMC */ + [PMC_TYPE] = {"PMC", CONTAINS_SUBPART, "PMCP", {NULL}}, + /* IUNIT */ + [IUNIT_TYPE] = {"IUNIT", NON_CRITICAL_COMP, "IUNP", {NULL}}, + /* NVM Config */ + [NVM_CONFIG_TYPE] = {"NVM_CONFIG", 0, NULL, {NULL}}, + /* UEP */ + [UEP_TYPE] = {"UEP", LIES_WITHIN_BPDT_4K | MANDATORY_BPDT_ENTRY, NULL, + {NULL}}, + /* UFS Rate B Config */ + [UFS_RATE_B_TYPE] = {"UFS_RATE_B", 0, NULL, {NULL}}, +}; + +/* + * Stores information about various components read from the input file. + * Also need to save any non-IFWI prefix and suffix in the image so that they + * can be restored when output image is created. + */ +struct ifwi_image { + struct buffer bpdt; + + struct buffer non_ifwi_prefix; + struct buffer non_ifwi_suffix; + + struct buffer subpart; + + struct buffer comp_buf[MAX_COMPS]; +} ifwi_image; + +static void alloc_buffer(struct buffer *b, size_t s, const char *n) +{ + if (buffer_create(b, s, n) == 0) + return; + + ERROR("Buffer allocation failure for %s (size = %zx).\n", n, s); + exit(-1); +} + +/* Read header/entry members in little-endian format. */ +static void read_member(void *src, size_t *offset, size_t size_bytes, void *dst) +{ + switch (size_bytes) { + case 1: + *(uint8_t *)dst = read_at_le8(src, *offset); + break; + case 2: + *(uint16_t *)dst = read_at_le16(src, *offset); + break; + case 4: + *(uint32_t *)dst = read_at_le32(src, *offset); + break; + case 8: + *(uint64_t *)dst = read_at_le64(src, *offset); + break; + default: + ERROR("Read size not supported %zd\n", size_bytes); + exit(-1); + } + + *offset += size_bytes; +} + +#define READ_MEMBER(m) read_member(data, &offset, sizeof(m), &m) + +/* Convert to little endian format. */ +static void fix_member(void *data, size_t *offset, size_t size_bytes) +{ + uint8_t *src = (uint8_t *)data + *offset; + + switch (size_bytes) { + case 1: + write_at_le8(data, *(uint8_t *)src, *offset); + break; + case 2: + write_at_le16(data, *(uint16_t *)src, *offset); + break; + case 4: + write_at_le32(data, *(uint32_t *)src, *offset); + break; + case 8: + write_at_le64(data, *(uint64_t *)src, *offset); + break; + default: + ERROR("Write size not supported %zd\n", size_bytes); + exit(-1); + } + *offset += size_bytes; +} + +#define FIX_MEMBER(m) fix_member(&m, &offset, sizeof(m)) + +static void print_subpart(const char *name) +{ + if (verbose == 0) + return; + + size_t i; + struct subpart *s = buffer_get(&ifwi_image.subpart); + + printf("\n%-25s %-25s\n", "Subpart Header", name); + printf("%-25s 0x%-23.8x\n", "Marker", s->h.marker); + printf("%-25s %-25d\n", "Num entries", s->h.num_entries); + printf("%-25s %-25d\n", "Header Version", s->h.header_version); + printf("%-25s %-25d\n", "Entry Version", s->h.entry_version); + printf("%-25s 0x%-23x\n", "Header Length", s->h.header_length); + printf("%-25s 0x%-23x\n", "Checksum", s->h.checksum); + printf("%-25s ", "Name"); + for (i = 0; i < sizeof(s->h.name); i++) + printf("%c", s->h.name[i]); + + printf("\n%s entries\n", name); + + printf("%-25s%-25s%-25s%-25s%-25s\n", "Entry #", "Name", "Offset", + "Length", "Rsvd"); + + printf("==============================================================" + "===========================================================\n"); + + for (i = 0; i < s->h.num_entries; i++) { + printf("%-25zd%-25.12s0x%-23x0x%-23x0x%-23x\n", i+1, + s->e[i].name, s->e[i].offset, s->e[i].length, + s->e[i].rsvd); + } + + printf("==============================================================" + "===========================================================\n"); +} + +static void bpdt_print_header(struct bpdt_header *h, const char *name) +{ + if (verbose == 0) + return; + + printf("%-25s %-25s\n", "Header", name); + printf("%-25s 0x%-23.8x\n", "Signature", h->signature); + printf("%-25s %-25d\n", "Descriptor count", h->descriptor_count); + printf("%-25s %-25d\n", "BPDT Version", h->bpdt_version); + printf("%-25s 0x%-23x\n", "XOR checksum", h->xor_redundant_block); + printf("%-25s 0x%-23x\n", "IFWI Version", h->ifwi_version); + printf("%-25s 0x%-23lx\n", "FIT Tool Version", h->fit_tool_version); +} + +static void bpdt_print_entries(struct bpdt_entry *e, size_t count, + const char *name) +{ + if (verbose == 0) + return; + + printf("%s entries\n", name); + + printf("%-25s%-25s%-25s%-25s%-25s%-25s\n", "Entry #", "Name", "Type", + "Flags", "Offset", "Size"); + + printf("==============================================================" + "==============================================================" + "=======================\n"); + + size_t i; + for (i = 0; i < count; i++) { + printf("%-25zd%-25s%-25d0x%-23.08x0x%-23x0x%-23x\n", i+1, + comp[e[i].type].name, e[i].type, e[i].flags, + e[i].offset, e[i].size); + } + + printf("==============================================================" + "==============================================================" + "=======================\n"); + +} + +static void bpdt_validate_header(struct bpdt_header *h, const char *name) +{ + assert (h->signature == BPDT_SIGNATURE); + + if (h->bpdt_version != 1) { + ERROR("Invalid header : %s\n", name); + exit(-1); + } + + DEBUG("Validated header : %s\n", name); +} + +static void bpdt_read_header(void *data, struct bpdt_header *h, + const char *name) +{ + size_t offset = 0; + + READ_MEMBER(h->signature); + READ_MEMBER(h->descriptor_count); + READ_MEMBER(h->bpdt_version); + READ_MEMBER(h->xor_redundant_block); + READ_MEMBER(h->ifwi_version); + READ_MEMBER(h->fit_tool_version); + + bpdt_validate_header(h, name); + bpdt_print_header(h, name); +} + +static void bpdt_read_entries(void *h, struct bpdt_entry *e, size_t count, + const char *name) +{ + size_t i, offset = 0; + void *data = (struct bpdt_header *)h + 1; + + for (i = 0; i < count; i++) { + READ_MEMBER(e[i].type); + READ_MEMBER(e[i].flags); + READ_MEMBER(e[i].offset); + READ_MEMBER(e[i].size); + } + + bpdt_print_entries(e, count, name); +} + +struct bpdt { + struct bpdt_header h; + struct bpdt_entry e[1]; +}; + +/* + * Given type of component, identify BPDT entry for it. + * Component could lie either within BPDT or S-BPDT. + */ +static struct bpdt_entry *__find_entry_by_type(struct bpdt_entry *e, + size_t count, int type) +{ + size_t i; + for (i = 0; i < count; i++) { + if (e[i].type == type) + break; + } + + if (i == count) + return NULL; + + return &e[i]; +} + +static struct bpdt_entry *find_entry_by_type(int type) +{ + struct bpdt *b = buffer_get(&ifwi_image.bpdt); + assert(b); + + struct bpdt_entry *curr = __find_entry_by_type(&b->e[0], + b->h.descriptor_count, + type); + + if (curr) + return curr; + + b = buffer_get(&ifwi_image.comp_buf[S_BPDT_TYPE]); + assert(b); + + return __find_entry_by_type(&b->e[0], b->h.descriptor_count, type); +} + +/* + * Find component type given its name. If the name does not exist, returns -1. + */ +static int find_type_by_name(const char *name) +{ + int i; + + for (i = 0; i < MAX_COMPS; i++) { + if ((strlen(comp[i].name) == strlen(name)) && + (!strcmp(comp[i].name, name))) + break; + } + + if (i == MAX_COMPS) { + ERROR("Invalid component name %s.\n", name); + return -1; + } + + return i; +} + +/* + * Read the content of a component from input file and store it in + * ifwi_image.comp_buf[COMPONENT_TYPE]. + * + * Returns the maximum offset occupied by the components. + */ +static size_t read_comp_buf(void *data, size_t size, struct bpdt_entry *e, + size_t count) +{ + size_t i, type; + struct buffer *buf; + size_t max_offset = 0; + + for (i = 0; i < count; i++) { + type = e[i].type; + + if (type >= MAX_COMPS) { + ERROR("Invalid component type %zd.\n", type); + exit(-1); + } + + if (buffer_size(&ifwi_image.comp_buf[type])) { + ERROR("Multiple components of type %zd(%s).\n", type, + comp[type].name); + exit(-1); + } + + if (e[i].size == 0) { + INFO("Dummy component %zd(%s). Skipping.\n", type, + comp[type].name); + continue; + } + + assert((e[i].offset + e[i].size) <= size); + + if ((e[i].offset + e[i].size) > max_offset) + max_offset = e[i].offset + e[i].size; + + /* Needs special handling for S-BPDT component. */ + if (type == S_BPDT_TYPE) + continue; + + buf = &ifwi_image.comp_buf[type]; + + alloc_buffer(buf, e[i].size, comp[type].name); + memcpy(buffer_get(buf), (uint8_t *)data + e[i].offset, + e[i].size); + } + + assert(max_offset); + return max_offset; +} + +/* + * Allocate buffer for bpdt header, entries and all component content. + * Returns offset in data where BPDT ends. + */ +static size_t alloc_bpdt_buffer(void *data, size_t size, size_t offset, + struct buffer *b, const char *name) +{ + struct bpdt_header bpdt_header; + assert((offset + BPDT_HEADER_SIZE) < size); + bpdt_read_header((uint8_t *)data + offset, &bpdt_header, name); + + /* Buffer to read BPDT header and entries. */ + alloc_buffer(b, BPDT_SIZE(bpdt_header.descriptor_count), name); + + struct bpdt *bpdt = buffer_get(b); + memcpy(&bpdt->h, &bpdt_header, BPDT_HEADER_SIZE); + + /* + * If no entries are present, maximum offset occupied is (offset + + * BPDT_HEADER_SIZE). + */ + if (bpdt->h.descriptor_count == 0) + return (offset + BPDT_HEADER_SIZE); + + /* Read all entries. */ + assert((offset + BPDT_SIZE(bpdt->h.descriptor_count)) < size); + bpdt_read_entries((uint8_t *)data + offset, &bpdt->e[0], + bpdt->h.descriptor_count, name); + + /* Read all component content in comp_buf. */ + return read_comp_buf(data, size, &bpdt->e[0], bpdt->h.descriptor_count); +} + +static void parse_sbpdt(void *data, size_t size) +{ + struct bpdt_entry *s; + s = find_entry_by_type(S_BPDT_TYPE); + if (!s) + return; + + assert(size > s->offset); + + alloc_bpdt_buffer(data, size, s->offset, + &ifwi_image.comp_buf[S_BPDT_TYPE], + "S-BPDT"); +} + +static void validate_subpart(const char *name) +{ + struct subpart *s = buffer_get(&ifwi_image.subpart); + + if ((s->h.marker != SUBPART_MARKER) || + (s->h.header_version != SUBPART_HEADER_VERSION_SUPPORTED) || + (s->h.entry_version != SUBPART_ENTRY_VERSION_SUPPORTED) || + (s->h.header_length != SUBPART_HEADER_SIZE)) { + ERROR("Invalid subpart for %s.\n", name); + exit(-1); + } +} + +static void parse_subpart(struct buffer *b, const char *name) +{ + struct buffer *s = &ifwi_image.subpart; + buffer_delete(s); + + struct subpart_header hdr; + size_t offset = 0; + uint8_t *data = buffer_get(b); + size_t size = buffer_size(b); + + /* Read Subpart header. */ + assert(size >= SUBPART_HEADER_SIZE); + READ_MEMBER(hdr.marker); + READ_MEMBER(hdr.num_entries); + READ_MEMBER(hdr.header_version); + READ_MEMBER(hdr.entry_version); + READ_MEMBER(hdr.header_length); + READ_MEMBER(hdr.checksum); + memcpy(hdr.name, data + offset, sizeof(hdr.name)); + offset += sizeof(hdr.name); + + assert(size > SUBPART_SIZE(hdr.num_entries)); + alloc_buffer(s, SUBPART_SIZE(hdr.num_entries), "Subpart"); + memcpy(buffer_get(s), &hdr, SUBPART_HEADER_SIZE); + + /* Read Subpart entries. */ + struct subpart *subpart = buffer_get(s); + struct subpart_entry *e = &subpart->e[0]; + uint32_t i; + for (i = 0; i < hdr.num_entries; i++) { + memcpy(e[i].name, data + offset, sizeof(e[i].name)); + offset += sizeof(e[i].name); + READ_MEMBER(e[i].offset); + READ_MEMBER(e[i].length); + READ_MEMBER(e[i].rsvd); + } + + validate_subpart(name); + print_subpart(name); +} + +/* Parse input image file to identify different components. */ +static int ifwi_parse(void) +{ + DEBUG("Parsing IFWI image...\n"); + const char *image_name = param.image_name; + + /* Read input file. */ + struct buffer buff; + if (buffer_from_file(&buff, image_name)) { + ERROR("Failed to read input file %s.\n", image_name); + return -1; + } + + INFO("Buffer %p size 0x%zx\n", buff.data, buff.size); + + /* Look for BPDT signature at 4K intervals. */ + size_t offset = 0; + void *data = buffer_get(&buff); + + while (offset < buffer_size(&buff)) { + if (read_at_le32(data, offset) == BPDT_SIGNATURE) + break; + offset += 4 * KiB; + } + + if (offset >= buffer_size(&buff)) { + ERROR("Image does not contain BPDT!!\n"); + return -1; + } + + /* Read non-IFWI prefix, if present. */ + if (offset) { + INFO("File contains non-IFWI prefix (size=0x%zx)\n", offset); + alloc_buffer(&ifwi_image.non_ifwi_prefix, offset, + "Non-IFWI Prefix"); + memcpy(buffer_get(&ifwi_image.non_ifwi_prefix), data, offset); + } + + data = (uint8_t *)data + offset; + size_t ifwi_size = buffer_size(&buff) - offset; + + /* Read BPDT and components. */ + uintptr_t end_offset = alloc_bpdt_buffer(data, ifwi_size, 0, + &ifwi_image.bpdt, "BPDT"); + + /* Parse S-BPDT, if any. */ + parse_sbpdt(data, ifwi_size); + + /* + * Check if there is any non-IFWI suffix. + * Assumption: non-IFWI suffix always starts on 4k boundary. + */ + end_offset = ALIGN(end_offset, 4 * KiB); + + if (end_offset >= ifwi_size) + return 0; + + size_t size = ifwi_size - end_offset; + + INFO("File contains non-IFWI suffix (offset = 0x%zx, size=0x%zx)\n", + end_offset, size); + alloc_buffer(&ifwi_image.non_ifwi_suffix, size, + "Non-IFWI Suffix"); + memcpy(buffer_get(&ifwi_image.non_ifwi_suffix), + (uint8_t *)data + end_offset, size); + + buffer_delete(&buff); + + DEBUG("Parsing done\n"); + + return 0; +} + +/* + * This function is used by repack to count the number of BPDT and S-BPDT + * entries that are present. It frees the current buffers used by the entries + * and allocates fresh buffers that can be used for repacking. Returns BPDT + * entries which are empty and need to be filled in. + */ +static void __bpdt_reset(struct buffer *b, size_t count) +{ + struct bpdt *bpdt = buffer_get(b); + + /* If count has not changed, just zero out BPDT entries. */ + if (bpdt->h.descriptor_count == count) { + memset(&bpdt->e[0], 0, BPDT_ENTRY_SIZE * count); + return; + } + + /* Else, re-allocate buffer of new size and then zero out entries. */ + char *name = strdup(b->name); + assert(name); + + struct bpdt_header temp; + bpdt->h.descriptor_count = count; + memcpy(&temp, &bpdt->h, BPDT_HEADER_SIZE); + + buffer_delete(b); + alloc_buffer(b, BPDT_SIZE(count), name); + + bpdt = buffer_get(b); + + memcpy(&bpdt->h, &temp, BPDT_HEADER_SIZE); + if (count == 0) + return; + + memset(&bpdt->e[0], 0, BPDT_ENTRY_SIZE * count); +} + +static void bpdt_reset(void) +{ + size_t i; + size_t bpdt_count = 0, sbpdt_count = 0, dummy_bpdt_count = 0; + + /* Count number of BPDT and S-BPDT entries. */ + for (i = 0; i < MAX_COMPS; i++) { + if (buffer_size(&ifwi_image.comp_buf[i]) == 0) { + if (comp[i].attr & MANDATORY_BPDT_ENTRY) { + bpdt_count++; + dummy_bpdt_count++; + } + continue; + } + + if (comp[i].attr & NON_CRITICAL_COMP) + sbpdt_count++; + else + bpdt_count++; + } + + DEBUG("Count: BPDT = %zd, Dummy BPDT = %zd, S-BPDT = %zd\n", bpdt_count, + dummy_bpdt_count, sbpdt_count); + + /* Update BPDT if required. */ + __bpdt_reset(&ifwi_image.bpdt, bpdt_count); + + /* Update S-BPDT if required. */ + __bpdt_reset(&ifwi_image.comp_buf[S_BPDT_TYPE], sbpdt_count); +} + +/* Initialize BPDT entries in header order. */ +static void bpdt_entries_init_header_order(void) +{ + int i, type; + size_t size; + + struct bpdt *bpdt, *sbpdt, *curr; + size_t bpdt_curr = 0, sbpdt_curr = 0, *count_ptr; + + bpdt = buffer_get(&ifwi_image.bpdt); + sbpdt = buffer_get(&ifwi_image.comp_buf[S_BPDT_TYPE]); + + for (i = 0; i < MAX_COMPS; i++) { + type = bpdt_header_order[i]; + size = buffer_size(&ifwi_image.comp_buf[type]); + + if ((size == 0) && !(comp[type].attr & MANDATORY_BPDT_ENTRY)) + continue; + + if (comp[type].attr & NON_CRITICAL_COMP) { + curr = sbpdt; + count_ptr = &sbpdt_curr; + } else { + curr = bpdt; + count_ptr = &bpdt_curr; + } + + assert(*count_ptr < curr->h.descriptor_count); + curr->e[*count_ptr].type = type; + curr->e[*count_ptr].flags = 0; + curr->e[*count_ptr].offset = 0; + curr->e[*count_ptr].size = size; + + (*count_ptr)++; + } +} + +/* Initialize offsets of entries using pack order. */ +static void bpdt_entries_init_pack_order(void) +{ + int i, type; + struct bpdt_entry *curr; + uint32_t alignment; + size_t curr_offset; + size_t max_offset = 0; + + curr_offset = MAX(512, buffer_size(&ifwi_image.bpdt)); + + for (i = 0; i < MAX_COMPS; i++) { + type = bpdt_pack_order[i]; + curr = find_entry_by_type(type); + + if ((curr == NULL) || (curr->size == 0)) + continue; + + if (comp[type].attr & LIES_WITHIN_BPDT_4K) + alignment = 1; + else + alignment = 4 * KiB; + + curr->offset = ALIGN(curr_offset, alignment); + curr_offset = curr->offset + curr->size; + + if (max_offset < curr_offset) + max_offset = curr_offset; + } + + /* + * Update size of S-BPDT to include size of all non-critical + * components. + * + * Assumption: S-BPDT always lies at the end of IFWI image. + */ + curr = find_entry_by_type(S_BPDT_TYPE); + assert(curr); + + curr->size = max_offset - curr->offset; +} + +/* + * Copy data from src to dst. + * curr_offset identifies the offset upto which data is written to in dst. + * write_offset identifies the offset at which data from src is to be written to + * dst. + * + * This function fills up FF in any hole present between end of last + * write(curr_offset) and offset for current src(write_offset). + * + * IMPORTANT: data_copy needs to be called in ascending order of write_offset to + * properly fill up holes with FF. + */ +static void data_copy(struct buffer *dst, size_t *curr_offset, + size_t write_offset, struct buffer *src) +{ + uint8_t *data_dst = buffer_get(dst); + uint8_t *data_src = buffer_get(src); + + assert(data_dst); + + if (buffer_size(src) == 0) + return; + + if (*curr_offset < write_offset) + memset(data_dst + *curr_offset, 0xFF, + write_offset - *curr_offset); + + memcpy(data_dst + write_offset, data_src, buffer_size(src)); + + *curr_offset = write_offset + buffer_size(src); +} + +/* + * Identify the next entry that lies immediately above or at the passed in + * offset. Component could lie either within BPDT or S-BPDT. + * + * entries = Entries in BPDT or S-BPDT + * count = Total number of entries in BPDT or S-BPDT + * offset = Offset at or above which the next component lies at + */ +static struct bpdt_entry *__get_next_entry(struct bpdt *bpdt, size_t offset) +{ + uint32_t i; + size_t lowest_offset = SIZE_MAX; + struct bpdt_entry *next = NULL; + + for (i = 0; i < bpdt->h.descriptor_count; i++) { + if (bpdt->e[i].offset == offset) { + next = &bpdt->e[i]; + break; + } + + if ((bpdt->e[i].offset > offset) && + (bpdt->e[i].offset < lowest_offset)) { + lowest_offset = bpdt->e[i].offset; + next = &bpdt->e[i]; + } + } + + return next; +} + +static struct bpdt_entry *get_next_entry(size_t offset) +{ + struct bpdt_entry *next; + next = __get_next_entry(buffer_get(&ifwi_image.bpdt), offset); + + if (next) + return next; + + return __get_next_entry(buffer_get(&ifwi_image.comp_buf[S_BPDT_TYPE]), + offset); +} + +/* Convert all members of BPDT to little-endian format. */ +static void bpdt_fixup_write_buffer(struct buffer *buf) +{ + struct bpdt *s = buffer_get(buf); + + struct bpdt_header *h = &s->h; + struct bpdt_entry *e = &s->e[0]; + + size_t count = h->descriptor_count; + + size_t offset = 0; + + FIX_MEMBER(h->signature); + FIX_MEMBER(h->descriptor_count); + FIX_MEMBER(h->bpdt_version); + FIX_MEMBER(h->xor_redundant_block); + FIX_MEMBER(h->ifwi_version); + FIX_MEMBER(h->fit_tool_version); + + uint32_t i; + for (i = 0; i < count; i++) { + FIX_MEMBER(e[i].type); + FIX_MEMBER(e[i].flags); + FIX_MEMBER(e[i].offset); + FIX_MEMBER(e[i].size); + } +} + +/* Write BPDT to output buffer after fixup. */ +static void bpdt_write(struct buffer *dst, size_t offset, struct buffer *src) +{ + bpdt_fixup_write_buffer(src); + memcpy(buffer_get(dst) + offset, buffer_get(src), buffer_size(src)); +} + +/* + * Follows these steps to re-create image: + * 1. Write any non-IFWI prefix. + * 2. Write out BPDT header and entries. + * 3. Write component buffers to respective offsets. + * 4. Write any non-IFWI suffix. + * + * While performing the above steps, make sure that any empty holes are filled + * with FF. + */ +static void ifwi_write(const char *image_name) +{ + struct bpdt_entry *s = find_entry_by_type(S_BPDT_TYPE); + assert(s); + + size_t bpdt_offset = buffer_size(&ifwi_image.non_ifwi_prefix); + size_t non_ifwi_suffix_offset = s->offset + s->size; + size_t non_ifwi_suffix_size = buffer_size(&ifwi_image.non_ifwi_suffix); + + if (non_ifwi_suffix_size) + non_ifwi_suffix_offset = ALIGN(s->offset + s->size, 4096); + + size_t total_size = bpdt_offset + non_ifwi_suffix_offset + + non_ifwi_suffix_size; + + struct buffer b; + size_t curr_offset = 0; + + alloc_buffer(&b, total_size, "Final-IFWI"); + + /* Copy non-IFWI prefix, if any. */ + data_copy(&b, &curr_offset, 0, &ifwi_image.non_ifwi_prefix); + + struct buffer bpdt; + buffer_splice(&bpdt, &b, curr_offset, buffer_size(&b) - curr_offset); + + curr_offset = buffer_size(&ifwi_image.bpdt);; + + /* Copy components. */ + struct bpdt_entry *curr; + while (1) { + curr = get_next_entry(curr_offset); + if (curr == NULL) + break; + + assert(curr->size != 0); + data_copy(&bpdt, &curr_offset, curr->offset, + &ifwi_image.comp_buf[curr->type]); + } + + assert (curr_offset == (s->offset + s->size)); + + /* + * Copy non-IFWI suffix, if any. + * Assumption: Non-IFWI suffix starts on 4k boundary. + */ + if (non_ifwi_suffix_size == 0) { + buffer_delete(&b); + return; + } + + data_copy(&bpdt, &curr_offset, non_ifwi_suffix_offset, + &ifwi_image.non_ifwi_suffix); + + /* + * Convert BPDT to little-endian format and write it to output buffer. + * S-BPDT is written first and then BPDT. + */ + bpdt_write(&bpdt, s->offset, &ifwi_image.comp_buf[S_BPDT_TYPE]); + bpdt_write(&bpdt, 0, &ifwi_image.bpdt); + + if (buffer_write_file(&b, image_name)) { + ERROR("File write error\n"); + exit(-1); + } + + buffer_delete(&b); +} + +/* + * Calculate size and offset of each component again since it might have changed + * because of add/delete operation. Also, re-create BPDT and S-BPDT entries and + * write back the new IFWI image to file. + */ +static void ifwi_repack(void) +{ + bpdt_reset(); + bpdt_entries_init_header_order(); + bpdt_entries_init_pack_order(); + + struct bpdt *b = buffer_get(&ifwi_image.bpdt); + bpdt_print_entries(&b->e[0], b->h.descriptor_count, "BPDT"); + + b = buffer_get(&ifwi_image.comp_buf[S_BPDT_TYPE]); + bpdt_print_entries(&b->e[0], b->h.descriptor_count, "S-BPDT"); + + ifwi_write(param.image_name); +} + +static enum ifwi_ret ifwi_raw_add(int type) +{ + if (buffer_from_file(&ifwi_image.comp_buf[type], param.file_name)) + return COMM_ERR; + + return REPACK_REQUIRED; +} + +static enum ifwi_ret ifwi_cbp_add(int type) +{ + if (!(comp[type].attr & CONTAINS_SUBPART) || + (comp[type].cbp_ops.cbp_add == NULL)) { + ERROR("Component %s(%d) does not support cbp ops.\n", + comp[type].name, type); + return COMM_ERR; + } + + parse_subpart(&ifwi_image.comp_buf[type], comp[type].name); + return comp[type].cbp_ops.cbp_add(type); +} + +static enum ifwi_ret ifwi_add(void) +{ + if (!param.file_name) { + ERROR("%s: -f option required\n", __func__); + return COMM_ERR; + } + + if (!param.comp_name) { + ERROR("%s: -n option required\n", __func__); + return COMM_ERR; + } + + int type = find_type_by_name(param.comp_name); + if (type == -1) + return COMM_ERR; + + struct bpdt_comp *curr_comp = &comp[type]; + + if (curr_comp->attr & AUTO_GENERATED) { + ERROR("Cannot delete auto-generated components.\n"); + return COMM_ERR; + } + + if (buffer_size(&ifwi_image.comp_buf[type])) { + ERROR("Image already contains component %s(%d).\n", + param.comp_name, type); + return COMM_ERR; + } + + if (param.subpart_ops) + return ifwi_cbp_add(type); + + return ifwi_raw_add(type); +} + +static enum ifwi_ret ifwi_delete(void) +{ + if (!param.comp_name) { + ERROR("%s: -n option required\n", __func__); + return COMM_ERR; + } + + int type = find_type_by_name(param.comp_name); + if (type == -1) + return COMM_ERR; + + struct bpdt_comp *curr_comp = &comp[type]; + + if (curr_comp->attr & AUTO_GENERATED) { + ERROR("Cannot delete auto-generated components.\n"); + return COMM_ERR; + } + + if (buffer_size(&ifwi_image.comp_buf[type]) == 0) { + ERROR("Image does not contain component %s(%d).\n", + param.comp_name, type); + return COMM_ERR; + } + + buffer_delete(&ifwi_image.comp_buf[type]); + + INFO("Component %s(%d) deleted.\n", comp[type].name, type); + + return REPACK_REQUIRED; +} + +static enum ifwi_ret ifwi_cbp_extract(int type) +{ + if (!(comp[type].attr & CONTAINS_SUBPART)) { + ERROR("Component %s(%d) does not support cbp ops.\n", + comp[type].name, type); + return COMM_ERR; + } + + parse_subpart(&ifwi_image.comp_buf[type], comp[type].name); + + uint32_t i; + struct subpart *s = buffer_get(&ifwi_image.subpart); + + for (i = 0; i < s->h.num_entries; i++) { + if (!strcmp((char *)s->e[i].name, param.file_name)) + break; + } + + if (i == s->h.num_entries) { + ERROR("File %s not found in subpartition for %s.\n", + param.file_name, param.comp_name); + exit(-1); + } + + struct buffer dst; + + buffer_splice(&dst, &ifwi_image.subpart, s->e[i].offset, + s->e[i].length); + + if (buffer_write_file(&dst, param.file_name)) + return COMM_ERR; + + INFO("Component %s(%d) stored in %s.\n", param.comp_name, type, + param.file_name); + + return NO_ACTION_REQUIRED; +} + +static enum ifwi_ret ifwi_raw_extract(int type) +{ + if (buffer_write_file(&ifwi_image.comp_buf[type], param.file_name)) + return COMM_ERR; + + INFO("Component %s(%d) stored in %s.\n", param.comp_name, type, + param.file_name); + + return NO_ACTION_REQUIRED; +} + +static enum ifwi_ret ifwi_extract(void) +{ + if (!param.file_name) { + ERROR("%s: -f option required\n", __func__); + return COMM_ERR; + } + + if (!param.comp_name) { + ERROR("%s: -n option required\n", __func__); + return COMM_ERR; + } + + int type = find_type_by_name(param.comp_name); + if (type == -1) + return COMM_ERR; + + if (type == S_BPDT_TYPE) { + ERROR("Nothing to extract.\n"); + return NO_ACTION_REQUIRED; + } + + if (buffer_size(&ifwi_image.comp_buf[type]) == 0) { + ERROR("Image does not contain component %s(%d).\n", + param.comp_name, type); + return COMM_ERR; + } + + INFO("Extracting component %s(%d).\n", param.comp_name, type); + if (param.subpart_ops) + return ifwi_cbp_extract(type); + + return ifwi_raw_extract(type); +} + +static enum ifwi_ret ifwi_print(void) +{ + verbose += 2; + + struct bpdt *b = buffer_get(&ifwi_image.bpdt); + + bpdt_print_header(&b->h, "BPDT"); + bpdt_print_entries(&b->e[0], b->h.descriptor_count, "BPDT"); + + b = buffer_get(&ifwi_image.comp_buf[S_BPDT_TYPE]); + bpdt_print_header(&b->h, "S-BPDT"); + bpdt_print_entries(&b->e[0], b->h.descriptor_count, "S-BPDT"); + + int i; + for (i = 0; i < MAX_COMPS ; i++) { + if (!(comp[i].attr & CONTAINS_SUBPART) || + (buffer_size(&ifwi_image.comp_buf[i]) == 0)) + continue; + + parse_subpart(&ifwi_image.comp_buf[i], comp[i].name); + } + + verbose -= 2; + + return NO_ACTION_REQUIRED; +} + +static enum ifwi_ret ifwi_raw_replace(int type) +{ + if (buffer_size(&ifwi_image.comp_buf[type]) == 0) { + INFO("Image does not contain component %s(%d).\n", + param.comp_name, type); + } else + buffer_delete(&ifwi_image.comp_buf[type]); + + return ifwi_raw_add(type); +} + +static void subpart_fixup_write_buffer(struct buffer *buf) +{ + struct subpart *s = buffer_get(buf); + struct subpart_header *h = &s->h; + struct subpart_entry *e = &s->e[0]; + + size_t count = h->num_entries; + size_t offset = 0; + + FIX_MEMBER(h->marker); + FIX_MEMBER(h->num_entries); + FIX_MEMBER(h->header_version); + FIX_MEMBER(h->entry_version); + FIX_MEMBER(h->header_length); + FIX_MEMBER(h->checksum); + offset += sizeof(h->name); + + uint32_t i; + for (i = 0; i < count; i++) { + offset += sizeof(e[i].name); + FIX_MEMBER(e[i].offset); + FIX_MEMBER(e[i].length); + FIX_MEMBER(e[i].rsvd); + } +} + +static enum ifwi_ret ifwi_cbp_replace(int type) +{ + if (buffer_size(&ifwi_image.comp_buf[type]) == 0) { + ERROR("Image does not contain component %s(%d).\n", + param.comp_name, type); + return COMM_ERR; + } + + if (!(comp[type].attr & CONTAINS_SUBPART)) { + ERROR("Component %s(%d) does not support cbp ops.\n", + comp[type].name, type); + return COMM_ERR; + } + + parse_subpart(&ifwi_image.comp_buf[type], comp[type].name); + + uint32_t i; + struct subpart *s = buffer_get(&ifwi_image.subpart); + + for (i = 0; i < s->h.num_entries; i++) { + if (!strcmp((char *)s->e[i].name, param.file_name)) + break; + } + + if (i == s->h.num_entries) { + ERROR("File %s not found in subpartition for %s.\n", + param.file_name, param.comp_name); + exit(-1); + } + + struct buffer b; + if (buffer_from_file(&b, param.file_name)) { + ERROR("Failed to read %s\n", param.file_name); + exit(-1); + } + + struct buffer dst; + size_t dst_size = buffer_size(&ifwi_image.comp_buf[type] + + buffer_size(&b) - s->e[i].length); + size_t comp_start = s->e[i].offset; + size_t comp_end = s->e[i].offset + s->e[i].length; + + alloc_buffer(&dst, dst_size, ifwi_image.comp_buf[type].name); + + uint8_t *src_data = buffer_get(&ifwi_image.comp_buf[type]); + uint8_t *dst_data = buffer_get(&dst); + size_t curr_offset = 0; + + /* Copy data before the sub-partition entry. */ + memcpy(dst_data + curr_offset, src_data, comp_start); + curr_offset += comp_start; + + /* Copy sub-partition entry. */ + memcpy(dst_data + curr_offset, buffer_get(&b), buffer_size(&b)); + curr_offset += buffer_size(&b); + + /* Copy remaining data. */ + memcpy(dst_data + curr_offset, src_data + comp_end, + buffer_size(&ifwi_image.comp_buf[type]) - comp_end); + + /* Update component buffer. */ + int offset = s->e[i].offset; + buffer_delete(&ifwi_image.comp_buf[type]); + ifwi_image.comp_buf[type] = dst; + + /* Update length of entry in the subpartition. */ + s->e[i].length = buffer_size(&b); + buffer_delete(&b); + + /* Adjust offsets of affected entries in subpartition. */ + offset = s->e[i].offset - offset; + for (; i < s->h.num_entries; i++) { + s->e[i].offset += offset; + } + + /* Convert members to litte-endian. */ + subpart_fixup_write_buffer(&ifwi_image.subpart); + + memcpy(dst_data, buffer_get(&ifwi_image.subpart), + buffer_size(&ifwi_image.subpart)); + + buffer_delete(&ifwi_image.subpart); + + return REPACK_REQUIRED; +} + +static enum ifwi_ret ifwi_replace(void) +{ + if (!param.file_name) { + ERROR("%s: -f option required\n", __func__); + return COMM_ERR; + } + + if (!param.comp_name) { + ERROR("%s: -n option required\n", __func__); + return COMM_ERR; + } + + int type = find_type_by_name(param.comp_name); + if (type == -1) + return COMM_ERR; + + struct bpdt_comp *curr_comp = &comp[type]; + + if (curr_comp->attr & AUTO_GENERATED) { + ERROR("Cannot replace auto-generated components.\n"); + return COMM_ERR; + } + + if (param.subpart_ops) + return ifwi_cbp_replace(type); + + return ifwi_raw_replace(type); +} + +static enum ifwi_ret ifwi_create(void) +{ + if (!param.file_name) { + ERROR("%s: -f option required\n", __func__); + return COMM_ERR; + } + + buffer_delete(&ifwi_image.non_ifwi_prefix); + buffer_delete(&ifwi_image.non_ifwi_suffix); + + param.image_name = param.file_name; + + return REPACK_REQUIRED; +} + +struct command { + const char *name; + const char *optstring; + enum ifwi_ret (*function)(void); +}; + +static const struct command commands[] = { + {"add", "f:n:svh?", ifwi_add}, + {"create", "f:vh?", ifwi_create}, + {"delete", "f:n:vh?", ifwi_delete}, + {"extract", "f:n:svh?", ifwi_extract}, + {"print", "h?", ifwi_print}, + {"replace", "f:n:svh?", ifwi_replace}, +}; + +static struct option long_options[] = { + {"file", required_argument, 0, 'f'}, + {"help", required_argument, 0, 'h'}, + {"name", required_argument, 0, 'n'}, + {"subpart_ops", no_argument, 0, 's'}, + {"verbose", no_argument, 0, 'v'}, + {NULL, 0, 0, 0 } +}; + +static void usage(const char *name) +{ + printf("ifwitool: Utility for IFWI manipulation\n\n" + "USAGE:\n" + " %s [-h]\n" + " %s FILE COMMAND [PARAMETERS]\n\n" + "COMMANDs:\n" + " add -f FILE -n NAME\n" + " create -f FILE\n" + " delete -n NAME\n" + " extract -f FILE -n NAME\n" + " print\n" + " replace -f FILE -n NAME\n", + name, name + ); +} + +int main(int argc, char **argv) +{ + if (argc < 3) { + usage(argv[0]); + return 1; + } + + param.image_name = argv[1]; + char *cmd = argv[2]; + optind += 2; + + uint32_t i; + + for (i = 0; i < ARRAY_SIZE(commands); i++) { + if (strcmp(cmd, commands[i].name) != 0) + continue; + + int c; + + while (1) { + int option_index; + + c = getopt_long(argc, argv, commands[i].optstring, + long_options, &option_index); + + if (c == -1) + break; + + /* Filter out illegal long options. */ + if (strchr(commands[i].optstring, c) == NULL) { + ERROR("%s: invalid option -- '%c'\n", argv[0], + c); + c = '?'; + } + + switch(c) { + case 'n': + param.comp_name = optarg; + break; + case 'f': + param.file_name = optarg; + break; + case 's': + param.subpart_ops = 1; + break; + case 'v': + verbose++; + break; + case 'h': + case '?': + usage(argv[0]); + return 1; + default: + break; + } + } + + if (ifwi_parse()) { + ERROR("%s: ifwi parsing failed\n", argv[0]); + return 1; + } + + enum ifwi_ret ret = commands[i].function(); + + if (ret == COMM_ERR) { + ERROR("%s: failed execution\n", argv[0]); + return 1; + } + + if (ret == REPACK_REQUIRED) + ifwi_repack(); + + return 0; + } + + ERROR("%s: invalid command\n", argv[0]); + return 1; +}

1 0

Patch set updated for coreboot: drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header
by Alexandru Gagniuc 24 May '16

24 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13331 -gerrit commit 9aaa9354056cbc16bbbc3c4952991939f4221482 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Oct 30 18:05:57 2015 -0700 drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header Previous FSP implementations in coreboot have included FspUpdVpd.h directly, along with with efi headers. Instead of taking that approach in FSP 2.0, we provide a semantic patch that, with minimal modifications, makes FspUpdVpd.h easier to include in coreboot, and eliminates reliance on external headers and definitions. Change-Id: I0c2a6f7baf6fb50ae22b64e08e653cfe1aefdaf9 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- .../intel/fsp2_0/header_util/fspupdvpd.spatch | 187 +++++++++++++++++++++ .../intel/fsp2_0/header_util/fspupdvpd_sanitize.sh | 33 ++++ 2 files changed, 220 insertions(+) diff --git a/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch new file mode 100644 index 0000000..d6bc820 --- /dev/null +++ b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch @@ -0,0 +1,187 @@ +/* + * Semantic patch for fspupdvpd_sanitize.sh. Please call the script directly. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This semantic patch is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +@ kill_pragma_pack @ +@@ +- #pragma pack(...) + +/* + * Convert named typedef'd structs + * Example : typedef struct name {} name_t; -> struct name {}; + */ +@ named_struct @ +identifier i; +type t; +@@ +typedef struct i { ... } t; + +/* Make typename usable as identifier */ +@ script:python named_struct_type @ +t << named_struct.t; +i; +@@ +coccinelle.i = t.rstrip('_t') + + +@ convert_named_struct_decls @ +type named_struct.t; +identifier named_struct_type.i; +identifier g; +@@ +- typedef struct g { ++ struct i { +... +} +- t +; + +/* Replace type with struct */ +@ named_typedef_to_struct @ +type named_struct.t; +identifier named_struct_type.i; +@@ +- t ++ struct i + + +/* + * Convert unnamed typedef'd structs + * Example : typedef struct {} name_t; -> struct name {}; + */ +@ unnamed_struct @ +type t; +@@ +typedef struct { ... } t; + +/* Make typename usable as identifier */ +@ script:python unnamed_struct_type @ +t << unnamed_struct.t; +i; +@@ +coccinelle.i = t.rstrip('_t') + +@ convert_unnamed_struct_decls @ +type unnamed_struct.t; +identifier unnamed_struct_type.i; +@@ +-typedef struct { ++struct i { + ... +} +- t +; + +/* + * Convert unnamed typedef'd enums + */ +@ unnamed_enum @ +type t; +@@ +typedef enum { ... } t; + +/* Make typename usable as identifier */ +@ script:python unnamed_enum_type @ +t << unnamed_enum.t; +i; +@@ +coccinelle.i = t.rstrip('_t') + +@ convert_unnamed_enum_decls @ +type unnamed_enum.t; +identifier unnamed_enum_type.i; +@@ +-typedef enum { ++enum i { + ... +} +- t +; + +/* Replace type with struct */ +@ unnamed_typedef_to_struct @ +type unnamed_struct.t; +identifier unnamed_struct_type.i; +@@ +-t ++struct i + +/* + * Pack _ALL_ structs + */ +@ pack_structs @ +identifier s; +@@ + +struct s { +... +} ++ __attribute__((packed)) +; + +/* + * BIGINT to stdint + */ +@ uint8_t @ +typedef UINT8; +typedef uint8_t; +@@ +- UINT8 ++ uint8_t + +@ uint16_t @ +typedef UINT16; +typedef uint16_t; +@@ +- UINT16 ++ uint16_t + +@ uint32_t @ +typedef UINT32; +typedef uint32_t; +@@ +- UINT32 ++ uint32_t + +@ uint64_t @ +typedef UINT64; +typedef uint64_t; +@@ +- UINT64 ++ uint64_t + +@ bool @ +typedef BOOLEAN; +typedef bool; +@@ +- BOOLEAN ++ bool + +@ wchar_t @ +typedef CHAR16; +typedef wchar_t; +@@ +- CHAR16 ++ wchar_t + +/* This rule can't be named "void" */ +@ replace_uppercase_void @ +typedef VOID; +@@ +- VOID ++ void diff --git a/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh b/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh new file mode 100644 index 0000000..2b50053 --- /dev/null +++ b/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh @@ -0,0 +1,33 @@ +# +# Convert the FspUpdVpd.h header file into a format usable by coreboot +# Usage: +# fspupdvpd_sanitize.sh <path/to/FspUpdVpd.h> +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2016 Intel Corp. +# (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +PWD=$(dirname "${BASH_SOURCE[0]}") + +SPATCH=spatch + +# Fix line terminations +dos2unix $1 + +# Clean up trailing whitespace +sed -e "s, $,,g" -i $1 + +# Now fix the actual coding style +$SPATCH -sp_file ${PWD}/fspupdvpd.spatch \ + -in_place $1

1 0

Patch set updated for coreboot: drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header
by Alexandru Gagniuc 24 May '16

24 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13331 -gerrit commit 03e81abbdcafcc7990bc13e5ea4ada814fe4c79a Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Oct 30 18:05:57 2015 -0700 drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header Previous FSP implementations in coreboot have included FspUpdVpd.h directly, along with with efi headers. Instead of taking that approach in FSP 2.0, we provide a semantic patch that, with minimal modifications, makes FspUpdVpd.h easier to include in coreboot, and eliminates reliance on external headers and definitions. Change-Id: I0c2a6f7baf6fb50ae22b64e08e653cfe1aefdaf9 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- .../intel/fsp2_0/header_util/fspupdvpd.spatch | 187 +++++++++++++++++++++ .../intel/fsp2_0/header_util/fspupdvpd_sanitize.sh | 34 ++++ 2 files changed, 221 insertions(+) diff --git a/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch new file mode 100644 index 0000000..d6bc820 --- /dev/null +++ b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch @@ -0,0 +1,187 @@ +/* + * Semantic patch for fspupdvpd_sanitize.sh. Please call the script directly. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This semantic patch is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +@ kill_pragma_pack @ +@@ +- #pragma pack(...) + +/* + * Convert named typedef'd structs + * Example : typedef struct name {} name_t; -> struct name {}; + */ +@ named_struct @ +identifier i; +type t; +@@ +typedef struct i { ... } t; + +/* Make typename usable as identifier */ +@ script:python named_struct_type @ +t << named_struct.t; +i; +@@ +coccinelle.i = t.rstrip('_t') + + +@ convert_named_struct_decls @ +type named_struct.t; +identifier named_struct_type.i; +identifier g; +@@ +- typedef struct g { ++ struct i { +... +} +- t +; + +/* Replace type with struct */ +@ named_typedef_to_struct @ +type named_struct.t; +identifier named_struct_type.i; +@@ +- t ++ struct i + + +/* + * Convert unnamed typedef'd structs + * Example : typedef struct {} name_t; -> struct name {}; + */ +@ unnamed_struct @ +type t; +@@ +typedef struct { ... } t; + +/* Make typename usable as identifier */ +@ script:python unnamed_struct_type @ +t << unnamed_struct.t; +i; +@@ +coccinelle.i = t.rstrip('_t') + +@ convert_unnamed_struct_decls @ +type unnamed_struct.t; +identifier unnamed_struct_type.i; +@@ +-typedef struct { ++struct i { + ... +} +- t +; + +/* + * Convert unnamed typedef'd enums + */ +@ unnamed_enum @ +type t; +@@ +typedef enum { ... } t; + +/* Make typename usable as identifier */ +@ script:python unnamed_enum_type @ +t << unnamed_enum.t; +i; +@@ +coccinelle.i = t.rstrip('_t') + +@ convert_unnamed_enum_decls @ +type unnamed_enum.t; +identifier unnamed_enum_type.i; +@@ +-typedef enum { ++enum i { + ... +} +- t +; + +/* Replace type with struct */ +@ unnamed_typedef_to_struct @ +type unnamed_struct.t; +identifier unnamed_struct_type.i; +@@ +-t ++struct i + +/* + * Pack _ALL_ structs + */ +@ pack_structs @ +identifier s; +@@ + +struct s { +... +} ++ __attribute__((packed)) +; + +/* + * BIGINT to stdint + */ +@ uint8_t @ +typedef UINT8; +typedef uint8_t; +@@ +- UINT8 ++ uint8_t + +@ uint16_t @ +typedef UINT16; +typedef uint16_t; +@@ +- UINT16 ++ uint16_t + +@ uint32_t @ +typedef UINT32; +typedef uint32_t; +@@ +- UINT32 ++ uint32_t + +@ uint64_t @ +typedef UINT64; +typedef uint64_t; +@@ +- UINT64 ++ uint64_t + +@ bool @ +typedef BOOLEAN; +typedef bool; +@@ +- BOOLEAN ++ bool + +@ wchar_t @ +typedef CHAR16; +typedef wchar_t; +@@ +- CHAR16 ++ wchar_t + +/* This rule can't be named "void" */ +@ replace_uppercase_void @ +typedef VOID; +@@ +- VOID ++ void diff --git a/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh b/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh new file mode 100644 index 0000000..8563279 --- /dev/null +++ b/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh @@ -0,0 +1,34 @@ +# +# Convert the FspUpdVpd.h header file into a format usable by coreboot +# Usage: +# fspupdvpd_sanitize.sh <path/to/FspUpdVpd.h> +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2016 Intel Corp. +# (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +HOME=$(dirname "${BASH_SOURCE[0]}") +DEST=$HOME + +SPATCH=spatch + +# Fix line terminations +dos2unix $1 + +# Clean up trailing whitespace +sed -e "s, $,,g" -i $1 + +# Now fix the actual coding style +$SPATCH -sp_file $HOME/fspupdvpd.spatch \ + -in_place $1

1 0

Patch set updated for coreboot: arm64: Add stack dump to exception handler
by Julius Werner 23 May '16

23 May '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14931 -gerrit commit e42f310e78b9b46fc8f32f41d14cc4242606f077 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri May 20 18:06:22 2016 -0700 arm64: Add stack dump to exception handler Some exceptions (like from calling a NULL function pointer) are easier to narrow down with a dump of the call stack. Let's take a page out of ARM32's book and add that feature to ARM64 as well. Also change the output format to two register columns, to make it easier to fit a whole exception dump on one screen. Applying to both coreboot and libpayload and syncing the output format between both back up. Change-Id: I19768d13d8fa8adb84f0edda2af12f20508eb2db Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- payloads/libpayload/arch/arm64/exception.c | 30 +++++++++++++++++++---- src/arch/arm64/armv8/exception.c | 38 ++++++++++++++++++++++-------- 2 files changed, 54 insertions(+), 14 deletions(-) diff --git a/payloads/libpayload/arch/arm64/exception.c b/payloads/libpayload/arch/arm64/exception.c index 2330a98..078a700 100644 --- a/payloads/libpayload/arch/arm64/exception.c +++ b/payloads/libpayload/arch/arm64/exception.c @@ -60,15 +60,35 @@ static struct exception_handler_info exceptions[EXC_COUNT] = { [EXC_SERROR_ELX_32] = {"_serror_elx_32"}, }; +static void dump_stack(uintptr_t addr, size_t bytes) +{ + int i, j; + const int words_per_line = 8; + uint64_t *ptr = (void *)ALIGN_DOWN(addr, words_per_line * sizeof(*ptr)); + + printf("Dumping stack:\n"); + for (i = bytes / sizeof(*ptr); i >= 0; i -= words_per_line) { + printf("%p: ", ptr + i); + for (j = i; j < i + words_per_line; j++) + printf("%016llx ", *(ptr + j)); + printf("\n"); + } +} + static void print_regs(struct exception_state *state) { int i; - printf("ELR = 0x%016llx\n",state->elr); - printf("ESR = 0x%08llx\n",state->esr); - for (i = 0; i < 31; i++) { - printf("X%02d = 0x%016llx\n", i, state->regs[i]); + printf("ELR = 0x%016llx ESR = 0x%08llx\n", + state->elr, state->esr); + printf("FAR = 0x%016llx SPSR = 0x%08x\n", + raw_read_far_current(), raw_read_spsr_current()); + for (i = 0; i < 30; i += 2) { + printf("X%02d = 0x%016llx X%02d = 0x%016llx\n", + i, state->regs[i], i + 1, state->regs[i + 1]); } + printf("X30 = 0x%016llx SP = 0x%016llx\n", + state->regs[30], raw_read_sp_el0()); } void exception_dispatch(struct exception_state *state, int idx); @@ -89,6 +109,8 @@ void exception_dispatch(struct exception_state *state, int idx) printf("exception _not_used.\n"); } print_regs(state); + /* Few words below SP in case we need state from a returned function. */ + dump_stack(raw_read_sp_el0() - 32, 512); if (test_exc) { state->elr += 4; diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index b872a55..c5cbbfe 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -57,22 +57,38 @@ static const char *exception_names[NUM_EXC_VIDS] = { [EXC_VID_LOW32_SERR] = "_serror_elx_32" }; +static void dump_stack(uintptr_t addr, size_t bytes) +{ + int i, j; + const int words_per_line = 8; + uint64_t *ptr = (void *)ALIGN_DOWN(addr, words_per_line * sizeof(*ptr)); + + printk(BIOS_DEBUG, "Dumping stack:\n"); + for (i = bytes / sizeof(*ptr); i >= 0; i -= words_per_line) { + printk(BIOS_DEBUG, "%p: ", ptr + i); + for (j = i; j < i + words_per_line; j++) + printk(BIOS_DEBUG, "%016llx ", *(ptr + j)); + printk(BIOS_DEBUG, "\n"); + } +} + static void print_regs(struct exc_state *exc_state) { int i; struct elx_state *elx = &exc_state->elx; struct regs *regs = &exc_state->regs; - uint64_t elx_esr = raw_read_esr_current(); - uint64_t elx_far = raw_read_far_current(); - - printk(BIOS_DEBUG, "ELR = 0x%016llx\n", elx->elr); - printk(BIOS_DEBUG, "ESR = 0x%016llx\n", elx_esr); - printk(BIOS_DEBUG, "SPSR = 0x%08llx\n", elx->spsr); - printk(BIOS_DEBUG, "FAR = 0x%016llx\n", elx_far); - printk(BIOS_DEBUG, "SP = 0x%016llx\n", regs->sp); - for (i = X0_INDEX; i < XMAX_INDEX; i++) - printk(BIOS_DEBUG, "X%02d = 0x%016llx\n", i, regs->x[i]); + printk(BIOS_DEBUG, "ELR = 0x%016llx ESR = 0x%08x\n", + elx->elr, raw_read_esr_current()); + printk(BIOS_DEBUG, "FAR = 0x%016llx SPSR = 0x%08x\n", + raw_read_far_current(), raw_read_spsr_current()); + for (i = 0; i < 30; i += 2) { + printk(BIOS_DEBUG, + "X%02d = 0x%016llx X%02d = 0x%016llx\n", + i, regs->x[i], i + 1, regs->x[i + 1]); + } + printk(BIOS_DEBUG, "X30 = 0x%016llx SP = 0x%016llx\n", + regs->x[30], regs->sp); } @@ -119,6 +135,8 @@ static void print_exception_info(struct exc_state *state, uint64_t idx) printk(BIOS_DEBUG, "exception %s\n", exception_names[idx]); print_regs(state); + /* Few words below SP in case we need state from a returned function. */ + dump_stack(state->regs.sp - 32, 512); } static void print_exception_and_die(struct exc_state *state, uint64_t idx)

1 0

Patch set updated for coreboot: arm64: Add stack dump to exception handler
by Julius Werner 23 May '16

23 May '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14931 -gerrit commit 2973ecbe7899da911f1e054fa82035521c5ba885 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri May 20 18:06:22 2016 -0700 arm64: Add stack dump to exception handler Some exceptions (like from calling a NULL function pointer) are easier to narrow down with a dump of the call stack. Let's take a page out of ARM32's book and add that feature to ARM64 as well. Also change the output format to two register columns, to make it easier to fit a whole exception dump on one screen. Applying to both coreboot and libpayload and syncing the output format between both back up. Change-Id: I19768d13d8fa8adb84f0edda2af12f20508eb2db Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- payloads/libpayload/arch/arm64/exception.c | 29 +++++++++++++++++++---- src/arch/arm64/armv8/exception.c | 37 ++++++++++++++++++++++-------- 2 files changed, 52 insertions(+), 14 deletions(-) diff --git a/payloads/libpayload/arch/arm64/exception.c b/payloads/libpayload/arch/arm64/exception.c index 2330a98..b364970 100644 --- a/payloads/libpayload/arch/arm64/exception.c +++ b/payloads/libpayload/arch/arm64/exception.c @@ -60,15 +60,35 @@ static struct exception_handler_info exceptions[EXC_COUNT] = { [EXC_SERROR_ELX_32] = {"_serror_elx_32"}, }; +static void dump_stack(uintptr_t addr, size_t bytes) +{ + int i, j; + const int line = 8; + uint64_t *ptr = (uint64_t *)ALIGN_DOWN(addr, line * sizeof(*ptr)); + + printf("Dumping stack:\n"); + for (i = bytes / sizeof(*ptr); i >= 0; i -= line) { + printf("%p: ", ptr + i); + for (j = i; j < i + line; j++) + printf("%016llx ", *(ptr + j)); + printf("\n"); + } +} + static void print_regs(struct exception_state *state) { int i; - printf("ELR = 0x%016llx\n",state->elr); - printf("ESR = 0x%08llx\n",state->esr); - for (i = 0; i < 31; i++) { - printf("X%02d = 0x%016llx\n", i, state->regs[i]); + printf("ELR = 0x%016llx ESR = 0x%08llx\n", + state->elr, state->esr); + printf("FAR = 0x%016llx SPSR = 0x%08x\n", + raw_read_far_current(), raw_read_spsr_current()); + for (i = 0; i < 30; i += 2) { + printf("X%02d = 0x%016llx X%02d = 0x%016llx\n", + i, state->regs[i], i + 1, state->regs[i + 1]); } + printf("X30 = 0x%016llx SP = 0x%016llx\n", + state->regs[30], raw_read_sp_el0()); } void exception_dispatch(struct exception_state *state, int idx); @@ -89,6 +109,7 @@ void exception_dispatch(struct exception_state *state, int idx) printf("exception _not_used.\n"); } print_regs(state); + dump_stack(raw_read_sp_el0() - 16, 512); if (test_exc) { state->elr += 4; diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index b872a55..7958d7c 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -57,22 +57,38 @@ static const char *exception_names[NUM_EXC_VIDS] = { [EXC_VID_LOW32_SERR] = "_serror_elx_32" }; +static void dump_stack(uintptr_t addr, size_t bytes) +{ + int i, j; + const int line = 8; + uint64_t *ptr = (uint64_t *)ALIGN_DOWN(addr, line * sizeof(*ptr)); + + printk(BIOS_DEBUG, "Dumping stack:\n"); + for (i = bytes / sizeof(*ptr); i >= 0; i -= line) { + printk(BIOS_DEBUG, "%p: ", ptr + i); + for (j = i; j < i + line; j++) + printk(BIOS_DEBUG, "%016llx ", *(ptr + j)); + printk(BIOS_DEBUG, "\n"); + } +} + static void print_regs(struct exc_state *exc_state) { int i; struct elx_state *elx = &exc_state->elx; struct regs *regs = &exc_state->regs; - uint64_t elx_esr = raw_read_esr_current(); - uint64_t elx_far = raw_read_far_current(); - - printk(BIOS_DEBUG, "ELR = 0x%016llx\n", elx->elr); - printk(BIOS_DEBUG, "ESR = 0x%016llx\n", elx_esr); - printk(BIOS_DEBUG, "SPSR = 0x%08llx\n", elx->spsr); - printk(BIOS_DEBUG, "FAR = 0x%016llx\n", elx_far); - printk(BIOS_DEBUG, "SP = 0x%016llx\n", regs->sp); - for (i = X0_INDEX; i < XMAX_INDEX; i++) - printk(BIOS_DEBUG, "X%02d = 0x%016llx\n", i, regs->x[i]); + printk(BIOS_DEBUG, "ELR = 0x%016llx ESR = 0x%08x\n", + elx->elr, raw_read_esr_current()); + printk(BIOS_DEBUG, "FAR = 0x%016llx SPSR = 0x%08x\n", + raw_read_far_current(), raw_read_spsr_current()); + for (i = 0; i < 30; i += 2) { + printk(BIOS_DEBUG, + "X%02d = 0x%016llx X%02d = 0x%016llx\n", + i, regs->x[i], i + 1, regs->x[i + 1]); + } + printk(BIOS_DEBUG, "X30 = 0x%016llx SP = 0x%016llx\n", + regs->x[30], regs->sp); } @@ -119,6 +135,7 @@ static void print_exception_info(struct exc_state *state, uint64_t idx) printk(BIOS_DEBUG, "exception %s\n", exception_names[idx]); print_regs(state); + dump_stack(state->regs.sp, 512); } static void print_exception_and_die(struct exc_state *state, uint64_t idx)

1 0

New patch to review for coreboot: soc/apollolake/memmap: Switch to SIMPLE_DEVICE API
by Alexandru Gagniuc 23 May '16

23 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14953 -gerrit commit 5ea5b3d2f02714c033161ae29547e44a3cc1c4b5 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon May 23 14:04:58 2016 -0700 soc/apollolake/memmap: Switch to SIMPLE_DEVICE API memmap.c functionality is designed to be used in more than ramstage. Therefore, it cannot use ramstage-specific APIs. In this case, the SIMPLE_DEVICE API offers a more consistent behavior across stages. Change-Id: Ic381fe1eb773fb0a5fb5887eb67d2228d2f0817d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/memmap.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index bf172cb..ae1394f 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -15,6 +15,14 @@ * GNU General Public License for more details. */ +/* + * The device_t returned by dev_find_slot() is different than the device_t + * passed to pci_write_config32(). If one needs to get access to the config.h + * of a device and perform i/o things are incorrect. One is a pointer while + * the other is a 32-bit integer. + */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <cbmem.h> #include <device/pci.h>

1 0

Patch set updated for coreboot: soc/apollolake: Use simpler macros for the northbridge PCI device
by Alexandru Gagniuc 23 May '16

23 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14890 -gerrit commit 05bbe6c252329fd559a72eedd061b1e9d69c1fa0 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed May 18 10:26:53 2016 -0700 soc/apollolake: Use simpler macros for the northbridge PCI device The NB_DEV_ROOT macro, is almost unreadable, as it depends on other stringified macros, and acts differently depending on the coreboot stage. For ramstage, it also hides a function call. Rewrite the macro in terms of more basic and readable macros. Change-Id: I9b7071d67c8d58926e9b01fadaa239db1120448c Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/chip.c | 2 +- src/soc/intel/apollolake/include/soc/pci_devs.h | 12 +++--------- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index f56e1f2..23dc892 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -100,7 +100,7 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) /* Load VBT before devicetree-specific config. */ silconfig->GraphicsConfigPtr = (uintptr_t)vbt; - struct device *dev = NB_DEV_ROOT; + struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index ec550e8..d11b9a7 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -17,26 +17,17 @@ #include <rules.h> -#define _NB_DEVFN(slot) PCI_DEVFN(NB_DEV_SLOT_ ## slot, 0) #define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func) - #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> #include <device/pci_def.h> -#define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot)) #define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func)) #else #include <arch/io.h> -#define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0) #define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func) #endif -/* North bridge devices */ -#define NB_DEV_SLOT_ROOT 0x00 -#define NB_DEVFN_ROOT _NB_DEVFN(ROOT) -#define NB_DEV_ROOT _NB_DEV(ROOT) - /* LPSS UART */ #define LPSS_DEV_SLOT_UART 0x18 #define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0) @@ -48,6 +39,9 @@ #define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2) #define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3) +#define NB_BUS 0 +#define NB_DEVFN PCI_DEVFN(0, 0) +#define NB_DEV_ROOT PCI_DEV(NB_BUS, 0x0, 0) #define P2SB_DEV PCI_DEV(0, 0xd, 0) #define PMC_DEV PCI_DEV(0, 0xd, 1) #define SPI_DEV PCI_DEV(0, 0xd, 2)

1 0

New patch to review for coreboot: filo: Specify libpayload path
by Antonello Dettori 23 May '16

23 May '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14952 -gerrit commit 2e8584cffec4e0970edd08d39b759a73dbe996c0 Author: Antonello Dettori <dettori.an(a)gmail.com> Date: Mon May 23 22:40:58 2016 +0200 filo: Specify libpayload path Fix to make filo build when selected as a payload from menuconfig. The "make *conf" commands were pointing the correct path of libpayload but "make" wasn't, resulting in a build error. Change-Id: Ia7592667b1719836d1509e5cbc01d23266fca9fd Signed-off-by: Antonello Dettori <dettori.an(a)gmail.com> --- payloads/external/FILO/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/FILO/Makefile b/payloads/external/FILO/Makefile index 13d3e8f..1a03f81 100644 --- a/payloads/external/FILO/Makefile +++ b/payloads/external/FILO/Makefile @@ -33,11 +33,11 @@ config: libpayload #echo "CONFIG_VGAHOOKS=y" >> filo/.config # This shows how to force a previously set .config option *off* #echo "# CONFIG_SMBIOS is not set" >> filo/.config - $(MAKE) -C filo oldconfig LIBCONFIG_PATH=../../../libpayload + #$(MAKE) -C filo oldconfig LIBCONFIG_PATH=../../../libpayload filo: config echo " MAKE FILO $(NAME-y)" - $(MAKE) -C filo + $(MAKE) -C filo LIBCONFIG_PATH=../../../libpayload libpayload: checkout cd ../../libpayload && $(MAKE) defconfig && \

1 0

Patch set updated for coreboot: google/rikku: Upstream Acer Chromebox CXI2
by Matt DeVillier 23 May '16

23 May '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12802 -gerrit commit 1de1c9155987b43ba219be6e342fe61ee55a8a89 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Fri Dec 25 01:36:40 2015 -0600 google/rikku: Upstream Acer Chromebox CXI2 Migrate google/rikku (Acer Chromebox CXI2) from Chromium tree to upstream, using google/guado as a baseline. original source: branch firmware-rikku-6301.110.B commit 2e71207 [CHERRY-PICK: broadwell: Update to microcode 0x1F] TEST=built and booted Linux on rikku with full functionality blobs required for working image: VGA BIOS (vgabios.bin) firmware descriptor (ifd.bin) Intel ME firmware (me.bin) MRC (mrc.bin) external reference code (refcode.elf) Change-Id: Iba618a0b2cf2d613f6429b3e7606e0b47fa97a4d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/rikku/Kconfig | 68 +++++ src/mainboard/google/rikku/Kconfig.name | 2 + src/mainboard/google/rikku/Makefile.inc | 24 ++ src/mainboard/google/rikku/acpi/chromeos.asl | 19 ++ src/mainboard/google/rikku/acpi/ec.asl | 0 .../google/rikku/acpi/haswell_pci_irqs.asl | 83 +++++ src/mainboard/google/rikku/acpi/mainboard.asl | 69 +++++ src/mainboard/google/rikku/acpi/platform.asl | 71 +++++ src/mainboard/google/rikku/acpi/superio.asl | 32 ++ src/mainboard/google/rikku/acpi/thermal.asl | 340 +++++++++++++++++++++ src/mainboard/google/rikku/acpi/video.asl | 39 +++ src/mainboard/google/rikku/acpi_tables.c | 66 ++++ src/mainboard/google/rikku/board_info.txt | 7 + src/mainboard/google/rikku/chromeos.c | 95 ++++++ src/mainboard/google/rikku/chromeos.fmd | 38 +++ src/mainboard/google/rikku/cmos.layout | 135 ++++++++ src/mainboard/google/rikku/devicetree.cb | 122 ++++++++ src/mainboard/google/rikku/dsdt.asl | 57 ++++ src/mainboard/google/rikku/fadt.c | 154 ++++++++++ src/mainboard/google/rikku/gpio.h | 120 ++++++++ src/mainboard/google/rikku/hda_verb.c | 109 +++++++ src/mainboard/google/rikku/lan.c | 191 ++++++++++++ src/mainboard/google/rikku/mainboard.c | 54 ++++ src/mainboard/google/rikku/onboard.h | 42 +++ src/mainboard/google/rikku/pei_data.c | 59 ++++ src/mainboard/google/rikku/romstage.c | 63 ++++ src/mainboard/google/rikku/smihandler.c | 88 ++++++ src/mainboard/google/rikku/spd/Makefile.inc | 16 + src/mainboard/google/rikku/spd/spd.c | 37 +++ src/mainboard/google/rikku/spd/spd.h | 22 ++ src/mainboard/google/rikku/thermal.h | 55 ++++ 31 files changed, 2277 insertions(+) diff --git a/src/mainboard/google/rikku/Kconfig b/src/mainboard/google/rikku/Kconfig new file mode 100644 index 0000000..83a99bd --- /dev/null +++ b/src/mainboard/google/rikku/Kconfig @@ -0,0 +1,68 @@ +if BOARD_GOOGLE_RIKKU + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_INTEL_BROADWELL + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_ITE_IT8772F + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select MMCONF_SUPPORT + select HAVE_SMI_HANDLER + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM + +config CHROMEOS + select CHROMEOS_VBNV_CMOS + select CHROMEOS_RAMOOPS_DYNAMIC + select VIRTUAL_DEV_SWITCH + select PHYSICAL_REC_SWITCH + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config VBOOT_REFCODE_INDEX + hex + default 0x3 + +config MAINBOARD_DIR + string + default google/rikku + +config MAINBOARD_PART_NUMBER + string + default "Rikku" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_FAMILY + string + depends on GENERATE_SMBIOS_TABLES + default "Google_Rikku" + +config GBB_HWID + string + depends on CHROMEOS + default "RIKKU TEST A-A 0702" + +endif diff --git a/src/mainboard/google/rikku/Kconfig.name b/src/mainboard/google/rikku/Kconfig.name new file mode 100644 index 0000000..00552d0 --- /dev/null +++ b/src/mainboard/google/rikku/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_RIKKU + bool "Rikku" diff --git a/src/mainboard/google/rikku/Makefile.inc b/src/mainboard/google/rikku/Makefile.inc new file mode 100644 index 0000000..552aa06 --- /dev/null +++ b/src/mainboard/google/rikku/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += lan.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +romstage-y += pei_data.c +ramstage-y += pei_data.c diff --git a/src/mainboard/google/rikku/acpi/chromeos.asl b/src/mainboard/google/rikku/acpi/chromeos.asl new file mode 100644 index 0000000..bad5f47 --- /dev/null +++ b/src/mainboard/google/rikku/acpi/chromeos.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name(OIPG, Package() { + Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button + Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect +}) diff --git a/src/mainboard/google/rikku/acpi/ec.asl b/src/mainboard/google/rikku/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/rikku/acpi/haswell_pci_irqs.asl b/src/mainboard/google/rikku/acpi/haswell_pci_irqs.asl new file mode 100644 index 0000000..3244365 --- /dev/null +++ b/src/mainboard/google/rikku/acpi/haswell_pci_irqs.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for IvyBridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // Mini-HD Audio 0:3.0 + Package() { 0x0003ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 18 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 22 }, + Package() { 0x001fffff, 1, 0, 18 }, + Package() { 0x001fffff, 2, 0, 17 }, + Package() { 0x001fffff, 3, 0, 16 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, 0, 20 }, + Package() { 0x0015ffff, 1, 0, 21 }, + Package() { 0x0015ffff, 2, 0, 21 }, + Package() { 0x0015ffff, 3, 0, 21 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, 0, 23 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Mini-HD Audio 0:3.0 + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + }) + } +} + diff --git a/src/mainboard/google/rikku/acpi/mainboard.asl b/src/mainboard/google/rikku/acpi/mainboard.asl new file mode 100644 index 0000000..fefb7a6 --- /dev/null +++ b/src/mainboard/google/rikku/acpi/mainboard.asl @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mainboard/google/rikku/onboard.h> + +Scope (\_SB) +{ + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } +} + +/* + * LAN connected to Root Port 3, becomes Root Port 1 after coalesce + */ +Scope (\_SB.PCI0.RP01) +{ + Device (ETH0) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package() { RIKKU_NIC_WAKE_GPIO, 3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (RIKKU_NIC_WAKE_GPIO, Local0) + + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) + } + } + } +} + +/* + * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce + */ +Scope (\_SB.PCI0.RP02) +{ + Device (WLAN) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package() { RIKKU_WLAN_WAKE_GPIO, 3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (RIKKU_WLAN_WAKE_GPIO, Local0) + + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) + } + } + } +} diff --git a/src/mainboard/google/rikku/acpi/platform.asl b/src/mainboard/google/rikku/acpi/platform.asl new file mode 100644 index 0000000..7ff90a8 --- /dev/null +++ b/src/mainboard/google/rikku/acpi/platform.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Initialize thermal defaults */ + \_TZ.THRM._INI () + + Return(Package(){0,0}) +} diff --git a/src/mainboard/google/rikku/acpi/superio.asl b/src/mainboard/google/rikku/acpi/superio.asl new file mode 100644 index 0000000..a65b3f5 --- /dev/null +++ b/src/mainboard/google/rikku/acpi/superio.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Values should match those defined in devicetree.cb */ + +#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller +#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR + +#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard +#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse +#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 +#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller +#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 +#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 +#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO +#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 + +#include "superio/ite/it8772f/acpi/superio.asl" + diff --git a/src/mainboard/google/rikku/acpi/thermal.asl b/src/mainboard/google/rikku/acpi/thermal.asl new file mode 100644 index 0000000..48c49dd --- /dev/null +++ b/src/mainboard/google/rikku/acpi/thermal.asl @@ -0,0 +1,340 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../thermal.h" + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + // Start fan at state 4 = lowest temp state + Method (_INI) + { + Store (4, \FLVL) + Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + + Method (TCHK, 0, Serialized) + { + // Get CPU Temperature from PECI via SuperIO TMPIN3 + Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + + // Check for "no reading available + If (LEqual (Local0, 0x80)) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // PECI raw value is an offset from Tj_max + Subtract (255, Local0, Local1) + + // Handle values greater than Tj_max + If (LGreaterEqual (Local1, \TMAX)) { + Return (CTOK (\TMAX)) + } + + // Subtract from Tj_max to get temperature + Subtract (\TMAX, Local1, Local0) + Return (CTOK (Local0)) + } + + Method (_TMP, 0, Serialized) + { + // Get temperature from SuperIO in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TMAX), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for SuperIO to re-poll + Sleep (1000) + + // Re-read temperature from SuperIO + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (FAN0_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (FAN1_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN1_THRESHOLD_ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (FAN2_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN2_THRESHOLD_ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (FAN3_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN3_THRESHOLD_ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (FAN4_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN4_THRESHOLD_ON)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (0, \FLVL) + Store (FAN0_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} + diff --git a/src/mainboard/google/rikku/acpi/video.asl b/src/mainboard/google/rikku/acpi/video.asl new file mode 100644 index 0000000..1405b04 --- /dev/null +++ b/src/mainboard/google/rikku/acpi/video.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/google/rikku/acpi_tables.c b/src/mainboard/google/rikku/acpi_tables.c new file mode 100644 index 0000000..0af2697 --- /dev/null +++ b/src/mainboard/google/rikku/acpi_tables.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <soc/acpi.h> +#include <soc/nvs.h> +#include "thermal.h" + + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tmps = TEMPERATURE_SENSOR_ID; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; + gnvs->flvl = 1; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} diff --git a/src/mainboard/google/rikku/board_info.txt b/src/mainboard/google/rikku/board_info.txt new file mode 100644 index 0000000..f705964 --- /dev/null +++ b/src/mainboard/google/rikku/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Acer +Board name: Chromebox CXI2 +Category: half +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/rikku/chromeos.c b/src/mainboard/google/rikku/chromeos.c new file mode 100644 index 0000000..d440968 --- /dev/null +++ b/src/mainboard/google/rikku/chromeos.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> +#include <soc/sata.h> + +#define GPIO_SPI_WP 58 +#define GPIO_REC_MODE 12 + +#define FLAG_SPI_WP 0 +#define FLAG_REC_MODE 1 +#define FLAG_DEV_MODE 2 + +#ifndef __PRE_RAM__ +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"}, + {GPIO_REC_MODE, ACTIVE_LOW, + get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, 1, "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} +#endif + +int get_write_protect_state(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 2); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); +#endif + return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 2); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); +#endif + return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; +} + +#ifdef __PRE_RAM__ +void save_chromeos_gpios(void) +{ + u32 flags = 0; + + /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ + if (get_gpio(GPIO_SPI_WP)) + flags |= (1 << FLAG_SPI_WP); + + /* Recovery: GPIO12 = RECOVERY_L, active low */ + if (!get_gpio(GPIO_REC_MODE)) + flags |= (1 << FLAG_REC_MODE); + + /* Developer: Virtual */ + + pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); +} +#endif diff --git a/src/mainboard/google/rikku/chromeos.fmd b/src/mainboard/google/rikku/chromeos.fmd new file mode 100644 index 0000000..113fba6 --- /dev/null +++ b/src/mainboard/google/rikku/chromeos.fmd @@ -0,0 +1,38 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0x600000 { + RW_SECTION_A@0x0 0xf0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0xdffc0 + RW_FWID_A@0xeffc0 0x40 + } + RW_SECTION_B@0xf0000 0xf0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0xdffc0 + RW_FWID_B@0xeffc0 0x40 + } + RW_MRC_CACHE@0x1e0000 0x10000 + RW_ELOG@0x1f0000 0x4000 + RW_SHARED@0x1f4000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x1f8000 0x2000 + RW_UNUSED@0x1fa000 0x6000 + RW_LEGACY(CBFS)@0x200000 0x200000 + WP_RO@0x400000 0x200000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x1f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x100000 + } + } + } +} diff --git a/src/mainboard/google/rikku/cmos.layout b/src/mainboard/google/rikku/cmos.layout new file mode 100644 index 0000000..f862cd6 --- /dev/null +++ b/src/mainboard/google/rikku/cmos.layout @@ -0,0 +1,135 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/google/rikku/devicetree.cb b/src/mainboard/google/rikku/devicetree.cb new file mode 100644 index 0000000..4d16ed6 --- /dev/null +++ b/src/mainboard/google/rikku/devicetree.cb @@ -0,0 +1,122 @@ +chip soc/intel/broadwell + + # Disable eDP Hotplug + register "gpu_dp_d_hotplug" = "0x00" + + # Enable DisplayPort C Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + + # Enable HDMI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + + + + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # SuperIO range is 0x700-0x73f + register "gen2_dec" = "0x003c0701" + + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000000" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sata_devslp_disable" = "0x1" + + register "sio_acpi_mode" = "0" + register "sio_i2c0_voltage" = "0" # 3.3V + register "sio_i2c1_voltage" = "0" # 3.3V + + # Force enable ASPM for PCIe Port 4 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip superio/ite/it8772f + # Skip keyboard init + register "skip_keyboard" = "1" + # Enable PECI on TMPIN3 + register "peci_tmpin" = "3" + # Enable FAN2 + register "fan2_enable" = "1" + + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x700 + io 0x62 = 0x710 + irq 0x70 = 0x09 + irq 0xf2 = 0x20 + irq 0xf4 = 0x0 + irq 0xfa = 0x12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x720 + io 0x62 = 0x730 + end + device pnp 2e.5 off + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end # Keyboard + device pnp 2e.6 off + irq 0x70 = 12 + end # Mouse + device pnp 2e.a off end # IR + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end +end diff --git a/src/mainboard/google/rikku/dsdt.asl b/src/mainboard/google/rikku/dsdt.asl new file mode 100644 index 0000000..663b3c5 --- /dev/null +++ b/src/mainboard/google/rikku/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/broadwell/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // CPU + #include <soc/intel/broadwell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <soc/intel/broadwell/acpi/pch.asl> + } + } + + // Thermal handler + #include "acpi/thermal.asl" + + // Chrome OS specific + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + // Chipset specific sleep states + #include <soc/intel/broadwell/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/google/rikku/fadt.c b/src/mainboard/google/rikku/fadt.c new file mode 100644 index 0000000..ace819d --- /dev/null +++ b/src/mainboard/google/rikku/fadt.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <device/pci.h> +#include <soc/acpi.h> +#include <cpu/x86/smm.h> +#include <soc/pch.h> +#include <soc/iomap.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = ACPI_BASE_ADDRESS; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x80; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 32; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 0; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/google/rikku/gpio.h b/src/mainboard/google/rikku/gpio.h new file mode 100644 index 0000000..f58ad24 --- /dev/null +++ b/src/mainboard/google/rikku/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef RIKKU_GPIO_H +#define RIKKU_GPIO_H + +#include <soc/gpio.h> + +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_UNUSED, /* 0: UNUSED */ + PCH_GPIO_UNUSED, /* 1: UNUSED */ + PCH_GPIO_UNUSED, /* 2: UNUSED */ + PCH_GPIO_UNUSED, /* 3: UNUSED */ + PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ + PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ + PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + PCH_GPIO_UNUSED, /* 11: SMBALERT */ + PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ + PCH_GPIO_UNUSED, /* 13: UNUSED */ + PCH_GPIO_UNUSED, /* 14: UNUSED */ + PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 16: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ + PCH_GPIO_UNUSED, /* 19: UNUSED */ + PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ + PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ + PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ + PCH_GPIO_UNUSED, /* 23: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ + PCH_GPIO_UNUSED, /* 25: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ + PCH_GPIO_UNUSED, /* 27: UNUSED */ + PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ + PCH_GPIO_UNUSED, /* 29: UNUSED */ + PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ + PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ + PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ + PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + PCH_GPIO_UNUSED, /* 37: UNUSED */ + PCH_GPIO_UNUSED, /* 38: UNUSED */ + PCH_GPIO_UNUSED, /* 39: UNUSED */ + PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ + PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ + PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ + PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ + PCH_GPIO_UNUSED, /* 48: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 49: POWER_LED */ + PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ + PCH_GPIO_UNUSED, /* 51: UNUSED */ + PCH_GPIO_UNUSED, /* 52: UNUSED */ + PCH_GPIO_UNUSED, /* 53: UNUSED */ + PCH_GPIO_UNUSED, /* 54: UNUSED */ + PCH_GPIO_UNUSED, /* 55: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ + PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ + PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ + PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ + PCH_GPIO_UNUSED, /* 61: UNUSED */ + PCH_GPIO_UNUSED, /* 62: UNUSED */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + PCH_GPIO_UNUSED, /* 64: UNUSED */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 67: UNUSED */ + PCH_GPIO_UNUSED, /* 68: UNUSED */ + PCH_GPIO_UNUSED, /* 69: UNUSED */ + PCH_GPIO_UNUSED, /* 70: UNUSED */ + PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + PCH_GPIO_UNUSED, /* 72: UNUSED */ + PCH_GPIO_UNUSED, /* 73: UNUSED */ + PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + PCH_GPIO_UNUSED, /* 76: UNUSED */ + PCH_GPIO_UNUSED, /* 77: UNUSED */ + PCH_GPIO_UNUSED, /* 78: UNUSED */ + PCH_GPIO_UNUSED, /* 79: UNUSED */ + PCH_GPIO_UNUSED, /* 80: UNUSED */ + PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + PCH_GPIO_UNUSED, /* 83: UNUSED */ + PCH_GPIO_UNUSED, /* 84: UNUSED */ + PCH_GPIO_UNUSED, /* 85: UNUSED */ + PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 87: UNUSED */ + PCH_GPIO_UNUSED, /* 88: UNUSED */ + PCH_GPIO_UNUSED, /* 89: UNUSED */ + PCH_GPIO_UNUSED, /* 90: UNUSED */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ + PCH_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/rikku/hda_verb.c b/src/mainboard/google/rikku/hda_verb.c new file mode 100644 index 0000000..284015d --- /dev/null +++ b/src/mainboard/google/rikku/hda_verb.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 + 0x10ec0283, // Subsystem ID + 0x0000000c, // Number of jacks (NID entries) + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ + 0x00172083, + 0x00172102, + 0x001722ec, + 0x00172310, + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) DMIC */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + + /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ + 0x01471cf0, + 0x01471d11, + 0x01471e11, + 0x01471f40, + + /* Pin Complex (NID 0x17) */ + 0x01771cf0, + 0x01771d11, + 0x01771e11, + 0x01771f41, + + /* Pin Complex (NID 0x18) MIC1 PORTB */ + 0x01971c11, // group 1, cap 1 + 0x01971d10, // black, jack detect + 0x01971ea7, // mic in, analog + 0x01971f03, // connector, left panel + + /* Pin Complex (NID 0x19) MIC2 PORTF */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, + + /* Pin Complex (NID 0x1A) LINE1 PORTC */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, + + /* Pin Complex (NID 0x1B) LINE2 PORTE */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, + + /* Pin Complex (NID 0x1d) PCBeep */ + 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable + 0x01d71d81, // mute spkr on hpout + 0x01d71e15, // pcbeep en able, checksum + 0x01d71f40, // no physical, internal + + /* Pin Complex (NID 0x1E) SPDIF-OUT */ + 0x01e71cf0, + 0x01e71d11, + 0x01e71e11, + 0x01e71f41, + + /* Pin Complex (NID 0x21) HPOUT PORT-I */ + 0x02171c1f, // group1, + 0x02171d10, // black, jack detect + 0x02171e21, // HPOut, 1/8 stereo + 0x02171f03, // connector, left panel + + /* Undocumented settings from Realtek (needed for beep_gen) */ + /* Widget node 0x20 */ + 0x02050010, + 0x02040c20, + 0x0205001b, + 0x0204081b, +}; + +const u32 pc_beep_verbs[] = { + 0x00170500, /* power up everything (codec, dac, adc, mixers) */ + 0x01470740, /* enable speaker out */ + 0x01470c02, /* set speaker EAPD pin */ + 0x0143b01f, /* unmute speaker */ + 0x00c37100, /* unmute mixer nid 0xc input 1 */ + 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/rikku/lan.c b/src/mainboard/google/rikku/lan.c new file mode 100644 index 0000000..e5676af --- /dev/null +++ b/src/mainboard/google/rikku/lan.c @@ -0,0 +1,191 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <string.h> +#include <types.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <fmap.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include "onboard.h" + +static unsigned int search(char *p, u8 *a, unsigned int lengthp, + unsigned int lengtha) +{ + int i, j; + + /* Searching */ + for (j = 0; j <= lengtha - lengthp; j++) { + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + if (i >= lengthp) + return j; + } + return lengtha; +} + +static unsigned char get_hex_digit(u8 *offset) +{ + unsigned char retval = 0; + + retval = *offset - '0'; + if (retval > 0x09) { + retval = *offset - 'A' + 0x0A; + if (retval > 0x0F) + retval = *offset - 'a' + 0x0a; + } + if (retval > 0x0F) { + printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", + *offset, *offset); + retval = 0; + } + + return retval; +} + +static int get_mac_address(u32 *high_dword, u32 *low_dword, + u8 *search_address, u32 search_length) +{ + char key[] = "ethernet_mac"; + unsigned int offset; + int i; + + offset = search(key, search_address, sizeof(key) - 1, search_length); + if (offset == search_length) { + printk(BIOS_DEBUG, + "Error: Could not locate '%s' in VPD\n", key); + return 0; + } + printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); + + offset += sizeof(key); /* move to next character */ + *high_dword = 0; + + /* Fetch the MAC address and put the octets in the correct order to + * be programmed. + * + * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 + * If the MAC address is 001122334455h: + * Write 33221100h to I/O register offset 0x00 via double word access + * Write 00005544h to I/O register offset 0x04 via double word access + */ + + for (i = 0; i < 4; i++) { + *high_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *high_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + *low_dword = 0; + for (i = 0; i < 2; i++) { + *low_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *low_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + return *high_dword | *low_dword; +} + +static void program_mac_address(u16 io_base) +{ + void *search_address = NULL; + size_t search_length = -1; + + /* Default MAC Address of A0:00:BA:D0:0B:AD */ + u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ + u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ + + if (IS_ENABLED(CONFIG_CHROMEOS)) { + struct region_device rdev; + + if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { + search_address = rdev_mmap_full(&rdev); + + if (search_address != NULL) + search_length = region_device_sz(&rdev); + } + } else { + search_address = cbfs_boot_map_with_leak("vpd.bin", + CBFS_TYPE_RAW, + &search_length); + } + + if (search_address == NULL) + printk(BIOS_ERR, "LAN: VPD not found.\n"); + else + get_mac_address(&high_dword, &low_dword, search_address, + search_length); + + if (io_base) { + printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); + printk(BIOS_DEBUG, "Programming MAC Address\n"); + + /* Disable register protection */ + outb(0xc0, io_base + 0x50); + outl(high_dword, io_base); + outl(low_dword, io_base + 0x04); + outb(0x60, io_base + 54); + /* Enable register protection again */ + outb(0x00, io_base + 0x50); + } +} + +void lan_init(void) +{ + u16 io_base = 0; + struct device *ethernet_dev = NULL; + + /* Get NIC's IO base address */ + ethernet_dev = dev_find_device(RIKKU_NIC_VENDOR_ID, + RIKKU_NIC_DEVICE_ID, 0); + if (ethernet_dev != NULL) { + io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; + + /* + * Battery life time - LAN PCIe should enter ASPM L1 to save + * power when LAN connection is idle. + * enable CLKREQ: LAN pci config space 0x81h=01 + */ + pci_write_config8(ethernet_dev, 0x81, 0x01); + } + + if (io_base) { + /* Program MAC address based on VPD data */ + program_mac_address(io_base); + + /* + * Program NIC LEDS + * + * RTL8105E Series EEPROM-Less Application Note, + * Section 5.6 LED Mode Configuration + * + * Step1: Write C0h to I/O register 0x50 via byte access to + * disable 'register protection' + * Step2: Write xx001111b to I/O register 0x52 via byte access + * (bit7 is LEDS1 and bit6 is LEDS0) + * Step3: Write 0x00 to I/O register 0x50 via byte access to + * enable 'register protection' + */ + outb(0xc0, io_base + 0x50); /* Disable protection */ + outb((RIKKU_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); + outb(0x00, io_base + 0x50); /* Enable register protection */ + } +} diff --git a/src/mainboard/google/rikku/mainboard.c b/src/mainboard/google/rikku/mainboard.c new file mode 100644 index 0000000..5bb8fab --- /dev/null +++ b/src/mainboard/google/rikku/mainboard.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <smbios.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include "onboard.h" + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +static void mainboard_init(device_t dev) +{ + lan_init(); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/google/rikku/onboard.h b/src/mainboard/google/rikku/onboard.h new file mode 100644 index 0000000..2711162 --- /dev/null +++ b/src/mainboard/google/rikku/onboard.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#ifndef __ACPI__ +void lan_init(void); +#endif + +/* defines for programming the MAC address */ +#define RIKKU_NIC_VENDOR_ID 0x10EC +#define RIKKU_NIC_DEVICE_ID 0x8168 + +/* 0x00: White LINK LED and Amber ACTIVE LED */ +#define RIKKU_NIC_LED_MODE 0x00 + +/* NIC wake is GPIO 8 */ +#define RIKKU_NIC_WAKE_GPIO 8 + +/* WLAN wake is GPIO 10 */ +#define RIKKU_WLAN_WAKE_GPIO 10 + +/* IT8772F defs */ +#define IT8772F_BASE 0x2e +#define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) +#define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) +#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0) + +#endif diff --git a/src/mainboard/google/rikku/pei_data.c b/src/mainboard/google/rikku/pei_data.c new file mode 100644 index 0000000..4eeabbe --- /dev/null +++ b/src/mainboard/google/rikku/pei_data.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 0; + + /* P0: VP8 */ + pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, + USB_PORT_MINI_PCIE); + /* P1: Port A, CN22 */ + pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, + USB_PORT_INTERNAL); + /* P2: Port B, CN23 */ + pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, + USB_PORT_INTERNAL); + /* P3: WLAN */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + /* P4: Port C, CN25 */ + pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P5: Port D, CN25 */ + pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P6: Card Reader */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P7: EMPTY */ + pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, + USB_PORT_SKIP); + + /* P1: CN22 */ + pei_data_usb3_port(pei_data, 0, 1, 0, 0); + /* P2: CN23 */ + pei_data_usb3_port(pei_data, 1, 1, 1, 0); + /* P3: CN25 */ + pei_data_usb3_port(pei_data, 2, 1, 2, 0); + /* P4: CN25 */ + pei_data_usb3_port(pei_data, 3, 1, 2, 0); +} diff --git a/src/mainboard/google/rikku/romstage.c b/src/mainboard/google/rikku/romstage.c new file mode 100644 index 0000000..5f06ed9 --- /dev/null +++ b/src/mainboard/google/rikku/romstage.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/romstage.h> +#include <mainboard/google/rikku/spd/spd.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8772f/it8772f.h> +#include "gpio.h" +#include "onboard.h" + +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data pei_data; + + post_code(0x32); + + /* Initialize GPIOs */ + init_gpios(mainboard_gpio_config); + + /* Fill out PEI DATA */ + memset(&pei_data, 0, sizeof(pei_data)); + mainboard_fill_pei_data(&pei_data); + mainboard_fill_spd_data(&pei_data); + rp->pei_data = &pei_data; + + /* Call into the real romstage main with this board's attributes. */ + romstage_common(rp); +} + +void mainboard_pre_console_init(void) +{ + /* Early SuperIO setup */ + ite_kill_watchdog(IT8772F_GPIO_DEV); + it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV); + ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Turn On GPIO10.LED */ + it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, + 0x01 /* output */, 0x01 /* 1=Simple IO function */, + SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + +} diff --git a/src/mainboard/google/rikku/smihandler.c b/src/mainboard/google/rikku/smihandler.c new file mode 100644 index 0000000..c0b8186 --- /dev/null +++ b/src/mainboard/google/rikku/smihandler.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <soc/pm.h> +#include <soc/smm.h> +#include <elog.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <soc/pm.h> +#include <soc/smm.h> +#include <superio/ite/it8772f/it8772f.h> +#include "onboard.h" + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + return 1; +} + +/* gpi_sts is GPIO 47:32 */ +void mainboard_smi_gpi(u32 gpi_sts) +{ +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: + it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, + 0x01 /* polarity */, 0x01 /* 1=pullup */, + 0x01 /* output */, 0x00, /* 0=Alternate function */ + SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + break; + case 5: + it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, + 0x01 /* output */, 0x01 /* 1=Simple IO function */, + SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + break; + default: + break; + } + return; +} + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + break; + case APM_CNT_ACPI_DISABLE: + break; + } + return 0; +} diff --git a/src/mainboard/google/rikku/spd/Makefile.inc b/src/mainboard/google/rikku/spd/Makefile.inc new file mode 100644 index 0000000..90f22d8 --- /dev/null +++ b/src/mainboard/google/rikku/spd/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd.c diff --git a/src/mainboard/google/rikku/spd/spd.c b/src/mainboard/google/rikku/spd/spd.c new file mode 100644 index 0000000..74879f2 --- /dev/null +++ b/src/mainboard/google/rikku/spd/spd.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/romstage.h> +#include <mainboard/google/rikku/spd/spd.h> + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *pei_data) +{ + pei_data->spd_addresses[0] = 0xa0; + pei_data->spd_addresses[1] = 0x00; + pei_data->spd_addresses[2] = 0xa4; + pei_data->spd_addresses[3] = 0x00; + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + // Enable 2x refresh mode + pei_data->ddr_refresh_2x = 1; + pei_data->dq_pins_interleaved = 1; +} diff --git a/src/mainboard/google/rikku/spd/spd.h b/src/mainboard/google/rikku/spd/spd.h new file mode 100644 index 0000000..e48d93f --- /dev/null +++ b/src/mainboard/google/rikku/spd/spd.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +struct pei_data; +void mainboard_fill_spd_data(struct pei_data *pei_data); + +#endif diff --git a/src/mainboard/google/rikku/thermal.h b/src/mainboard/google/rikku/thermal.h new file mode 100644 index 0000000..92e9b98 --- /dev/null +++ b/src/mainboard/google/rikku/thermal.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +#define TEMPERATURE_SENSOR_ID 0 /* PECI */ + +/* Fan is OFF */ +#define FAN4_THRESHOLD_OFF 0 +#define FAN4_THRESHOLD_ON 0 +#define FAN4_PWM 0x84 + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 42 +#define FAN3_THRESHOLD_ON 47 +#define FAN3_PWM 0xa5 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 54 +#define FAN2_THRESHOLD_ON 59 +#define FAN2_PWM 0xb2 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 66 +#define FAN1_THRESHOLD_ON 71 +#define FAN1_PWM 0xc9 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 78 +#define FAN0_THRESHOLD_ON 83 +#define FAN0_PWM 0xd8 + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif

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coreboot-gerrit May 2016