Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14959
-gerrit
commit adf071427f993ee36b59aa17e9e8ed7a95bc2eb8
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue May 24 14:50:45 2016 -0500
vendorcode/google/chromeos/vboot2: use cbmem for postcar region selection
When the vboot cbfs selection runs in postcar stage it should be
utilizing cbmem to locate the vboot selected region.
Change-Id: I027ba19438468bd690d74ae55007393f051fde42
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/vendorcode/google/chromeos/vboot2/common.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/vendorcode/google/chromeos/vboot2/common.c b/src/vendorcode/google/chromeos/vboot2/common.c
index 4282408..749f328 100644
--- a/src/vendorcode/google/chromeos/vboot2/common.c
+++ b/src/vendorcode/google/chromeos/vboot2/common.c
@@ -65,8 +65,8 @@ static struct selected_region *vb2_selected_region(void)
{
struct selected_region *sel_reg = NULL;
- /* Ramstage always uses cbmem as a source of truth. */
- if (ENV_RAMSTAGE)
+ /* Ramstage and postcar always uses cbmem as a source of truth. */
+ if (ENV_RAMSTAGE || ENV_POSTCAR)
sel_reg = cbmem_find(CBMEM_ID_VBOOT_SEL_REG);
else if (ENV_ROMSTAGE) {
/* Try cbmem first. Fall back on working data if not found. */
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14958
-gerrit
commit 4396882d5ff587c4b981ac3306d45a718e735a60
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue May 24 14:47:10 2016 -0500
console/post: be explicit about conditional cmos_post_log() compiling
The current code was using !__PRE_RAM__ as a proxy for ramstage
conditional compilation. In the face of postcar stage not defining
__PRE_RAM__ (because it's after RAM is up) these code paths
can fail to compile with a __SIMPLE_DEVICE__ defined for the entire
stage. Remedy the current situation by just compiling explicity for
ramstage because that was the original intent. In the future,
the __SIMPLE_DEVICE__ selection for postcar can also be re-evaluated.
Change-Id: I0f887f1e45f0cf5c235ae5144eaa227921e7119b
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/console/post.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/console/post.c b/src/console/post.c
index b43bd09..481a1f4 100644
--- a/src/console/post.c
+++ b/src/console/post.c
@@ -20,6 +20,7 @@
#include <device/device.h>
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
+#include <rules.h>
/* Write POST information */
@@ -41,7 +42,7 @@ void __attribute__((weak)) mainboard_post(uint8_t value)
DECLARE_SPIN_LOCK(cmos_post_lock)
-#if !defined(__PRE_RAM__)
+#if ENV_RAMSTAGE
void cmos_post_log(void)
{
u8 code = 0;
@@ -122,7 +123,7 @@ void post_log_clear(void)
post_log_extra(0);
}
#endif /* CONFIG_CMOS_POST_EXTRA */
-#endif /* !__PRE_RAM__ */
+#endif /* ENV_RAMSTAGE */
static void cmos_post_code(u8 value)
{
the following patch was just integrated into master:
commit 2c51572435e8d7bded99ff4c83fc392cdae47772
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri May 20 18:06:22 2016 -0700
arm64: Add stack dump to exception handler
Some exceptions (like from calling a NULL function pointer) are easier
to narrow down with a dump of the call stack. Let's take a page out of
ARM32's book and add that feature to ARM64 as well. Also change the
output format to two register columns, to make it easier to fit a whole
exception dump on one screen.
Applying to both coreboot and libpayload and syncing the output format
between both back up.
Change-Id: I19768d13d8fa8adb84f0edda2af12f20508eb2db
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/14931
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/14931 for details.
-gerrit
Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14929
-gerrit
commit f8568c2217713d95da9ff7d54ffd7c3e7ae7e683
Author: Bora Guvendik <bora.guvendik(a)intel.com>
Date: Tue May 17 15:54:27 2016 -0700
intel/amenia: Extend IFD size by 512 KB
Increase BIOS region size by 512KB since device extension size
is reduced from 1MB to 512KB
BUG=chrome-os-partner:52589
TEST=Build Coreboot and boots
CQ-DEPEND=CL:*259448,CL:345642,CL:*259445
Change-Id: Ib81b117a3afe730aafa54b4ef31b1e9ab1f67111
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com>
---
src/mainboard/intel/amenia/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig
index e83b151..ec76119 100644
--- a/src/mainboard/intel/amenia/Kconfig
+++ b/src/mainboard/intel/amenia/Kconfig
@@ -41,7 +41,7 @@ config PREBUILT_SPI_IMAGE
config IFD_BIOS_END
hex
- default 0x6FF000
+ default 0x77F000
config IFD_BIOS_START
hex
Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14929
-gerrit
commit a7f877502d4eb1cfe63d7735c6269c924cf90cb1
Author: Bora Guvendik <bora.guvendik(a)intel.com>
Date: Tue May 17 15:54:27 2016 -0700
intel/amenia: Extend IFD size by 512 KB
Increase BIOS region size by 512KB since device extension size
is reduced from 1MB to 512KB
BUG=chrome-os-partner:52589
TEST=Build Coreboot and boots
CQ-DEPEND=CL:*259448,CL:345642,CL:*259445
Change-Id: Ib81b117a3afe730aafa54b4ef31b1e9ab1f67111
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com>
---
src/mainboard/intel/amenia/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig
index e83b151..ec76119 100644
--- a/src/mainboard/intel/amenia/Kconfig
+++ b/src/mainboard/intel/amenia/Kconfig
@@ -41,7 +41,7 @@ config PREBUILT_SPI_IMAGE
config IFD_BIOS_END
hex
- default 0x6FF000
+ default 0x77F000
config IFD_BIOS_START
hex
the following patch was just integrated into master:
commit c123ccfa127b58a20ad3efa800c0e73f307f0ac5
Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com>
Date: Thu May 19 19:32:13 2016 -0700
intel/amenia: Configure Trackpad IC_SDA_HOLD time
Elan trackpad needs greater sda hold time.
Configure IC_SDA_HOLD register to increase
the i2c sda hold time by 0.3us.
Change-Id: I3d966eed62a059ecb6a0a88e9f4e6b4ba7a925e4
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com>
Reviewed-on: https://review.coreboot.org/14922
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/14922 for details.
-gerrit