coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: sio/winbond/common: Add function to configure pin mux
by Timothy Pearson 25 May '16

25 May '16

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14960 -gerrit commit 6a75a4a07428530b59db80992dbaac1a19763e2a Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Tue May 24 15:48:50 2016 -0500 sio/winbond/common: Add function to configure pin mux Certain mainboards require SuperIO pinmux configuration before peripherals will become operational. Allow each mainboard to configure the pinmux(es) of Winbond chips if needed. Change-Id: Ice19f8d8514b66b15920a5b893700d636ed75cec Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/superio/winbond/common/early_serial.c | 13 +++++++++++++ src/superio/winbond/common/winbond.h | 9 ++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_serial.c index 6482a94..aebbd38 100644 --- a/src/superio/winbond/common/early_serial.c +++ b/src/superio/winbond/common/early_serial.c @@ -66,3 +66,16 @@ void winbond_enable_serial(pnp_devfn_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); } + +void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state) +{ + uint8_t byte; + + /* Configure pin mux */ + pnp_enter_conf_state(dev); + byte = pnp_read_config(dev, offset); + byte &= ~mask; + byte |= state; + pnp_write_config(dev, offset, byte); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h index 1f7e7b1..48dd120 100644 --- a/src/superio/winbond/common/winbond.h +++ b/src/superio/winbond/common/winbond.h @@ -20,7 +20,14 @@ #include <arch/io.h> #include <stdint.h> -void winbond_enable_serial(pnp_devfn_t dev, u16 iobase); +#define W83667HG_SPI_PINMUX_OFFSET 0x2a + +#define W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK (1 << 2) +#define W83667HG_SPI_PINMUX_GPIO4 (0 << 2) +#define W83667HG_SPI_PINMUX_SERIAL_B (1 << 2) + +void winbond_enable_serial(pnp_devfn_t dev, uint16_t iobase); +void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state); void pnp_enter_conf_state(pnp_devfn_t dev); void pnp_exit_conf_state(pnp_devfn_t dev);

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Patch set updated for coreboot: soc/intel/apollolake: enable RTC
by Jagadish Krishnamoorthy 25 May '16

25 May '16

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Patch set updated for coreboot: soc/intel/apollolake: enable RTC
by Jagadish Krishnamoorthy 25 May '16

25 May '16

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Patch set updated for coreboot: soc/intel/apollolake: enable RTC
by Jagadish Krishnamoorthy 25 May '16

25 May '16

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Patch set updated for coreboot: soc/intel/apollolake: enable RTC
by Jagadish Krishnamoorthy 25 May '16

25 May '16

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Patch set updated for coreboot: soc/intel/apollolake: Provide No Connect macro for unused Pad
by Jagadish Krishnamoorthy 25 May '16

25 May '16

Jagadish Krishnamoorthy (jagadish.krishnamoorthy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14956 -gerrit commit c07464a91548c15a7f4af741d7c9fdb91387b267 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Fri May 20 19:28:59 2016 -0700 soc/intel/apollolake: Provide No Connect macro for unused Pad Change-Id: Iba506054a3d631c8e538d44e1ca6877dd02c2ca9 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> --- src/soc/intel/apollolake/include/soc/gpio.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 4d9973c..3b6ca0a 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -54,6 +54,14 @@ typedef uint32_t gpio_t; PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull)) +/* No Connect configuration for unused pad. + * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term + */ +#define PAD_NC(pad, pull) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull)) + /* General purpose input, routed to APIC */ #define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \

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Patch set updated for coreboot: WIP: intel/amenia: Add changes for image assembly
by Bora Guvendik 25 May '16

25 May '16

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14897 -gerrit commit 75761510bb67046837d73346675817ff84bbf03f Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Wed May 18 14:56:27 2016 -0700 WIP: intel/amenia: Add changes for image assembly Insert bootblock Use different base images for different variants Use generated fmd files for different variants BUG=chrome-os-partner:51844 BRANCH=none TEST=boots to chrome OS Change-Id: I0e92858486ecf4720b8bcdf64bae97d9476caabc Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 17 +++++++++++++++-- src/soc/intel/apollolake/Makefile.inc | 5 +++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index e83b151..ee892b5 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -35,9 +35,22 @@ config FMAP_FILE string default "amenia" -config PREBUILT_SPI_IMAGE +config HAVE_IFD_BIN + default y + +config APOLLOLAKE_A0 + bool + default y + +config IFD_BIN_PATH + string "Path and filename of the descriptor.bin file" + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/reef.bin.orig.a0" if APOLLOLAKE_A0 + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/reef.bin.orig.b0" if !APOLLOLAKE_A0 + +config FMDFILE string - default "amenia.bin.orig.a0" + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/reef.bin.orig.a0.fmd" if APOLLOLAKE_A0 + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/reef.bin.orig.b0.fmd" if !APOLLOLAKE_A0 config IFD_BIOS_END hex diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 607ad13..909226b 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -68,4 +68,9 @@ files_added:: $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward endif +build_complete:: + $(CBFSTOOL) $(obj)/coreboot.rom write \ + -r bootblock \ + -f $(objcbfs)/bootblock.bin + endif

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Patch set updated for coreboot: WIP: intel/amenia: Add changes for image assembly
by Bora Guvendik 25 May '16

25 May '16

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14897 -gerrit commit ce5f53876a5741fc01e8554cc9829ec5a1c8d3e2 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Wed May 18 14:56:27 2016 -0700 WIP: intel/amenia: Add changes for image assembly Insert bootblock Build base images for different variants Generate fmd files for different variants BUG=chrome-os-partner:51844 BRANCH=none TEST=boots to chrome OS Change-Id: I0e92858486ecf4720b8bcdf64bae97d9476caabc Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 17 +++++++++++++++-- src/soc/intel/apollolake/Makefile.inc | 5 +++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index e83b151..ee892b5 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -35,9 +35,22 @@ config FMAP_FILE string default "amenia" -config PREBUILT_SPI_IMAGE +config HAVE_IFD_BIN + default y + +config APOLLOLAKE_A0 + bool + default y + +config IFD_BIN_PATH + string "Path and filename of the descriptor.bin file" + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/reef.bin.orig.a0" if APOLLOLAKE_A0 + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/reef.bin.orig.b0" if !APOLLOLAKE_A0 + +config FMDFILE string - default "amenia.bin.orig.a0" + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/reef.bin.orig.a0.fmd" if APOLLOLAKE_A0 + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/reef.bin.orig.b0.fmd" if !APOLLOLAKE_A0 config IFD_BIOS_END hex diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 607ad13..909226b 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -68,4 +68,9 @@ files_added:: $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward endif +build_complete:: + $(CBFSTOOL) $(obj)/coreboot.rom write \ + -r bootblock \ + -f $(objcbfs)/bootblock.bin + endif

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Patch set updated for coreboot: soc/intel/apollolake: enable RTC
by Jagadish Krishnamoorthy 25 May '16

25 May '16

Jagadish Krishnamoorthy (jagadish.krishnamoorthy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14883 -gerrit commit 55bf1c3c59507278a3c45a026985d141f2d29242 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Tue May 17 18:06:49 2016 -0700 soc/intel/apollolake: enable RTC BUG=none TEST=Boot to OS and verfiy if rtc0 device is created under /sys/class/rtc/ Change-Id: Idec569255859816fda467bb42a215c00f7c0e16e Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> --- src/soc/intel/apollolake/include/soc/pm.h | 1 + src/soc/intel/apollolake/lpc.c | 27 +++++++++++++++++++++++++++ src/soc/intel/apollolake/pmutil.c | 6 ++++++ 3 files changed, 34 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 6b12886..b33159a 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -144,5 +144,6 @@ void disable_pm1_control(uint32_t mask); void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); +uint32_t get_pmcon1_reg(void); #endif diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 48dfb1f..896ff6a 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -15,13 +15,17 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> #include <soc/acpi.h> #include <soc/lpc.h> #include <soc/pci_ids.h> +#include <soc/pm.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" @@ -43,6 +47,26 @@ * opens up IO and memory windows as needed. */ +static void rtc_init(void) +{ + uint32_t gen_pmcon1; + int rtc_fail; + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps != NULL) + gen_pmcon1 = ps->gen_pmcon1; + else + gen_pmcon1 = get_pmcon1_reg(); + + rtc_fail = !!(gen_pmcon1 & RPS); + /* Ensure the date is set including century byte. */ + cmos_check_update_date(); + if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)) + init_vbnv_cmos(rtc_fail); + else + cmos_init(rtc_fail); +} + static void lpc_init(struct device *dev) { uint8_t scnt; @@ -61,6 +85,9 @@ static void lpc_init(struct device *dev) else if (cfg->serirq_mode == SERIRQ_CONTINUOUS) scnt |= SCNT_EN | SCNT_MODE; pci_write_config8(dev, REG_SERIRQ_CTL, scnt); + + /* Initialize RTC */ + rtc_init(); } static void soc_lpc_add_io_resources(device_t dev) diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 16c8a04..9b19b5e 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -265,6 +265,12 @@ uint32_t clear_gpe_status(void) return print_gpe_sts(reset_gpe_status()); } +uint32_t get_pmcon1_reg(void) +{ + uintptr_t pmc_bar0 = read_pmc_mmio_bar(); + return read32((void *)(pmc_bar0 + GEN_PMCON1)); +} + void clear_pmc_status(void) { uint32_t prsts;

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Patch set updated for coreboot: ifwitool: Support subpart add operation for bootblock
by Furquan Shaikh 25 May '16

25 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14957 -gerrit commit ee042a8ab949624ba22b2bd91033b5ecd1efc455 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue May 24 11:45:27 2016 -0700 ifwitool: Support subpart add operation for bootblock Change-Id: Iee86d6291c71958e4d8e68afaa984a05010dcaaf Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- util/cbfstool/ifwitool.c | 247 +++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 219 insertions(+), 28 deletions(-) diff --git a/util/cbfstool/ifwitool.c b/util/cbfstool/ifwitool.c index b3893aa..428eddb 100644 --- a/util/cbfstool/ifwitool.c +++ b/util/cbfstool/ifwitool.c @@ -16,6 +16,7 @@ #include <commonlib/endian.h> #include <getopt.h> #include <stdlib.h> +#include <time.h> #include "common.h" @@ -85,11 +86,67 @@ struct subpart { #define SUBPART_SIZE(c) (SUBPART_HEADER_SIZE + (c) * \ SUBPART_ENTRY_SIZE) +struct manifest_header { + uint32_t header_type; + uint32_t header_length; + uint32_t header_version; + uint32_t flags; + uint32_t vendor; + uint32_t date; + uint32_t size; + uint32_t id; + uint32_t rsvd; + uint64_t version; + uint32_t svn; + uint64_t rsvd1; + uint8_t rsvd2[64]; + uint32_t modulus_size; + uint32_t exponent_size; + uint8_t public_key[256]; + uint32_t exponent; + uint8_t signature[256]; +} __attribute__((packed)); + +#define DWORD_SIZE 4 +#define MANIFEST_HDR_SIZE (sizeof(struct manifest_header)) +#define MANIFEST_ID_MAGIC (0x324e4d24) + +struct module { + uint8_t name[12]; + uint8_t type; + uint8_t hash_alg; + uint16_t hash_size; + uint32_t metadata_size; + uint8_t metadata_hash[32]; +} __attribute__((packed)); + +#define MODULE_SIZE (sizeof(struct module)) + +struct signed_pkg_info_ext { + uint32_t ext_type; + uint32_t ext_length; + uint8_t name[4]; + uint32_t vcn; + uint8_t bitmap[16]; + uint32_t svn; + uint8_t rsvd[16]; +} __attribute__((packed)); + +#define SIGNED_PKG_INFO_EXT_TYPE 0x15 +#define SIGNED_PKG_INFO_EXT_SIZE \ + (sizeof(struct signed_pkg_info_ext)) + +#define MANIFEST_SIZE(c) (MANIFEST_HDR_SIZE + \ + SIGNED_PKG_INFO_EXT_SIZE + \ + MODULE_SIZE * c) + +#define EXT_SIZE(c) (SIGNED_PKG_INFO_EXT_SIZE + \ + MODULE_SIZE * c) /* * Attributes for various IFWI components. * LIES_WITHIN_BPDT_4K = Component should lie within the same 4K block as BPDT. * NON_CRITICAL_COMP = Component entry should be present in S-BPDT. - * CONTAINS_SUBPART = Component might require subpart operation (TODO(furquan)) + * CONTAINS_SUBPART = Component might require subpart operation * AUTO_GENERATED = Component is generated by the tool. * MANDATORY_BPDT_ENTRY = Even if component is deleted, BPDT should contain an * entry for it with size 0 and offset 0. @@ -191,6 +248,8 @@ struct cbp_ops { enum ifwi_ret (*cbp_add)(int); }; +static enum ifwi_ret ibb_cbp_add(int); + struct bpdt_comp { const char *name; uint32_t attr; @@ -208,7 +267,7 @@ struct bpdt_comp { /* uCode */ [UCODE_TYPE] = {"uCODE", CONTAINS_SUBPART, "UCOD", {NULL}}, /* IBB */ - [IBB_TYPE] = {"bootblock", CONTAINS_SUBPART, "IBBP", {NULL}}, + [IBB_TYPE] = {"bootblock", CONTAINS_SUBPART, "IBBP", {ibb_cbp_add}}, /* S-BPDT */ [S_BPDT_TYPE] = {"S_BPDT", AUTO_GENERATED | MANDATORY_BPDT_ENTRY, NULL, {NULL}}, @@ -1112,6 +1171,164 @@ static void ifwi_repack(void) ifwi_write(param.image_name); } +static void init_subpart_header(struct subpart_header *hdr, size_t count, + const char *name) +{ + memset(hdr, 0, sizeof(*hdr)); + + hdr->marker = SUBPART_MARKER; + hdr->num_entries = count; + hdr->header_version = SUBPART_HEADER_VERSION_SUPPORTED; + hdr->entry_version = SUBPART_ENTRY_VERSION_SUPPORTED; + hdr->header_length = SUBPART_HEADER_SIZE; + memcpy(hdr->name, name, sizeof(hdr->name)); +} + +static size_t init_subpart_entry(struct subpart_entry *e, struct buffer *b, + size_t offset) +{ + memset(e, 0, sizeof(*e)); + + assert(strlen(b->name) <= sizeof(e->name)); + strncpy((char *)e->name, (char *)b->name, sizeof(e->name)); + e->offset = offset; + e->length = buffer_size(b); + + return (offset + buffer_size(b)); +} + +static void init_manifest_header(struct manifest_header *hdr, size_t size) +{ + memset(hdr, 0, sizeof(*hdr)); + + hdr->header_type = 0x4; + assert((MANIFEST_HDR_SIZE % DWORD_SIZE) == 0); + hdr->header_length = MANIFEST_HDR_SIZE / DWORD_SIZE; + hdr->header_version = 0x10000; + hdr->vendor = 0x8086; + + struct tm *local_time; + time_t curr_time; + char buffer[11]; + + curr_time = time(NULL); + local_time = localtime(&curr_time); + strftime(buffer, sizeof(buffer), "0x%Y%m%d", local_time); + hdr->date = strtoul(buffer, NULL, 16); + + assert((size % DWORD_SIZE) == 0); + hdr->size = size / DWORD_SIZE; + hdr->id = MANIFEST_ID_MAGIC; +} + +static void init_signed_pkg_info_ext(struct signed_pkg_info_ext *ext, + size_t count, const char *name) +{ + memset(ext, 0, sizeof(*ext)); + + ext->ext_type = SIGNED_PKG_INFO_EXT_TYPE; + ext->ext_length = EXT_SIZE(count); + memcpy(ext->name, name, sizeof(ext->name)); +} + +static void subpart_fixup_write_buffer(struct buffer *buf) +{ + struct subpart *s = buffer_get(buf); + struct subpart_header *h = &s->h; + struct subpart_entry *e = &s->e[0]; + + size_t count = h->num_entries; + size_t offset = 0; + + FIX_MEMBER(h->marker); + FIX_MEMBER(h->num_entries); + FIX_MEMBER(h->header_version); + FIX_MEMBER(h->entry_version); + FIX_MEMBER(h->header_length); + FIX_MEMBER(h->checksum); + offset += sizeof(h->name); + + uint32_t i; + for (i = 0; i < count; i++) { + offset += sizeof(e[i].name); + FIX_MEMBER(e[i].offset); + FIX_MEMBER(e[i].length); + FIX_MEMBER(e[i].rsvd); + } +} + +static void create_subpart(struct buffer *dst, struct buffer *info[], + size_t count, const char *name) +{ + alloc_buffer(&ifwi_image.subpart, SUBPART_SIZE(count), "subpart"); + struct subpart_header *h = buffer_get(&ifwi_image.subpart); + struct subpart_entry *e = (struct subpart_entry *)(h + 1); + + init_subpart_header(h, count, name); + + size_t curr_offset = SUBPART_SIZE(count); + size_t i; + + for (i = 0; i < count; i++) { + curr_offset = init_subpart_entry(&e[i], info[i], + curr_offset); + } + + alloc_buffer(dst, curr_offset, name); + uint8_t *data = buffer_get(dst); + + for (i = 0; i < count; i++) { + memcpy(data + e[i].offset, buffer_get(info[i]), + buffer_size(info[i])); + } + + h->checksum = calc_checksum((struct subpart *)h); + + print_subpart(name); + + subpart_fixup_write_buffer(&ifwi_image.subpart); + memcpy(data, buffer_get(&ifwi_image.subpart), + buffer_size(&ifwi_image.subpart)); +} + +static enum ifwi_ret ibb_cbp_add(int type) +{ +#define DUMMY_IBB_SIZE (4 * KiB) + + assert (type == IBB_TYPE); + + /* Entry # 1 - IBBP.man */ + struct buffer manifest; + alloc_buffer(&manifest, MANIFEST_SIZE(0), "IBBP.man"); + + struct manifest_header *man_hdr = buffer_get(&manifest); + init_manifest_header(man_hdr, MANIFEST_SIZE(0)); + + struct signed_pkg_info_ext *ext; + ext = (struct signed_pkg_info_ext *)(man_hdr + 1); + + init_signed_pkg_info_ext(ext, 0, comp[type].name); + + /* Entry # 2 - IBBL */ + struct buffer ibbl; + if (buffer_from_file(&ibbl, param.file_name)) + return COMM_ERR; + + /* Entry # 3 - IBB */ + struct buffer ibb; + alloc_buffer(&ibb, DUMMY_IBB_SIZE, "IBB"); + memset(buffer_get(&ibb), 0xFF, DUMMY_IBB_SIZE); + + /* Create subpartition. */ + struct buffer *info[] = { + &manifest, &ibbl, &ibb, + }; + create_subpart(&ifwi_image.comp_buf[type], &info[0], ARRAY_SIZE(info), + comp[type].subpart_name); + + return REPACK_REQUIRED; +} + static enum ifwi_ret ifwi_raw_add(int type) { if (buffer_from_file(&ifwi_image.comp_buf[type], param.file_name)) @@ -1321,32 +1538,6 @@ static enum ifwi_ret ifwi_raw_replace(int type) return ifwi_raw_add(type); } -static void subpart_fixup_write_buffer(struct buffer *buf) -{ - struct subpart *s = buffer_get(buf); - struct subpart_header *h = &s->h; - struct subpart_entry *e = &s->e[0]; - - size_t count = h->num_entries; - size_t offset = 0; - - FIX_MEMBER(h->marker); - FIX_MEMBER(h->num_entries); - FIX_MEMBER(h->header_version); - FIX_MEMBER(h->entry_version); - FIX_MEMBER(h->header_length); - FIX_MEMBER(h->checksum); - offset += sizeof(h->name); - - uint32_t i; - for (i = 0; i < count; i++) { - offset += sizeof(e[i].name); - FIX_MEMBER(e[i].offset); - FIX_MEMBER(e[i].length); - FIX_MEMBER(e[i].rsvd); - } -} - static enum ifwi_ret ifwi_cbp_replace(int type) { if (buffer_size(&ifwi_image.comp_buf[type]) == 0) {

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coreboot-gerrit May 2016