coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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1843 discussions

Patch merged into coreboot/master: vendorcode/google/chromeos/vboot2: use cbmem for postcar region selection
by gerrit＠coreboot.org 25 May '16

25 May '16

the following patch was just integrated into master: commit e6dcafbc1a6b3468ae57003dd481b5143970a61c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 24 14:50:45 2016 -0500 vendorcode/google/chromeos/vboot2: use cbmem for postcar region selection When the vboot cbfs selection runs in postcar stage it should be utilizing cbmem to locate the vboot selected region. Change-Id: I027ba19438468bd690d74ae55007393f051fde42 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14959 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/14959 for details. -gerrit

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Patch merged into coreboot/master: console/post: be explicit about conditional cmos_post_log() compiling
by gerrit＠coreboot.org 25 May '16

25 May '16

the following patch was just integrated into master: commit 9acd39d95ebf7ffb318a91322d531a777c9b133e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 24 14:47:10 2016 -0500 console/post: be explicit about conditional cmos_post_log() compiling The current code was using !__PRE_RAM__ as a proxy for ramstage conditional compilation. In the face of postcar stage not defining __PRE_RAM__ (because it's after RAM is up) these code paths can fail to compile with a __SIMPLE_DEVICE__ defined for the entire stage. Remedy the current situation by just compiling explicity for ramstage because that was the original intent. In the future, the __SIMPLE_DEVICE__ selection for postcar can also be re-evaluated. Change-Id: I0f887f1e45f0cf5c235ae5144eaa227921e7119b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14958 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/14958 for details. -gerrit

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New patch to review for coreboot: sio/winbond/w83667hg-a: Add pinmux defines for UART B
by Timothy Pearson 25 May '16

25 May '16

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14965 -gerrit commit b09012ef737322d237271f9dd49c1ba87f21a213 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Wed May 25 10:22:10 2016 -0500 sio/winbond/w83667hg-a: Add pinmux defines for UART B Change-Id: Ib98c69de781d2b651ec168d03250cacc918c5c1f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/superio/winbond/w83667hg-a/w83667hg-a.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/superio/winbond/w83667hg-a/w83667hg-a.h b/src/superio/winbond/w83667hg-a/w83667hg-a.h index 0c0d427..d4e7110 100644 --- a/src/superio/winbond/w83667hg-a/w83667hg-a.h +++ b/src/superio/winbond/w83667hg-a/w83667hg-a.h @@ -18,6 +18,13 @@ #ifndef SUPERIO_WINBOND_W83667HG_A #define SUPERIO_WINBOND_W83667HG_A +/* Pinmux configuration defines */ +#define W83667HG_SPI_PINMUX_OFFSET 0x2a + +#define W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK (1 << 2) +#define W83667HG_SPI_PINMUX_GPIO4 (0 << 2) +#define W83667HG_SPI_PINMUX_SERIAL_B (1 << 2) + /* Logical Device Numbers (LDN). */ #define W83667HG_A_FDC 0x00 #define W83667HG_A_PP 0x01

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Patch set updated for coreboot: mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header
by Timothy Pearson 25 May '16

25 May '16

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14892 -gerrit commit d4bb0eb95b7f8785a740e2102b18ce8dfc390cbc Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed May 18 13:33:13 2016 -0500 mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header The ASUS KGPE-D16/KCMA-D8 have an on-board header for a second RS-232 serial port, however it is disabled by default due to the SuperIO default pin mux settings. Enable the secondary serial port early in romstage to allow use for coreboot console if desired. Change-Id: I5b83659dd8b0d6af559c9ceccee55c4cc2f17165 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kcma-d8/dsdt.asl | 24 ++++++++++++++++++++++++ src/mainboard/asus/kcma-d8/romstage.c | 8 ++++++-- src/mainboard/asus/kgpe-d16/dsdt.asl | 24 ++++++++++++++++++++++++ src/mainboard/asus/kgpe-d16/romstage.c | 8 ++++++-- 4 files changed, 60 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl index ef87d31..d305af5 100644 --- a/src/mainboard/asus/kcma-d8/dsdt.asl +++ b/src/mainboard/asus/kcma-d8/dsdt.asl @@ -587,6 +587,30 @@ DefinitionBlock ( }) } } + + /* UART 2 */ + Device (URT2) + { + Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART + Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // Always enable + } + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + } } /* High Precision Event Timer */ diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 9d1d95f..a9d647c 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -46,7 +46,8 @@ #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" -#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) +#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) +#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) static void activate_spd_rom(const struct mem_controller *ctrl); @@ -401,9 +402,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_pci_port80(); /* Initialize early serial */ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE); console_init(); + /* Configure secondary serial port pin mux */ + winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B); + /* Disable LPC legacy DMA support to prevent lockup */ byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0x78); byte &= ~(1 << 0); diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index 5f9195a..d364f1f 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -587,6 +587,30 @@ DefinitionBlock ( }) } } + + /* UART 2 */ + Device (URT2) + { + Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART + Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // Always enable + } + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + } } /* High Precision Event Timer */ diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 5a7400e..1ff1ed3 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -46,7 +46,8 @@ #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" -#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) +#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) +#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) static void activate_spd_rom(const struct mem_controller *ctrl); @@ -442,9 +443,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_pci_port80(); /* Initialize early serial */ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE); console_init(); + /* Configure secondary serial port pin mux */ + winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B); + /* Disable LPC legacy DMA support to prevent lockup */ byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0x78); byte &= ~(1 << 0);

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Patch set updated for coreboot: sio/winbond/common: Add function to configure pin mux
by Timothy Pearson 25 May '16

25 May '16

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14960 -gerrit commit 7530c90c89db1ec6eaaf1a0c96cafc98202d015a Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Tue May 24 15:48:50 2016 -0500 sio/winbond/common: Add function to configure pin mux Certain mainboards require SuperIO pinmux configuration before peripherals will become operational. Allow each mainboard to configure the pinmux(es) of Winbond chips if needed. Change-Id: Ice19f8d8514b66b15920a5b893700d636ed75cec Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- 3rdparty/blobs | 2 +- src/superio/winbond/common/early_serial.c | 13 +++++++++++++ src/superio/winbond/common/winbond.h | 3 ++- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index cca0337..b0eeddd 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit cca0337ea0fba8a07a73ad1627338dd5738f4d3f +Subproject commit b0eeddd4f5c583818e66521f2552cd3448b357b2 diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_serial.c index 6482a94..aebbd38 100644 --- a/src/superio/winbond/common/early_serial.c +++ b/src/superio/winbond/common/early_serial.c @@ -66,3 +66,16 @@ void winbond_enable_serial(pnp_devfn_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); } + +void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state) +{ + uint8_t byte; + + /* Configure pin mux */ + pnp_enter_conf_state(dev); + byte = pnp_read_config(dev, offset); + byte &= ~mask; + byte |= state; + pnp_write_config(dev, offset, byte); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h index 1f7e7b1..6e67eeb 100644 --- a/src/superio/winbond/common/winbond.h +++ b/src/superio/winbond/common/winbond.h @@ -20,7 +20,8 @@ #include <arch/io.h> #include <stdint.h> -void winbond_enable_serial(pnp_devfn_t dev, u16 iobase); +void winbond_enable_serial(pnp_devfn_t dev, uint16_t iobase); +void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state); void pnp_enter_conf_state(pnp_devfn_t dev); void pnp_exit_conf_state(pnp_devfn_t dev);

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New patch to review for coreboot: util/riscvtools: Add script that turns coreboot.rom into an ELF
by Jonathan Neuschäfer 25 May '16

25 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14964 -gerrit commit 55486e1fe0de53378ce4927e1b14550b45bc0b54 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed May 25 07:42:37 2016 +0200 util/riscvtools: Add script that turns coreboot.rom into an ELF This is required because the current version of SPIKE doesn't support loading flat files yet. Change-Id: If745d78712ca8108b5dcc21591201bc2d3f70b86 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- util/riscvtools/make-spike-elf.sh | 27 +++++++++++++++++++++++++++ util/riscvtools/spike-elf.ld | 11 +++++++++++ 2 files changed, 38 insertions(+) diff --git a/util/riscvtools/make-spike-elf.sh b/util/riscvtools/make-spike-elf.sh new file mode 100755 index 0000000..4241c54 --- /dev/null +++ b/util/riscvtools/make-spike-elf.sh @@ -0,0 +1,27 @@ +#!/bin/sh +# +# This script is based on: +# https://docs.google.com/document/d/1Pvf9Yxorcd3sbgs8WcomcTl3J4bmX6e1UE0ROCe… + +set -e + +usage() { + echo "This script converts a flat file into an ELF, that can be passed" + echo "to SPIKE, the RISC-V reference emulator." + echo "" + echo "Usage: $0 coreboot.rom coreboot.elf" +} + +if [ $# -ne 2 ]; then + usage + exit 1 +fi + +FLAT_FILE="$1" +OBJECT_FILE=$(mktemp /tmp/coreboot-spike.XXXXXX.o) +ELF_FILE="$2" +TOOL_PATH="$(dirname "$0")" + +objcopy -I binary -O elf32-i386 --binary-architecture i386 "$FLAT_FILE" "$OBJECT_FILE" +ld -m elf_i386 "$OBJECT_FILE" -T "$TOOL_PATH/spike-elf.ld" -o "$ELF_FILE" +rm "$OBJECT_FILE" diff --git a/util/riscvtools/spike-elf.ld b/util/riscvtools/spike-elf.ld new file mode 100644 index 0000000..c103136 --- /dev/null +++ b/util/riscvtools/spike-elf.ld @@ -0,0 +1,11 @@ +/* See make-spike-elf.sh */ + +ENTRY(_start); +SECTIONS +{ + _start = 0x0000; + . = 0x0000; + .data : { + *(.data) + } +}

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Patch set updated for coreboot: MAINTAINERS: Add myself for Apollolake SoC, FSP2.0, and Amenia mb
by Andrey Petrov 25 May '16

25 May '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14963 -gerrit commit a06f17e83db5f22b938a436ebf63d87bdf657fdd Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue May 24 22:01:56 2016 -0700 MAINTAINERS: Add myself for Apollolake SoC, FSP2.0, and Amenia mb Change-Id: I9931263f0f51d6c726bd7c72042fae1155affb6e Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- MAINTAINERS | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 13b68f9..69dcb98 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -236,17 +236,32 @@ M: York Yang <york.yang(a)intel.com> S: Supported F: src/drivers/intel/fsp1_1/ +INTEL FSP 2.0 +M: Andrey Petrov <andrey.petrov(a)intel.com> +S: Supported +F: src/drivers/intel/fsp2_0/ + INTEL STRAGO MAINBOARD M: Hannah Williams <hannah.williams(a)intel.com> S: Supported F: /src/mainboard/intel/strago/ +INTEL AMENIA MAINBOARD +M: Andrey Petrov <andrey.petrov(a)intel.com> +S: Supported +F: src/mainboard/intel/amenia/ + INTEL BRASWELL SOC M: Hannah Williams <hannah.williams(a)intel.com> S: Supported F: /src/soc/intel/braswell F: /src/vendorcode/intel/fsp/fsp1_1/braswell +INTEL APOLLOLAKE_SOC +M: Andrey Petrov <andrey.petrov(a)intel.com> +S: Supported +F: src/soc/intel/apollolake/ + ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS M: Timothy Pearson <tpearson(a)raptorengineeringinc.com> S: Supported

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New patch to review for coreboot: MAINTAINERS: Add myself for Apollolake SoC, FSP2.0, and Amenia mb
by Andrey Petrov 25 May '16

25 May '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14963 -gerrit commit 935640e617b456beaaf72b6e109f605b30b3fd3a Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue May 24 22:01:56 2016 -0700 MAINTAINERS: Add myself for Apollolake SoC, FSP2.0, and Amenia mb Change-Id: I9931263f0f51d6c726bd7c72042fae1155affb6e Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- MAINTAINERS | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 13b68f9..a4f0d96 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -236,17 +236,32 @@ M: York Yang <york.yang(a)intel.com> S: Supported F: src/drivers/intel/fsp1_1/ +INTEL FSP 2.0 +M: Andrey Petrov <andrey.petrov(a)intel.com> +S: Supported +F: src/drivers/intel/fsp2_0/ + INTEL STRAGO MAINBOARD M: Hannah Williams <hannah.williams(a)intel.com> S: Supported F: /src/mainboard/intel/strago/ +INTEL AMENIA MAINBOARD +M: Andrey Petrov <andrey.petrov(a)intel.com> +S: Supported +F: src/mainboard/intel/amenia + INTEL BRASWELL SOC M: Hannah Williams <hannah.williams(a)intel.com> S: Supported F: /src/soc/intel/braswell F: /src/vendorcode/intel/fsp/fsp1_1/braswell +INTEL APOLLOLAKE_SOC +M: Andrey Petrov <andrey.petrov(a)intel.com> +S: Supported +F: src/soc/intel/apollolake/ + ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS M: Timothy Pearson <tpearson(a)raptorengineeringinc.com> S: Supported

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Patch set updated for coreboot: arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constant
by Jonathan Neuschäfer 25 May '16

25 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14962 -gerrit commit 932c8ec9820a7b13ecd4d9e4eac00cf4ff25ab1a Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed May 25 01:06:37 2016 +0200 arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constant Change-Id: I9759771fa6fc708d7d97509c5f5e0cefb8ab4c96 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/trap_util.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index bc09dc9..0118ffc 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -108,7 +108,7 @@ supervisor_trap_entry: csrw mscratch, sp # load in the top of the machine stack - la sp, 0x80FFF0 - 64 + li sp, 0x80FFF0 - 64 1:addi sp,sp,-320 save_tf move a0,sp

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Patch set updated for coreboot: mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header
by Timothy Pearson 25 May '16

25 May '16

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14892 -gerrit commit b6702c8dc63d249650726acb16eb8bf03d615896 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed May 18 13:33:13 2016 -0500 mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header The ASUS KGPE-D16/KCMA-D8 have an on-board header for a second RS-232 serial port, however it is disabled by default due to the SuperIO default pin mux settings. Enable the secondary serial port early in romstage to allow use for coreboot console if desired. Change-Id: I5b83659dd8b0d6af559c9ceccee55c4cc2f17165 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kcma-d8/dsdt.asl | 24 ++++++++++++++++++++++++ src/mainboard/asus/kcma-d8/romstage.c | 8 ++++++-- src/mainboard/asus/kgpe-d16/dsdt.asl | 24 ++++++++++++++++++++++++ src/mainboard/asus/kgpe-d16/romstage.c | 8 ++++++-- 4 files changed, 60 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl index ef87d31..d305af5 100644 --- a/src/mainboard/asus/kcma-d8/dsdt.asl +++ b/src/mainboard/asus/kcma-d8/dsdt.asl @@ -587,6 +587,30 @@ DefinitionBlock ( }) } } + + /* UART 2 */ + Device (URT2) + { + Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART + Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // Always enable + } + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + } } /* High Precision Event Timer */ diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 9d1d95f..a9d647c 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -46,7 +46,8 @@ #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" -#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) +#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) +#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) static void activate_spd_rom(const struct mem_controller *ctrl); @@ -401,9 +402,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_pci_port80(); /* Initialize early serial */ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE); console_init(); + /* Configure secondary serial port pin mux */ + winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B); + /* Disable LPC legacy DMA support to prevent lockup */ byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0x78); byte &= ~(1 << 0); diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index 5f9195a..d364f1f 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -587,6 +587,30 @@ DefinitionBlock ( }) } } + + /* UART 2 */ + Device (URT2) + { + Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART + Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // Always enable + } + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + } } /* High Precision Event Timer */ diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 5a7400e..1ff1ed3 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -46,7 +46,8 @@ #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" -#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) +#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) +#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) static void activate_spd_rom(const struct mem_controller *ctrl); @@ -442,9 +443,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_pci_port80(); /* Initialize early serial */ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE); console_init(); + /* Configure secondary serial port pin mux */ + winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B); + /* Disable LPC legacy DMA support to prevent lockup */ byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0x78); byte &= ~(1 << 0);

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coreboot-gerrit May 2016