coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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1843 discussions

Patch set updated for coreboot: soc/apollolake: remove _RMV and _DSW methods from xhci.asl
by Hannah Williams 26 May '16

26 May '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14966 -gerrit commit d552127357e3f1ebaa443c1fc98b7406b5ea030c Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed May 25 11:12:43 2016 -0700 soc/apollolake: remove _RMV and _DSW methods from xhci.asl Change-Id: Ic314656f34fda10e58e55bdefeb0a1f0c6ab5ae2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/acpi/xhci.asl | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index fc67074..c07c707 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -1,4 +1,5 @@ -/* This file is part of the coreboot project. +/* + * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corporation. * @@ -13,29 +14,18 @@ */ /* XHCI Controller 0:15.0 */ -Device(XHC1) { - Name(_ADR, 0x00150000) // Device 21, Function 0 +Device (XHC1) { + Name (_ADR, 0x00150000) /* Device 21, Function 0 */ Name (_S3D, 3) /* D3 supported in S3 */ Name (_S0W, 3) /* D3 can wake device in S0 */ Name (_S3W, 3) /* D3 can wake system from S3 */ - // Declare XHCI GPE status and enable bits are bit 13 + /* Declare XHCI GPE status and enable bits are bit 13 */ Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 }) - Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake - { - Return (Zero) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - Return (Zero) - } - - Method(_STA, 0) + Method (_STA, 0) { Return (0xF) } - }

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Patch merged into coreboot/master: superiotool: Add support for chip NCT6102D / NCT6106D
by gerrit＠coreboot.org 26 May '16

26 May '16

the following patch was just integrated into master: commit 15a53c632991bd3cb202051f58eed465068663da Author: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> Date: Thu Mar 31 17:03:53 2016 +0200 superiotool: Add support for chip NCT6102D / NCT6106D Add support for chip NCT6102D / NCT6106D in superiotool Change-Id: I689ff8e796f43a5aac144e9898df750407588b1f Signed-off-by: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> Reviewed-on: https://review.coreboot.org/14206 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14206 for details. -gerrit

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New patch to review for coreboot: APL: Add support to enable google ChromeEC
by Shaunak Saha 25 May '16

25 May '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14967 -gerrit commit 9f43657a0cb13900aa900a00454566743b2514da Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Wed May 25 11:34:43 2016 -0700 APL: Add support to enable google ChromeEC ChromeEC is needed for EC controlled features to work properly. This patch adds support to enable ChromeEC from Amenia mainboard like PNOT method and LPCB and also the nvs fields. Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/acpi/cpu.asl | 118 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/globalnvs.asl | 5 ++ src/soc/intel/apollolake/acpi/lpc.asl | 23 +++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 + src/soc/intel/apollolake/include/soc/nvs.h | 7 +- 5 files changed, 155 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/acpi/cpu.asl b/src/soc/intel/apollolake/acpi/cpu.asl new file mode 100644 index 0000000..a202ceb --- /dev/null +++ b/src/soc/intel/apollolake/acpi/cpu.asl @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* These devices are created at runtime */ +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) + +/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ +Method (PNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST + } +} + +/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ +Method (PPCN) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC + } +} + +/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ +Method (TNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC + } +} + +/* Return a package containing enabled processor entries */ +Method (PPKG) +{ + If (LGreaterEqual (\PCNT, 8)) { + Return (Package() + { + \_PR.CP00, + \_PR.CP01, + \_PR.CP02, + \_PR.CP03, + \_PR.CP04, + \_PR.CP05, + \_PR.CP06, + \_PR.CP07 + }) + } ElseIf (LGreaterEqual (\PCNT, 4)) { + Return (Package () + { + \_PR.CP00, + \_PR.CP01, + \_PR.CP02, + \_PR.CP03 + }) + } ElseIf (LGreaterEqual (\PCNT, 2)) { + Return (Package () + { + \_PR.CP00, + \_PR.CP01 + }) + } Else { + Return (Package () + { + \_PR.CP00 + }) + } +} diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 2ef5031..e311a6e 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -28,6 +28,11 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Nothing here yet, folks */ Offset (0x00), + PCNT, 8, // 0x01 - Processor Count + PPCM, 8, // 0x02 - Max PPC State + LIDS, 8, // 0x03 - LID State + PWRS, 8, // 0x04 - AC Power State + DPTE, 8, // 0x05 - Enable DPTF /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/acpi/lpc.asl b/src/soc/intel/apollolake/acpi/lpc.asl new file mode 100644 index 0000000..818c636 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/lpc.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel LPC Bus Device - 0:1f.0 */ + +Device (LPCB) +{ + Name(_ADR, 0x001f0000) +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 0584439..51ea5f9 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -23,3 +23,6 @@ /* GPIO controller */ #include "gpio.asl" + +/* LPC */ +#include "lpc.asl" diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 8b3a3af..b090658 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,7 +28,12 @@ struct global_nvs_t { /* Miscellaneous */ - uint8_t unused[256]; + u8 pcnt; /* 0x01 - Processor Count */ + u8 ppcm; /* 0x02 - Max PPC State */ + u8 lids; /* 0x03 - LID State */ + u8 pwrs; /* 0x04 - AC Power State */ + u8 dpte; /* 0x05 - Enable DPTF */ + uint8_t unused[251]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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Patch set updated for coreboot: soc/intel/apollolake: Provide No Connect macro for unused Pad
by Jagadish Krishnamoorthy 25 May '16

25 May '16

Jagadish Krishnamoorthy (jagadish.krishnamoorthy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14956 -gerrit commit baf8b2bc22edaba88506a2c266d7d83862f4c9f5 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Fri May 20 19:28:59 2016 -0700 soc/intel/apollolake: Provide No Connect macro for unused Pad Change-Id: Iba506054a3d631c8e538d44e1ca6877dd02c2ca9 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> --- src/soc/intel/apollolake/include/soc/gpio.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 4d9973c..f01284e 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -54,6 +54,11 @@ typedef uint32_t gpio_t; PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull)) +/* No Connect configuration for unused pad. + * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term + */ +#define PAD_NC(pad, pull) PAD_CFG_GPI(pad, pull, DEEP) + /* General purpose input, routed to APIC */ #define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \

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New patch to review for coreboot: soc/apollolake: remove _RMV and _DSW methods from xhci.asl
by Hannah Williams 25 May '16

25 May '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14966 -gerrit commit d4c6629419fb4c38a47a9d0f30992af95547ef36 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed May 25 11:12:43 2016 -0700 soc/apollolake: remove _RMV and _DSW methods from xhci.asl Change-Id: Ic314656f34fda10e58e55bdefeb0a1f0c6ab5ae2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/acpi/xhci.asl | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index fc67074..8b40dfa 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -1,4 +1,5 @@ -/* This file is part of the coreboot project. +/* + * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corporation. * @@ -13,26 +14,16 @@ */ /* XHCI Controller 0:15.0 */ -Device(XHC1) { - Name(_ADR, 0x00150000) // Device 21, Function 0 +Device (XHC1) { + Name(_ADR, 0x00150000) /* Device 21, Function 0 */ Name (_S3D, 3) /* D3 supported in S3 */ Name (_S0W, 3) /* D3 can wake device in S0 */ Name (_S3W, 3) /* D3 can wake system from S3 */ - // Declare XHCI GPE status and enable bits are bit 13 + /* Declare XHCI GPE status and enable bits are bit 13 */ Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 }) - Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake - { - Return (Zero) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - Return (Zero) - } - Method(_STA, 0) { Return (0xF)

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Patch set updated for coreboot: WIP: intel/amenia: Add changes for image assembly
by Bora Guvendik 25 May '16

25 May '16

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14897 -gerrit commit 21ee42a539fdd5cb392a051f672e6fce973bf6bc Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Wed May 18 14:56:27 2016 -0700 WIP: intel/amenia: Add changes for image assembly Insert bootblock Build base images for different variants Generate fmd files for different variants BUG=chrome-os-partner:51844 BRANCH=none TEST=boots to chrome OS Change-Id: I0e92858486ecf4720b8bcdf64bae97d9476caabc Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 17 +++++++++++++++-- src/soc/intel/apollolake/Makefile.inc | 5 +++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index e83b151..a6b0362 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -35,9 +35,22 @@ config FMAP_FILE string default "amenia" -config PREBUILT_SPI_IMAGE +config HAVE_IFD_BIN + default y + +config APOLLOLAKE_A0 + bool + default y + +config IFD_BIN_PATH + string "Path and filename of the descriptor.bin file" + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0" if APOLLOLAKE_A0 + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.b0" if !APOLLOLAKE_A0 + +config FMDFILE string - default "amenia.bin.orig.a0" + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0.fmd" if APOLLOLAKE_A0 + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.b0.fmd" if !APOLLOLAKE_A0 config IFD_BIOS_END hex diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 607ad13..909226b 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -68,4 +68,9 @@ files_added:: $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward endif +build_complete:: + $(CBFSTOOL) $(obj)/coreboot.rom write \ + -r bootblock \ + -f $(objcbfs)/bootblock.bin + endif

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Patch merged into coreboot/master: intel/amenia: Extend IFD size by 512 KB
by gerrit＠coreboot.org 25 May '16

25 May '16

the following patch was just integrated into master: commit b2b425b05be47610537c4c841fb75da627552a45 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Tue May 17 15:54:27 2016 -0700 intel/amenia: Extend IFD size by 512 KB Increase BIOS region size by 512KB since device extension size is reduced from 1MB to 512KB BUG=chrome-os-partner:52589 TEST=Build Coreboot and boots CQ-DEPEND=CL:*259448,CL:345642,CL:*259445 Change-Id: Ib81b117a3afe730aafa54b4ef31b1e9ab1f67111 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-on: https://review.coreboot.org/14929 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14929 for details. -gerrit

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Patch merged into coreboot/master: soc/apollolake: Enable Wake from USB devices
by gerrit＠coreboot.org 25 May '16

25 May '16

the following patch was just integrated into master: commit 1cdce27cadb6239aca04192f28b74d976f2795d3 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Tue Apr 5 10:03:38 2016 -0700 soc/apollolake: Enable Wake from USB devices Change-Id: Ib0b30a5779681488e80000a2570fc2fd4c69e908 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/14893 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14893 for details. -gerrit

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Patch merged into coreboot/master: soc/apollolake: SOC specific SMM code
by gerrit＠coreboot.org 25 May '16

25 May '16

the following patch was just integrated into master: commit d9c84ca7ef0142df99c01832fe8683faec257436 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri May 13 00:47:14 2016 -0700 soc/apollolake: SOC specific SMM code Add SMI handlers that map to SOC specific SMI events Update relocation_handler in mp_ops Change-Id: Idefddaf41cf28240f5f8172b00462a7f893889e7 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/14808 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14808 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/common: Add common smihandler code
by gerrit＠coreboot.org 25 May '16

25 May '16

the following patch was just integrated into master: commit ba0fc470ddf13af322c79bac291ad475331e09a3 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed May 4 18:15:49 2016 -0700 soc/intel/common: Add common smihandler code Provide default handler for some SMI events. Provide the framework for extracting data from SMM Save State area for processors with SMM revision 30100 and 30101. The SOC specific code should initialize southbridge_smi with event handlers. For SMM Save state handling, SOC code should implement get_smm_save_state_ops which initializes the SOC specific ops for SMM Save State handling. Change-Id: I0aefb6dbb2b1cac5961f9e43f4752b5929235df3 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/14615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14615 for details. -gerrit

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coreboot-gerrit May 2016