coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake: provide SMM dependency requirements
by Aaron Durbin 26 May '16

26 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14977 -gerrit commit 0a6100816c2e1a90891c040f0bd57efa5cc4838a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 26 14:22:34 2016 -0500 soc/intel/apollolake: provide SMM dependency requirements Depending on which options are selected there needs to be certain functions supplied. However, the spi, mmap_boot, and tsc_freq modules were not included in the SMM builds. Fix the omission. Change-Id: I25ab42886cfd46770ce0f4beee65f2f4d15649f3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index b8f0c18..1ea21f6 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -29,8 +29,11 @@ romstage-y += mmap_boot.c romstage-y += tsc_freq.c romstage-y += pmutil.c +smm-y += mmap_boot.c smm-y += pmutil.c smm-y += smihandler.c +smm-y += spi.c +smm-y += tsc_freq.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c

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Patch set updated for coreboot: mainboard/google/reef: increase BIOS region size
by Aaron Durbin 26 May '16

26 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14974 -gerrit commit 73d62aaf62b68f4161af9ac659385caef17bec8c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 26 12:01:19 2016 -0500 mainboard/google/reef: increase BIOS region size An updated descriptor expands the BIOS region while descreasing the 'device expansion region' utilized by the CSE. Update the end region marker to reflect this new size as well as the chromeos.fmd file which needs to be adjusted for logical boot parition 2 requirement which resides halfway through the BIOS region. The GBB was moved and shunk to accommodate the change. Change-Id: I7baa5282d7c608af648b5773c4dfa123060a6e45 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 2 +- src/mainboard/google/reef/chromeos.fmd | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index e49e8b6..5d8ded6 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -19,7 +19,7 @@ config BOOT_MEDIA_SPI_BUS config IFD_BIOS_END hex - default 0x6FF000 + default 0x77F000 config IFD_BIOS_START hex diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index a3fb8b5..3f7c3aa 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -10,9 +10,9 @@ FLASH 8M { RO_FRID@0x4800 0x40 RO_FRID_PAD@0x4840 0x7c0 COREBOOT(CBFS)@0x5000 0x17b000 + GBB@0x180000 0x40000 # logical boot partition 2. Remove with updated CSE - SIGN_CSE@0x180000 0x10000 - GBB@0x190000 0x70000 + SIGN_CSE@0x1c0000 0x10000 } } MISC_RW@0x400000 0x1a000 { @@ -34,6 +34,6 @@ FLASH 8M { FW_MAIN_B(CBFS)@0x10000 0x162fc0 RW_FWID_B@0x172fc0 0x40 } - DEVICE_EXTENSION@0x700000 0x100000 + DEVICE_EXTENSION@0x77f000 0x80000 }

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New patch to review for coreboot: soc/intel/apollolake: provide SMM dependency requirements
by Aaron Durbin 26 May '16

26 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14977 -gerrit commit 49ddda81915fc702d2f1fe65987f231f0f59bbe8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 26 14:22:34 2016 -0500 soc/intel/apollolake: provide SMM dependency requirements Depending on which options are selected there needs to be certain functions supplied. However, the spi, mmap_boot, and tsc_freq modules were not included in the SMM builds. Fix the omission. Change-Id: I25ab42886cfd46770ce0f4beee65f2f4d15649f3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index b8f0c18..1ea21f6 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -29,8 +29,11 @@ romstage-y += mmap_boot.c romstage-y += tsc_freq.c romstage-y += pmutil.c +smm-y += mmap_boot.c smm-y += pmutil.c smm-y += smihandler.c +smm-y += spi.c +smm-y += tsc_freq.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c

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Patch set updated for coreboot: google/reef: Sync chromeos.fmd with fmap.dts and fix offsets
by Aaron Durbin 26 May '16

26 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14975 -gerrit commit e497fa571f01de0b8cf4d20d944d239fe515a771 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 25 17:04:55 2016 -0700 google/reef: Sync chromeos.fmd with fmap.dts and fix offsets CQ-DEPEND=CL:347460 BUG=chrome-os-partner:53689 BRANCH=None TEST="emerge-reef chromeos-bootimage" completes without error Change-Id: Ic954e29628423937604772a8d2d0414954e6ba3e Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/347441 Commit-Ready: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/chromeos.fmd | 57 +++++++++++++++++----------------- 1 file changed, 28 insertions(+), 29 deletions(-) diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index 5e8b559..a3fb8b5 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -1,40 +1,39 @@ FLASH 8M { - WP_RO 4M { - SI_ALL 2M { - SI_DESC 4K - bootblock@509056 32K + WP_RO@0x0 0x400000 { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + bootblock@0x7c480 0x8000 } - RO_SECTION@2M 2M { - RO_VPD 0x4000 - FMAP 0x800 - RO_FRID 0x40 - RO_FRID_PAD 0x7c0 - COREBOOT(CBFS) + RO_SECTION@0x200000 0x200000 { + RO_VPD@0x0 0x4000 + FMAP@0x4000 0x800 + RO_FRID@0x4800 0x40 + RO_FRID_PAD@0x4840 0x7c0 + COREBOOT(CBFS)@0x5000 0x17b000 # logical boot partition 2. Remove with updated CSE - SIGN_CSE@0x180000 64K - # GBB grows to fill the remaining region... - GBB + SIGN_CSE@0x180000 0x10000 + GBB@0x190000 0x70000 } } - MISC_RW { - RW_MRC_CACHE 64K - RW_ELOG 16K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K + MISC_RW@0x400000 0x1a000 { + RW_MRC_CACHE@0x0 0x10000 + RW_ELOG@0x10000 0x4000 + RW_SHARED@0x14000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 } - RW_VPD 8K + RW_VPD@0x18000 0x2000 } - RW_SECTION_A 0xf0000 { - VBLOCK_A 64K - FW_MAIN_A(CBFS) 768K - RW_FWID_A 64 + RW_SECTION_A@0x41a000 0x173000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x162fc0 + RW_FWID_A@0x172fc0 0x40 } - RW_SECTION_B 0xf0000 { - VBLOCK_B 64K - FW_MAIN_B(CBFS) 768K - RW_FWID_B 64 + RW_SECTION_B@0x58d000 0x173000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x162fc0 + RW_FWID_B@0x172fc0 0x40 } - DEVICE_EXTENSION@7M 1M + DEVICE_EXTENSION@0x700000 0x100000 }

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Patch set updated for coreboot: mainboard/google/reef: increase BIOS region size
by Aaron Durbin 26 May '16

26 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14974 -gerrit commit b4df45dc005bd6fa23b50256afd63abe3c832376 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 26 12:01:19 2016 -0500 mainboard/google/reef: increase BIOS region size An updated descriptor expands the BIOS region while descreasing the 'device expansion region' utilized by the CSE. Update the end region marker to reflect this new size as well as the chromeos.fmd file which needs to be adjusted for logical boot parition 2 requirement which resides halfway through the BIOS region. Change-Id: I7baa5282d7c608af648b5773c4dfa123060a6e45 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 2 +- src/mainboard/google/reef/chromeos.fmd | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index e49e8b6..5d8ded6 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -19,7 +19,7 @@ config BOOT_MEDIA_SPI_BUS config IFD_BIOS_END hex - default 0x6FF000 + default 0x77F000 config IFD_BIOS_START hex diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index a3fb8b5..95b28c9 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -10,9 +10,9 @@ FLASH 8M { RO_FRID@0x4800 0x40 RO_FRID_PAD@0x4840 0x7c0 COREBOOT(CBFS)@0x5000 0x17b000 + GBB@0x180000 0x70000 # logical boot partition 2. Remove with updated CSE - SIGN_CSE@0x180000 0x10000 - GBB@0x190000 0x70000 + SIGN_CSE@0x1f0000 0x10000 } } MISC_RW@0x400000 0x1a000 { @@ -34,6 +34,6 @@ FLASH 8M { FW_MAIN_B(CBFS)@0x10000 0x162fc0 RW_FWID_B@0x172fc0 0x40 } - DEVICE_EXTENSION@0x700000 0x100000 + DEVICE_EXTENSION@0x77f000 0x80000 }

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Patch set updated for coreboot: mainboard/google/reef: support verstage
by Aaron Durbin 26 May '16

26 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14973 -gerrit commit 4efa5182a125969ef974cf2660874111edfef2b5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 26 11:02:56 2016 -0500 mainboard/google/reef: support verstage The chromeos.c suport needs to be linked into verstage so it will link. Change-Id: If85e232a3721443edfbbd278b32f72302f13f3a8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc index b38a4e6..f8fbbf3 100644 --- a/src/mainboard/google/reef/Makefile.inc +++ b/src/mainboard/google/reef/Makefile.inc @@ -6,3 +6,5 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c

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Patch set updated for coreboot: soc/intel/apollolake: add support for verstage
by Aaron Durbin 26 May '16

26 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14972 -gerrit commit 6ea57b993465cb7f47046315aeea023c496a613c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 26 11:00:44 2016 -0500 soc/intel/apollolake: add support for verstage There previously was no support for building verstage on apollolake. Add that suport by linking in the appropriate modules as well as providing vboot_platform_is_resuming(). The link address for verstage is the same as FSP-M because they would never be in CAR along side each other. Additionally, program the ACPI I/O BAR and enable decoding so sleep state can be determined for early firmware verification. Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Kconfig | 6 ++++++ src/soc/intel/apollolake/Makefile.inc | 6 ++++++ src/soc/intel/apollolake/bootblock/bootblock.c | 6 ++++++ src/soc/intel/apollolake/pmutil.c | 12 ++++++++++++ 4 files changed, 30 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4643887..d6c5ffc 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -123,6 +123,12 @@ config ROMSTAGE_ADDR help The base address (in CAR) where romstage should be linked +config VERSTAGE_ADDR + hex + default 0xfef60000 + help + The base address (in CAR) where verstage should be linked + config CACHE_MRC_SETTINGS bool default y diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 80617a7..b8f0c18 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -56,6 +56,12 @@ postcar-y += mmap_boot.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c +verstage-y += memmap.c +verstage-y += mmap_boot.c +verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +verstage-y += tsc_freq.c +verstage-y += pmutil.c + CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include # Since FSP-M runs in CAR we need to relocate it to a specific address diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 8279432..b8d6f22 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -67,6 +67,12 @@ void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo) pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + /* Decode the ACPI I/O port range for early firmware verification.*/ + dev = PMC_DEV; + pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MASTER); + /* Call lib/bootblock.c main */ bootblock_main_with_timestamp(((uint64_t)tsc_hi << 32) | tsc_lo); } diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 16c8a04..9340ba5 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -26,6 +26,7 @@ #include <soc/pm.h> #include <device/device.h> #include <device/pci.h> +#include <vendorcode/google/chromeos/vboot_common.h> static uintptr_t read_pmc_mmio_bar(void) { @@ -336,3 +337,14 @@ int fill_power_state(struct chipset_power_state *ps) printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps->prev_sleep_state; } + +int vboot_platform_is_resuming(void) +{ + int typ; + + if (!(inw(ACPI_PMIO_BASE + PM1_STS) & WAK_STS)) + return 0; + + typ = (inl(ACPI_PMIO_BASE + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT; + return typ == SLP_TYP_S3; +}

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Patch set updated for coreboot: arch/x86: provide verstage support for CONFIG_C_ENVIRONMENT_BOOTBLOCK
by Aaron Durbin 26 May '16

26 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14971 -gerrit commit 8a64bd14d4438a12173f25d86832f91d9bddfb53 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 26 10:55:48 2016 -0500 arch/x86: provide verstage support for CONFIG_C_ENVIRONMENT_BOOTBLOCK When CONFIG_C_ENVIRONMENT_BOOTBLOCK is employed there's no need for a chipset specific verstage entry point because cache-as-ram has already been initialized. Therefore, provide a default entry point for verstage in that environment. Change-Id: Idd8f45bd58d3e5b251d1e38cca7ae794b8b77a28 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 4 ++++ src/arch/x86/verstage.c | 23 +++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 536caa3..28bb8ea 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -178,6 +178,10 @@ verstage-y += memset.c verstage-y += memcpy.c verstage-y += memmove.c verstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c +# If C environment is used for bootblock it means there's no need +# for a chipset-specific car_stage_entry() so use the generic one +# which just calls verstage(). +verstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += verstage.c verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c diff --git a/src/arch/x86/verstage.c b/src/arch/x86/verstage.c new file mode 100644 index 0000000..a44bf0f --- /dev/null +++ b/src/arch/x86/verstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Provide an entry point for verstage when it's a separate stage. */ +void asmlinkage car_stage_entry(void) +{ + verstage(); +}

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Patch set updated for coreboot: mainboard/google/reef: increase BIOS region size
by Aaron Durbin 26 May '16

26 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14974 -gerrit commit 0081f1cd2f737e41bf62477b187a8ed7c918c2c0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 26 12:01:19 2016 -0500 mainboard/google/reef: increase BIOS region size An updated descriptor expands the BIOS region while descreasing the 'device expansion region' utilized by the CSE. Update the end region marker to reflect this new size as well as the chromeos.fmd file which needs to be adjusted for logical boot parition 2 requirement which resides halfway through the BIOS region. Change-Id: I7baa5282d7c608af648b5773c4dfa123060a6e45 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 2 +- src/mainboard/google/reef/chromeos.fmd | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index e49e8b6..5d8ded6 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -19,7 +19,7 @@ config BOOT_MEDIA_SPI_BUS config IFD_BIOS_END hex - default 0x6FF000 + default 0x77F000 config IFD_BIOS_START hex diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index a3fb8b5..95b28c9 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -10,9 +10,9 @@ FLASH 8M { RO_FRID@0x4800 0x40 RO_FRID_PAD@0x4840 0x7c0 COREBOOT(CBFS)@0x5000 0x17b000 + GBB@0x180000 0x70000 # logical boot partition 2. Remove with updated CSE - SIGN_CSE@0x180000 0x10000 - GBB@0x190000 0x70000 + SIGN_CSE@0x1f0000 0x10000 } } MISC_RW@0x400000 0x1a000 { @@ -34,6 +34,6 @@ FLASH 8M { FW_MAIN_B(CBFS)@0x10000 0x162fc0 RW_FWID_B@0x172fc0 0x40 } - DEVICE_EXTENSION@0x700000 0x100000 + DEVICE_EXTENSION@0x77f000 0x80000 }

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Patch set updated for coreboot: Added CL7 support
by HAOUAS Elyes 26 May '16

26 May '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14976 -gerrit commit 35c0b28f3d6f6349a29546c925a1015dfb97bc3a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu May 26 19:53:29 2016 +0200 Added CL7 support according to "JEDEC_DDR2_SPD_Specification_Rev1.3.pdf" Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3) page 16 and page 60, CL7 support added Change-Id: I22aaf064ab8767755f74dfdb44e32d13fc61b2c4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/include/spd.h | 1 + src/include/spd_ddr2.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/include/spd.h b/src/include/spd.h index ea1b355..7aaf4dd 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -145,6 +145,7 @@ enum spd_memory_type { #define SPD_CAS_LATENCY_DDR2_4 (1 << 4) #define SPD_CAS_LATENCY_DDR2_5 (1 << 5) #define SPD_CAS_LATENCY_DDR2_6 (1 << 6) +#define SPD_CAS_LATENCY_DDR2_7 (1 << 7) /* SPD_SUPPORTED_BURST_LENGTHS values. */ #define SPD_BURST_LENGTH_1 1 diff --git a/src/include/spd_ddr2.h b/src/include/spd_ddr2.h index 21aacf6..a31b4aa 100644 --- a/src/include/spd_ddr2.h +++ b/src/include/spd_ddr2.h @@ -80,6 +80,7 @@ #define SPD_CAS_LAT_4 (1<<4) #define SPD_CAS_LAT_5 (1<<5) #define SPD_CAS_LAT_6 (1<<6) + #define SPD_CAS_LAT_7 (1<<7) #define SPD_TRP 27 /* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) + (val & 3) * 0.25)ns */ #define SPD_TRRD 28

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coreboot-gerrit May 2016