coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: sio/winbond/w83667hg-a: Add pinmux defines for UART B
by Martin Roth 27 May '16

27 May '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14965 -gerrit commit 3210de4e7b294d2c25872b8cfc264029ca5b55a2 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Wed May 25 10:22:10 2016 -0500 sio/winbond/w83667hg-a: Add pinmux defines for UART B Change-Id: Ib98c69de781d2b651ec168d03250cacc918c5c1f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/superio/winbond/w83667hg-a/w83667hg-a.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/superio/winbond/w83667hg-a/w83667hg-a.h b/src/superio/winbond/w83667hg-a/w83667hg-a.h index 0c0d427..d4e7110 100644 --- a/src/superio/winbond/w83667hg-a/w83667hg-a.h +++ b/src/superio/winbond/w83667hg-a/w83667hg-a.h @@ -18,6 +18,13 @@ #ifndef SUPERIO_WINBOND_W83667HG_A #define SUPERIO_WINBOND_W83667HG_A +/* Pinmux configuration defines */ +#define W83667HG_SPI_PINMUX_OFFSET 0x2a + +#define W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK (1 << 2) +#define W83667HG_SPI_PINMUX_GPIO4 (0 << 2) +#define W83667HG_SPI_PINMUX_SERIAL_B (1 << 2) + /* Logical Device Numbers (LDN). */ #define W83667HG_A_FDC 0x00 #define W83667HG_A_PP 0x01

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Patch set updated for coreboot: sio/winbond/common: Add function to configure pin mux
by Martin Roth 27 May '16

27 May '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14960 -gerrit commit b5a057ea74bbffcca7b43623e66d240da68df5b0 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Tue May 24 15:48:50 2016 -0500 sio/winbond/common: Add function to configure pin mux Certain mainboards require SuperIO pinmux configuration before peripherals will become operational. Allow each mainboard to configure the pinmux(es) of Winbond chips if needed. Change-Id: Ice19f8d8514b66b15920a5b893700d636ed75cec Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- 3rdparty/blobs | 2 +- src/superio/winbond/common/early_serial.c | 13 +++++++++++++ src/superio/winbond/common/winbond.h | 3 ++- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index cca0337..b0eeddd 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit cca0337ea0fba8a07a73ad1627338dd5738f4d3f +Subproject commit b0eeddd4f5c583818e66521f2552cd3448b357b2 diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_serial.c index 6482a94..aebbd38 100644 --- a/src/superio/winbond/common/early_serial.c +++ b/src/superio/winbond/common/early_serial.c @@ -66,3 +66,16 @@ void winbond_enable_serial(pnp_devfn_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); } + +void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state) +{ + uint8_t byte; + + /* Configure pin mux */ + pnp_enter_conf_state(dev); + byte = pnp_read_config(dev, offset); + byte &= ~mask; + byte |= state; + pnp_write_config(dev, offset, byte); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h index 1f7e7b1..6e67eeb 100644 --- a/src/superio/winbond/common/winbond.h +++ b/src/superio/winbond/common/winbond.h @@ -20,7 +20,8 @@ #include <arch/io.h> #include <stdint.h> -void winbond_enable_serial(pnp_devfn_t dev, u16 iobase); +void winbond_enable_serial(pnp_devfn_t dev, uint16_t iobase); +void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state); void pnp_enter_conf_state(pnp_devfn_t dev); void pnp_exit_conf_state(pnp_devfn_t dev);

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Patch merged into coreboot/master: soc/intel/apollolake: Provide No Connect macro for unused Pad
by gerrit＠coreboot.org 26 May '16

26 May '16

the following patch was just integrated into master: commit a9ac2d9b914d849b207d3f6c73892240017bf932 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Fri May 20 19:28:59 2016 -0700 soc/intel/apollolake: Provide No Connect macro for unused Pad Change-Id: Iba506054a3d631c8e538d44e1ca6877dd02c2ca9 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Reviewed-on: https://review.coreboot.org/14956 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14956 for details. -gerrit

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Patch merged into coreboot/master: MAINTAINERS: Add myself for Apollolake SoC, FSP2.0, and Amenia mb
by gerrit＠coreboot.org 26 May '16

26 May '16

the following patch was just integrated into master: commit 842dfe8d63d994681fddc70076cefafbe5b941a9 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue May 24 22:01:56 2016 -0700 MAINTAINERS: Add myself for Apollolake SoC, FSP2.0, and Amenia mb Change-Id: I9931263f0f51d6c726bd7c72042fae1155affb6e Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/14963 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/14963 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: enable RTC
by gerrit＠coreboot.org 26 May '16

26 May '16

the following patch was just integrated into master: commit b6b233a6e545e9da8ba1372979df69cf2bdc007f Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Tue May 17 18:06:49 2016 -0700 soc/intel/apollolake: enable RTC BUG=none TEST=Boot to OS and verfiy if rtc0 device is created under /sys/class/rtc/ Change-Id: Idec569255859816fda467bb42a215c00f7c0e16e Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Reviewed-on: https://review.coreboot.org/14883 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14883 for details. -gerrit

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Patch merged into coreboot/master: cbfstool: Move cbfs_file_get_header to fit.c
by gerrit＠coreboot.org 26 May '16

26 May '16

the following patch was just integrated into master: commit 1ac194e14a90563635b0a0a6a82ada87dcb8dbde Author: Furquan Shaikh <furquan(a)google.com> Date: Mon May 23 08:44:46 2016 -0700 cbfstool: Move cbfs_file_get_header to fit.c Since fit.c is the only caller of this function move it out of common.c and into fit.c. Change-Id: I64cc31a6d89ee425c5b07745ea5ca9437e2f3fcf Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/14949 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/14949 for details. -gerrit

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Patch merged into coreboot/master: drivers/intel/fsp2_0: Send post codes around calls to the blobs
by gerrit＠coreboot.org 26 May '16

26 May '16

the following patch was just integrated into master: commit c4ea8f7d3fb56b43482b8abd8405280f50d98864 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon May 23 12:16:58 2016 -0700 drivers/intel/fsp2_0: Send post codes around calls to the blobs By design, FSP will send POST codes to port 80. In this case we have both coreboot and FSP pushing post codes, which may make debugging harder. In order to get a clear picture of where FSP execution begins and ends, send post codes before and after any call to the FSP blobs. Note that sending a post code both before and after is mostly useful on chromeec enabled boards, where the EC console will provide a historic list of post codes. Change-Id: Icfd22b4f6d9e91b01138f97efd711d9204028eb1 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Reviewed-on: https://review.coreboot.org/14951 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/14951 for details. -gerrit

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Patch merged into coreboot/master: splash: Put the suffix of splash file to CBFS name
by gerrit＠coreboot.org 26 May '16

26 May '16

the following patch was just integrated into master: commit c16918ac11c32338ba99656ec47ca05e26a731ac Author: zbao <fishbaozi(a)gmail.com> Date: Sat May 21 10:20:58 2016 +0800 splash: Put the suffix of splash file to CBFS name The previous code harded the suffix of splash file as "jpg". Actually, SeaBIOS supports both jpg and bmp. Change-Id: I06c4b14aae7f75be3406652a94612b5f30ce91c2 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/14932 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14932 for details. -gerrit

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Patch merged into coreboot/master: soc/apollolake: Use simpler macros for the northbridge PCI device
by gerrit＠coreboot.org 26 May '16

26 May '16

the following patch was just integrated into master: commit 944655dadaf595bf655f266eb35ca2f17c8410eb Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed May 18 10:26:53 2016 -0700 soc/apollolake: Use simpler macros for the northbridge PCI device The NB_DEV_ROOT macro, is almost unreadable, as it depends on other stringified macros, and acts differently depending on the coreboot stage. For ramstage, it also hides a function call. Rewrite the macro in terms of more basic and readable macros. Change-Id: I9b7071d67c8d58926e9b01fadaa239db1120448c Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Reviewed-on: https://review.coreboot.org/14890 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14890 for details. -gerrit

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Patch merged into coreboot/master: soc/apollolake/memmap: Switch to SIMPLE_DEVICE API
by gerrit＠coreboot.org 26 May '16

26 May '16

the following patch was just integrated into master: commit bbac5ace53d57ad9acb0f979850c6a5e72c5f874 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon May 23 14:04:58 2016 -0700 soc/apollolake/memmap: Switch to SIMPLE_DEVICE API memmap.c functionality is designed to be used in more than ramstage. Therefore, it cannot use ramstage-specific APIs. In this case, the SIMPLE_DEVICE API offers a more consistent behavior across stages. Change-Id: Ic381fe1eb773fb0a5fb5887eb67d2228d2f0817d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Reviewed-on: https://review.coreboot.org/14953 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14953 for details. -gerrit

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coreboot-gerrit May 2016