coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: [UNVERIFIED] lb_new_record: Make sure that records are 8-byte aligned
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14985 -gerrit commit 1e795cad1e0e1579c60c329a58147b301f4b8819 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:03 2016 +0200 [UNVERIFIED] lb_new_record: Make sure that records are 8-byte aligned Some records contain uint64_t fields that could trigger an unaligned memory access fault on RISC-V. I have not yet tested whether this patch breaks any other architectures. Change-Id: I54ff68ca00009a0977249adc839fadc4a1d6881d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/lib/coreboot_table.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 3af2be6..cf37776 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -87,6 +87,10 @@ struct lb_record *lb_new_record(struct lb_header *header) struct lb_record *rec; rec = lb_last_record(header); if (header->table_entries) { + /* Make sure that the next record is sufficiently aligned to + * avoid an unaligned memory access. */ + rec->size = ALIGN_UP(rec->size, sizeof(uint64_t)); + header->table_bytes += rec->size; } rec = lb_last_record(header);

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Patch set updated for coreboot: commonlib/lz4: Avoid unaligned memory access on RISC-V
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14983 -gerrit commit d2708336d2645dc06d03aec17c1cf4085089cc4c Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:02 2016 +0200 commonlib/lz4: Avoid unaligned memory access on RISC-V From the User-Level ISA Specification v2.0: "We do not mandate atomicity for misaligned accesses so simple implementations can just use a machine trap and software handler to handle misaligned accesses." (— http://riscv.org/specifications/) Spike traps on unaligned accesses. Change-Id: Ia57786916f4076cc08513f4e331c2deec9cfa785 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/commonlib/lz4_wrapper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/lz4_wrapper.c index 772f791..93fa7e8 100644 --- a/src/commonlib/lz4_wrapper.c +++ b/src/commonlib/lz4_wrapper.c @@ -63,6 +63,11 @@ static void LZ4_copy8(void *dst, const void *src) : [src]"r"(src), [dst]"r"(dst) : "memory" ); #endif +#elif defined(__riscv__) + /* RISC-V implementations may trap on any unaligned access. */ + int i; + for (i = 0; i < 8; i++) + ((uint8_t *)dst)[i] = ((uint8_t *)src)[i]; #else *(uint64_t *)dst = *(const uint64_t *)src; #endif

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New patch to review for coreboot: [DO NOT MERGE] Some workarounds for RISC-V incompatibilities
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14986 -gerrit commit 6e536db013b7eb172676429d9f06de4399b36e48 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:03 2016 +0200 [DO NOT MERGE] Some workarounds for RISC-V incompatibilities Our current GCC port uses newer CSR numbers that don't work with Spike 3bfc00ef anymore, but newer Spike versions introduce some weirdness that I have to understand before switching to them. I'm submitting this patch to Gerrit so that others can use it locally if they want to run coreboot in Spike. Change-Id: I7fe5358738cef08a8ce0a789928b24fdfd2e481c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/bootblock.S | 4 ++-- src/drivers/uart/htif.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 029e9e4..7185e29 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -39,7 +39,7 @@ _start: # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE - csrr a0, mhartid + csrr a0, CSR_MHARTID call hls_init //poison the stack @@ -48,7 +48,7 @@ _start: sd t0, 0(t1) la t0, exception_handler - csrw stvec, t0 + csrw CSR_STVEC, t0 # clear any pending interrupts csrwi sip, 0 diff --git a/src/drivers/uart/htif.c b/src/drivers/uart/htif.c index 7533981..8bd9f8f 100644 --- a/src/drivers/uart/htif.c +++ b/src/drivers/uart/htif.c @@ -42,11 +42,11 @@ void uart_tx_byte(int idx, unsigned char data) return; /* Device 1: console; command 1: write */ - write_csr(mtohost, TOHOST_CMD(1, 1, data)); + write_csr(0x780, TOHOST_CMD(1, 1, data)); /* Read from mfromhost to avoid some kind of race condition when * characters are printed to fast */ - read_csr(mfromhost); + read_csr(0x781); } unsigned char uart_rx_byte(int idx)

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New patch to review for coreboot: [UNVERIFIED] lb_new_record: Make sure that records are 8-byte aligned
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14985 -gerrit commit d79d0e2abe4ca3e30d14cf2c5579e159c88fee8f Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:03 2016 +0200 [UNVERIFIED] lb_new_record: Make sure that records are 8-byte aligned Some records contain uint64_t fields that could trigger an unaligned memory access fault on RISC-V. I have not yet tested whether this patch breaks any other architectures. Change-Id: I54ff68ca00009a0977249adc839fadc4a1d6881d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/lib/coreboot_table.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 3af2be6..cf37776 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -87,6 +87,10 @@ struct lb_record *lb_new_record(struct lb_header *header) struct lb_record *rec; rec = lb_last_record(header); if (header->table_entries) { + /* Make sure that the next record is sufficiently aligned to + * avoid an unaligned memory access. */ + rec->size = ALIGN_UP(rec->size, sizeof(uint64_t)); + header->table_bytes += rec->size; } rec = lb_last_record(header);

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New patch to review for coreboot: lib/hardwaremain: Add \n to "Boot failed" message
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14984 -gerrit commit ef5d6e7171ddb6a2c87300c8bf6e4b40761f3d5b Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:02 2016 +0200 lib/hardwaremain: Add \n to "Boot failed" message Change-Id: I106fccd725a5c944f4e8e0f196b31c9344f588c7 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/lib/hardwaremain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 10ef96c..ab4d9f4 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -227,7 +227,7 @@ static boot_state_t bs_payload_boot(void *arg) { payload_run(); - printk(BIOS_EMERG, "Boot failed"); + printk(BIOS_EMERG, "Boot failed\n"); /* Returning from this state will fail because the following signals * return to a completed state. */ return BS_PAYLOAD_BOOT;

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New patch to review for coreboot: commonlib/lz4: Avoid unaligned memory access on RISC-V
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14983 -gerrit commit a898edc645d73caffd2182b82b19c26ff71fad96 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:02 2016 +0200 commonlib/lz4: Avoid unaligned memory access on RISC-V From the User-Level ISA Specification v2.0: "We do not mandate atomicity for misaligned accesses so simple implementations can just use a machine trap and software handler to handle misaligned accesses." (— http://riscv.org/specifications/) Spike traps on unaligned accesses. Change-Id: Ia57786916f4076cc08513f4e331c2deec9cfa785 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/commonlib/lz4_wrapper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/lz4_wrapper.c index 772f791..ad014fa 100644 --- a/src/commonlib/lz4_wrapper.c +++ b/src/commonlib/lz4_wrapper.c @@ -63,6 +63,10 @@ static void LZ4_copy8(void *dst, const void *src) : [src]"r"(src), [dst]"r"(dst) : "memory" ); #endif +#elif __riscv__ /* RISC-V implementations may trap on any unaligned access. */ + int i; + for (i = 0; i < 8; i++) + ((uint8_t *)dst)[i] = ((uint8_t *)src)[i]; #else *(uint64_t *)dst = *(const uint64_t *)src; #endif

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New patch to review for coreboot: [DO NOT MERGE] Add new RISC-V HTIF console driver
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14982 -gerrit commit f8471fc66b2c966e8482a3ff3e24812193f96a63 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:02 2016 +0200 [DO NOT MERGE] Add new RISC-V HTIF console driver The HTIF is already deprecated and has been removed in newer versions of Spike. In the older Spike 3bfc00ef this driver works. Maybe src/drivers/emulation/riscv would be a better place. Change-Id: I8b25829e8cc17ec9604c6e1391a2f96eefe71d07 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/drivers/uart/Kconfig | 9 ++++++ src/drivers/uart/Makefile.inc | 7 ++++ src/drivers/uart/htif.c | 75 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 91 insertions(+) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 4faa48d..12514b9 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -73,3 +73,12 @@ config UART_PCI_ADDR * Bus << 20 * Device << 15 * Function << 12 + +config DRIVERS_UART_HTIF + bool "RISC-V HTIF console" + default n + depends on ARCH_RISCV + help + Support for the console part of the RISC-V Host-Target Interface. + + Currently, only output is implemented. diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 4b2aa53..232e80a 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -36,4 +36,11 @@ romstage-y += pl011.c ramstage-y += pl011.c endif +ifeq ($(CONFIG_DRIVERS_UART_HTIF),y) +bootblock-y += htif.c +verstage-y += htif.c +romstage-y += htif.c +ramstage-y += htif.c +endif + endif diff --git a/src/drivers/uart/htif.c b/src/drivers/uart/htif.c new file mode 100644 index 0000000..7533981 --- /dev/null +++ b/src/drivers/uart/htif.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/encoding.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <console/uart.h> +#include <delay.h> +#include <device/device.h> +#include <rules.h> +#include <spike_util.h> +#include <stdint.h> + +/* Driver for console output over RISC-V's Host-Target Interface (HTIF) */ + +uintptr_t uart_platform_base(int idx) +{ + if (idx == 0) + return CSR_MTOHOST; + return 0; +} + +void uart_init(int idx) +{ +} + +void uart_tx_byte(int idx, unsigned char data) +{ + if (idx != 0) + return; + + /* Device 1: console; command 1: write */ + write_csr(mtohost, TOHOST_CMD(1, 1, data)); + + /* Read from mfromhost to avoid some kind of race condition when + * characters are printed to fast */ + read_csr(mfromhost); +} + +unsigned char uart_rx_byte(int idx) +{ + // not yet implemented + return 0; +} + +void uart_tx_flush(int idx) +{ +} + +#if ENV_RAMSTAGE +void uart_fill_lb(void *data) +{ + /* bogus: */ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_IO_MAPPED; + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial.baud = default_baudrate(); + serial.regwidth = sizeof(uint8_t); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif

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New patch to review for coreboot: [UNVERIFIED] mb/emulation/*-riscv: Use new "mipi" CSR name
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14981 -gerrit commit 5a9de06004bcc685ce5655eed89b1b41d7171cff Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:02 2016 +0200 [UNVERIFIED] mb/emulation/*-riscv: Use new "mipi" CSR name I don't know the exact semantics, because the Privileged Spec 1.9 (which defines this CSR) hasn't been publicly released yet. Change-Id: Ice369536d8ae9f46797b9f936f45ed6d7c511de6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/qemu-riscv/qemu_util.c | 2 +- src/mainboard/emulation/spike-riscv/spike_util.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/emulation/qemu-riscv/qemu_util.c b/src/mainboard/emulation/qemu-riscv/qemu_util.c index fca7d56..41a5d62 100644 --- a/src/mainboard/emulation/qemu-riscv/qemu_util.c +++ b/src/mainboard/emulation/qemu-riscv/qemu_util.c @@ -60,7 +60,7 @@ uintptr_t mcall_send_ipi(uintptr_t recipient) if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) { mb(); - write_csr(send_ipi, recipient); + write_csr(mipi, recipient); } return 0; diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index fca7d56..41a5d62 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -60,7 +60,7 @@ uintptr_t mcall_send_ipi(uintptr_t recipient) if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) { mb(); - write_csr(send_ipi, recipient); + write_csr(mipi, recipient); } return 0;

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Patch set updated for coreboot: util/riscvtools: Add script that turns coreboot.rom into an ELF
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14964 -gerrit commit 5d736677ac9d0e7b36021395403322ec19043b3c Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:03 2016 +0200 util/riscvtools: Add script that turns coreboot.rom into an ELF This is required because the current version of SPIKE doesn't support loading flat files yet. Change-Id: If745d78712ca8108b5dcc21591201bc2d3f70b86 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- util/riscvtools/make-spike-elf.sh | 27 +++++++++++++++++++++++++++ util/riscvtools/spike-elf.ld | 11 +++++++++++ 2 files changed, 38 insertions(+) diff --git a/util/riscvtools/make-spike-elf.sh b/util/riscvtools/make-spike-elf.sh new file mode 100755 index 0000000..4241c54 --- /dev/null +++ b/util/riscvtools/make-spike-elf.sh @@ -0,0 +1,27 @@ +#!/bin/sh +# +# This script is based on: +# https://docs.google.com/document/d/1Pvf9Yxorcd3sbgs8WcomcTl3J4bmX6e1UE0ROCe… + +set -e + +usage() { + echo "This script converts a flat file into an ELF, that can be passed" + echo "to SPIKE, the RISC-V reference emulator." + echo "" + echo "Usage: $0 coreboot.rom coreboot.elf" +} + +if [ $# -ne 2 ]; then + usage + exit 1 +fi + +FLAT_FILE="$1" +OBJECT_FILE=$(mktemp /tmp/coreboot-spike.XXXXXX.o) +ELF_FILE="$2" +TOOL_PATH="$(dirname "$0")" + +objcopy -I binary -O elf32-i386 --binary-architecture i386 "$FLAT_FILE" "$OBJECT_FILE" +ld -m elf_i386 "$OBJECT_FILE" -T "$TOOL_PATH/spike-elf.ld" -o "$ELF_FILE" +rm "$OBJECT_FILE" diff --git a/util/riscvtools/spike-elf.ld b/util/riscvtools/spike-elf.ld new file mode 100644 index 0000000..c103136 --- /dev/null +++ b/util/riscvtools/spike-elf.ld @@ -0,0 +1,11 @@ +/* See make-spike-elf.sh */ + +ENTRY(_start); +SECTIONS +{ + _start = 0x0000; + . = 0x0000; + .data : { + *(.data) + } +}

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Patch set updated for coreboot: arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constant
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14962 -gerrit commit a4751089207fd5b47d946d79fbcbb28f87884a65 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:03 2016 +0200 arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constant Change-Id: I9759771fa6fc708d7d97509c5f5e0cefb8ab4c96 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/trap_util.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index bc09dc9..0118ffc 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -108,7 +108,7 @@ supervisor_trap_entry: csrw mscratch, sp # load in the top of the machine stack - la sp, 0x80FFF0 - 64 + li sp, 0x80FFF0 - 64 1:addi sp,sp,-320 save_tf move a0,sp

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coreboot-gerrit May 2016