coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

1 participants
1843 discussions

Patch merged into coreboot/master: broadwell/me: Fix out-of-bounds array access error
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit aa431c0e1774a34b0b6dacd9b0d44de3c82d4922 Author: Evan Lojewski <meklort(a)meklort.com> Date: Mon Apr 18 20:19:03 2016 -0600 broadwell/me: Fix out-of-bounds array access error Fix an issue where a broadwell machine without the ME installed could result in an invalid status code being reported. For certain values, this would result in the intel_me_status function never returning. Fix has been tested on a samus board w and w/o the ME blob installed. Change-Id: I96667d3b89393f161e4d4efe0544efac98367e6c Signed-off-by: Evan Lojewski <meklort(a)gmail.com> Reviewed-on: https://review.coreboot.org/14409 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)google.com> See https://review.coreboot.org/14409 for details. -gerrit

1 0

New patch to review for coreboot: {cpu, soc}/intel: remove unused smm_init() function
by Aaron Durbin 04 May '16

04 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14605 -gerrit commit 6b9e0b52e625fbbe5b01d5442d511d212bf7048c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 4 09:00:13 2016 -0500 {cpu,soc}/intel: remove unused smm_init() function There used to be a need for an empty smm_init() function because initialize_cpus() called it even though nothing called initialize_cpus(). However, garbage collection at link time is implemented so there's no reason to provide an empty function to satisfy a symbol that is completely culled during link. Remove it. Change-Id: Ic13c85f1d3d57e38e7132e4289a98a95829f765a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/smmrelocate.c | 9 --------- src/soc/intel/baytrail/placeholders.c | 3 --- src/soc/intel/braswell/smm.c | 4 ---- src/soc/intel/broadwell/smmrelocate.c | 9 --------- src/soc/intel/fsp_baytrail/placeholders.c | 4 ---- src/soc/intel/skylake/smmrelocate.c | 11 ----------- 6 files changed, 40 deletions(-) diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 5c50ad1c..34a3551 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -352,15 +352,6 @@ void smm_relocate(void) smm_initiate_relocation(); } -void smm_init(void) -{ - /* smm_init() is normally called from initialize_cpus() in - * lapic_cpu_init.c. However, that path is no longer used. Don't reuse - * the function name because that would cause confusion. - * The smm_initialize() function above is used to setup SMM at the - * appropriate time. */ -} - void smm_lock(void) { /* LOCK the SMM memory window and enable normal SMM. diff --git a/src/soc/intel/baytrail/placeholders.c b/src/soc/intel/baytrail/placeholders.c index 500ced2..b110f5f 100644 --- a/src/soc/intel/baytrail/placeholders.c +++ b/src/soc/intel/baytrail/placeholders.c @@ -17,8 +17,5 @@ #include <device/pci_rom.h> #include <soc/acpi.h> - -void smm_init(void) {} - /* Rmodules don't like weak symbols. */ u32 map_oprom_vendev(u32 vendev) { return vendev; } diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index 8318050..3a7ab1c 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -29,10 +29,6 @@ /* Save settings which will be committed in SMI functions. */ static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT]; -void smm_init(void) -{ -} - void southcluster_smm_save_param(int param, uint32_t data) { smm_save_params[param] = data; diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 0cc6399..6fd609b 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -316,15 +316,6 @@ void smm_relocate(void) smm_initiate_relocation(); } -void smm_init(void) -{ - /* smm_init() is normally called from initialize_cpus() in - * lapic_cpu_init.c. However, that path is no longer used. Don't reuse - * the function name because that would cause confusion. - * The smm_initialize() function above is used to setup SMM at the - * appropriate time. */ -} - void smm_lock(void) { /* LOCK the SMM memory window and enable normal SMM. diff --git a/src/soc/intel/fsp_baytrail/placeholders.c b/src/soc/intel/fsp_baytrail/placeholders.c index 248aba2..587f0e9 100644 --- a/src/soc/intel/fsp_baytrail/placeholders.c +++ b/src/soc/intel/fsp_baytrail/placeholders.c @@ -20,9 +20,5 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) -void smm_init(void) {} -#endif - /* Rmodules don't like weak symbols. */ u32 map_oprom_vendev(u32 vendev) { return vendev; } diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index fcb89de..9428dcc 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -302,17 +302,6 @@ void smm_relocate(void) smm_initiate_relocation(); } -void smm_init(void) -{ - /* - * smm_init() is normally called from initialize_cpus() in - * lapic_cpu_init.c. However, that path is no longer used. Don't reuse - * the function name because that would cause confusion. - * The smm_initialize() function above is used to setup SMM at the - * appropriate time. - */ -} - void smm_lock(void) { /*

1 0

Patch set updated for coreboot: cpu/x86: remove BACKUP_DEFAULT_SMM_REGION option
by Aaron Durbin 04 May '16

04 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14561 -gerrit commit d1afc4d0dbb686cee8a927d7934892a0ebe16cfb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Apr 30 15:14:18 2016 -0500 cpu/x86: remove BACKUP_DEFAULT_SMM_REGION option Unconditionally provide the backup default SMM area API. There's no reason to guard the symbols behind anything since linker garbage collection is implemented. A board or chipset is free to use the code or not without needing to select an option. Change-Id: I14cf1318136a17f48ba5ae119507918190e25387 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/Kconfig | 1 - src/cpu/x86/Kconfig | 6 ---- src/cpu/x86/Makefile.inc | 1 + src/cpu/x86/backup_default_smm.c | 64 ++++++++++++++++++++++++++++++++++++ src/cpu/x86/smm/Makefile.inc | 1 - src/cpu/x86/smm/backup_default_smm.c | 64 ------------------------------------ src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/skylake/Kconfig | 1 - 10 files changed, 65 insertions(+), 76 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 779f1d6..ec75391 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -10,7 +10,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select BACKUP_DEFAULT_SMM_REGION select HAVE_MONOTONIC_TIMER select SMP select MMX diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 6cd65cc..e80f02b 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -127,12 +127,6 @@ config PLATFORM_USES_FSP1_0 Selected for Intel processors/platform combinations that use the Intel Firmware Support Package (FSP) 1.0 for initialization. -config BACKUP_DEFAULT_SMM_REGION - def_bool n - help - The CPU support will select this option if the default SMM region - needs to be backed up for suspend/resume purposes. - config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING def_bool n help diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 0efbdd7..1724a06 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -5,6 +5,7 @@ endif subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c +ramstage-y += backup_default_smm.c additional-dirs += $(obj)/cpu/x86 diff --git a/src/cpu/x86/backup_default_smm.c b/src/cpu/x86/backup_default_smm.c new file mode 100644 index 0000000..2023aed --- /dev/null +++ b/src/cpu/x86/backup_default_smm.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <cbmem.h> +#include <cpu/x86/smm.h> + +void *backup_default_smm_area(void) +{ + void *save_area; + const void *default_smm = (void *)SMM_DEFAULT_BASE; + + if (!IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + return NULL; + + /* + * The buffer needs to be preallocated regardless. In the non-resume + * path it will be allocated for handling resume. Note that cbmem_add() + * does a find before the addition. + */ + save_area = cbmem_add(CBMEM_ID_SMM_SAVE_SPACE, SMM_DEFAULT_SIZE); + + if (save_area == NULL) { + printk(BIOS_DEBUG, "SMM save area not added.\n"); + return NULL; + } + + /* Only back up the area on S3 resume. */ + if (acpi_is_wakeup_s3()) { + memcpy(save_area, default_smm, SMM_DEFAULT_SIZE); + return save_area; + } + + /* + * Not the S3 resume path. No need to restore memory contents after + * SMM relocation. + */ + return NULL; +} + +void restore_default_smm_area(void *smm_save_area) +{ + void *default_smm = (void *)SMM_DEFAULT_BASE; + + if (smm_save_area == NULL) + return; + + memcpy(default_smm, smm_save_area, SMM_DEFAULT_SIZE); +} diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 72c9796..32f5ea7 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -13,7 +13,6 @@ ## GNU General Public License for more details. ## -ramstage-$(CONFIG_BACKUP_DEFAULT_SMM_REGION) += backup_default_smm.c ramstage-y += smm_module_loader.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) diff --git a/src/cpu/x86/smm/backup_default_smm.c b/src/cpu/x86/smm/backup_default_smm.c deleted file mode 100644 index 2023aed..0000000 --- a/src/cpu/x86/smm/backup_default_smm.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <arch/acpi.h> -#include <console/console.h> -#include <cbmem.h> -#include <cpu/x86/smm.h> - -void *backup_default_smm_area(void) -{ - void *save_area; - const void *default_smm = (void *)SMM_DEFAULT_BASE; - - if (!IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) - return NULL; - - /* - * The buffer needs to be preallocated regardless. In the non-resume - * path it will be allocated for handling resume. Note that cbmem_add() - * does a find before the addition. - */ - save_area = cbmem_add(CBMEM_ID_SMM_SAVE_SPACE, SMM_DEFAULT_SIZE); - - if (save_area == NULL) { - printk(BIOS_DEBUG, "SMM save area not added.\n"); - return NULL; - } - - /* Only back up the area on S3 resume. */ - if (acpi_is_wakeup_s3()) { - memcpy(save_area, default_smm, SMM_DEFAULT_SIZE); - return save_area; - } - - /* - * Not the S3 resume path. No need to restore memory contents after - * SMM relocation. - */ - return NULL; -} - -void restore_default_smm_area(void *smm_save_area) -{ - void *default_smm = (void *)SMM_DEFAULT_BASE; - - if (smm_save_area == NULL) - return; - - memcpy(default_smm, smm_save_area, SMM_DEFAULT_SIZE); -} diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 8de32de..fcf382e 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -11,7 +11,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 053aa29..3c6f788 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -11,7 +11,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 33644e8..1c29d77 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -11,7 +11,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 302b575..0b7dc8c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select ACPI_NHLT - select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS

1 0

Patch set updated for coreboot: soc/intel/baytrail: convert to using common MP and SMM init
by Aaron Durbin 04 May '16

04 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14580 -gerrit commit 283f74fafab941048435f33bcbae90018256d806 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 3 11:12:52 2016 -0500 soc/intel/baytrail: convert to using common MP and SMM init In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I5c5d678d7adb4c489752cca80b20f785ec8749d4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/cpu.c | 262 ++++++++++++++----------------------------- 1 file changed, 87 insertions(+), 175 deletions(-) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index fd9c7fb..94c3f2b 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -32,36 +32,6 @@ #include <soc/ramstage.h> #include <soc/smm.h> -static void smm_relocate(void); -static void enable_smis(void); - -static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(smm_relocate, smm_relocate), - MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), - /* Wait for APs to finish initialization before proceeding. */ - MP_FR_BLOCK_APS(NULL, enable_smis), -}; - -/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ -static int adjust_apic_id(int index, int apic_id) -{ - return 2 * index; -} - -/* Package level MSRs */ -const struct reg_script package_msr_script[] = { - /* Set Package TDP to ~7W */ - REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa), - REG_MSR_RMW(MSR_PP1_POWER_LIMIT, ~(0x7f << 17), 0), - REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702), - REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b), - REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0), - REG_MSR_WRITE(MSR_CPU_THERM_CFG1, 0x00000305), - REG_MSR_WRITE(MSR_CPU_THERM_CFG2, 0x0405500d), - REG_MSR_WRITE(MSR_CPU_THERM_SENS_CFG, 0x27), - REG_SCRIPT_END -}; - /* Core level MSRs */ const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ @@ -74,48 +44,6 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) -{ - struct bus *cpu_bus = dev->link_list; - const struct pattrs *pattrs = pattrs_get(); - struct mp_params mp_params; - uint32_t bsmrwac; - void *default_smm_area; - - /* Set up MTRRs based on physical address size. */ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); - - mp_params.num_cpus = pattrs->num_cpus, - mp_params.parallel_microcode_load = 1, - mp_params.adjust_apic_id = adjust_apic_id; - mp_params.flight_plan = &mp_steps[0]; - mp_params.num_records = ARRAY_SIZE(mp_steps); - mp_params.microcode_pointer = pattrs->microcode_patch; - - default_smm_area = backup_default_smm_area(); - - /* - * Configure the BUNIT to allow dirty cache line evictions in non-SMM - * mode for the lines that were dirtied while in SMM mode. Otherwise - * the writes would be silently dropped. - */ - bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; - iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); - - /* Set package MSRs */ - reg_script_run(package_msr_script); - - /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */ - enable_turbo(); - - if (mp_init(cpu_bus, &mp_params)) { - printk(BIOS_ERR, "MP initialization failure.\n"); - } - - restore_default_smm_area(default_smm_area); -} - static void baytrail_core_init(device_t cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); @@ -151,7 +79,7 @@ static const struct cpu_driver driver __cpu_driver = { /* - * SMM loading and initialization. + * MP and SMM loading initialization. */ struct smm_relocation_attrs { @@ -162,98 +90,55 @@ struct smm_relocation_attrs { static struct smm_relocation_attrs relo_attrs; -static void adjust_apic_id_map(struct smm_loader_params *smm_params) -{ - int i; - struct smm_runtime *runtime = smm_params->runtime; - - for (i = 0; i < CONFIG_MAX_CPUS; i++) - runtime->apic_id_to_cpu[i] = mp_get_apic_id(i); -} - -static void asmlinkage cpu_smm_do_relocation(void *arg) -{ - msr_t smrr; - em64t100_smm_state_save_area_t *smm_state; - const struct smm_module_params *p; - const struct smm_runtime *runtime; - int cpu; - - p = arg; - runtime = p->runtime; - cpu = p->cpu; - - if (cpu >= CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Invalid CPU number assigned in SMM stub: %d\n", cpu); - return; - } - - /* Set up SMRR. */ - smrr.lo = relo_attrs.smrr_base; - smrr.hi = 0; - wrmsr(SMRR_PHYS_BASE, smrr); - smrr.lo = relo_attrs.smrr_mask; - smrr.hi = 0; - wrmsr(SMRR_PHYS_MASK, smrr); - - /* The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. */ - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + runtime->smbase); - smm_state->smbase = relo_attrs.smbase - cpu * runtime->save_state_size; - printk(BIOS_DEBUG, "New SMBASE 0x%08x\n", smm_state->smbase); -} +/* Package level MSRs */ +static const struct reg_script package_msr_script[] = { + /* Set Package TDP to ~7W */ + REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa), + REG_MSR_RMW(MSR_PP1_POWER_LIMIT, ~(0x7f << 17), 0), + REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702), + REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b), + REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0), + REG_MSR_WRITE(MSR_CPU_THERM_CFG1, 0x00000305), + REG_MSR_WRITE(MSR_CPU_THERM_CFG2, 0x0405500d), + REG_MSR_WRITE(MSR_CPU_THERM_SENS_CFG, 0x27), + REG_SCRIPT_END +}; -static int install_relocation_handler(int num_cpus) +static void pre_mp_init(void) { - const int save_state_size = sizeof(em64t100_smm_state_save_area_t); + uint32_t bsmrwac; - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = 1, - .handler = (smm_handler_t)&cpu_smm_do_relocation, - }; + /* Set up MTRRs based on physical address size. */ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); - if (smm_setup_relocation_handler(&smm_params)) - return -1; + /* + * Configure the BUNIT to allow dirty cache line evictions in non-SMM + * mode for the lines that were dirtied while in SMM mode. Otherwise + * the writes would be silently dropped. + */ + bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; + iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); - adjust_apic_id_map(&smm_params); + /* Set package MSRs */ + reg_script_run(package_msr_script); - return 0; + /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */ + enable_turbo(); } -static int install_permanent_handler(int num_cpus) +static int get_cpu_count(void) { - /* There are num_cpus concurrent stacks and num_cpus concurrent save - * state areas. Lastly, set the stack size to the save state size. */ - int save_state_size = sizeof(em64t100_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = num_cpus, - }; - const int tseg_size = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; - - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", - relo_attrs.smbase); - - if (smm_load_module((void *)relo_attrs.smbase, tseg_size, &smm_params)) - return -1; - - adjust_apic_id_map(&smm_params); - - return 0; + const struct pattrs *pattrs = pattrs_get(); + + return pattrs->num_cpus; } -static int smm_load_handlers(void) +static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) { /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); - const struct pattrs *pattrs = pattrs_get(); /* Initialize global tracking state. */ relo_attrs.smbase = (uint32_t)smm_region_start(); @@ -261,36 +146,29 @@ static int smm_load_handlers(void) relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - /* Install handlers. */ - if (install_relocation_handler(pattrs->num_cpus) < 0) { - printk(BIOS_ERR, "Unable to install SMM relocation handler.\n"); - return -1; - } + *perm_smbase = relo_attrs.smbase; + *perm_smsize = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; + *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); +} - if (install_permanent_handler(pattrs->num_cpus) < 0) { - printk(BIOS_ERR, "Unable to install SMM permanent handler.\n"); - return -1; - } +/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ +static int adjust_apic_id(int index, int apic_id) +{ + return 2 * index; +} - /* Ensure the SMM handlers hit DRAM before performing first SMI. */ - wbinvd(); +static void get_microcode_info(const void **microcode, int *parallel) +{ + const struct pattrs *pattrs = pattrs_get(); - return 0; + *microcode = pattrs->microcode_patch; + *parallel = 1; } -static void smm_relocate(void) +static void per_cpu_smm_trigger(void) { const struct pattrs *pattrs = pattrs_get(); - /* Load relocation and permanent handler. */ - if (boot_cpu()) { - if (smm_load_handlers() < 0) { - printk(BIOS_ERR, "Error loading SMM handlers.\n"); - return; - } - southcluster_smm_clear_state(); - } - /* Relocate SMM space. */ smm_initiate_relocation(); @@ -298,7 +176,41 @@ static void smm_relocate(void) intel_microcode_load_unlocked(pattrs->microcode_patch); } -static void enable_smis(void) +static void relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) { - southcluster_smm_enable_smi(); + msr_t smrr; + em64t100_smm_state_save_area_t *smm_state; + + /* Set up SMRR. */ + smrr.lo = relo_attrs.smrr_base; + smrr.hi = 0; + wrmsr(SMRR_PHYS_BASE, smrr); + smrr.lo = relo_attrs.smrr_mask; + smrr.hi = 0; + wrmsr(SMRR_PHYS_MASK, smrr); + + smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); + smm_state->smbase = staggered_smbase; +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = get_smm_info, + .get_microcode_info = get_microcode_info, + .adjust_cpu_apic_entry = adjust_apic_id, + .pre_mp_smm_init = southcluster_smm_clear_state, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = relocation_handler, + .post_mp_init = southcluster_smm_enable_smi, +}; + +void baytrail_init_cpus(device_t dev) +{ + struct bus *cpu_bus = dev->link_list; + + if (mp_init_with_smm(cpu_bus, &mp_ops)) { + printk(BIOS_ERR, "MP initialization failure.\n"); + } }

1 0

Patch set updated for coreboot: soc/intel/fsp_baytrail: convert to using common MP and SMM init
by Aaron Durbin 04 May '16

04 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14581 -gerrit commit a6175ffd1bc46bc7235bd6dcfb2f471bdc624fb1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 3 11:31:32 2016 -0500 soc/intel/fsp_baytrail: convert to using common MP and SMM init In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I709ea938b720f26b351a1f950593efe077edb997 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/fsp_baytrail/cpu.c | 214 +++++++++++---------------------------- 1 file changed, 60 insertions(+), 154 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 3856a06..3fba0b7 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -30,32 +30,10 @@ #include <soc/msr.h> #include <soc/pattrs.h> #include <soc/ramstage.h> -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) #include <soc/smm.h> -static void smm_relocate(void); -static void enable_smis(void); - -static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(smm_relocate, smm_relocate), - MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), - /* Wait for APs to finish initialization before proceeding. */ - MP_FR_BLOCK_APS(NULL, enable_smis), -}; -#else /* CONFIG_HAVE_SMI_HANDLER */ -static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), -}; -#endif - -/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ -static int adjust_apic_id(int index, int apic_id) -{ - return 2 * index; -} - /* Core level MSRs */ -const struct reg_script core_msr_script[] = { +static const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold */ REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), /* Disable C1E */ @@ -64,29 +42,6 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) -{ - struct bus *cpu_bus = dev->link_list; - const struct pattrs *pattrs = pattrs_get(); - struct mp_params mp_params; - - x86_mtrr_check(); - - /* Enable the local cpu apics */ - setup_lapic(); - - mp_params.num_cpus = pattrs->num_cpus, - mp_params.parallel_microcode_load = 1, - mp_params.adjust_apic_id = adjust_apic_id; - mp_params.flight_plan = &mp_steps[0]; - mp_params.num_records = ARRAY_SIZE(mp_steps); - mp_params.microcode_pointer = pattrs->microcode_patch; - - if (mp_init(cpu_bus, &mp_params)) { - printk(BIOS_ERR, "MP initialization failure.\n"); - } -} - static void baytrail_core_init(device_t cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); @@ -123,9 +78,8 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) /* - * SMM loading and initialization. + * MP and SMM loading initialization. */ struct smm_relocation_attrs { @@ -136,98 +90,26 @@ struct smm_relocation_attrs { static struct smm_relocation_attrs relo_attrs; -static void adjust_apic_id_map(struct smm_loader_params *smm_params) +static void pre_mp_init(void) { - int i; - struct smm_runtime *runtime = smm_params->runtime; - - for (i = 0; i < CONFIG_MAX_CPUS; i++) - runtime->apic_id_to_cpu[i] = mp_get_apic_id(i); -} - -static void asmlinkage cpu_smm_do_relocation(void *arg) -{ - msr_t smrr; - em64t100_smm_state_save_area_t *smm_state; - const struct smm_module_params *p; - const struct smm_runtime *runtime; - int cpu; - - p = arg; - runtime = p->runtime; - cpu = p->cpu; - - if (cpu >= CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Invalid CPU number assigned in SMM stub: %d\n", cpu); - return; - } - - /* Set up SMRR. */ - smrr.lo = relo_attrs.smrr_base; - smrr.hi = 0; - wrmsr(SMRR_PHYS_BASE, smrr); - smrr.lo = relo_attrs.smrr_mask; - smrr.hi = 0; - wrmsr(SMRR_PHYS_MASK, smrr); - - /* The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. */ - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + runtime->smbase); - smm_state->smbase = relo_attrs.smbase - cpu * runtime->save_state_size; - printk(BIOS_DEBUG, "New SMBASE 0x%08x\n", smm_state->smbase); -} - -static int install_relocation_handler(int num_cpus) -{ - const int save_state_size = sizeof(em64t100_smm_state_save_area_t); - - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = 1, - .handler = (smm_handler_t)&cpu_smm_do_relocation, - }; - - if (smm_setup_relocation_handler(&smm_params)) - return -1; - - adjust_apic_id_map(&smm_params); + x86_mtrr_check(); - return 0; + /* Enable the local cpu apics */ + setup_lapic(); } -static int install_permanent_handler(int num_cpus) +static int get_cpu_count(void) { - /* There are num_cpus concurrent stacks and num_cpus concurrent save - * state areas. Lastly, set the stack size to the save state size. */ - int save_state_size = sizeof(em64t100_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = num_cpus, - }; - const int tseg_size = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; - - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", - relo_attrs.smbase); - - if (smm_load_module((void *)relo_attrs.smbase, tseg_size, &smm_params)) - return -1; - - adjust_apic_id_map(&smm_params); + const struct pattrs *pattrs = pattrs_get(); - return 0; + return pattrs->num_cpus; } -static int smm_load_handlers(void) +static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) { /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); - const struct pattrs *pattrs = pattrs_get(); /* Initialize global tracking state. */ relo_attrs.smbase = (uint32_t)smm_region_start(); @@ -235,41 +117,65 @@ static int smm_load_handlers(void) relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - /* Install handlers. */ - if (install_relocation_handler(pattrs->num_cpus) < 0) { - printk(BIOS_ERR, "Unable to install SMM relocation handler.\n"); - return -1; - } + *perm_smbase = relo_attrs.smbase; + *perm_smsize = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; + *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); +} - if (install_permanent_handler(pattrs->num_cpus) < 0) { - printk(BIOS_ERR, "Unable to install SMM permanent handler.\n"); - return -1; - } +/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ +static int adjust_apic_id(int index, int apic_id) +{ + return 2 * index; +} - /* Ensure the SMM handlers hit DRAM before performing first SMI. */ - wbinvd(); +static void get_microcode_info(const void **microcode, int *parallel) +{ + const struct pattrs *pattrs = pattrs_get(); - return 0; + *microcode = pattrs->microcode_patch; + *parallel = 1; } -static void smm_relocate(void) +static void relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) { + msr_t smrr; + em64t100_smm_state_save_area_t *smm_state; - /* Load relocation and permanent handler. */ - if (boot_cpu()) { - if (smm_load_handlers() < 0) { - printk(BIOS_ERR, "Error loading SMM handlers.\n"); - return; - } - southcluster_smm_clear_state(); - } + /* Set up SMRR. */ + smrr.lo = relo_attrs.smrr_base; + smrr.hi = 0; + wrmsr(SMRR_PHYS_BASE, smrr); + smrr.lo = relo_attrs.smrr_mask; + smrr.hi = 0; + wrmsr(SMRR_PHYS_MASK, smrr); - /* Relocate SMM space. */ - smm_initiate_relocation(); + smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); + smm_state->smbase = staggered_smbase; } static void enable_smis(void) { - southcluster_smm_enable_smi(); + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) + southcluster_smm_enable_smi(); +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = get_smm_info, + .get_microcode_info = get_microcode_info, + .adjust_cpu_apic_entry = adjust_apic_id, + .pre_mp_smm_init = southcluster_smm_clear_state, + .relocation_handler = relocation_handler, + .post_mp_init = enable_smis, +}; + +void baytrail_init_cpus(device_t dev) +{ + struct bus *cpu_bus = dev->link_list; + + if (mp_init_with_smm(cpu_bus, &mp_ops)) { + printk(BIOS_ERR, "MP initialization failure.\n"); + } } -#endif

1 0

Patch set updated for coreboot: cpu/x86/mp_init: reduce exposure of internal implementation
by Aaron Durbin 04 May '16

04 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14598 -gerrit commit f59ecd160238e131c7f6365616231a752e7d356a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 3 17:49:57 2016 -0500 cpu/x86/mp_init: reduce exposure of internal implementation With all users converted to using the mp_ops callbacks there's no need to expose that surface area. Therefore, keep it all within the mp_init compilation unit. Change-Id: Ia1cc5326c1fa5ffde86b90d805b8379f4e4f46cd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mp_init.c | 78 ++++++++++++++++++++++++++++++++++++++++++++-- src/include/cpu/x86/mp.h | 81 ------------------------------------------------ 2 files changed, 75 insertions(+), 84 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 362cda3..b9084c7 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -38,6 +38,57 @@ #include <thread.h> #define MAX_APIC_IDS 256 + +typedef void (*mp_callback_t)(void); + +/* + * A mp_flight_record details a sequence of calls for the APs to perform + * along with the BSP to coordinate sequencing. Each flight record either + * provides a barrier for each AP before calling the callback or the APs + * are allowed to perform the callback without waiting. Regardless, each + * record has the cpus_entered field incremented for each record. When + * the BSP observes that the cpus_entered matches the number of APs + * the bsp_call is called with bsp_arg and upon returning releases the + * barrier allowing the APs to make further progress. + * + * Note that ap_call() and bsp_call() can be NULL. In the NULL case the + * callback will just not be called. + */ +struct mp_flight_record { + atomic_t barrier; + atomic_t cpus_entered; + mp_callback_t ap_call; + mp_callback_t bsp_call; +} __attribute__((aligned(CACHELINE_SIZE))); + +#define _MP_FLIGHT_RECORD(barrier_, ap_func_, bsp_func_) \ + { \ + .barrier = ATOMIC_INIT(barrier_), \ + .cpus_entered = ATOMIC_INIT(0), \ + .ap_call = ap_func_, \ + .bsp_call = bsp_func_, \ + } + +#define MP_FR_BLOCK_APS(ap_func_, bsp_func_) \ + _MP_FLIGHT_RECORD(0, ap_func_, bsp_func_) + +#define MP_FR_NOBLOCK_APS(ap_func_, bsp_func_) \ + _MP_FLIGHT_RECORD(1, ap_func_, bsp_func_) + +/* The mp_params structure provides the arguments to the mp subsystem + * for bringing up APs. */ +struct mp_params { + int num_cpus; /* Total cpus include BSP */ + int parallel_microcode_load; + const void *microcode_pointer; + /* adjust_apic_id() is called for every potential apic id in the + * system up from 0 to CONFIG_MAX_CPUS. Return adjusted apic_id. */ + int (*adjust_apic_id)(int index, int apic_id); + /* Flight plan for APs and BSP. */ + struct mp_flight_record *flight_plan; + int num_records; +}; + /* This needs to match the layout in the .module_parametrs section. */ struct sipi_params { uint16_t gdtlimit; @@ -514,7 +565,26 @@ static void init_bsp(struct bus *cpu_bus) cpus[info->index].apic_id = cpu_path.apic.apic_id; } -int mp_init(struct bus *cpu_bus, struct mp_params *p) +/* + * mp_init() will set up the SIPI vector and bring up the APs according to + * mp_params. Each flight record will be executed according to the plan. Note + * that the MP infrastructure uses SMM default area without saving it. It's + * up to the chipset or mainboard to either e820 reserve this area or save this + * region prior to calling mp_init() and restoring it after mp_init returns. + * + * At the time mp_init() is called the MTRR MSRs are mirrored into APs then + * caching is enabled before running the flight plan. + * + * The MP initialization has the following properties: + * 1. APs are brought up in parallel. + * 2. The ordering of coreboot cpu number and APIC ids is not deterministic. + * Therefore, one cannot rely on this property or the order of devices in + * the device tree unless the chipset or mainboard know the APIC ids + * a priori. + * + * mp_init() returns < 0 on error, 0 on success. + */ +static int mp_init(struct bus *cpu_bus, struct mp_params *p) { int num_cpus; int num_aps; @@ -563,14 +633,16 @@ int mp_init(struct bus *cpu_bus, struct mp_params *p) return bsp_do_flight_plan(p); } -void mp_initialize_cpu(void) +/* Calls cpu_initialize(info->index) which calls the coreboot CPU drivers. */ +static void mp_initialize_cpu(void) { /* Call back into driver infrastructure for the AP initialization. */ struct cpu_info *info = cpu_info(); cpu_initialize(info->index); } -int mp_get_apic_id(int cpu_slot) +/* Returns apic id for coreboot cpu number or < 0 on failure. */ +static int mp_get_apic_id(int cpu_slot) { if (cpu_slot >= CONFIG_MAX_CPUS || cpu_slot < 0) return -1; diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index ff88a20..9742df0 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -29,56 +29,6 @@ static inline void mfence(void) __asm__ __volatile__("mfence\t\n": : :"memory"); } -typedef void (*mp_callback_t)(void); - -/* - * A mp_flight_record details a sequence of calls for the APs to perform - * along with the BSP to coordinate sequencing. Each flight record either - * provides a barrier for each AP before calling the callback or the APs - * are allowed to perform the callback without waiting. Regardless, each - * record has the cpus_entered field incremented for each record. When - * the BSP observes that the cpus_entered matches the number of APs - * the bsp_call is called with bsp_arg and upon returning releases the - * barrier allowing the APs to make further progress. - * - * Note that ap_call() and bsp_call() can be NULL. In the NULL case the - * callback will just not be called. - */ -struct mp_flight_record { - atomic_t barrier; - atomic_t cpus_entered; - mp_callback_t ap_call; - mp_callback_t bsp_call; -} __attribute__((aligned(CACHELINE_SIZE))); - -#define _MP_FLIGHT_RECORD(barrier_, ap_func_, bsp_func_) \ - { \ - .barrier = ATOMIC_INIT(barrier_), \ - .cpus_entered = ATOMIC_INIT(0), \ - .ap_call = ap_func_, \ - .bsp_call = bsp_func_, \ - } - -#define MP_FR_BLOCK_APS(ap_func_, bsp_func_) \ - _MP_FLIGHT_RECORD(0, ap_func_, bsp_func_) - -#define MP_FR_NOBLOCK_APS(ap_func_, bsp_func_) \ - _MP_FLIGHT_RECORD(1, ap_func_, bsp_func_) - -/* The mp_params structure provides the arguments to the mp subsystem - * for bringing up APs. */ -struct mp_params { - int num_cpus; /* Total cpus include BSP */ - int parallel_microcode_load; - const void *microcode_pointer; - /* adjust_apic_id() is called for every potential apic id in the - * system up from 0 to CONFIG_MAX_CPUS. Return adjusted apic_id. */ - int (*adjust_apic_id)(int index, int apic_id); - /* Flight plan for APs and BSP. */ - struct mp_flight_record *flight_plan; - int num_records; -}; - /* The sequence of the callbacks are in calling order. */ struct mp_ops { /* @@ -175,37 +125,6 @@ struct mp_ops { int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops); /* - * mp_init() will set up the SIPI vector and bring up the APs according to - * mp_params. Each flight record will be executed according to the plan. Note - * that the MP infrastructure uses SMM default area without saving it. It's - * up to the chipset or mainboard to either e820 reserve this area or save this - * region prior to calling mp_init() and restoring it after mp_init returns. - * - * At the time mp_init() is called the MTRR MSRs are mirrored into APs then - * caching is enabled before running the flight plan. - * - * The MP initialization has the following properties: - * 1. APs are brought up in parallel. - * 2. The ordering of coreboot cpu number and APIC ids is not deterministic. - * Therefore, one cannot rely on this property or the order of devices in - * the device tree unless the chipset or mainboard know the APIC ids - * a priori. - * - * mp_init() returns < 0 on error, 0 on success. - */ -int mp_init(struct bus *cpu_bus, struct mp_params *params); - -/* - * Useful functions to use in flight records when sequencing APs. - */ - -/* Calls cpu_initialize(info->index) which calls the coreboot CPU drivers. */ -void mp_initialize_cpu(void); - -/* Returns apic id for coreboot cpu number or < 0 on failure. */ -int mp_get_apic_id(int cpu_slot); - -/* * SMM helpers to use with initializing CPUs. */

1 0

Patch set updated for coreboot: cpu/intel/haswell: convert to using common MP and SMM init
by Aaron Durbin 04 May '16

04 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14596 -gerrit commit 06d8ad2d1bce3bd6d23658d4d3e99493abae86f5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 3 17:26:35 2016 -0500 cpu/intel/haswell: convert to using common MP and SMM init In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I80b5b94b62bdd001581eb56513a0d532fffb64e8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/haswell.h | 8 +- src/cpu/intel/haswell/haswell_init.c | 124 +++++++++++++--------------- src/cpu/intel/haswell/smmrelocate.c | 153 ++++++----------------------------- 3 files changed, 88 insertions(+), 197 deletions(-) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 9236b77..8298fb1 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -193,14 +193,16 @@ void intel_cpu_haswell_finalize_smm(void); /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -/* Returns 0 on success, < 0 on failure. */ -int smm_initialize(void); +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase); +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size); +void smm_initialize(void); void smm_relocate(void); struct bus; void bsp_init_and_start_aps(struct bus *cpu_bus); /* Determine if HyperThreading is disabled. The variable is not valid until * setup_ap_init() has been called. */ -extern int ht_disabled; #endif /* CPU identification */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index f488ef6..74147ab 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -714,20 +714,6 @@ static void configure_mca(void) wrmsr(IA32_MC0_STATUS + (i * 4), msr); } -static void bsp_init_before_ap_bringup(struct bus *cpu_bus) -{ - /* Setup MTRRs based on physical address size. */ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); - - initialize_vr_config(); - - if (haswell_is_ult()) { - calibrate_24mhz_bclk(); - configure_pch_power_sharing(); - } -} - /* All CPUs including BSP will run the following function. */ static void haswell_init(struct device *cpu) { @@ -765,47 +751,27 @@ static void haswell_init(struct device *cpu) /* MP initialization support. */ static const void *microcode_patch; -int ht_disabled; +static int ht_disabled; -static int adjust_apic_id_ht_disabled(int index, int apic_id) +static void pre_mp_init(void) { - return 2 * index; -} - -static void relocate_and_load_microcode(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); -} + /* Setup MTRRs based on physical address size. */ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); -static void enable_smis(void) -{ - /* Now that all APs have been relocated as well as the BSP let SMIs - * start flowing. */ - southbridge_smm_enable_smi(); + initialize_vr_config(); - /* Lock down the SMRAM space. */ - smm_lock(); + if (haswell_is_ult()) { + calibrate_24mhz_bclk(); + configure_pch_power_sharing(); + } } -static struct mp_flight_record mp_steps[] = { - MP_FR_NOBLOCK_APS(relocate_and_load_microcode, - relocate_and_load_microcode), - MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), - /* Wait for APs to finish initialization before proceeding. */ - MP_FR_BLOCK_APS(NULL, enable_smis), -}; - -void bsp_init_and_start_aps(struct bus *cpu_bus) +static int get_cpu_count(void) { - void *smm_save_area; + msr_t msr; int num_threads; int num_cores; - msr_t msr; - struct mp_params mp_params; msr = rdmsr(CORE_THREAD_COUNT_MSR); num_threads = (msr.lo >> 0) & 0xffff; @@ -815,36 +781,60 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) ht_disabled = num_threads == num_cores; - /* Perform any necessary BSP initialization before APs are brought up. - * This call also allows the BSP to prepare for any secondary effects - * from calling cpu_initialize() such as smm_init(). */ - bsp_init_before_ap_bringup(cpu_bus); + return num_threads; +} +static void get_microcode_info(const void **microcode, int *parallel) +{ microcode_patch = intel_microcode_find(); + *microcode = microcode_patch; + *parallel = 1; +} - /* Save default SMM area before relocation occurs. */ - smm_save_area = backup_default_smm_area(); - - mp_params.num_cpus = num_threads; - mp_params.parallel_microcode_load = 1; +static int adjust_apic_id(int index, int apic_id) +{ if (ht_disabled) - mp_params.adjust_apic_id = adjust_apic_id_ht_disabled; + return 2 * index; else - mp_params.adjust_apic_id = NULL; - mp_params.flight_plan = &mp_steps[0]; - mp_params.num_records = ARRAY_SIZE(mp_steps); - mp_params.microcode_pointer = microcode_patch; + return index; +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); - /* Load relocation and permeanent handlers. Then initiate relocation. */ - if (smm_initialize()) - printk(BIOS_CRIT, "SMM Initialiazation failed...\n"); + /* After SMM relocation a 2nd microcode load is required. */ + intel_microcode_load_unlocked(microcode_patch); +} - if (mp_init(cpu_bus, &mp_params)) { +static void post_mp_init(void) +{ + /* Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. */ + southbridge_smm_enable_smi(); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, + .adjust_cpu_apic_entry = adjust_apic_id, + .pre_mp_smm_init = smm_initialize, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; + +void bsp_init_and_start_aps(struct bus *cpu_bus) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops)) { printk(BIOS_ERR, "MP initialization failure.\n"); } - - /* Restore the default SMM region. */ - restore_default_smm_area(smm_save_area); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 99a972e..5c50ad1c 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -91,9 +91,9 @@ static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask); } -static void update_save_state(int cpu, - struct smm_relocation_params *relo_params, - const struct smm_runtime *runtime) +static void update_save_state(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) { u32 smbase; u32 iedbase; @@ -101,7 +101,7 @@ static void update_save_state(int cpu, /* The relocated handler runs with all CPUs concurrently. Therefore * stagger the entry points adjusting SMBASE downwards by save state * size * CPU num. */ - smbase = relo_params->smram_base - cpu * runtime->save_state_size; + smbase = staggered_smbase; iedbase = relo_params->ied_base; printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", @@ -132,8 +132,8 @@ static void update_save_state(int cpu, } else { em64t101_smm_state_save_area_t *save_state; - save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE - - runtime->save_state_size); + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - + sizeof(*save_state)); save_state->smbase = smbase; save_state->iedbase = iedbase; @@ -161,24 +161,11 @@ static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) /* The relocation work is actually performed in SMM context, but the code * resides in the ramstage module. This occurs by trampolining from the default * SMRAM entry point to here. */ -static void asmlinkage cpu_smm_do_relocation(void *arg) +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) { msr_t mtrr_cap; - struct smm_relocation_params *relo_params; - const struct smm_module_params *p; - const struct smm_runtime *runtime; - int cpu; - - p = arg; - runtime = p->runtime; - relo_params = p->arg; - cpu = p->cpu; - - if (cpu >= CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Invalid CPU number assigned in SMM stub: %d\n", cpu); - return; - } + struct smm_relocation_params *relo_params = &smm_reloc_params; printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); @@ -207,7 +194,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) } /* Make appropriate changes to the save state map. */ - update_save_state(cpu, relo_params, runtime); + update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); /* Write EMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); @@ -290,49 +277,6 @@ static void fill_in_relocation_params(struct device *dev, params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; } -static void adjust_apic_id_map(struct smm_loader_params *smm_params) -{ - struct smm_runtime *runtime; - int i; - - /* Adjust the APIC id map if HT is disabled. */ - if (!ht_disabled) - return; - - runtime = smm_params->runtime; - - /* The APIC ids increment by 2 when HT is disabled. */ - for (i = 0; i < CONFIG_MAX_CPUS; i++) - runtime->apic_id_to_cpu[i] = runtime->apic_id_to_cpu[i] * 2; -} - -static int install_relocation_handler(int num_cpus, - struct smm_relocation_params *relo_params) -{ - /* The default SMM entry can happen in parallel or serially. If the - * default SMM entry is done in parallel the BSP has already setup - * the saving state to each CPU's MSRs. At least one save state size - * is required for the initial SMM entry for the BSP to determine if - * parallel SMM relocation is even feasible. Set the stack size to - * the save state size, and call into the do_relocation handler. */ - int save_state_size = sizeof(em64t101_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = 1, - .handler = (smm_handler_t)&cpu_smm_do_relocation, - .handler_arg = (void *)relo_params, - }; - - if (smm_setup_relocation_handler(&smm_params)) - return -1; - - adjust_apic_id_map(&smm_params); - - return 0; -} - static void setup_ied_area(struct smm_relocation_params *params) { char *ied_base; @@ -357,88 +301,43 @@ static void setup_ied_area(struct smm_relocation_params *params) //memset(ied_base + (2 << 20), 0, (2 << 20)); } -static int install_permanent_handler(int num_cpus, - struct smm_relocation_params *relo_params) +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) { - /* There are num_cpus concurrent stacks and num_cpus concurrent save - * state areas. Lastly, set the stack size to the save state size. */ - int save_state_size = sizeof(em64t101_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = num_cpus, - }; - - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", - relo_params->smram_base); - if (smm_load_module((void *)relo_params->smram_base, - relo_params->smram_size, &smm_params)) - return -1; - - adjust_apic_id_map(&smm_params); - - return 0; -} - -static int cpu_smm_setup(void) -{ - struct device *dev; - int num_cpus; - msr_t msr; + device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - fill_in_relocation_params(dev, &smm_reloc_params); setup_ied_area(&smm_reloc_params); - msr = rdmsr(CORE_THREAD_COUNT_MSR); - num_cpus = msr.lo & 0xffff; - if (num_cpus > CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", - num_cpus, CONFIG_MAX_CPUS); - } - - if (install_relocation_handler(num_cpus, &smm_reloc_params)) { - printk(BIOS_CRIT, "SMM Relocation handler install failed.\n"); - return -1; - } - - if (install_permanent_handler(num_cpus, &smm_reloc_params)) { - printk(BIOS_CRIT, "SMM Permanent handler install failed.\n"); - return -1; - } - - /* Ensure the SMM handlers hit DRAM before performing first SMI. */ - /* TODO(adurbin): Is this really needed? */ - wbinvd(); - - return 0; + *perm_smbase = smm_reloc_params.smram_base; + *perm_smsize = smm_reloc_params.smram_size; + *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } -int smm_initialize(void) +void smm_initialize(void) { - /* Return early if CPU SMM setup failed. */ - if (cpu_smm_setup()) - return -1; - /* Clear the SMM state in the southbridge. */ southbridge_smm_clear_state(); - /* Run the relocation handler. */ + /* + * Run the relocation handler for on the BSP to check and set up + * parallel SMM relocation. + */ smm_initiate_relocation(); if (smm_reloc_params.smm_save_state_in_msrs) { printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); } - - return 0; } +/* The default SMM entry can happen in parallel or serially. If the + * default SMM entry is done in parallel the BSP has already setup + * the saving state to each CPU's MSRs. At least one save state size + * is required for the initial SMM entry for the BSP to determine if + * parallel SMM relocation is even feasible. */ void smm_relocate(void) { /*

1 0

Patch set updated for coreboot: soc/intel/skylake: convert to using common MP and SMM init
by Aaron Durbin 04 May '16

04 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14597 -gerrit commit 4175d1fb36f9255367eb22d6f2d8c469d84bf10d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 3 17:45:59 2016 -0500 soc/intel/skylake: convert to using common MP and SMM init In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I5c4674ed258922b6616d75f070df976ef9fad209 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/cpu.c | 147 ++++++++++++++------------------ src/soc/intel/skylake/include/soc/cpu.h | 6 -- src/soc/intel/skylake/include/soc/smm.h | 15 ++-- src/soc/intel/skylake/smmrelocate.c | 144 ++++--------------------------- 4 files changed, 92 insertions(+), 220 deletions(-) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 17fa0ae..b7353ca 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -346,13 +346,6 @@ static void configure_mca(void) wrmsr(IA32_MC0_STATUS + (i * 4), msr); } -static void bsp_init_before_ap_bringup(struct bus *cpu_bus) -{ - /* Setup MTRRs based on physical address size. */ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); -} - /* All CPUs including BSP will run the following function. */ static void cpu_core_init(device_t cpu) { @@ -382,48 +375,6 @@ static void cpu_core_init(device_t cpu) enable_turbo(); } -/* MP initialization support. */ -static const void *microcode_patch; -int ht_disabled; - -static int adjust_apic_id_ht_disabled(int index, int apic_id) -{ - return 2 * index; -} - -static void relocate_and_load_microcode(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); -} - -static void enable_smis(void) -{ - /* - * Now that all APs have been relocated as well as the BSP let SMIs - * start flowing. - */ - southbridge_smm_enable_smi(); - - /* Lock down the SMRAM space. */ -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - smm_lock(); -#endif -} - -static struct mp_flight_record mp_steps[] = { - MP_FR_NOBLOCK_APS(relocate_and_load_microcode, - relocate_and_load_microcode), -#if IS_ENABLED(CONFIG_SMP) - MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), - /* Wait for APs to finish initialization before proceeding. */ -#endif - MP_FR_BLOCK_APS(NULL, enable_smis), -}; - static struct device_operations cpu_dev_ops = { .init = cpu_core_init, }; @@ -439,14 +390,22 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; -void soc_init_cpus(device_t dev) +/* MP initialization support. */ +static const void *microcode_patch; +static int ht_disabled; + +static void pre_mp_init(void) { - struct bus *cpu_bus = dev->link_list; + /* Setup MTRRs based on physical address size. */ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_cpu_count(void) +{ + msr_t msr; int num_threads; int num_cores; - msr_t msr; - struct mp_params mp_params; - void *smm_save_area; msr = rdmsr(CORE_THREAD_COUNT_MSR); num_threads = (msr.lo >> 0) & 0xffff; @@ -456,45 +415,69 @@ void soc_init_cpus(device_t dev) ht_disabled = num_threads == num_cores; - /* - * Perform any necessary BSP initialization before APs are brought up. - * This call also allows the BSP to prepare for any secondary effects - * from calling cpu_initialize() such as smm_init(). - */ - bsp_init_before_ap_bringup(cpu_bus); + return num_threads; +} +static void get_microcode_info(const void **microcode, int *parallel) +{ microcode_patch = intel_microcode_find(); + *microcode = microcode_patch; + *parallel = 1; +} - /* Save default SMM area before relocation occurs. */ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) - smm_save_area = backup_default_smm_area(); - else - smm_save_area = NULL; - - mp_params.num_cpus = num_threads; - mp_params.parallel_microcode_load = 1; +static int adjust_apic_id(int index, int apic_id) +{ if (ht_disabled) - mp_params.adjust_apic_id = adjust_apic_id_ht_disabled; + return 2 * index; else - mp_params.adjust_apic_id = NULL; - mp_params.flight_plan = &mp_steps[0]; - mp_params.num_records = ARRAY_SIZE(mp_steps); - mp_params.microcode_pointer = microcode_patch; + return index; +} - /* Load relocation and permeanent handlers. Then initiate relocation. */ - if (smm_initialize()) - printk(BIOS_CRIT, "SMM Initialiazation failed...\n"); +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); - if (IS_ENABLED(CONFIG_SMP)) - if (mp_init(cpu_bus, &mp_params)) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* After SMM relocation a 2nd microcode load is required. */ + intel_microcode_load_unlocked(microcode_patch); +} +static void post_mp_init(void) +{ /* Set Max Ratio */ set_max_ratio(); - /* Restore the default SMM region. */ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) - restore_default_smm_area(smm_save_area); + /* + * Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. + */ + southbridge_smm_enable_smi(); + + /* Lock down the SMRAM space. */ +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + smm_lock(); +#endif +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, + .adjust_cpu_apic_entry = adjust_apic_id, + .pre_mp_smm_init = smm_initialize, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; + +void soc_init_cpus(device_t dev) +{ + struct bus *cpu_bus = dev->link_list; + + if (mp_init_with_smm(cpu_bus, &mp_ops)) { + printk(BIOS_ERR, "MP initialization failure.\n"); + } } int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 8dd9742..f91a0ef 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -57,12 +57,6 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -/* - * Determine if HyperThreading is disabled. - * The variable is not valid until setup_ap_init() has been called. - */ -extern int ht_disabled; - /* CPU identification */ u32 cpu_family_model(void); u32 cpu_stepping(void); diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 94bdc55..fa8da46 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -53,7 +53,11 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts); #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) -int smm_initialize(void); +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase); +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size); +void smm_initialize(void); void smm_relocate(void); /* These helpers are for performing SMM relocation. */ @@ -68,10 +72,11 @@ void southbridge_clear_smi_status(void); void southbridge_smm_clear_state(void); void southbridge_smm_enable_smi(void); #else /* CONFIG_HAVE_SMI_HANDLER */ -static inline int smm_initialize(void) -{ - return 0; -} +static inline void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) {} +static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) {} +static inline void smm_initialize(void) {} static inline void smm_relocate(void) {} static inline void southbridge_trigger_smi(void) {} diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index a14721f..fcb89de 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -54,9 +54,9 @@ static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) wrmsr(UNCORE_PRMRR_PHYS_MASK_MSR, relo_params->uncore_emrr_mask); } -static void update_save_state(int cpu, - struct smm_relocation_params *relo_params, - const struct smm_runtime *runtime) +static void update_save_state(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) { u32 smbase; u32 iedbase; @@ -66,7 +66,7 @@ static void update_save_state(int cpu, * stagger the entry points adjusting SMBASE downwards by save state * size * CPU num. */ - smbase = relo_params->smram_base - cpu * runtime->save_state_size; + smbase = staggered_smbase; iedbase = relo_params->ied_base; printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", @@ -101,8 +101,8 @@ static void update_save_state(int cpu, } else { em64t101_smm_state_save_area_t *save_state; - save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE - - runtime->save_state_size); + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - + sizeof(*save_state)); save_state->smbase = smbase; save_state->iedbase = iedbase; @@ -132,24 +132,11 @@ static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) * resides in the ramstage module. This occurs by trampolining from the default * SMRAM entry point to here. */ -static void asmlinkage cpu_smm_do_relocation(void *arg) +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) { msr_t mtrr_cap; - struct smm_relocation_params *relo_params; - const struct smm_module_params *p; - const struct smm_runtime *runtime; - int cpu; - - p = arg; - runtime = p->runtime; - relo_params = p->arg; - cpu = p->cpu; - - if (cpu >= CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Invalid CPU number assigned in SMM stub: %d\n", cpu); - return; - } + struct smm_relocation_params *relo_params = &smm_reloc_params; printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); @@ -184,7 +171,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) } /* Make appropriate changes to the save state map. */ - update_save_state(cpu, relo_params, runtime); + update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); /* Write EMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); @@ -250,51 +237,6 @@ static void fill_in_relocation_params(device_t dev, params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; } -static void adjust_apic_id_map(struct smm_loader_params *smm_params) -{ - struct smm_runtime *runtime; - int i; - - /* Adjust the APIC id map if HT is disabled. */ - if (!ht_disabled) - return; - - runtime = smm_params->runtime; - - /* The APIC ids increment by 2 when HT is disabled. */ - for (i = 0; i < CONFIG_MAX_CPUS; i++) - runtime->apic_id_to_cpu[i] = runtime->apic_id_to_cpu[i] * 2; -} - -static int install_relocation_handler(int num_cpus, - struct smm_relocation_params *relo_params) -{ - /* - * The default SMM entry can happen in parallel or serially. If the - * default SMM entry is done in parallel the BSP has already setup - * the saving state to each CPU's MSRs. At least one save state size - * is required for the initial SMM entry for the BSP to determine if - * parallel SMM relocation is even feasible. Set the stack size to - * the save state size, and call into the do_relocation handler. - */ - int save_state_size = sizeof(em64t101_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = 1, - .handler = (smm_handler_t)&cpu_smm_do_relocation, - .handler_arg = (void *)relo_params, - }; - - if (smm_setup_relocation_handler(&smm_params)) - return -1; - - adjust_apic_id_map(&smm_params); - - return 0; -} - static void setup_ied_area(struct smm_relocation_params *params) { char *ied_base; @@ -317,37 +259,10 @@ static void setup_ied_area(struct smm_relocation_params *params) memset(ied_base + (1 << 20), 0, (32 << 10)); } -static int install_permanent_handler(int num_cpus, - struct smm_relocation_params *relo_params) -{ - /* - * There are num_cpus concurrent stacks and num_cpus concurrent save - * state areas. Lastly, set the stack size to the save state size. - */ - int save_state_size = sizeof(em64t101_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = num_cpus, - }; - - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", - relo_params->smram_base); - if (smm_load_module((void *)relo_params->smram_base, - relo_params->smram_size, &smm_params)) - return -1; - - adjust_apic_id_map(&smm_params); - - return 0; -} - -static int cpu_smm_setup(void) +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) { device_t dev = SA_DEV_ROOT; - int num_cpus; - msr_t msr; printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); @@ -356,46 +271,21 @@ static int cpu_smm_setup(void) if (smm_reloc_params.ied_size) setup_ied_area(&smm_reloc_params); - msr = rdmsr(CORE_THREAD_COUNT_MSR); - num_cpus = msr.lo & 0xffff; - if (num_cpus > CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", - num_cpus, CONFIG_MAX_CPUS); - } - - if (install_relocation_handler(num_cpus, &smm_reloc_params)) { - printk(BIOS_CRIT, "SMM Relocation handler install failed.\n"); - return -1; - } - - if (install_permanent_handler(num_cpus, &smm_reloc_params)) { - printk(BIOS_CRIT, "SMM Permanent handler install failed.\n"); - return -1; - } - - /* Ensure the SMM handlers hit DRAM before performing first SMI. */ - wbinvd(); - - return 0; } -int smm_initialize(void) +void smm_initialize(void) { - /* Return early if CPU SMM setup failed. */ - if (cpu_smm_setup()) - return -1; - /* Clear the SMM state in the southbridge. */ southbridge_smm_clear_state(); - /* Run the relocation handler. */ + /* + * Run the relocation handler for on the BSP to check and set up + * parallel SMM relocation. + */ smm_initiate_relocation(); if (smm_reloc_params.smm_save_state_in_msrs) printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); - - return 0; } void smm_relocate(void)

1 0

Patch set updated for coreboot: soc/intel/apollolake: convert to using common MP init
by Aaron Durbin 04 May '16

04 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14594 -gerrit commit ab0fc12e8f4ad47b6e547969643a7f8ae8bced27 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 3 15:56:24 2016 -0500 soc/intel/apollolake: convert to using common MP init In order to reduce duplication of code use the common MP initialization flow. Change-Id: I8cfb5ba6f6a31fecde2ce3bf997f87c4486ab3ab Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/cpu.c | 43 ++++++++++++++++++------------------------ 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 21cd33a..99cb5ad 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -56,12 +56,25 @@ static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt) * creates the MTRR solution that the APs will use. Otherwise APs will try to * apply the incomplete solution as the BSP is calculating it. */ -static void bsp_pre_mp_setup(void) +static void pre_mp_init(void) { x86_setup_mtrrs_with_detect(); x86_mtrr_check(); } +/* Find CPU topology */ +static int get_cpu_count(void) +{ + unsigned int num_virt_cores, num_phys_cores; + + read_cpu_topology(&num_phys_cores, &num_virt_cores); + + printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n", + num_phys_cores, num_virt_cores); + + return num_virt_cores; +} + /* * CPU initialization recipe * @@ -69,34 +82,14 @@ static void bsp_pre_mp_setup(void) * the microcode on all cores before releasing them from reset. That means that * the BSP and all APs will come up with the same microcode revision. */ -static struct mp_flight_record flight_plan[] = { - /* NOTE: MTRR solution must be calculated before firing up the APs */ - MP_FR_NOBLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, }; void apollolake_init_cpus(device_t dev) { - unsigned int num_virt_cores, num_phys_cores; - - /* Pre-flight check */ - bsp_pre_mp_setup(); - - /* Find CPU topology */ - read_cpu_topology(&num_phys_cores, &num_virt_cores); - printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n", - num_phys_cores, num_virt_cores); - - /* Systems check */ - struct mp_params flight_data_recorder = { - .num_cpus = num_virt_cores, - .parallel_microcode_load = 0, - .microcode_pointer = NULL, - .adjust_apic_id = NULL, - .flight_plan = flight_plan, - .num_records = ARRAY_SIZE(flight_plan), - }; - /* Clear for take-off */ - if (mp_init(dev->link_list, &flight_data_recorder) < 0) + if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); }

1 0

Patch set updated for coreboot: cpu/x86: combine multiprocessor and SMM initialization
by Aaron Durbin 04 May '16

04 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14557 -gerrit commit dc2551ff243d548d69ae1719df905f9a95f527d0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 22:55:49 2016 -0500 cpu/x86: combine multiprocessor and SMM initialization In order to reduce code duplication provide a common flow through callback functions that performs the multiprocessor and optionally SMM initialization. The existing MP flight records are utilized but a common flow is provided such that the chipset/cpu only needs to provide a mp_ops structure which has callbacks to gather info and provide hooks at certain points in the sequence. All current users of the MP code can be switched over to this flow since there haven't been any flight records that are overly complicated and long. After the conversion has taken place most of the surface area of the MP API can be hidden away within the compilation unit proper. Change-Id: I6f70969631012982126f0d0d76e5fac6880c24f0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mp_init.c | 242 +++++++++++++++++++++++++++++++++++++++++++++++ src/include/cpu/x86/mp.h | 96 +++++++++++++++++++ 2 files changed, 338 insertions(+) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 2180d98..362cda3 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -607,3 +607,245 @@ void smm_initiate_relocation(void) smm_initiate_relocation_parallel(); spin_unlock(&smm_relocation_lock); } + +struct mp_state { + struct mp_ops ops; + int cpu_count; + uintptr_t perm_smbase; + size_t perm_smsize; + size_t smm_save_state_size; + int do_smm; +} mp_state; + +static int is_smm_enabled(void) +{ + return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && mp_state.do_smm; +} + +static void smm_disable(void) +{ + mp_state.do_smm = 0; +} + +static void smm_enable(void) +{ + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) + mp_state.do_smm = 1; +} + +static void asmlinkage smm_do_relocation(void *arg) +{ + const struct smm_module_params *p; + const struct smm_runtime *runtime; + int cpu; + uintptr_t curr_smbase; + uintptr_t perm_smbase; + + p = arg; + runtime = p->runtime; + cpu = p->cpu; + curr_smbase = runtime->smbase; + + if (cpu >= CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Invalid CPU number assigned in SMM stub: %d\n", cpu); + return; + } + + /* + * The permanent handler runs with all cpus concurrently. Precalculate + * the location of the new SMBASE. If using SMM modules then this + * calculation needs to match that of the module loader. + */ + perm_smbase = mp_state.perm_smbase; + perm_smbase -= cpu * runtime->save_state_size; + + printk(BIOS_DEBUG, "New SMBASE 0x%08lx\n", perm_smbase); + + /* Setup code checks this callback for validity. */ + mp_state.ops.relocation_handler(cpu, curr_smbase, perm_smbase); +} + +static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params) +{ + int i; + struct smm_runtime *runtime = smm_params->runtime; + + for (i = 0; i < CONFIG_MAX_CPUS; i++) + runtime->apic_id_to_cpu[i] = mp_get_apic_id(i); +} + +static int install_relocation_handler(int num_cpus, size_t save_state_size) +{ + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = 1, + .handler = smm_do_relocation, + }; + + /* Allow callback to override parameters. */ + if (mp_state.ops.adjust_smm_params != NULL) + mp_state.ops.adjust_smm_params(&smm_params, 0); + + if (smm_setup_relocation_handler(&smm_params)) + return -1; + + adjust_smm_apic_id_map(&smm_params); + + return 0; +} + +static int install_permanent_handler(int num_cpus, uintptr_t smbase, + size_t smsize, size_t save_state_size) +{ + /* There are num_cpus concurrent stacks and num_cpus concurrent save + * state areas. Lastly, set the stack size to the save state size. */ + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = num_cpus, + }; + + /* Allow callback to override parameters. */ + if (mp_state.ops.adjust_smm_params != NULL) + mp_state.ops.adjust_smm_params(&smm_params, 1); + + printk(BIOS_DEBUG, "Installing SMM handler to 0x%08lx\n", smbase); + + if (smm_load_module((void *)smbase, smsize, &smm_params)) + return -1; + + adjust_smm_apic_id_map(&smm_params); + + return 0; +} + +/* Load SMM handlers as part of MP flight record. */ +static void load_smm_handlers(void) +{ + size_t smm_save_state_size = mp_state.smm_save_state_size; + + /* Do nothing if SMM is disabled.*/ + if (!is_smm_enabled()) + return; + + /* Install handlers. */ + if (install_relocation_handler(mp_state.cpu_count, + smm_save_state_size) < 0) { + printk(BIOS_ERR, "Unable to install SMM relocation handler.\n"); + smm_disable(); + } + + if (install_permanent_handler(mp_state.cpu_count, mp_state.perm_smbase, + mp_state.perm_smsize, smm_save_state_size) < 0) { + printk(BIOS_ERR, "Unable to install SMM permanent handler.\n"); + smm_disable(); + } + + /* Ensure the SMM handlers hit DRAM before performing first SMI. */ + wbinvd(); + + /* + * Indicate that the SMM handlers have been loaded and MP + * initialization is about to start. + */ + if (is_smm_enabled() && mp_state.ops.pre_mp_smm_init != NULL) + mp_state.ops.pre_mp_smm_init(); +} + +/* Trigger SMM as part of MP flight record. */ +static void trigger_smm_relocation(void) +{ + /* Do nothing if SMM is disabled.*/ + if (!is_smm_enabled() || mp_state.ops.per_cpu_smm_trigger == NULL) + return; + /* Trigger SMM mode for the currently running processor. */ + mp_state.ops.per_cpu_smm_trigger(); +} + +static struct mp_flight_record mp_steps[] = { + /* Once the APs are up load the SMM handlers. */ + MP_FR_BLOCK_APS(NULL, load_smm_handlers), + /* Perform SMM relocation. */ + MP_FR_NOBLOCK_APS(trigger_smm_relocation, trigger_smm_relocation), + /* Initialize each cpu through the driver framework. */ + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), + /* Wait for APs to finish everything else then let them park. */ + MP_FR_BLOCK_APS(NULL, NULL), +}; + +static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) +{ + /* + * Make copy of the ops so that defaults can be set in the non-const + * structure if needed. + */ + memcpy(&state->ops, ops, sizeof(*ops)); + + if (ops->get_cpu_count != NULL) + state->cpu_count = ops->get_cpu_count(); + + if (ops->get_smm_info != NULL) + ops->get_smm_info(&state->perm_smbase, &state->perm_smsize, + &state->smm_save_state_size); + + /* + * Default to smm_initiate_relocation() if trigger callback isn't + * provided. + */ + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && + ops->per_cpu_smm_trigger == NULL) + mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation; +} + +int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) +{ + int ret; + void *default_smm_area; + struct mp_params mp_params; + + if (mp_ops->pre_mp_init != NULL) + mp_ops->pre_mp_init(); + + fill_mp_state(&mp_state, mp_ops); + + memset(&mp_params, 0, sizeof(mp_params)); + + if (mp_state.cpu_count <= 0) { + printk(BIOS_ERR, "Invalid cpu_count: %d\n", mp_state.cpu_count); + return -1; + } + + /* Sanity check SMM state. */ + if (mp_state.perm_smsize != 0 && mp_state.smm_save_state_size != 0 && + mp_state.ops.relocation_handler != NULL) + smm_enable(); + + if (is_smm_enabled()) + printk(BIOS_INFO, "Will perform SMM setup.\n"); + + mp_params.num_cpus = mp_state.cpu_count; + /* Gather microcode information. */ + if (mp_state.ops.get_microcode_info != NULL) + mp_state.ops.get_microcode_info(&mp_params.microcode_pointer, + &mp_params.parallel_microcode_load); + mp_params.adjust_apic_id = mp_state.ops.adjust_cpu_apic_entry; + mp_params.flight_plan = &mp_steps[0]; + mp_params.num_records = ARRAY_SIZE(mp_steps); + + /* Perform backup of default SMM area. */ + default_smm_area = backup_default_smm_area(); + + ret = mp_init(cpu_bus, &mp_params); + + restore_default_smm_area(default_smm_area); + + /* Signal callback on success if it's provided. */ + if (ret == 0 && mp_state.ops.post_mp_init != NULL) + mp_state.ops.post_mp_init(); + + return ret; +} diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 3227975..ff88a20 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -17,6 +17,7 @@ #define _X86_MP_H_ #include <arch/smp/atomic.h> +#include <cpu/x86/smm.h> #define CACHELINE_SIZE 64 @@ -78,6 +79,101 @@ struct mp_params { int num_records; }; +/* The sequence of the callbacks are in calling order. */ +struct mp_ops { + /* + * Optionally provide a callback prior to kicking off MP + * startup. This callback is done prior to loading the SIPI + * vector but after gathering the MP state information. Please + * see the sequence below. + */ + void (*pre_mp_init)(void); + /* + * Return the number of logical x86 execution contexts that + * need to be brought out of SIPI state as well as have SMM + * handlers installed. + */ + int (*get_cpu_count)(void); + /* + * Optionally fill in permanent SMM region and save state size. If + * this callback is not present no SMM handlers will be installed. + * The perm_smsize is the size available to house the permanent SMM + * handler. + */ + void (*get_smm_info)(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size); + /* + * Optionally fill in pointer to microcode and indicate if the APs + * can load the microcode in parallel. + */ + void (*get_microcode_info)(const void **microcode, int *parallel); + /* + * Optionally provide a function which adjusts the APIC id + * map to cpu number. By default the cpu number and APIC id + * are 1:1. To change the APIC id for a given cpu return the + * new APIC id. It's called for each cpu as indicated by + * get_cpu_count(). + */ + int (*adjust_cpu_apic_entry)(int cpu, int cur_apic_id); + /* + * Optionally adjust SMM handler parameters to override the default + * values. The is_perm variable indicates if the parameters to adjust + * are for the relocation handler or the permanent handler. This + * function is therefore called twice -- once for each handler. + * By default the parameters for each SMM handler are: + * stack_size num_concurrent_stacks num_concurrent_save_states + * relo: save_state_size get_cpu_count() 1 + * perm: save_state_size get_cpu_count() get_cpu_count() + */ + void (*adjust_smm_params)(struct smm_loader_params *slp, int is_perm); + /* + * Optionally provide a callback prior to the APs starting SMM + * relocation or cpu driver initialization. However, note that + * this callback is called after SMM handlers have been loaded. + */ + void (*pre_mp_smm_init)(void); + /* + * Optional function to use to trigger SMM to perform relocation. If + * not provided, smm_initiate_relocation() is used. + */ + void (*per_cpu_smm_trigger)(void); + /* + * This function is called while each cpu is in the SMM relocation + * handler. Its primary purpose is to adjust the SMBASE for the + * permanent handler. The parameters passed are the current cpu + * running the relocation handler, current SMBASE of relocation handler, + * and the pre-calculated staggered cpu SMBASE address of the permanent + * SMM handler. + */ + void (*relocation_handler)(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase); + /* + * Optionally provide a callback that is called after the APs + * and the BSP have gone through the initialion sequence. + */ + void (*post_mp_init)(void); +}; + +/* + * mp_init_with_smm() returns < 0 on failure and 0 on success. The mp_ops + * argument is used to drive the multiprocess initialization. Unless otherwise + * stated each callback is called on the BSP only. The sequence of operations + * is the following: + * 1. pre_mp_init() + * 2. get_cpu_count() + * 3. get_smm_info() + * 4. get_microcode_info() + * 5. adjust_cpu_apic_entry() for each number of get_cpu_count() + * 6. adjust_smm_params(is_perm=0) + * 7. adjust_smm_params(is_perm=1) + * 8. pre_mp_smm_init() + * 9. per_cpu_smm_trigger() in parallel for all cpus which calls + * relocation_handler() in SMM. + * 10. mp_initialize_cpu() for each cpu + * 11. post_mp_init() + */ +int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops); + /* * mp_init() will set up the SIPI vector and bring up the APs according to * mp_params. Each flight record will be executed according to the plan. Note

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2016