coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

1 participants
1843 discussions

Patch merged into coreboot/master: nb/intel/gm45: Fix native text mode initialization
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit 1e302cbd09bb304309476113c149c2c0d09a2a86 Author: Nick High <nhigh(a)openmailbox.org> Date: Tue Apr 26 17:22:05 2016 -0400 nb/intel/gm45: Fix native text mode initialization The LVDS port is configured to accept data from pipe A, but the panel fitter and VGA were attached to pipe B. Changes to VGACNTRL: - select pipe A instead of pipe B. - disable VGA centering to fix jitter. TEST=Build and run on Thinkpad X200 in both text and framebuffer modes. Change-Id: I2356f264580d8b021952c217de3477291d866f98 Signed-off-by: Nick High <nhigh(a)openmailbox.org> Reviewed-on: https://review.coreboot.org/14524 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See https://review.coreboot.org/14524 for details. -gerrit

1 0

Patch merged into coreboot/master: lib/reg_script: Add display support
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit 564dc9c7c89a94ff1b7803ef9937ca4f0dd95809 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 15:07:19 2016 -0700 lib/reg_script: Add display support Add the ability to enable the display of the script: * Added REG_SCRIPT_COMMAND_DISPLAY to enable and disable display output * Added context values to manage display support * display_state - Updated by the command to enable or disable display * display_features - May be updated by step routine to control what the step displays for register and value * display_prefix - Prefix to display before register data * Added REG_SCRIPT_DISPLAY_ON and REG_SCRIPT_DISPLAY_OFF macros to control the display from the register script * Added REG_SCRIPT_DISPLAY_REGISTER and REG_SCRIPT_DISPLAY_VALUE as two features of the common display. With these features enabled the following is output: * Write: <optional prefix> register <-- value * Read: <optional prefix> register --> value TEST=Build and run on Galileo Gen2 Change-Id: If0d4d61ed8ef48ec20082b327f358fd1987e3fb9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14553 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14553 for details. -gerrit

1 0

Patch set updated for coreboot: ec/google/chromeec/ec_lpc: Declare used IO ports as a resource
by Alexandru Gagniuc 04 May '16

04 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14585 -gerrit commit 2bddbf3754fed27e719eb59fa2b50da893a9ffe1 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Mar 30 14:38:44 2016 -0700 ec/google/chromeec/ec_lpc: Declare used IO ports as a resource Chrome EC uses IO ports 0x800 -> 0x9ff to communicate over LPC; however, those ports were not declared as a resource. This had two major downsides: * It allowed the allocator to assign said ports to other devices * It required manually open up an IO window in the LPC bridge. The LPC bridge on many chromeec boards had to be painstakingly adjusted to meet these constraints. The advantage of declaring the resources upfront is that the lpc bridge can now scan its child resources and automatically open up IO windows, as requested by its LPC children devices. Change-Id: I35c4e48dddb7300674d7a9858b590c1f20e3b0e3 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/ec/google/chromeec/ec_lpc.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 021735e..56196f0 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -409,7 +409,20 @@ static void lpc_ec_init(struct device *dev) static void lpc_ec_read_resources(struct device *dev) { - /* Nothing, but this function avoids an error on serial console. */ + unsigned int idx = 0; + struct resource * res; + + /* + * Declare the IO ports that we are using: + * 0x800->0x8ff: Two successive HOST_CMD regions, each 0x80 bytes + * 0x900->0x9ff: EC memory (check ecmem.asl) + */ + res = new_resource(dev, idx++); + res->base = EC_HOST_CMD_REGION0; + res->size = 2 * EC_HOST_CMD_REGION_SIZE; + if (!IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)) + res->size += EC_MEMMAP_SIZE; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void lpc_ec_enable_resources(struct device *dev)

1 0

Patch merged into coreboot/master: crosfirmware: Make script more silent
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit d3fccfbc41988b110d6861f53ee3b8908e90e422 Author: Joseph Pillow <joseph.a.pillow(a)gmail.com> Date: Thu Apr 21 16:15:10 2016 -0700 crosfirmware: Make script more silent Remove debug output and parted messages. Change-Id: I6416a88b5fdb4c92741439e9edb5f753f885cbe3 Signed-off-by: Joseph Pillow <joseph.a.pillow(a)gmail.com> Reviewed-on: https://review.coreboot.org/14460 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14460 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/fsp_baytrail: convert to using common MP and SMM init
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit 2a07a4d62b2512091abb3b38e753137a63347e2c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 3 11:31:32 2016 -0500 soc/intel/fsp_baytrail: convert to using common MP and SMM init In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I709ea938b720f26b351a1f950593efe077edb997 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14581 Tested-by: build bot (Jenkins) Reviewed-by: Ben Gardner <gardner.ben(a)gmail.com> See https://review.coreboot.org/14581 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/baytrail: convert to using common MP and SMM init
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit b04bb6550459f0e3d1eaaebe80029ed2692c728c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 3 11:12:52 2016 -0500 soc/intel/baytrail: convert to using common MP and SMM init In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I5c5d678d7adb4c489752cca80b20f785ec8749d4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14580 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)google.com> See https://review.coreboot.org/14580 for details. -gerrit

1 0

Patch merged into coreboot/master: cpu/x86: combine multiprocessor and SMM initialization
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit 82501922b67e41e596447aee5b42bc4655a927f4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 22:55:49 2016 -0500 cpu/x86: combine multiprocessor and SMM initialization In order to reduce code duplication provide a common flow through callback functions that performs the multiprocessor and optionally SMM initialization. The existing MP flight records are utilized but a common flow is provided such that the chipset/cpu only needs to provide a mp_ops structure which has callbacks to gather info and provide hooks at certain points in the sequence. All current users of the MP code can be switched over to this flow since there haven't been any flight records that are overly complicated and long. After the conversion has taken place most of the surface area of the MP API can be hidden away within the compilation unit proper. Change-Id: I6f70969631012982126f0d0d76e5fac6880c24f0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14557 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14557 for details. -gerrit

1 0

Patch merged into coreboot/master: cpu/x86: remove BACKUP_DEFAULT_SMM_REGION option
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit d87c7bc07c03d80fc7c346a027cb000657f1e76b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Apr 30 15:14:18 2016 -0500 cpu/x86: remove BACKUP_DEFAULT_SMM_REGION option Unconditionally provide the backup default SMM area API. There's no reason to guard the symbols behind anything since linker garbage collection is implemented. A board or chipset is free to use the code or not without needing to select an option. Change-Id: I14cf1318136a17f48ba5ae119507918190e25387 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14561 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14561 for details. -gerrit

1 0

Patch set updated for coreboot: soc/apollolake/lpc: Allow configuring SERIRQ via devicetree
by Alexandru Gagniuc 04 May '16

04 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14586 -gerrit commit 3080be10a5ddc7cffa6ce338da64cd16f43a722d Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon Apr 4 10:47:49 2016 -0700 soc/apollolake/lpc: Allow configuring SERIRQ via devicetree Every other SOC uses a CONFIG_* flag to enable or disable SERIRQ continuous mode. Why they do that is beyond me, but the way we implement it on apollolake is via devicetree. Change-Id: I6e05758e5e264c6b0015467dd25add3bffe2b040 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/chip.h | 10 ++++++++++ src/soc/intel/apollolake/lpc.c | 24 ++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 9d2bc46..d74084e 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -20,6 +20,13 @@ #define CLKREQ_DISABLED 0xf +/* Serial IRQ control. SERIRQ_QUIET is the default (0). */ +enum serirq_mode { + SERIRQ_QUIET, + SERIRQ_CONTINUOUS, + SERIRQ_OFF, +}; + struct soc_intel_apollolake_config { /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has @@ -32,6 +39,9 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp3_clkreq_pin; uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin; + + /* Configure serial IRQ (SERIRQ) line. */ + enum serirq_mode serirq_mode; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 5b552d8..ce9f001 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -22,6 +23,8 @@ #include <soc/lpc.h> #include <soc/pci_ids.h> +#include "chip.h" + /* * SCOPE: * The purpose of this driver is to eliminate manual resource allocation for @@ -40,6 +43,26 @@ * opens up IO and memory windows as needed. */ +static void lpc_init(struct device *dev) +{ + uint8_t scnt; + struct soc_intel_apollolake_config *cfg; + + cfg = dev->chip_info; + if (!cfg) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + + scnt = pci_read_config8(dev, REG_SERIRQ_CTL); + scnt &= ~(SCNT_EN | SCNT_MODE); + if (cfg->serirq_mode == SERIRQ_QUIET) + scnt |= SCNT_EN; + else if (cfg->serirq_mode == SERIRQ_CONTINUOUS); + scnt |= SCNT_EN | SCNT_MODE; + pci_write_config8(dev, REG_SERIRQ_CTL, scnt); +} + static void soc_lpc_add_io_resources(device_t dev) { struct resource *res; @@ -116,6 +139,7 @@ static struct device_operations device_ops = { .enable_resources = &pci_dev_enable_resources, .write_acpi_tables = southbridge_write_acpi_tables, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, + .init = lpc_init, .scan_bus = scan_lpc_bus, };

1 0

Patch set updated for coreboot: lib/reg_script: Add display support
by Leroy P Leahy 04 May '16

04 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14553 -gerrit commit beeb62c8738478663258de4477cb489dc4f59031 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 15:07:19 2016 -0700 lib/reg_script: Add display support Add the ability to enable the display of the script: * Added REG_SCRIPT_COMMAND_DISPLAY to enable and disable display output * Added context values to manage display support * display_state - Updated by the command to enable or disable display * display_features - May be updated by step routine to control what the step displays for register and value * display_prefix - Prefix to display before register data * Added REG_SCRIPT_DISPLAY_ON and REG_SCRIPT_DISPLAY_OFF macros to control the display from the register script * Added REG_SCRIPT_DISPLAY_REGISTER and REG_SCRIPT_DISPLAY_VALUE as two features of the common display. With these features enabled the following is output: * Write: <optional prefix> register <-- value * Read: <optional prefix> register --> value TEST=Build and run on Galileo Gen2 Change-Id: If0d4d61ed8ef48ec20082b327f358fd1987e3fb9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/reg_script.h | 22 +++++++++++++ src/lib/reg_script.c | 82 +++++++++++++++++++++++++++++++++++++++++------- 2 files changed, 93 insertions(+), 11 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index da01481..d7ed326 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -47,6 +47,10 @@ enum { REG_SCRIPT_COMMAND_POLL, REG_SCRIPT_COMMAND_SET_DEV, REG_SCRIPT_COMMAND_NEXT, + REG_SCRIPT_COMMAND_DISPLAY, + + /* Insert new types above this comment */ + REG_SCRIPT_COMMAND_END, }; @@ -92,6 +96,9 @@ struct reg_script_context { device_t dev; struct resource *res; const struct reg_script *step; + uint8_t display_state; /* Only modified by reg_script_run_step */ + uint8_t display_features; /* Step routine modifies to control display */ + const char *display_prefix; /* Prefix tag to display */ }; struct reg_script_bus_entry { @@ -132,6 +139,21 @@ struct reg_script_bus_entry { .res_index = res_index_, \ } +/* Display control */ +#define REG_SCRIPT_DISPLAY_ALL 0xff +#define REG_SCRIPT_DISPLAY_REGISTER 0x02 +#define REG_SCRIPT_DISPLAY_VALUE 0x01 +#define REG_SCRIPT_DISPLAY_NOTHING 0 + +#define REG_SCRIPT_DISPLAY_OFF \ + { .command = REG_SCRIPT_COMMAND_DISPLAY, \ + .value = REG_SCRIPT_DISPLAY_NOTHING, \ + } +#define REG_SCRIPT_DISPLAY_ON \ + { .command = REG_SCRIPT_COMMAND_DISPLAY, \ + .value = REG_SCRIPT_DISPLAY_ALL, \ + } + /* * PCI */ diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 9e20134..ace9325 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -415,24 +415,62 @@ static const struct reg_script_bus_entry return NULL; } +static void reg_script_display(struct reg_script_context *ctx, + const struct reg_script *step, const char *arrow, uint64_t value) +{ + /* Display the register address and data */ + if (ctx->display_prefix != NULL) + printk(BIOS_INFO, "%s: ", ctx->display_prefix); + if (ctx->display_features & REG_SCRIPT_DISPLAY_REGISTER) + printk(BIOS_INFO, "0x%08x %s ", step->reg, arrow); + if (ctx->display_features & REG_SCRIPT_DISPLAY_VALUE) + switch (step->size) { + case REG_SCRIPT_SIZE_8: + printk(BIOS_INFO, "0x%02x\n", (uint8_t)value); + break; + case REG_SCRIPT_SIZE_16: + printk(BIOS_INFO, "0x%04x\n", (int16_t)value); + break; + case REG_SCRIPT_SIZE_32: + printk(BIOS_INFO, "0x%08x\n", (uint32_t)value); + break; + default: + printk(BIOS_INFO, "0x%016llx\n", value); + break; + } +} + static uint64_t reg_script_read(struct reg_script_context *ctx) { const struct reg_script *step = reg_script_get_step(ctx); + uint64_t value = 0; switch (step->type) { case REG_SCRIPT_TYPE_PCI: - return reg_script_read_pci(ctx); + ctx->display_prefix = "PCI"; + value = reg_script_read_pci(ctx); + break; case REG_SCRIPT_TYPE_IO: - return reg_script_read_io(ctx); + ctx->display_prefix = "IO"; + value = reg_script_read_io(ctx); + break; case REG_SCRIPT_TYPE_MMIO: - return reg_script_read_mmio(ctx); + ctx->display_prefix = "MMIO"; + value = reg_script_read_mmio(ctx); + break; case REG_SCRIPT_TYPE_RES: - return reg_script_read_res(ctx); + ctx->display_prefix = "RES"; + value = reg_script_read_res(ctx); + break; case REG_SCRIPT_TYPE_MSR: - return reg_script_read_msr(ctx); + ctx->display_prefix = "MSR"; + value = reg_script_read_msr(ctx); + break; #if HAS_IOSF case REG_SCRIPT_TYPE_IOSF: - return reg_script_read_iosf(ctx); + ctx->display_prefix = "IOSF"; + value = reg_script_read_iosf(ctx); + break; #endif /* HAS_IOSF */ default: { @@ -441,14 +479,19 @@ static uint64_t reg_script_read(struct reg_script_context *ctx) /* Read from the platform specific bus */ bus = find_bus(step); if (NULL != bus) - return bus->reg_script_read(ctx); + value = bus->reg_script_read(ctx); + break; } printk(BIOS_ERR, "Unsupported read type (0x%x) for this device!\n", step->type); - break; + return 0; } - return 0; + + /* Display the register address and data */ + if (ctx->display_features) + reg_script_display(ctx, step, "-->", value); + return value; } static void reg_script_write(struct reg_script_context *ctx) @@ -457,22 +500,28 @@ static void reg_script_write(struct reg_script_context *ctx) switch (step->type) { case REG_SCRIPT_TYPE_PCI: + ctx->display_prefix = "PCI"; reg_script_write_pci(ctx); break; case REG_SCRIPT_TYPE_IO: + ctx->display_prefix = "IO"; reg_script_write_io(ctx); break; case REG_SCRIPT_TYPE_MMIO: + ctx->display_prefix = "MMIO"; reg_script_write_mmio(ctx); break; case REG_SCRIPT_TYPE_RES: + ctx->display_prefix = "RES"; reg_script_write_res(ctx); break; case REG_SCRIPT_TYPE_MSR: + ctx->display_prefix = "MSR"; reg_script_write_msr(ctx); break; #if HAS_IOSF case REG_SCRIPT_TYPE_IOSF: + ctx->display_prefix = "IOSF"; reg_script_write_iosf(ctx); break; #endif /* HAS_IOSF */ @@ -484,14 +533,18 @@ static void reg_script_write(struct reg_script_context *ctx) bus = find_bus(step); if (NULL != bus) { bus->reg_script_write(ctx); - return; + break; } } printk(BIOS_ERR, "Unsupported write type (0x%x) for this device!\n", step->type); - break; + return; } + + /* Display the register address and data */ + if (ctx->display_features) + reg_script_display(ctx, step, "<--", step->value); } static void reg_script_rmw(struct reg_script_context *ctx) @@ -557,6 +610,8 @@ static void reg_script_run_step(struct reg_script_context *ctx, { uint64_t value = 0, try; + ctx->display_features = ctx->display_state; + ctx->display_prefix = NULL; switch (step->command) { case REG_SCRIPT_COMMAND_READ: (void)reg_script_read(ctx); @@ -589,6 +644,10 @@ static void reg_script_run_step(struct reg_script_context *ctx, case REG_SCRIPT_COMMAND_NEXT: reg_script_run_next(ctx, step->next); break; + case REG_SCRIPT_COMMAND_DISPLAY: + ctx->display_state = step->value; + break; + default: printk(BIOS_WARNING, "Invalid command: %08x\n", step->command); @@ -624,6 +683,7 @@ void reg_script_run_on_dev(device_t dev, const struct reg_script *step) { struct reg_script_context ctx; + ctx.display_state = REG_SCRIPT_DISPLAY_NOTHING; reg_script_set_dev(&ctx, dev); reg_script_set_step(&ctx, step); reg_script_run_with_context(&ctx);

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2016