coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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Patch set updated for filo: Point to the correct libpayload path
by Stefan Reinauer 04 May '16

04 May '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14355 -gerrit commit 70d4dd247f91b1a01466d931ecd1b7eb89e67c89 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 13 16:23:48 2016 -0700 Point to the correct libpayload path libpayload is not standalone, so assume it lives under coreboot to make out of the box builds easier. Change-Id: Ib6240e7459a7e56f911c01e1ebe9f535cc0e50ad Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 35d2b6e..4d4472e 100644 --- a/Makefile +++ b/Makefile @@ -26,10 +26,14 @@ export obj := $(src)/build export objk := $(src)/build/util/kconfig ifndef LIBCONFIG_PATH - LIBCONFIG_PATH := $(src)/../libpayload +LIBCONFIG_PATH := $(src)/../coreboot/payloads/libpayload endif export LIBCONFIG_PATH +ifeq ($(wildcard $(LIBCONFIG_PATH)/*),) +$(error Could not find libpayload at $(LIBCONFIG_PATH)) +endif + export KERNELVERSION := $(PROGRAM_VERSION) export KCONFIG_AUTOHEADER := $(obj)/config.h export KCONFIG_AUTOCONFIG := $(obj)/auto.conf

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Patch merged into filo/master: Add ARM support
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit c83796450f685dc81229631f5f2e9a554927b3f8 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 14 15:48:17 2016 -0700 Add ARM support Change-Id: I9325f6df06cf85ecd77abef5c0a7b4d2742466f4 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14370 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli(a)googlemail.com> See https://review.coreboot.org/14370 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Update Python to 3.5.1
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit 3dc5d079fe99472b1e82cb28d75fffa735a1bd6a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 21 19:29:03 2016 -0700 buildgcc: Update Python to 3.5.1 Change-Id: I57f935b94ab0db2e9ff9434fb496d470bb4ec987 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14463 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14463 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Update gdb and expat
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit 498f3d0cd59d3c3e6ff2ef43f24e205b249556f8 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 21 18:10:15 2016 -0700 buildgcc: Update gdb and expat Update gdb to 7.11 and expat to 2.1.1 riscv64-elf is still broken. Change-Id: Id7605f4274fcb15f9c3e366f5c492328f70f7956 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14461 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See https://review.coreboot.org/14461 for details. -gerrit

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Patch merged into coreboot/master: crossgcc: Update toolchain
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit ae8e3a0bbb1d028e9d18572304ec93e1495976f5 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Sat Apr 2 10:50:59 2016 +0800 crossgcc: Update toolchain New tools: * mpfr 3.1.4 * binutils 2.26 * gcc 5.3.0 * llvm/clang 3.8.0 Patch changes: * binutils-2.25_fix-aarch64.patch: fixed in 2.26 * binutils-2.25_host-clang.patch: the positions of header file includes have been adjusted * binutils-2.25_no-bfd-doc.patch: update to 2.26 * binutils-2.25_riscv.patch: update from riscv-gnu-toolchain * gcc-5.2.0_elf_biarch.patch: update to 5.3.0 * gcc-5.2.0_gnat.patch: update to 5.3.0 * gcc-5.2.0_libgcc.patch: update to 5.3.0 * gcc-5.2.0_nds32.patch: update to 5.3.0 * gcc-5.2.0_riscv.patch: update from riscv-gnu-toolchain * cfe-3.7.1.src_frontend.patch: update to 3.8.0 In the latest code of riscv-gnu-toolchain project, the patch for {binutils,gcc}/config.sub has been removed, and the target is renamed as riscv32 and riscv64. The `riscv' to `riscv64' change in xcompile is in another commit. Test results: All GCC and LLVM/clang toolchain build successfully. x86,arm: qemu boots power8: firmware fails to boot aarch64,mips: not tested riscv: firmware fails to build with new binutils clang: firmware fails to boot Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Change-Id: I42ce89c29263d768d161c28199994f17d0389633 Reviewed-on: https://review.coreboot.org/14227 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14227 for details. -gerrit

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Patch merged into coreboot/master: soc/apollolake: Set BootMode based on previous sleep state
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit 2da008afa622e5469a34cd9d9712d498e84e4ea8 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Wed Apr 27 15:20:14 2016 -0700 soc/apollolake: Set BootMode based on previous sleep state - fill_power_state makes a copy of the current snapshot of power management registers in CAR variable "power_state" for use in ramstage - migrate_power_state adds CAR variable "power_state" to CBMEM (CBMEM_ID_POWER_STATE) - s3_resume state is updated in romstage_handoff block Change-Id: I842b85c5e562893b58cd3b3f6432695fbd4430bf Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Reviewed-on: https://review.coreboot.org/14550 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14550 for details. -gerrit

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Patch merged into coreboot/master: soc/apollolake/romstage: Do not cast const to non-const pointers
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit 15f755bd01d6bf9692ed0395d1f813dca9fa2013 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon May 2 13:40:15 2016 -0700 soc/apollolake/romstage: Do not cast const to non-const pointers That was a workaround for the MRC cache API, which has since been reworked. The workaround is no longer needed. Change-Id: I1c1883f3ea37245615248459cd993ed774bf92de Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Reviewed-on: https://review.coreboot.org/14574 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14574 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/common/mrc_cache: Honor MRC data as a constant pointer
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit 1116fa86e3f4f1cf50773ba0959d9d4f7a5ebb92 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Mar 4 14:38:19 2016 -0800 soc/intel/common/mrc_cache: Honor MRC data as a constant pointer The MRC cache API has absolutely no reason to modify the data it is asked to stash. Reflect that by taking all "data" parameters as const void *. Change-Id: I7a14ffd7d5726aa9aa5db81df82c06e7f87b9d9f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Reviewed-on: https://review.coreboot.org/14250 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> See https://review.coreboot.org/14250 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/sandybridge/raminit: support calling dram_freq multiple times
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit 9c9bde3aa35922cf680c91f9260dd7905cc8cb6b Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 17:20:02 2016 +0100 nb/intel/sandybridge/raminit: support calling dram_freq multiple times The PLL will never lock if the requested frequency is already set. As the fallback may request the same frequency again exit early to prevent a hang. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I625b2956346d8c50cca84def6190c076bf99dbec Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/14174 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14174 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/sandybridge/raminit: add additional fallbacks
by gerrit＠coreboot.org 04 May '16

04 May '16

the following patch was just integrated into master: commit 2ccb74b6e97381ce2b2f8520076204f7737ade4c Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 12:16:29 2016 +0100 nb/intel/sandybridge/raminit: add additional fallbacks Add the following fallbacks: * Try decreasing clock frequency. In case of DDR1600 the next possible value of DDR1333 is being used. * Try decreasing clock frequency. In case of DDR1333 the next possible value of DDR1066 is being used. * Disable failing channel. The system may be able to boot with a single channel enabled. The fallbacks are untested. Change-Id: I3be7034ad25312b3ebf47a54f335a3893f8d7cc1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/14173 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14173 for details. -gerrit

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coreboot-gerrit May 2016