coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: drivers/intel/fsp2_0: Update to FSP draft 9
by Andrey Petrov 05 May '16

05 May '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14614 -gerrit commit 63dcb5e1a21c1c6f3e7fd907a0e85f5d0e815291 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed May 4 17:30:16 2016 -0700 drivers/intel/fsp2_0: Update to FSP draft 9 Recent FSP draft slightly changed FSP_INFO_HEADER structure. This change keeps FSP driver code in sync with header changes. Change-Id: I3536f766a312b9eb73ab8940d91dc9b9dfa347f1 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/info_header.h | 10 ++++--- src/drivers/intel/fsp2_0/util.c | 34 ++++++++++++++++++---- 2 files changed, 35 insertions(+), 9 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 468101e..2d30614 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -21,15 +21,17 @@ #define FSP_HDR_OFFSET 0x94 #define FSP_HDR_LEN 0x48 #define FSP_HDR_SIGNATURE "FSPH" -#define FSP_HDR_ATTRIB_FSPT (0b0001 << 28) -#define FSP_HDR_ATTRIB_FSPM (0b0010 << 28) -#define FSP_HDR_ATTRIB_FSPS (0b0011 << 28) +#define FSP_HDR_ATTRIB_FSPT 0b0001 +#define FSP_HDR_ATTRIB_FSPM 0b0010 +#define FSP_HDR_ATTRIB_FSPS 0b0011 struct fsp_header { uint32_t fsp_revision; size_t image_size; uintptr_t image_base; - uint32_t image_attribute; + uint16_t image_attribute; + uint8_t spec_version; + uint16_t component_attribute; size_t cfg_region_offset; size_t cfg_region_size; size_t notify_phase_entry_offset; diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 743bc9a..2eb6cf9 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -42,13 +42,15 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) if (!looks_like_fsp_header(raw_hdr)) return CB_ERR; + hdr->spec_version = read8(raw_hdr + 10); hdr->revision = read8(raw_hdr + 11); hdr->fsp_revision = read32(raw_hdr + 12); memcpy(hdr->image_id, raw_hdr + 16, ARRAY_SIZE(hdr->image_id)); hdr->image_id[ARRAY_SIZE(hdr->image_id) - 1] = '\0'; hdr->image_size = read32(raw_hdr + 24); hdr->image_base = read32(raw_hdr + 28); - hdr->image_attribute = read32(raw_hdr + 32); + hdr->image_attribute = read16(raw_hdr + 32); + hdr->component_attribute = read16(raw_hdr + 34); hdr->cfg_region_offset = read32(raw_hdr + 36); hdr->cfg_region_size = read32(raw_hdr + 40); hdr->notify_phase_entry_offset = read32(raw_hdr + 56); @@ -60,17 +62,39 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) void fsp_print_header_info(const struct fsp_header *hdr) { - printk(BIOS_DEBUG, "Revision %u, image ID: %s, base 0x%lx + 0x%zx\n", - hdr->revision, hdr->image_id, hdr->image_base, hdr->image_size); + union { + uint32_t val; + struct { + uint8_t bld_num; + uint8_t revision; + uint8_t minor; + uint8_t major; + } rev; + } revision; + + revision.val = hdr->fsp_revision; + + printk(BIOS_DEBUG, "Spec version: v%u.%u\n", (hdr->spec_version >> 4 ), + hdr->spec_version & 0xf); + printk(BIOS_DEBUG, "Revision: %u.%u.%u, Build Number %u\n", + revision.rev.major, + revision.rev.minor, + revision.rev.revision, + revision.rev.bld_num); + printk(BIOS_DEBUG, "Type: %s/%s\n", + (hdr->component_attribute & 1 ) ? "release" : "debug", + (hdr->component_attribute & 2 ) ? "test" : "official"); + printk(BIOS_DEBUG, "image ID: %s, base 0x%lx + 0x%zx\n", + hdr->image_id, hdr->image_base, hdr->image_size); printk(BIOS_DEBUG, "\tConfig region 0x%zx + 0x%zx\n", hdr->cfg_region_offset, hdr->cfg_region_size); - if (hdr->image_attribute & FSP_HDR_ATTRIB_FSPM) { + if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) { printk(BIOS_DEBUG, "\tMemory init offset 0x%zx\n", hdr->memory_init_entry_offset); } - if (hdr->image_attribute & FSP_HDR_ATTRIB_FSPS) { + if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) { printk(BIOS_DEBUG, "\tSilicon init offset 0x%zx\n", hdr->silicon_init_entry_offset); printk(BIOS_DEBUG, "\tNotify phase offset 0x%zx\n",

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New patch to review for coreboot: soc/intel/apollolake: Correct PCI write size in romstage
by Furquan Shaikh 05 May '16

05 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14613 -gerrit commit a2546983dd6c13ef806c48364cf54a8e38256dd5 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 4 16:03:36 2016 -0700 soc/intel/apollolake: Correct PCI write size in romstage 1. PCI command reg write should be 16-bit. 2. HPTC reg write should be 8-bit. Also, use macros instead of hard-coded values. Currently, the macros are defined in romstage.c, but if more P2SB macros are added, it would be good to move them to a separate header file. Change-Id: Iad1eb6a95467a41ecf454092808d357425c4c2fc Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/romstage.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 6b49bbd..8ec94a7 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -44,6 +44,21 @@ static struct chipset_power_state power_state CAR_GLOBAL; +/* High Performance Event Timer Configuration */ +#define P2SB_HPTC 0x60 +#define P2SB_HPTC_ADDRESS_ENABLE (1 << 7) +/* + * ADDRESS_SELECT ENCODING_RANGE + * 0 0xFED0 0000 - 0xFED0 03FF + * 1 0xFED0 1000 - 0xFED0 13FF + * 2 0xFED0 2000 - 0xFED0 23FF + * 3 0xFED0 3000 - 0xFED0 33FF + */ +#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0) +#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0) +#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0) +#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0) + /* * Enables several BARs and devices which are needed for memory init * - MCH_BASE_ADDR is needed in order to talk to the memory controller @@ -65,12 +80,13 @@ static void soc_early_romstage_init(void) pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); - pci_write_config32(pmc, PCI_COMMAND, + pci_write_config16(pmc, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); /* Enable decoding for HPET. Needed for FSP global pointer storage */ - pci_write_config32(P2SB_DEV, 0x60, 1<<7); + pci_write_config8(P2SB_DEV, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | + P2SB_HPTC_ADDRESS_ENABLE); } static void disable_watchdog(void)

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New patch to review for coreboot: drivers/uart: Use uart_platform_refclk for all UART models
by Leroy P Leahy 05 May '16

05 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14612 -gerrit commit 54c609fa6fe75a42a6b1d6faa15e02f138992b10 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Mar 16 10:21:59 2016 -0700 drivers/uart: Use uart_platform_refclk for all UART models Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/cpu/allwinner/a10/Kconfig | 1 + src/cpu/ti/am335x/Kconfig | 1 + src/drivers/uart/Kconfig | 8 ++++++++ src/drivers/uart/uart8250io.c | 7 +------ src/drivers/uart/util.c | 7 +++++++ src/soc/imgtec/pistachio/Kconfig | 1 + src/soc/intel/apollolake/uart_early.c | 6 ------ src/soc/intel/quark/Kconfig | 1 + src/soc/intel/skylake/uart_debug.c | 11 ----------- src/soc/marvell/armada38x/Kconfig | 1 + src/soc/nvidia/tegra132/Kconfig | 1 + src/southbridge/amd/pi/hudson/Kconfig | 1 + 12 files changed, 23 insertions(+), 23 deletions(-) diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 814b69e..0e5aba9 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -13,5 +13,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE + select UART_OVERRIDE_REFCLK endif # if CPU_ALLWINNER_A10 diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index 8d3c691..f44c69d 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -7,5 +7,6 @@ config CPU_TI_AM335X select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select GENERIC_UDELAY + select UART_OVERRIDE_REFCLK bool default n diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index aaf6e0e..cae9453 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -20,6 +20,13 @@ config UART_OVERRIDE_INPUT_CLOCK_DIVIDER Set to "y" when the platform overrides the uart_input_clock_divider routine. +config UART_OVERRIDE_REFCLK + boolean + default n + help + Set to "y" when the platform overrides the uart_platform_refclk + routine. + config DRIVERS_UART_8250MEM bool default n @@ -39,6 +46,7 @@ config DRIVERS_UART_OXPCIE depends on PCI select DRIVERS_UART_8250MEM select EARLY_PCI_BRIDGE + select UART_OVERRIDE_REFCLK help Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index d85e497..59e0b11 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -27,11 +27,6 @@ /* Should support 8250, 16450, 16550, 16550A type UARTs */ -/* Nominal values only, good for the range of choices Kconfig offers for - * set of standard baudrates. - */ -#define BAUDRATE_REFCLK (115200 * 16) - /* Expected character delay at 1200bps is 9ms for a working UART * and no flow-control. Assume UART as stuck if shift register * or FIFO takes more than 50ms per character to appear empty. @@ -110,7 +105,7 @@ uintptr_t uart_platform_base(int idx) void uart_init(int idx) { unsigned int div; - div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK, + div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), uart_input_clock_divider()); uart8250_init(uart_platform_base(idx), div); } diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index 53c32ed..d92c7e4 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -49,3 +49,10 @@ unsigned int uart_input_clock_divider(void) return 16; } #endif + +# if !IS_ENABLED(CONFIG_UART_OVERRIDE_REFCLK) +unsigned int uart_platform_refclk(void) +{ + return 115200 * 16; +} +#endif diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 5ea6b95..da33cc5 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -25,6 +25,7 @@ config CPU_IMGTEC_PISTACHIO select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB select HAVE_HARD_RESET + select UART_OVERRIDE_REFCLK bool if CPU_IMGTEC_PISTACHIO diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c index e8dfeda..0e53060 100644 --- a/src/soc/intel/apollolake/uart_early.c +++ b/src/soc/intel/apollolake/uart_early.c @@ -68,12 +68,6 @@ uintptr_t uart_platform_base(int idx) return (CONFIG_CONSOLE_UART_BASE_ADDRESS); } -unsigned int uart_platform_refclk(void) -{ - /* That's within 0.5% of the actual value we've set earlier */ - return 115200 * 16; -} - static const struct pad_config uart_gpios[] = { PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */ diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index ebdc899..1eb4fff 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_SETS_MTRRS select TSC_CONSTANT_RATE + select UART_OVERRIDE_REFCLK select UDELAY_TSC select UNCOMPRESSED_RAMSTAGE select USE_MARCH_586 diff --git a/src/soc/intel/skylake/uart_debug.c b/src/soc/intel/skylake/uart_debug.c index c463bea..f3d576b 100644 --- a/src/soc/intel/skylake/uart_debug.c +++ b/src/soc/intel/skylake/uart_debug.c @@ -18,17 +18,6 @@ #include <soc/iomap.h> #include <soc/serialio.h> -unsigned int uart_platform_refclk(void) -{ - /* - * Set M and N divisor inputs and enable clock. - * Main reference frequency to UART is: - * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz - * The different order below is to handle integer math overflow. - */ - return 120 * MHz / SIO_REG_PPR_CLOCK_N_DIV * SIO_REG_PPR_CLOCK_M_DIV; -} - uintptr_t uart_platform_base(int idx) { /* Same base address for all debug port usage. In reality UART2 diff --git a/src/soc/marvell/armada38x/Kconfig b/src/soc/marvell/armada38x/Kconfig index 6754a0f..ed8cbe8 100644 --- a/src/soc/marvell/armada38x/Kconfig +++ b/src/soc/marvell/armada38x/Kconfig @@ -10,6 +10,7 @@ config SOC_MARVELL_ARMADA38X select RETURN_FROM_VERSTAGE select BOOTBLOCK_CUSTOM select GENERIC_UDELAY + select UART_OVERRIDE_REFCLK if SOC_MARVELL_ARMADA38X diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 502e7c4..08ed475 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -13,6 +13,7 @@ config SOC_NVIDIA_TEGRA132 select HAVE_HARD_RESET select HAVE_UART_SPECIAL select GENERIC_GPIO_LIB + select UART_OVERRIDE_REFCLK if SOC_NVIDIA_TEGRA132 diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index aa55339..8fe3b2d 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -235,6 +235,7 @@ config HUDSON_UART select DRIVERS_UART_8250MEM select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO + select UART_OVERRIDE_REFCLK help There are two UART controllers in Kern. The UART registers are memory-mapped. UART

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New patch to review for coreboot: drivers/uart: Enable override for input clock divider
by Leroy P Leahy 05 May '16

05 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14611 -gerrit commit 51f39261b7228eecff4c59bd3390c5df23a74711 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed May 4 13:13:20 2016 -0700 drivers/uart: Enable override for input clock divider Allow the platform to override the input clock divider by adding the uart_input_clock_divider routine. This routine combines the baud-rate oversample divider with any other input clock divider. The default routine returns 16 which is the standard baud-rate oversampling value. A platform may override this default "weak" routine by providing a new routine and selecting UART_OVERRIDE_INPUT_CLOCK_DIVIDER. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Ieb6453b045d84702b8f730988d0fed9f253f63e2 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/uart/Kconfig | 7 +++++++ src/drivers/uart/uart8250io.c | 5 ++--- src/drivers/uart/uart8250mem.c | 3 ++- src/drivers/uart/util.c | 7 +++++++ src/include/console/uart.h | 4 ++++ 5 files changed, 22 insertions(+), 4 deletions(-) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index dbdfcb0..aaf6e0e 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -13,6 +13,13 @@ config DRIVERS_UART_8250IO config NO_UART_ON_SUPERIO def_bool n +config UART_OVERRIDE_INPUT_CLOCK_DIVIDER + boolean + default n + help + Set to "y" when the platform overrides the uart_input_clock_divider + routine. + config DRIVERS_UART_8250MEM bool default n diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 9fdf8a1..d85e497 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -30,8 +30,7 @@ /* Nominal values only, good for the range of choices Kconfig offers for * set of standard baudrates. */ -#define BAUDRATE_REFCLK (115200) -#define BAUDRATE_OVERSAMPLE (1) +#define BAUDRATE_REFCLK (115200 * 16) /* Expected character delay at 1200bps is 9ms for a working UART * and no flow-control. Assume UART as stuck if shift register @@ -112,7 +111,7 @@ void uart_init(int idx) { unsigned int div; div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK, - BAUDRATE_OVERSAMPLE); + uart_input_clock_divider()); uart8250_init(uart_platform_base(idx), div); } diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index f7e0cdf..9dac2f7 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -117,7 +117,8 @@ void uart_init(int idx) return; unsigned int div; - div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16); + div = uart_baudrate_divisor(default_baudrate(), + uart_platform_refclk(), uart_input_clock_divider()); uart8250_mem_init(base, div); } diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index 4121f60..53c32ed 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -42,3 +42,10 @@ unsigned int uart_baudrate_divisor(unsigned int baudrate, { return (1 + (2 * refclk) / (baudrate * oversample)) / 2; } + +# if !IS_ENABLED(CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER) +unsigned int uart_input_clock_divider(void) +{ + return 16; +} +#endif diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 8458086..a3d650b 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -35,6 +35,10 @@ unsigned int default_baudrate(void); unsigned int uart_baudrate_divisor(unsigned int baudrate, unsigned int refclk, unsigned int oversample); +/* Returns the oversample divisor multiplied by any other divisors that act + * on the input clock + */ +unsigned int uart_input_clock_divider(void); void uart_init(int idx); void uart_tx_byte(int idx, unsigned char data);

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New patch to review for coreboot: soc/intel/quark: Identify the console UART
by Leroy P Leahy 05 May '16

05 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14610 -gerrit commit 720d8c64b78b4121eb15362180a2ea5ba1539530 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed May 4 12:50:51 2016 -0700 soc/intel/quark: Identify the console UART Pass the UART identifier to CorebootPayloadPkg Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: I9db1c31c3544d56b66f5a79ac8c3acee41788983 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 8485aa3..ebdc899 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -60,6 +60,12 @@ config TTYS0_LCS depends on ENABLE_BUILTIN_HSUART1 default 3 +# Console: PCI UART bus 0 << 20, device 20 << 15, function 5 << 12 +config UART_PAYLOAD_PARAM + hex + depends on ENABLE_BUILTIN_HSUART1 + default 0x000a5000 + ##### # Debug support # The following options provide debug support for the Quark coreboot

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New patch to review for coreboot: coreboot_tables: Extend serial port description
by Leroy P Leahy 05 May '16

05 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14609 -gerrit commit 25c8a79f3f9e5712985b1fef59ae788ab5085248 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed May 4 11:59:19 2016 -0700 coreboot_tables: Extend serial port description Extend the serial port description to include the input clock frequency and a payload specific value. Without the input frequency it is impossible for the payload to compute the baud-rate divisor without making an assumption about the frequency. This breaks down when the UART is able to support multiple input clock frequencies. Add a payload specific value to provide the payload with additional data. The UART_PAYLOAD_PARAM Kconfig value provides the default for this field to prevent breaking existing coreboot implementations and allow this value to be easily selected for the payloads. Currently the only payload to consume these new fields is the EDK-II CorebootPayloadPkg. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Id4b4455bbf9583f0d66c315d38c493a81fd852a8 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- payloads/libpayload/include/coreboot_tables.h | 10 ++++++++++ src/commonlib/include/commonlib/coreboot_tables.h | 10 ++++++++++ src/drivers/uart/Kconfig | 13 +++++++++++++ src/drivers/uart/oxpcie_early.c | 5 +++++ src/drivers/uart/pl011.c | 5 +++++ src/drivers/uart/uart8250io.c | 5 +++++ src/drivers/uart/uart8250mem.c | 5 +++++ src/lib/coreboot_table.c | 2 ++ 8 files changed, 55 insertions(+) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 276f25f..039bb66 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -121,6 +121,16 @@ struct cb_serial { u32 baseaddr; u32 baud; u32 regwidth; + + /* Crystal or input frequency to the chip containing the UART. + * Provide the board specific details to allow the payload to + * initialize the chip containing the UART and make independent + * decisions as to which dividers to select and their values + * to eventually arrive at the desired console baud-rate. */ + uint32_t input_hertz; + + /* Payload specific value */ + uint32_t payload_param; }; #define CB_TAG_CONSOLE 0x00010 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 5c28791..ed9abbb 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -173,6 +173,16 @@ struct lb_serial { uint32_t baseaddr; uint32_t baud; uint32_t regwidth; + + /* Crystal or input frequency to the chip containing the UART. + * Provide the board specific details to allow the payload to + * initialize the chip containing the UART and make independent + * decisions as to which dividers to select and their values + * to eventually arrive at the desired console baud-rate. */ + uint32_t input_hertz; + + /* Payload specific value */ + uint32_t payload_param; }; #define LB_TAG_CONSOLE 0x0010 diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index f4ad011..dbdfcb0 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -41,3 +41,16 @@ config DRIVERS_UART_PL011 bool default n select HAVE_UART_SPECIAL + +config UART_USE_REFCLK_AS_INPUT_CLOCK + bool + default n + help + Use uart_platform_refclk to specify the input clock value. + +config UART_PAYLOAD_PARAM + hex "Payload specific parameter for UART configuration" + default 0 + help + Payload specific value to help with UART configuration. Refer to + the payload to determine the proper value to use. diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index eb91d31..60a598a 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -92,6 +92,11 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); serial.regwidth = 1; + if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK)) + serial.input_hertz = uart_platform_refclk(); + else + serial.input_hertz = 0; + serial.payload_param = CONFIG_UART_PAYLOAD_PARAM; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index aa55c68..9e9e6bd 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -48,6 +48,11 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); serial.regwidth = 1; + if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK)) + serial.input_hertz = uart_platform_refclk(); + else + serial.input_hertz = 0; + serial.payload_param = CONFIG_UART_PAYLOAD_PARAM; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 63bc42f..9fdf8a1 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -139,6 +139,11 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); serial.regwidth = 1; + if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK)) + serial.input_hertz = uart_platform_refclk(); + else + serial.input_hertz = 0; + serial.payload_param = CONFIG_UART_PAYLOAD_PARAM; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 278ddb8..f7e0cdf 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -156,6 +156,11 @@ void uart_fill_lb(void *data) serial.regwidth = sizeof(uint32_t); else serial.regwidth = sizeof(uint8_t); + if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK)) + serial.input_hertz = uart_platform_refclk(); + else + serial.input_hertz = 0; + serial.payload_param = CONFIG_UART_PAYLOAD_PARAM; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 4dbac19..f532e36 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -119,6 +119,8 @@ void lb_add_serial(struct lb_serial *new_serial, void *data) serial->baseaddr = new_serial->baseaddr; serial->baud = new_serial->baud; serial->regwidth = new_serial->regwidth; + serial->input_hertz = new_serial->input_hertz; + serial->payload_param = new_serial->payload_param; } void lb_add_console(uint16_t consoletype, void *data)

1 0

Patch set updated for coreboot: soc/intel/quark: Add temperature sensor support
by Leroy P Leahy 05 May '16

05 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14565 -gerrit commit f37e85f8241da1804d4f10689ea26ad1b2a12971 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 30 08:48:52 2016 -0700 soc/intel/quark: Add temperature sensor support Migrate the temperature sensor support from QuarkFspPkg into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: I6dc68c735375c9d1777693264674521f67397556 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/chip.c | 95 ++++++++++++++++++++++++++++ src/soc/intel/quark/include/soc/reg_access.h | 48 ++++++++++++++ src/soc/intel/quark/reg_access.c | 54 ++++++++++++++++ 3 files changed, 197 insertions(+) diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 7ea8a06..30ab48a 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -17,9 +17,104 @@ #include <console/console.h> #include <device/device.h> #include <soc/ramstage.h> +#include <soc/reg_access.h> + +/* Cat Trip Clear value must be less than Cat Trip Set value */ +#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105 +#define PLATFORM_CATASTROPHIC_CLEAR_CELSIUS 65 + +static const struct reg_script thermal_init_script[] = { + + /* Setup RMU Thermal sensor registers for Ratiometric mode. */ + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG, + ~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK + | B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK + | B_TSCGF1_CONFIG_ISNSINTERNALVREFEN + | B_TSCGF1_CONFIG_IBGEN + | B_TSCGF1_CONFIG_IBGCHOPEN), + ((V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP) + | (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSCHOPSEL_BP) + | (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP) + | (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE + << B_TSCGF1_CONFIG_IBGEN_BP) + | (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE + << B_TSCGF1_CONFIG_IBGCHOPEN_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2, + ~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK + | B_TSCGF2_CONFIG2_ISPARECTRL_MASK + | B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK), + ((V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE + << B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP) + | (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE + << B_TSCGF2_CONFIG2_ISPARECTRL_BP) + | (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE + << B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG, + ~(B_TSCGF2_CONFIG_IDSCONTROL_MASK + | B_TSCGF2_CONFIG_IDSTIMING_MASK), + ((V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE + << B_TSCGF2_CONFIG_IDSCONTROL_BP) + | (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE + << B_TSCGF2_CONFIG_IDSTIMING_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, + ~B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK, + V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE + << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP), + + /* Enable RMU Thermal sensor with a Catastrophic Trip point. */ + + /* Set up Catastrophic Trip point. + * + * Trip Register fields are 8-bit temperature values of granularity 1 + * degree C where 0x00 corresponds to -50 degrees C and 0xFF corresponds + * to 205 degrees C. + * + * Add 50 to Celsius values to get values for register fields. + */ + REG_RMU_TEMP_RMW(QUARK_NC_RMU_REG_TS_TRIP, + ~(TS_CAT_TRIP_SET_THOLD_MASK | TS_CAT_TRIP_CLEAR_THOLD_MASK), + (((PLATFORM_CATASTROPHIC_TRIP_CELSIUS + 50) + << TS_CAT_TRIP_SET_THOLD_BP) + | ((PLATFORM_CATASTROPHIC_CLEAR_CELSIUS + 50) + << TS_CAT_TRIP_CLEAR_THOLD_BP))), + + /* To enable the TS do the following: + * 1) Take the TS out of reset by setting itsrst to 0x0. + * 2) Enable the TS using RMU Thermal sensor mode register. + */ + REG_SOC_UNIT_AND(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, + ~B_TSCGF3_CONFIG_ITSRST), + REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_TS_MODE, TS_ENABLE), + + /* Lock all RMU Thermal sensor control & trip point registers. */ + REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_CONFIG, TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE), + REG_SCRIPT_END +}; static void chip_init(void *chip_info) { + /* Validate the temperature settings */ + ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); + ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS + > PLATFORM_CATASTROPHIC_CLEAR_CELSIUS); + + /* Set the temperature settings */ + reg_script_run(thermal_init_script); + + /* Verify that the thermal configuration is locked */ + ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) + & (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) + == (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); + /* Perform silicon specific init. */ if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) intel_silicon_init(); diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 934c75d..ddca668 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -18,10 +18,13 @@ #include <fsp/util.h> #include <reg_script.h> +#include <soc/IntelQNCConfig.h> #include <soc/QuarkNcSocId.h> enum { USB_PHY_REGS = 1, + SOC_UNIT_REGS, + RMU_TEMP_REGS, }; enum { @@ -32,6 +35,50 @@ enum { #define SOC_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_) \ _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ size_, reg_, mask_, value_, timeout_, reg_set_) + +/* RMU temperature register access macros */ +#define REG_RMU_TEMP_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + RMU_TEMP_REGS) +#define REG_RMU_TEMP_READ(reg_) \ + REG_RMU_TEMP_ACCESS(READ, reg_, 0, 0, 0) +#define REG_RMU_TEMP_WRITE(reg_, value_) \ + REG_RMU_TEMP_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_RMU_TEMP_AND(reg_, value_) \ + REG_RMU_TEMP_RMW(reg_, value_, 0) +#define REG_RMU_TEMP_RMW(reg_, mask_, value_) \ + REG_RMU_TEMP_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_RMU_TEMP_RXW(reg_, mask_, value_) \ + REG_RMU_TEMP_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_RMU_TEMP_OR(reg_, value_) \ + REG_RMU_TEMP_RMW(reg_, 0xffffffff, value_) +#define REG_RMU_TEMP_POLL(reg_, mask_, value_, timeout_) \ + REG_RMU_TEMP_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_RMU_TEMP_XOR(reg_, value_) \ + REG_RMU_TEMP_RXW(reg_, 0xffffffff, value_) + +/* Temperature sensor access macros */ +#define REG_SOC_UNIT_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + SOC_UNIT_REGS) +#define REG_SOC_UNIT_READ(reg_) \ + REG_SOC_UNIT_ACCESS(READ, reg_, 0, 0, 0) +#define REG_SOC_UNIT_WRITE(reg_, value_) \ + REG_SOC_UNIT_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_SOC_UNIT_AND(reg_, value_) \ + REG_SOC_UNIT_RMW(reg_, value_, 0) +#define REG_SOC_UNIT_RMW(reg_, mask_, value_) \ + REG_SOC_UNIT_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_SOC_UNIT_RXW(reg_, mask_, value_) \ + REG_SOC_UNIT_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_SOC_UNIT_OR(reg_, value_) \ + REG_SOC_UNIT_RMW(reg_, 0xffffffff, value_) +#define REG_SOC_UNIT_POLL(reg_, mask_, value_, timeout_) \ + REG_SOC_UNIT_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_SOC_UNIT_XOR(reg_, value_) \ + REG_SOC_UNIT_RXW(reg_, 0xffffffff, value_) + +/* USB register access macros */ #define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ USB_PHY_REGS) @@ -56,5 +103,6 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); void mdr_write(uint32_t value); void mea_write(uint32_t reg_address); +uint32_t reg_rmu_temp_read(uint32_t reg_address); #endif /* _QUARK_REG_ACCESS_H_ */ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 278fc7e..fb80f3d 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -45,6 +45,40 @@ void mea_write(uint32_t reg_address) & QNC_MEA_MASK); } +uint32_t reg_rmu_temp_read(uint32_t reg_address) +{ + /* Read the RMU temperature register */ + mea_write(reg_address); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_RMU_SB_PORT_ID, reg_address); + return mdr_read(); +} + +static void reg_rmu_temp_write(uint32_t reg_address, uint32_t value) +{ + /* Write the RMU temperature register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_RMU_SB_PORT_ID, reg_address); +} + +static uint32_t reg_soc_unit_read(uint32_t reg_address) +{ + /* Read the temperature sensor register */ + mea_write(reg_address); + mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + reg_address); + return mdr_read(); +} + +static void reg_soc_unit_write(uint32_t reg_address, uint32_t value) +{ + /* Write the temperature sensor register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_ALT_OPCODE_WRITE, QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + reg_address); +} + static uint32_t reg_usb_read(uint32_t reg_address) { /* Read the USB register */ @@ -76,6 +110,16 @@ static uint64_t reg_read(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return 0; + case RMU_TEMP_REGS: + ctx->display_prefix = "RMU TEMP"; + value = reg_rmu_temp_read(step->reg); + break; + + case SOC_UNIT_REGS: + ctx->display_prefix = "SOC Unit"; + value = reg_soc_unit_read(step->reg); + break; + case USB_PHY_REGS: ctx->display_prefix = "USB PHY"; value = reg_usb_read(step->reg); @@ -96,6 +140,16 @@ static void reg_write(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return; + case RMU_TEMP_REGS: + ctx->display_prefix = "RMU TEMP"; + reg_rmu_temp_write(step->reg, (uint32_t)step->value); + break; + + case SOC_UNIT_REGS: + ctx->display_prefix = "SOC Unit"; + reg_soc_unit_write(step->reg, (uint32_t)step->value); + break; + case USB_PHY_REGS: ctx->display_prefix = "USB PHY"; reg_usb_write(step->reg, (uint32_t)step->value);

1 0

Patch set updated for coreboot: soc/intel/quark: Add script time delay support
by Leroy P Leahy 05 May '16

05 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14555 -gerrit commit 752dc5e87823e433889e328763da0327dad8672f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 16:36:02 2016 -0700 soc/intel/quark: Add script time delay support Add time delay support to the scripts. TEST=Build and run on Galileo Gen2 Change-Id: I2c87977e2a2547e00769e59e1ee81fbbb5dff33f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/reg_access.h | 6 ++++++ src/soc/intel/quark/reg_access.c | 10 ++++++++++ 2 files changed, 16 insertions(+) diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index ddca668..c6b786a 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -16,6 +16,7 @@ #ifndef _QUARK_REG_ACCESS_H_ #define _QUARK_REG_ACCESS_H_ +#include <delay.h> #include <fsp/util.h> #include <reg_script.h> #include <soc/IntelQNCConfig.h> @@ -25,6 +26,7 @@ enum { USB_PHY_REGS = 1, SOC_UNIT_REGS, RMU_TEMP_REGS, + MICROSECOND_DELAY, }; enum { @@ -78,6 +80,10 @@ enum { #define REG_SOC_UNIT_XOR(reg_, value_) \ REG_SOC_UNIT_RXW(reg_, 0xffffffff, value_) +/* Time delays */ +#define TIME_DELAY_USEC(value_) \ + SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 0, value_, 0, MICROSECOND_DELAY) + /* USB register access macros */ #define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index fb80f3d..be02340 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -150,6 +150,16 @@ static void reg_write(struct reg_script_context *ctx) reg_soc_unit_write(step->reg, (uint32_t)step->value); break; + case MICROSECOND_DELAY: + /* The actual delay is >= the requested delay */ + if (ctx->display_features) { + /* Higher baud-rates will reduce the impact of displaying this message */ + printk(BIOS_INFO, "Delay %lld uSec\n", step->value); + ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; + } + udelay(step->value); + break; + case USB_PHY_REGS: ctx->display_prefix = "USB PHY"; reg_usb_write(step->reg, (uint32_t)step->value);

1 0

New patch to review for coreboot: util/cbfstool: fix x86 execute-in-place semantics for all fmd regions
by Aaron Durbin 05 May '16

05 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14608 -gerrit commit 135c70c0b358f48de044f49fee13655f251fbcd4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 4 16:07:15 2016 -0500 util/cbfstool: fix x86 execute-in-place semantics for all fmd regions A previous patch [1] to make top-aligned addresses work within per fmap regions caused a significant regression in the semantics of adding programs that need to be execute-in-place (XIP) on x86 systems. Correct the regression by providing new function, convert_to_from_absolute_top_aligned(), which top aligns against the entire boot media. [1] 9731119b cbfstool: make top-aligned address work per-region Change-Id: I3b685abadcfc76dab8846eec21e9114a23577578 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbfstool/cbfstool.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 1d1577f..b1b410f 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -106,6 +106,21 @@ static bool region_is_modern_cbfs(const char *region) /* * Converts between offsets from the start of the specified image region and + * "top-aligned" offsets from the top of the entire boot media. See comment + * below for convert_to_from_top_aligned() about forming addresses. + */ +static unsigned convert_to_from_absolute_top_aligned( + const struct buffer *region, unsigned offset) +{ + assert(region); + + size_t image_size = partitioned_file_total_size(param.image_file); + + return image_size - region->offset - offset; +} + +/* + * Converts between offsets from the start of the specified image region and * "top-aligned" offsets from the top of the image region. Works in either * direction: pass in one type of offset and receive the other type. * N.B. A top-aligned offset is always a positive number, and should not be @@ -123,8 +138,7 @@ static unsigned convert_to_from_top_aligned(const struct buffer *region, return region->size - offset; } - size_t image_size = partitioned_file_total_size(param.image_file); - return image_size - region->offset - offset; + return convert_to_from_absolute_top_aligned(region, offset); } static int do_cbfs_locate(int32_t *cbfs_addr, size_t metadata_size) @@ -462,8 +476,8 @@ static int cbfstool_convert_fsp(struct buffer *buffer, /* Ensure the address is a memory mapped one. */ if (!IS_TOP_ALIGNED_ADDRESS(address)) - address = -convert_to_from_top_aligned(param.image_region, - address); + address = -convert_to_from_absolute_top_aligned( + param.image_region, address); /* Create a copy of the buffer to attempt relocation. */ if (buffer_create(&fsp, buffer_size(buffer), "fsp")) @@ -498,9 +512,13 @@ static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset, return 1; } - /* Pass in a top aligned address. */ - address = -convert_to_from_top_aligned(param.image_region, - address); + /* + * Ensure the address is a memory mapped one. This assumes + * x86 semantics about th boot media being directly mapped + * below 4GiB in the CPU address space. + **/ + address = -convert_to_from_absolute_top_aligned( + param.image_region, address); *offset = address; ret = parse_elf_to_xip_stage(buffer, &output, offset,

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Patch set updated for coreboot: ec/google/chromeec/ec_lpc: Declare used IO ports as a resource
by Alexandru Gagniuc 05 May '16

05 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14585 -gerrit commit 1a234fbf0eee0b3e3cb8f32f0a515a07852c40fe Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Mar 30 14:38:44 2016 -0700 ec/google/chromeec/ec_lpc: Declare used IO ports as a resource Chrome EC uses IO ports 0x800 -> 0x9ff to communicate over LPC; however, those ports were not declared as a resource. This had two major downsides: * It allowed the allocator to assign said ports to other devices * It required manually open up an IO window in the LPC bridge. The LPC bridge on many chromeec boards had to be painstakingly adjusted to meet these constraints. The advantage of declaring the resources upfront is that the lpc bridge can now scan its child resources and automatically open up IO windows, as requested by its LPC children devices. Change-Id: I35c4e48dddb7300674d7a9858b590c1f20e3b0e3 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/ec/google/chromeec/ec.h | 4 ++++ src/ec/google/chromeec/ec_lpc.c | 29 ++++++++++++++++++++++++++++- src/ec/google/chromeec/ec_mec.c | 1 - 3 files changed, 32 insertions(+), 2 deletions(-) diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 7f52362..85f41ad 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -59,6 +59,10 @@ int google_chromeec_vstore_info(uint32_t *locked); int google_chromeec_vstore_read(int slot, uint8_t *data); int google_chromeec_vstore_write(int slot, uint8_t *data, size_t size); +/* MEC uses 0x800/0x804 as register/index pair, thus an 8-byte resource. */ +#define MEC_EMI_BASE 0x800 +#define MEC_EMI_SIZE 8 + /* For MEC, access ranges 0x800 thru 0x9ff using EMI interface instead of LPC */ #define MEC_EMI_RANGE_START EC_HOST_CMD_REGION0 #define MEC_EMI_RANGE_END (EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE) diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 021735e..f9d0f8b 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include <assert.h> #include <console/console.h> #include <delay.h> #include <device/pnp.h> @@ -407,9 +408,35 @@ static void lpc_ec_init(struct device *dev) google_chromeec_init(); } +/* + * Declare the IO ports that we are using: + * + * All ECs (not explicitly declared): + * 0x60/0x64, 0x62/0x66, 0x80, 0x200->0x207 + * + * mec1322: 0x800->0x807 + * All others: 0x800->0x9ff + * + * EC_GOOGLE_CHROMEEC_ACPI_MEMMAP is only used for MEC ECs. + */ static void lpc_ec_read_resources(struct device *dev) { - /* Nothing, but this function avoids an error on serial console. */ + unsigned int idx = 0; + struct resource * res; + + + res = new_resource(dev, idx++); + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) { + res->base = MEC_EMI_BASE; + res->size = MEC_EMI_SIZE; + } else { + res->base = EC_HOST_CMD_REGION0; + res->size = 2 * EC_HOST_CMD_REGION_SIZE; + /* Make sure MEMMAP region follows host cmd region. */ + assert(res->base + res->size == EC_LPC_ADDR_MEMMAP); + res->size += EC_MEMMAP_SIZE; + } + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void lpc_ec_enable_resources(struct device *dev) diff --git a/src/ec/google/chromeec/ec_mec.c b/src/ec/google/chromeec/ec_mec.c index a9bc282..4cd0823 100644 --- a/src/ec/google/chromeec/ec_mec.c +++ b/src/ec/google/chromeec/ec_mec.c @@ -32,7 +32,6 @@ enum { }; /* EMI registers are relative to base */ -#define MEC_EMI_BASE 0x800 #define MEC_EMI_HOST_TO_EC (MEC_EMI_BASE + 0) #define MEC_EMI_EC_TO_HOST (MEC_EMI_BASE + 1) #define MEC_EMI_EC_ADDRESS_B0 (MEC_EMI_BASE + 2)

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coreboot-gerrit May 2016