coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: util/cbfstool: fix x86 execute-in-place semantics for all fmd regions
by Aaron Durbin 05 May '16

05 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14608 -gerrit commit 6fd05f3130a3c699d0f279e9b3fc9f2faa0246b9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 4 16:07:15 2016 -0500 util/cbfstool: fix x86 execute-in-place semantics for all fmd regions A previous patch [1] to make top-aligned addresses work within per fmap regions caused a significant regression in the semantics of adding programs that need to be execute-in-place (XIP) on x86 systems. Correct the regression by providing new function, convert_to_from_absolute_top_aligned(), which top aligns against the entire boot media. [1] 9731119b cbfstool: make top-aligned address work per-region Change-Id: I3b685abadcfc76dab8846eec21e9114a23577578 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbfstool/cbfstool.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 1d1577f..b1b410f 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -106,6 +106,21 @@ static bool region_is_modern_cbfs(const char *region) /* * Converts between offsets from the start of the specified image region and + * "top-aligned" offsets from the top of the entire boot media. See comment + * below for convert_to_from_top_aligned() about forming addresses. + */ +static unsigned convert_to_from_absolute_top_aligned( + const struct buffer *region, unsigned offset) +{ + assert(region); + + size_t image_size = partitioned_file_total_size(param.image_file); + + return image_size - region->offset - offset; +} + +/* + * Converts between offsets from the start of the specified image region and * "top-aligned" offsets from the top of the image region. Works in either * direction: pass in one type of offset and receive the other type. * N.B. A top-aligned offset is always a positive number, and should not be @@ -123,8 +138,7 @@ static unsigned convert_to_from_top_aligned(const struct buffer *region, return region->size - offset; } - size_t image_size = partitioned_file_total_size(param.image_file); - return image_size - region->offset - offset; + return convert_to_from_absolute_top_aligned(region, offset); } static int do_cbfs_locate(int32_t *cbfs_addr, size_t metadata_size) @@ -462,8 +476,8 @@ static int cbfstool_convert_fsp(struct buffer *buffer, /* Ensure the address is a memory mapped one. */ if (!IS_TOP_ALIGNED_ADDRESS(address)) - address = -convert_to_from_top_aligned(param.image_region, - address); + address = -convert_to_from_absolute_top_aligned( + param.image_region, address); /* Create a copy of the buffer to attempt relocation. */ if (buffer_create(&fsp, buffer_size(buffer), "fsp")) @@ -498,9 +512,13 @@ static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset, return 1; } - /* Pass in a top aligned address. */ - address = -convert_to_from_top_aligned(param.image_region, - address); + /* + * Ensure the address is a memory mapped one. This assumes + * x86 semantics about th boot media being directly mapped + * below 4GiB in the CPU address space. + **/ + address = -convert_to_from_absolute_top_aligned( + param.image_region, address); *offset = address; ret = parse_elf_to_xip_stage(buffer, &output, offset,

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Patch set updated for coreboot: inteltool: handle unsafe dumping of graphics registers
by Stefan Tauner 05 May '16

05 May '16

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14627 -gerrit commit 59fe6988eaf24b2d2e06a872c4068065407b0967 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Thu May 5 17:54:10 2016 +0200 inteltool: handle unsafe dumping of graphics registers The current implementation from Vladimir simply dumps 1 MB of memory contents starting at the base address of the second PCI device (which most likely is the VGA controller on Intel systems). This locks up a number of different systems, e.g. my Ibex Peak-based T410s. This patch documents the issue and stops dumping the graphics registers for the -a/--all parameter. Change-Id: I581bdc63db60afaf4792bc11fbeed73aab57f63a Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/inteltool.8 | 3 ++- util/inteltool/inteltool.c | 5 ++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8 index f496475..49aafc3 100644 --- a/util/inteltool/inteltool.8 +++ b/util/inteltool/inteltool.8 @@ -35,7 +35,8 @@ Dump I/O Controller Hub (ICH) southbridge RCBA registers. Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control. .TP .B "\-f, \-\-gfx" -Dump graphics registers. +.RB "Dump graphics registers. " \ +"Due to unknown reasons this might lock up some systems after a few seconds." .TP .B "\-p, \-\-pmbase" Dump I/O Controller Hub (ICH) southbridge PMBASE registers. diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index f71fabd..f471efd 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -220,7 +220,7 @@ void print_usage(const char *name) " -v | --version: print the version\n" " -h | --help: print this help\n\n" " -s | --spi: dump southbridge spi and bios_cntrl registers\n" - " -f | --gfx: dump graphics registers\n" + " -f | --gfx: dump graphics registers (may lock up machine!)\n" " -g | --gpio: dump southbridge GPIO registers\n" " -G | --gpio-diffs: show GPIO differences from defaults\n" " -r | --rcba: dump southbridge RCBA registers\n" @@ -232,7 +232,7 @@ void print_usage(const char *name) " -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n" " -M | --msrs: dump CPU MSRs\n" " -A | --ambs: dump AMB registers\n" - " -a | --all: dump all known registers\n" + " -a | --all: dump all known (safe) registers\n" "\n"); exit(1); } @@ -326,7 +326,6 @@ int main(int argc, char *argv[]) dump_coremsrs = 1; dump_ambs = 1; dump_spi = 1; - dump_gfx = 1; break; case 'A': dump_ambs = 1;

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Patch merged into coreboot/master: soc/intel/quark: Add script time delay support
by gerrit＠coreboot.org 05 May '16

05 May '16

the following patch was just integrated into master: commit 4c3f5dc03ce5fa19cd087a62430239df6d86e54d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 16:36:02 2016 -0700 soc/intel/quark: Add script time delay support Add time delay support to the scripts. TEST=Build and run on Galileo Gen2 Change-Id: I2c87977e2a2547e00769e59e1ee81fbbb5dff33f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14555 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14555 for details. -gerrit

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Patch set updated for coreboot: soc/intel/quark: Add script time delay support
by Leroy P Leahy 05 May '16

05 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14555 -gerrit commit c87989cb3443867c4e38d45146edfaa4a7f305cb Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 16:36:02 2016 -0700 soc/intel/quark: Add script time delay support Add time delay support to the scripts. TEST=Build and run on Galileo Gen2 Change-Id: I2c87977e2a2547e00769e59e1ee81fbbb5dff33f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/reg_access.h | 6 ++++++ src/soc/intel/quark/reg_access.c | 10 ++++++++++ 2 files changed, 16 insertions(+) diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index ddca668..c6b786a 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -16,6 +16,7 @@ #ifndef _QUARK_REG_ACCESS_H_ #define _QUARK_REG_ACCESS_H_ +#include <delay.h> #include <fsp/util.h> #include <reg_script.h> #include <soc/IntelQNCConfig.h> @@ -25,6 +26,7 @@ enum { USB_PHY_REGS = 1, SOC_UNIT_REGS, RMU_TEMP_REGS, + MICROSECOND_DELAY, }; enum { @@ -78,6 +80,10 @@ enum { #define REG_SOC_UNIT_XOR(reg_, value_) \ REG_SOC_UNIT_RXW(reg_, 0xffffffff, value_) +/* Time delays */ +#define TIME_DELAY_USEC(value_) \ + SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 0, value_, 0, MICROSECOND_DELAY) + /* USB register access macros */ #define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index fb80f3d..be02340 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -150,6 +150,16 @@ static void reg_write(struct reg_script_context *ctx) reg_soc_unit_write(step->reg, (uint32_t)step->value); break; + case MICROSECOND_DELAY: + /* The actual delay is >= the requested delay */ + if (ctx->display_features) { + /* Higher baud-rates will reduce the impact of displaying this message */ + printk(BIOS_INFO, "Delay %lld uSec\n", step->value); + ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; + } + udelay(step->value); + break; + case USB_PHY_REGS: ctx->display_prefix = "USB PHY"; reg_usb_write(step->reg, (uint32_t)step->value);

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New patch to review for coreboot: inteltool: handle unsafe dumping of graphics registers
by Stefan Tauner 05 May '16

05 May '16

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14627 -gerrit commit e27aa597ebe4ff6002b162e5f2583b278a81a8c6 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Thu May 5 17:54:10 2016 +0200 inteltool: handle unsafe dumping of graphics registers The current implementation from Vladimir simply dumps 1 MB of memory contents starting at the base address of the second PCI device (which most likely is the VGA controller on Intel systems). This locks up a number of different systems, e.g. my Ibex Peak-based T410s. This patch documents the issue and stops dumping the graphics registers for the -a/--all parameter. Change-Id: I581bdc63db60afaf4792bc11fbeed73aab57f63a Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/inteltool.8 | 3 ++- util/inteltool/inteltool.c | 5 ++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8 index f496475..49aafc3 100644 --- a/util/inteltool/inteltool.8 +++ b/util/inteltool/inteltool.8 @@ -35,7 +35,8 @@ Dump I/O Controller Hub (ICH) southbridge RCBA registers. Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control. .TP .B "\-f, \-\-gfx" -Dump graphics registers. +.RB "Dump graphics registers. " \ +"Due to unknown reasons this might lock up some systems after a few seconds." .TP .B "\-p, \-\-pmbase" Dump I/O Controller Hub (ICH) southbridge PMBASE registers. diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index f71fabd..f471efd 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -220,7 +220,7 @@ void print_usage(const char *name) " -v | --version: print the version\n" " -h | --help: print this help\n\n" " -s | --spi: dump southbridge spi and bios_cntrl registers\n" - " -f | --gfx: dump graphics registers\n" + " -f | --gfx: dump graphics registers (may lock up machine!)\n" " -g | --gpio: dump southbridge GPIO registers\n" " -G | --gpio-diffs: show GPIO differences from defaults\n" " -r | --rcba: dump southbridge RCBA registers\n" @@ -232,7 +232,7 @@ void print_usage(const char *name) " -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n" " -M | --msrs: dump CPU MSRs\n" " -A | --ambs: dump AMB registers\n" - " -a | --all: dump all known registers\n" + " -a | --all: dump all known (safe) registers\n" "\n"); exit(1); } @@ -326,7 +326,6 @@ int main(int argc, char *argv[]) dump_coremsrs = 1; dump_ambs = 1; dump_spi = 1; - dump_gfx = 1; break; case 'A': dump_ambs = 1;

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Patch merged into coreboot/master: soc/intel/quark: Add temperature sensor support
by gerrit＠coreboot.org 05 May '16

05 May '16

the following patch was just integrated into master: commit 63e3dff02f5b66b32b32fd1497f820532af25a07 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 30 08:48:52 2016 -0700 soc/intel/quark: Add temperature sensor support Migrate the temperature sensor support from QuarkFspPkg into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: I6dc68c735375c9d1777693264674521f67397556 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14565 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14565 for details. -gerrit

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New patch to review for coreboot: soc/intel: indicate to build system that XIP_ROM_SIZE isn't used
by Aaron Durbin 05 May '16

05 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14626 -gerrit commit 83d6a6e885c924601c215a03bc759793be24a887 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 5 10:38:03 2016 -0500 soc/intel: indicate to build system that XIP_ROM_SIZE isn't used The XIP_ROM_SIZE Kconfig variable isn't used for these chipsets. Therefore, indicate as such so that romstage can be placed in cbfs less rigidly. Change-Id: If5cae10b90e05029df56c282e8adf37fa0102955 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/braswell/Kconfig | 1 + src/soc/intel/skylake/Kconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bdb8eeb..d52d592 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -23,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index fcf382e..df8765d 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NO_FIXED_XIP_ROM_SIZE select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select PARALLEL_MP diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 3c6f788..3466aad 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NO_FIXED_XIP_ROM_SIZE select RELOCATABLE_MODULES select PARALLEL_MP select PCIEXP_ASPM diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 0b7dc8c..1ac0647 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS select IOAPIC select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK

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New patch to review for coreboot: cpu/x86: don't treat all chipsets the same regarding XIP_ROM_SIZE
by Aaron Durbin 05 May '16

05 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14625 -gerrit commit 14c092b4fec1d7a33bdbb9c527fa2eb3b3ee8e70 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 5 10:34:22 2016 -0500 cpu/x86: don't treat all chipsets the same regarding XIP_ROM_SIZE Previously, the XIP_ROM_SIZE Kconfig variable is used globally on x86 platforms with the assumption that all chipsets utilize this value. For the chipsets which do not use the variable it can lead to unnecessary alignment constraints in cbfs for romstage. Therefore, allow those chipsets a path to not be burdened by not passing '-P $(XIP_ROM_SIZE)' to cbfstool when adding romstage. Change-Id: Id8692df5ecec116a72b8e5886d86648ca959c78b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- Makefile.inc | 7 ++++++- src/cpu/x86/Kconfig | 11 +++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 94273df..9890e14 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -798,7 +798,12 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) # # Make sure that segment for .car.data is ignored while adding romstage. $(CONFIG_CBFS_PREFIX)/romstage-align := 64 -$(CONFIG_CBFS_PREFIX)/romstage-options := --xip -S .car.data -P $(CONFIG_XIP_ROM_SIZE) +$(CONFIG_CBFS_PREFIX)/romstage-options := --xip -S .car.data +# If XIP_ROM_SIZE isn't being used don't overly constrain romstage by passing +# -P with a default value. +ifneq ($(CONFIG_NO_FIXED_XIP_ROM_SIZE),y) +$(CONFIG_CBFS_PREFIX)/romstage-options += -P $(CONFIG_XIP_ROM_SIZE) +endif endif cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index e80f02b..74d87e2 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -69,8 +69,19 @@ config TSC_SYNC_MFENCE to execute an mfence instruction in order to synchronize rdtsc. This is true for all modern Intel CPUs. +config NO_FIXED_XIP_ROM_SIZE + bool + default n + help + The XIP_ROM_SIZE Kconfig variable is used globally on x86 + with the assumption that all chipsets utilize this value. + For the chipsets which do not use the variable it can lead + to unnecessary alignment constraints in cbfs for romstage. + Therefore, allow those chipsets a path to not be burdened. + config XIP_ROM_SIZE hex + depends on !NO_FIXED_XIP_ROM_SIZE default ROM_SIZE if ROMCC default 0x10000

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New patch to review for coreboot: inteltool: update documentation
by Stefan Tauner 05 May '16

05 May '16

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14624 -gerrit commit a1825eb28504fdb27dcfe1f305cbb2d6d018cb69 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Thu May 5 17:29:39 2016 +0200 inteltool: update documentation - manpage - usage message - new warning message if -S is used on an unsupported chipset Change-Id: I1acaa5f4232b65244ec00fd22ec7460d9cc387f1 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/inteltool.8 | 20 ++++++++++++++++---- util/inteltool/inteltool.c | 6 +++--- util/inteltool/ivy_memory.c | 2 +- util/inteltool/memory.c | 5 +++++ 4 files changed, 25 insertions(+), 8 deletions(-) diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8 index 5956bcd..f496475 100644 --- a/util/inteltool/inteltool.8 +++ b/util/inteltool/inteltool.8 @@ -1,8 +1,8 @@ -.TH INTELTOOL 8 "May 14, 2008" +.TH INTELTOOL 8 .SH NAME inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters .SH SYNOPSIS -.B inteltool \fR[\fB\-vh?grpmedPMa\fR] +.B inteltool \fR[\fB\-vh?gGrpmedPMaAsfS\fR] .SH DESCRIPTION .B inteltool is a handy little tool for dumping the configuration space of Intel(R) @@ -20,24 +20,33 @@ Show a help text and exit. Show version information and exit. .TP .B "\-a, \-\-all" -Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge -and Intel(R) Core CPU MSRs. +Dump all known information listed below. .TP .B "\-g, \-\-gpio" Dump I/O Controller Hub (ICH) southbridge GPIO registers. .TP +.B "\-G, \-\-gpio-diffs" +Show only GPIO register differences from hardware defaults. +.TP .B "\-r, \-\-rcba" Dump I/O Controller Hub (ICH) southbridge RCBA registers. .TP .B "\-s, \-\-spi" Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control. .TP +.B "\-f, \-\-gfx" +Dump graphics registers. +.TP .B "\-p, \-\-pmbase" Dump I/O Controller Hub (ICH) southbridge PMBASE registers. .TP .B "\-m, \-\-mchbar" Dump Intel(R) northbridge MCHBAR registers. .TP +.BR "\-S" " \fIfile\fR, " "\-\-spd=" "\fIfile\fR" +Dump the memory registers as above and store the current timing settings +into \fIfile\fR. +.TP .B "\-e, \-\-epbar" Dump Intel(R) northbridge EPBAR registers. .TP @@ -49,6 +58,9 @@ Dump Intel(R) northbridge PCIEXBAR registers. .TP .B "\-M, \-\-msrs" Dump Intel(R) CPU MSRs. +.TP +.B "\-A, \-\-ambs" +Dump Advanced Memory Buffer (AMB) registers. .SH BUGS Please report any bugs on the coreboot mailing list .RB "(" http://coreboot.org/Mailinglist ")." diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 113eb4d..f71fabd 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -215,7 +215,7 @@ void print_version(void) void print_usage(const char *name) { - printf("usage: %s [-vh?gGrpmedPMas]\n", name); + printf("usage: %s [-vh?gGrpmedPMaAsfS]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" @@ -226,7 +226,7 @@ void print_usage(const char *name) " -r | --rcba: dump southbridge RCBA registers\n" " -p | --pmbase: dump southbridge Power Management registers\n\n" " -m | --mchbar: dump northbridge Memory Controller registers\n" - " -S FILE | --spd=FILE: generate spd.bin equivalent to current timings\n" + " -S FILE | --spd=FILE: as above and create a file storing current timings\n" " -e | --epbar: dump northbridge EPBAR registers\n" " -d | --dmibar: dump northbridge DMIBAR registers\n" " -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n" @@ -241,7 +241,7 @@ int main(int argc, char *argv[]) { struct pci_access *pacc; struct pci_dev *sb = NULL, *nb, *gfx = NULL, *dev; - const char *dump_spd_file = 0; + const char *dump_spd_file = NULL; int i, opt, option_index = 0; unsigned int id; diff --git a/util/inteltool/ivy_memory.c b/util/inteltool/ivy_memory.c index 0dfa799..92e61ac 100644 --- a/util/inteltool/ivy_memory.c +++ b/util/inteltool/ivy_memory.c @@ -359,7 +359,7 @@ void ivybridge_dump_timings(const char *dump_spd_file) printf("/* SPD matching current mode: */\n"); - FILE *dump_spd = 0; + FILE *dump_spd = NULL; if (dump_spd_file) { dump_spd = fopen (dump_spd_file, "wb"); diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 5f04729..686c1e7 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -253,6 +253,8 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1); dump_timings (); + if (dump_spd_file != NULL) + printf("\nCreating a memory timings file is not supported on this chipset.\n"); break; case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: @@ -263,6 +265,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: ivybridge_dump_timings(dump_spd_file); break; + default: + if (dump_spd_file != NULL) + printf("\nCreating a memory timings file is not supported on this chipset.\n"); } unmap_physical((void *)mchbar, size); return 0;

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New patch to review for coreboot: xip: Do not pass --xip for romstage and verstage if CAR supports code execution
by Furquan Shaikh 05 May '16

05 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14623 -gerrit commit e6ba54cccd1bea9851c2d29cf01782e1ae9d0478 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 4 23:25:16 2016 -0700 xip: Do not pass --xip for romstage and verstage if CAR supports code execution On modern x86 platform like apollolake, pre-RAM stages verstage and romstage run within the cache-as-ram region. Thus, we do not need to pass in the --xip parameter to cbfstool while adding these stages. Introduce a new Kconfig variable XIP_STAGES which is default true for only those X86 platforms that do not support C_ENVIRONMENT_BOOTBLOCK. Change-Id: I2848046472f40f09ce7fc230c258b0389851b2ea Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- Makefile.inc | 9 ++++++++- src/Kconfig | 8 ++++++++ src/vendorcode/google/chromeos/vboot2/Makefile.inc | 10 ++++++++-- 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 94273df..ba5a63e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -798,7 +798,14 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) # # Make sure that segment for .car.data is ignored while adding romstage. $(CONFIG_CBFS_PREFIX)/romstage-align := 64 -$(CONFIG_CBFS_PREFIX)/romstage-options := --xip -S .car.data -P $(CONFIG_XIP_ROM_SIZE) +$(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data" + +# If CAR does not support execution of code, romstage on x86 is expected to be +# xip. +ifeq ($(CONFIG_XIP_STAGES),y) +$(CONFIG_CBFS_PREFIX)/romstage-options += --xip -P $(CONFIG_XIP_ROM_SIZE) +endif + endif cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage diff --git a/src/Kconfig b/src/Kconfig index f9bd661..965fa98 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -199,6 +199,14 @@ config INCLUDE_CONFIG_FILE config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440 +config XIP_STAGES + bool "Identifies if a platform uses xip stages." + default y if (ARCH_X86 && !C_ENVIRONMENT_BOOTBLOCK) + default n + help + Pass in --xip parameter to cbfstool while adding stages that need to + execute in place. + config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index f934884..3d7dc79 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -76,9 +76,15 @@ cbfs-files-$(CONFIG_SEPARATE_VERSTAGE) += $(CONFIG_CBFS_PREFIX)/verstage $(CONFIG_CBFS_PREFIX)/verstage-file := $(objcbfs)/verstage.elf $(CONFIG_CBFS_PREFIX)/verstage-type := stage $(CONFIG_CBFS_PREFIX)/verstage-compression := $(CBFS_PRERAM_COMPRESS_FLAG) -# Verstage on x86 expected to be xip. + ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) -$(CONFIG_CBFS_PREFIX)/verstage-options := -a 64 --xip -S ".car.data" +$(CONFIG_CBFS_PREFIX)/verstage-options := -a 64 -S ".car.data" + +# If CAR does not support execution of code, verstage on x86 is expected to be +# xip. +ifeq ($(CONFIG_XIP_STAGES),y) +$(CONFIG_CBFS_PREFIX)/verstage-options += --xip +endif endif

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coreboot-gerrit May 2016