coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: lib/reg_script: Fix braces
by gerrit＠coreboot.org 05 May '16

05 May '16

the following patch was just integrated into master: commit f7dd6d5da13131d5161185c60e757ae4c4406f46 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed May 4 17:52:56 2016 -0700 lib/reg_script: Fix braces In If0d4d61ed8ef48ec20082b327f358fd1987e3fb9 the code was changed from one to two lines in the body of an if() statement, without adding braces. Change-Id: Ibbbdf240157adae95151fb2ce0135948caa60108 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14621 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> See https://review.coreboot.org/14621 for details. -gerrit

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Patch set updated for coreboot: xip: Do not pass --xip for romstage and verstage if CAR supports code execution
by Furquan Shaikh 05 May '16

05 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14623 -gerrit commit 5772b062164f2f086ccca1abf777a902ceb97644 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 4 23:25:16 2016 -0700 xip: Do not pass --xip for romstage and verstage if CAR supports code execution On modern x86 platform like apollolake, pre-RAM stages verstage and romstage run within the cache-as-ram region. Thus, we do not need to pass in the --xip parameter to cbfstool while adding these stages. Introduce a new Kconfig variable NO_XIP_EARLY_STAGES which is default false for all x86 platforms. Apollolake selects this option since it supports code execution with CAR. Change-Id: I2848046472f40f09ce7fc230c258b0389851b2ea Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- Makefile.inc | 9 ++++++++- src/Kconfig | 8 ++++++++ src/soc/intel/apollolake/Kconfig | 1 + src/vendorcode/google/chromeos/vboot2/Makefile.inc | 10 ++++++++-- 4 files changed, 25 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 94273df..b02b8c3 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -798,7 +798,14 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) # # Make sure that segment for .car.data is ignored while adding romstage. $(CONFIG_CBFS_PREFIX)/romstage-align := 64 -$(CONFIG_CBFS_PREFIX)/romstage-options := --xip -S .car.data -P $(CONFIG_XIP_ROM_SIZE) +$(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data" + +# If CAR does not support execution of code, romstage on x86 is expected to be +# xip. +ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y) +$(CONFIG_CBFS_PREFIX)/romstage-options += --xip -P $(CONFIG_XIP_ROM_SIZE) +endif + endif cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage diff --git a/src/Kconfig b/src/Kconfig index f9bd661..b56f0107 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -199,6 +199,14 @@ config INCLUDE_CONFIG_FILE config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440 +config NO_XIP_EARLY_STAGES + bool + default n if ARCH_X86 + default y + help + Identify if --xip parameter needs to be passed into cbfstool for early + stages. + config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bdb8eeb..b05c1da 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS # Misc options select C_ENVIRONMENT_BOOTBLOCK + select NO_XIP_EARLY_STAGES select COLLECT_TIMESTAMPS select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index f934884..b0a3c12 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -76,9 +76,15 @@ cbfs-files-$(CONFIG_SEPARATE_VERSTAGE) += $(CONFIG_CBFS_PREFIX)/verstage $(CONFIG_CBFS_PREFIX)/verstage-file := $(objcbfs)/verstage.elf $(CONFIG_CBFS_PREFIX)/verstage-type := stage $(CONFIG_CBFS_PREFIX)/verstage-compression := $(CBFS_PRERAM_COMPRESS_FLAG) -# Verstage on x86 expected to be xip. + ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) -$(CONFIG_CBFS_PREFIX)/verstage-options := -a 64 --xip -S ".car.data" +$(CONFIG_CBFS_PREFIX)/verstage-options := -a 64 -S ".car.data" + +# If CAR does not support execution of code, verstage on x86 is expected to be +# xip. +ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y) +$(CONFIG_CBFS_PREFIX)/verstage-options += --xip +endif endif

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Patch set updated for coreboot: xip: Do not pass --xip for romstage and verstage if CAR supports code execution
by Furquan Shaikh 05 May '16

05 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14623 -gerrit commit 7f13c55c39624ab79b0ac32781e7bf8b5df46cc7 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 4 23:25:16 2016 -0700 xip: Do not pass --xip for romstage and verstage if CAR supports code execution On modern x86 platform like apollolake, pre-RAM stages verstage and romstage run within the cache-as-ram region. Thus, we do not need to pass in the --xip parameter to cbfstool while adding these stages. Introduce a new Kconfig variable NO_XIP_EARLY_STAGES which is default false for all x86 platforms. Apollolake selects this option since it supports code execution with CAR. Change-Id: I2848046472f40f09ce7fc230c258b0389851b2ea Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- Makefile.inc | 9 ++++++++- src/Kconfig | 5 +++++ src/soc/intel/apollolake/Kconfig | 1 + src/vendorcode/google/chromeos/vboot2/Makefile.inc | 10 ++++++++-- 4 files changed, 22 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 94273df..b02b8c3 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -798,7 +798,14 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) # # Make sure that segment for .car.data is ignored while adding romstage. $(CONFIG_CBFS_PREFIX)/romstage-align := 64 -$(CONFIG_CBFS_PREFIX)/romstage-options := --xip -S .car.data -P $(CONFIG_XIP_ROM_SIZE) +$(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data" + +# If CAR does not support execution of code, romstage on x86 is expected to be +# xip. +ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y) +$(CONFIG_CBFS_PREFIX)/romstage-options += --xip -P $(CONFIG_XIP_ROM_SIZE) +endif + endif cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage diff --git a/src/Kconfig b/src/Kconfig index f9bd661..aa9fa36 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -199,6 +199,11 @@ config INCLUDE_CONFIG_FILE config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440 +config NO_XIP_EARLY_STAGES + bool + default n if ARCH_X86 + default y + config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bdb8eeb..b05c1da 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS # Misc options select C_ENVIRONMENT_BOOTBLOCK + select NO_XIP_EARLY_STAGES select COLLECT_TIMESTAMPS select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index f934884..b0a3c12 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -76,9 +76,15 @@ cbfs-files-$(CONFIG_SEPARATE_VERSTAGE) += $(CONFIG_CBFS_PREFIX)/verstage $(CONFIG_CBFS_PREFIX)/verstage-file := $(objcbfs)/verstage.elf $(CONFIG_CBFS_PREFIX)/verstage-type := stage $(CONFIG_CBFS_PREFIX)/verstage-compression := $(CBFS_PRERAM_COMPRESS_FLAG) -# Verstage on x86 expected to be xip. + ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) -$(CONFIG_CBFS_PREFIX)/verstage-options := -a 64 --xip -S ".car.data" +$(CONFIG_CBFS_PREFIX)/verstage-options := -a 64 -S ".car.data" + +# If CAR does not support execution of code, verstage on x86 is expected to be +# xip. +ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y) +$(CONFIG_CBFS_PREFIX)/verstage-options += --xip +endif endif

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Patch set updated for coreboot: xip: Do not pass --xip for romstage and verstage if CAR supports code execution
by Furquan Shaikh 05 May '16

05 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14623 -gerrit commit 0b7e2af1166d9c389a0bdc90690c702dfe62d017 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 4 23:25:16 2016 -0700 xip: Do not pass --xip for romstage and verstage if CAR supports code execution On modern x86 platform like apollolake, pre-RAM stages verstage and romstage run within the cache-as-ram region. Thus, we do not need to pass in the --xip parameter to cbfstool while adding these stages. Introduce a new Kconfig variable NO_XIP_EARLY_STAGES which is default false for all x86 platforms. Apollolake selects this option since it supports code execution with CAR. Change-Id: I2848046472f40f09ce7fc230c258b0389851b2ea Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- Makefile.inc | 9 ++++++++- src/Kconfig | 8 ++++++++ src/soc/intel/apollolake/Kconfig | 1 + src/vendorcode/google/chromeos/vboot2/Makefile.inc | 10 ++++++++-- 4 files changed, 25 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 94273df..b02b8c3 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -798,7 +798,14 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) # # Make sure that segment for .car.data is ignored while adding romstage. $(CONFIG_CBFS_PREFIX)/romstage-align := 64 -$(CONFIG_CBFS_PREFIX)/romstage-options := --xip -S .car.data -P $(CONFIG_XIP_ROM_SIZE) +$(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data" + +# If CAR does not support execution of code, romstage on x86 is expected to be +# xip. +ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y) +$(CONFIG_CBFS_PREFIX)/romstage-options += --xip -P $(CONFIG_XIP_ROM_SIZE) +endif + endif cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage diff --git a/src/Kconfig b/src/Kconfig index f9bd661..b56f0107 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -199,6 +199,14 @@ config INCLUDE_CONFIG_FILE config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440 +config NO_XIP_EARLY_STAGES + bool + default n if ARCH_X86 + default y + help + Identify if --xip parameter needs to be passed into cbfstool for early + stages. + config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bdb8eeb..b05c1da 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS # Misc options select C_ENVIRONMENT_BOOTBLOCK + select NO_XIP_EARLY_STAGES select COLLECT_TIMESTAMPS select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index f934884..b0a3c12 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -76,9 +76,15 @@ cbfs-files-$(CONFIG_SEPARATE_VERSTAGE) += $(CONFIG_CBFS_PREFIX)/verstage $(CONFIG_CBFS_PREFIX)/verstage-file := $(objcbfs)/verstage.elf $(CONFIG_CBFS_PREFIX)/verstage-type := stage $(CONFIG_CBFS_PREFIX)/verstage-compression := $(CBFS_PRERAM_COMPRESS_FLAG) -# Verstage on x86 expected to be xip. + ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) -$(CONFIG_CBFS_PREFIX)/verstage-options := -a 64 --xip -S ".car.data" +$(CONFIG_CBFS_PREFIX)/verstage-options := -a 64 -S ".car.data" + +# If CAR does not support execution of code, verstage on x86 is expected to be +# xip. +ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y) +$(CONFIG_CBFS_PREFIX)/verstage-options += --xip +endif endif

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Patch set updated for coreboot: xip: Do not pass --xip for romstage and verstage if CAR supports code execution
by Furquan Shaikh 05 May '16

05 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14623 -gerrit commit 48b8466407730bd98c8c927f4158f2198cba63d5 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 4 23:25:16 2016 -0700 xip: Do not pass --xip for romstage and verstage if CAR supports code execution On modern x86 platform like apollolake, pre-RAM stages verstage and romstage run within the cache-as-ram region. Thus, we do not need to pass in the --xip parameter to cbfstool while adding these stages. Introduce a new Kconfig variable NO_XIP_EARLY_STAGES which is default false for all x86 platforms. Apollolake selects this option since it supports code execution with CAR. Change-Id: I2848046472f40f09ce7fc230c258b0389851b2ea Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- Makefile.inc | 9 ++++++++- src/Kconfig | 8 ++++++++ src/soc/intel/apollolake/Kconfig | 1 + src/vendorcode/google/chromeos/vboot2/Makefile.inc | 10 ++++++++-- 4 files changed, 25 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 94273df..b02b8c3 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -798,7 +798,14 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) # # Make sure that segment for .car.data is ignored while adding romstage. $(CONFIG_CBFS_PREFIX)/romstage-align := 64 -$(CONFIG_CBFS_PREFIX)/romstage-options := --xip -S .car.data -P $(CONFIG_XIP_ROM_SIZE) +$(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data" + +# If CAR does not support execution of code, romstage on x86 is expected to be +# xip. +ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y) +$(CONFIG_CBFS_PREFIX)/romstage-options += --xip -P $(CONFIG_XIP_ROM_SIZE) +endif + endif cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage diff --git a/src/Kconfig b/src/Kconfig index f9bd661..0ec4852 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -199,6 +199,14 @@ config INCLUDE_CONFIG_FILE config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440 +config NO_XIP_EARLY_STAGES + bool "Identify if a platform uses xip early stages." + default n if ARCH_X86 + default y + help + Identify if --xip parameter needs to be passed into cbfstool for early + stages. + config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bdb8eeb..b05c1da 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS # Misc options select C_ENVIRONMENT_BOOTBLOCK + select NO_XIP_EARLY_STAGES select COLLECT_TIMESTAMPS select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index f934884..b0a3c12 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -76,9 +76,15 @@ cbfs-files-$(CONFIG_SEPARATE_VERSTAGE) += $(CONFIG_CBFS_PREFIX)/verstage $(CONFIG_CBFS_PREFIX)/verstage-file := $(objcbfs)/verstage.elf $(CONFIG_CBFS_PREFIX)/verstage-type := stage $(CONFIG_CBFS_PREFIX)/verstage-compression := $(CBFS_PRERAM_COMPRESS_FLAG) -# Verstage on x86 expected to be xip. + ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) -$(CONFIG_CBFS_PREFIX)/verstage-options := -a 64 --xip -S ".car.data" +$(CONFIG_CBFS_PREFIX)/verstage-options := -a 64 -S ".car.data" + +# If CAR does not support execution of code, verstage on x86 is expected to be +# xip. +ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y) +$(CONFIG_CBFS_PREFIX)/verstage-options += --xip +endif endif

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Patch set updated for coreboot: {cpu, soc}/intel: remove unused smm_init() function
by Aaron Durbin 05 May '16

05 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14605 -gerrit commit bff8ea8d3d32ddbe87431fb616012ab397e61004 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 4 09:00:13 2016 -0500 {cpu,soc}/intel: remove unused smm_init() function There used to be a need for an empty smm_init() function because initialize_cpus() called it even though nothing called initialize_cpus(). However, garbage collection at link time is implemented so there's no reason to provide an empty function to satisfy a symbol that is completely culled during link. Remove it. Change-Id: Ic13c85f1d3d57e38e7132e4289a98a95829f765a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/smmrelocate.c | 9 --------- src/soc/intel/baytrail/placeholders.c | 3 --- src/soc/intel/braswell/smm.c | 4 ---- src/soc/intel/broadwell/smmrelocate.c | 9 --------- src/soc/intel/fsp_baytrail/placeholders.c | 4 ---- src/soc/intel/skylake/smmrelocate.c | 11 ----------- 6 files changed, 40 deletions(-) diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 5c50ad1c..34a3551 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -352,15 +352,6 @@ void smm_relocate(void) smm_initiate_relocation(); } -void smm_init(void) -{ - /* smm_init() is normally called from initialize_cpus() in - * lapic_cpu_init.c. However, that path is no longer used. Don't reuse - * the function name because that would cause confusion. - * The smm_initialize() function above is used to setup SMM at the - * appropriate time. */ -} - void smm_lock(void) { /* LOCK the SMM memory window and enable normal SMM. diff --git a/src/soc/intel/baytrail/placeholders.c b/src/soc/intel/baytrail/placeholders.c index 500ced2..b110f5f 100644 --- a/src/soc/intel/baytrail/placeholders.c +++ b/src/soc/intel/baytrail/placeholders.c @@ -17,8 +17,5 @@ #include <device/pci_rom.h> #include <soc/acpi.h> - -void smm_init(void) {} - /* Rmodules don't like weak symbols. */ u32 map_oprom_vendev(u32 vendev) { return vendev; } diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index 8318050..3a7ab1c 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -29,10 +29,6 @@ /* Save settings which will be committed in SMI functions. */ static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT]; -void smm_init(void) -{ -} - void southcluster_smm_save_param(int param, uint32_t data) { smm_save_params[param] = data; diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 0cc6399..6fd609b 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -316,15 +316,6 @@ void smm_relocate(void) smm_initiate_relocation(); } -void smm_init(void) -{ - /* smm_init() is normally called from initialize_cpus() in - * lapic_cpu_init.c. However, that path is no longer used. Don't reuse - * the function name because that would cause confusion. - * The smm_initialize() function above is used to setup SMM at the - * appropriate time. */ -} - void smm_lock(void) { /* LOCK the SMM memory window and enable normal SMM. diff --git a/src/soc/intel/fsp_baytrail/placeholders.c b/src/soc/intel/fsp_baytrail/placeholders.c index 248aba2..587f0e9 100644 --- a/src/soc/intel/fsp_baytrail/placeholders.c +++ b/src/soc/intel/fsp_baytrail/placeholders.c @@ -20,9 +20,5 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) -void smm_init(void) {} -#endif - /* Rmodules don't like weak symbols. */ u32 map_oprom_vendev(u32 vendev) { return vendev; } diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 0c08068..807aaa3 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -305,17 +305,6 @@ void smm_relocate(void) smm_initiate_relocation(); } -void smm_init(void) -{ - /* - * smm_init() is normally called from initialize_cpus() in - * lapic_cpu_init.c. However, that path is no longer used. Don't reuse - * the function name because that would cause confusion. - * The smm_initialize() function above is used to setup SMM at the - * appropriate time. - */ -} - void smm_lock(void) { /*

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Patch set updated for coreboot: cpu/x86/mp_init: reduce exposure of internal implementation
by Aaron Durbin 05 May '16

05 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14598 -gerrit commit cc25601a5782d94ae1edfabcd3003412f60c83e0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 3 17:49:57 2016 -0500 cpu/x86/mp_init: reduce exposure of internal implementation With all users converted to using the mp_ops callbacks there's no need to expose that surface area. Therefore, keep it all within the mp_init compilation unit. Change-Id: Ia1cc5326c1fa5ffde86b90d805b8379f4e4f46cd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mp_init.c | 78 ++++++++++++++++++++++++++++++++++++++++++++-- src/include/cpu/x86/mp.h | 81 ------------------------------------------------ 2 files changed, 75 insertions(+), 84 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 362cda3..b9084c7 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -38,6 +38,57 @@ #include <thread.h> #define MAX_APIC_IDS 256 + +typedef void (*mp_callback_t)(void); + +/* + * A mp_flight_record details a sequence of calls for the APs to perform + * along with the BSP to coordinate sequencing. Each flight record either + * provides a barrier for each AP before calling the callback or the APs + * are allowed to perform the callback without waiting. Regardless, each + * record has the cpus_entered field incremented for each record. When + * the BSP observes that the cpus_entered matches the number of APs + * the bsp_call is called with bsp_arg and upon returning releases the + * barrier allowing the APs to make further progress. + * + * Note that ap_call() and bsp_call() can be NULL. In the NULL case the + * callback will just not be called. + */ +struct mp_flight_record { + atomic_t barrier; + atomic_t cpus_entered; + mp_callback_t ap_call; + mp_callback_t bsp_call; +} __attribute__((aligned(CACHELINE_SIZE))); + +#define _MP_FLIGHT_RECORD(barrier_, ap_func_, bsp_func_) \ + { \ + .barrier = ATOMIC_INIT(barrier_), \ + .cpus_entered = ATOMIC_INIT(0), \ + .ap_call = ap_func_, \ + .bsp_call = bsp_func_, \ + } + +#define MP_FR_BLOCK_APS(ap_func_, bsp_func_) \ + _MP_FLIGHT_RECORD(0, ap_func_, bsp_func_) + +#define MP_FR_NOBLOCK_APS(ap_func_, bsp_func_) \ + _MP_FLIGHT_RECORD(1, ap_func_, bsp_func_) + +/* The mp_params structure provides the arguments to the mp subsystem + * for bringing up APs. */ +struct mp_params { + int num_cpus; /* Total cpus include BSP */ + int parallel_microcode_load; + const void *microcode_pointer; + /* adjust_apic_id() is called for every potential apic id in the + * system up from 0 to CONFIG_MAX_CPUS. Return adjusted apic_id. */ + int (*adjust_apic_id)(int index, int apic_id); + /* Flight plan for APs and BSP. */ + struct mp_flight_record *flight_plan; + int num_records; +}; + /* This needs to match the layout in the .module_parametrs section. */ struct sipi_params { uint16_t gdtlimit; @@ -514,7 +565,26 @@ static void init_bsp(struct bus *cpu_bus) cpus[info->index].apic_id = cpu_path.apic.apic_id; } -int mp_init(struct bus *cpu_bus, struct mp_params *p) +/* + * mp_init() will set up the SIPI vector and bring up the APs according to + * mp_params. Each flight record will be executed according to the plan. Note + * that the MP infrastructure uses SMM default area without saving it. It's + * up to the chipset or mainboard to either e820 reserve this area or save this + * region prior to calling mp_init() and restoring it after mp_init returns. + * + * At the time mp_init() is called the MTRR MSRs are mirrored into APs then + * caching is enabled before running the flight plan. + * + * The MP initialization has the following properties: + * 1. APs are brought up in parallel. + * 2. The ordering of coreboot cpu number and APIC ids is not deterministic. + * Therefore, one cannot rely on this property or the order of devices in + * the device tree unless the chipset or mainboard know the APIC ids + * a priori. + * + * mp_init() returns < 0 on error, 0 on success. + */ +static int mp_init(struct bus *cpu_bus, struct mp_params *p) { int num_cpus; int num_aps; @@ -563,14 +633,16 @@ int mp_init(struct bus *cpu_bus, struct mp_params *p) return bsp_do_flight_plan(p); } -void mp_initialize_cpu(void) +/* Calls cpu_initialize(info->index) which calls the coreboot CPU drivers. */ +static void mp_initialize_cpu(void) { /* Call back into driver infrastructure for the AP initialization. */ struct cpu_info *info = cpu_info(); cpu_initialize(info->index); } -int mp_get_apic_id(int cpu_slot) +/* Returns apic id for coreboot cpu number or < 0 on failure. */ +static int mp_get_apic_id(int cpu_slot) { if (cpu_slot >= CONFIG_MAX_CPUS || cpu_slot < 0) return -1; diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index ff88a20..9742df0 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -29,56 +29,6 @@ static inline void mfence(void) __asm__ __volatile__("mfence\t\n": : :"memory"); } -typedef void (*mp_callback_t)(void); - -/* - * A mp_flight_record details a sequence of calls for the APs to perform - * along with the BSP to coordinate sequencing. Each flight record either - * provides a barrier for each AP before calling the callback or the APs - * are allowed to perform the callback without waiting. Regardless, each - * record has the cpus_entered field incremented for each record. When - * the BSP observes that the cpus_entered matches the number of APs - * the bsp_call is called with bsp_arg and upon returning releases the - * barrier allowing the APs to make further progress. - * - * Note that ap_call() and bsp_call() can be NULL. In the NULL case the - * callback will just not be called. - */ -struct mp_flight_record { - atomic_t barrier; - atomic_t cpus_entered; - mp_callback_t ap_call; - mp_callback_t bsp_call; -} __attribute__((aligned(CACHELINE_SIZE))); - -#define _MP_FLIGHT_RECORD(barrier_, ap_func_, bsp_func_) \ - { \ - .barrier = ATOMIC_INIT(barrier_), \ - .cpus_entered = ATOMIC_INIT(0), \ - .ap_call = ap_func_, \ - .bsp_call = bsp_func_, \ - } - -#define MP_FR_BLOCK_APS(ap_func_, bsp_func_) \ - _MP_FLIGHT_RECORD(0, ap_func_, bsp_func_) - -#define MP_FR_NOBLOCK_APS(ap_func_, bsp_func_) \ - _MP_FLIGHT_RECORD(1, ap_func_, bsp_func_) - -/* The mp_params structure provides the arguments to the mp subsystem - * for bringing up APs. */ -struct mp_params { - int num_cpus; /* Total cpus include BSP */ - int parallel_microcode_load; - const void *microcode_pointer; - /* adjust_apic_id() is called for every potential apic id in the - * system up from 0 to CONFIG_MAX_CPUS. Return adjusted apic_id. */ - int (*adjust_apic_id)(int index, int apic_id); - /* Flight plan for APs and BSP. */ - struct mp_flight_record *flight_plan; - int num_records; -}; - /* The sequence of the callbacks are in calling order. */ struct mp_ops { /* @@ -175,37 +125,6 @@ struct mp_ops { int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops); /* - * mp_init() will set up the SIPI vector and bring up the APs according to - * mp_params. Each flight record will be executed according to the plan. Note - * that the MP infrastructure uses SMM default area without saving it. It's - * up to the chipset or mainboard to either e820 reserve this area or save this - * region prior to calling mp_init() and restoring it after mp_init returns. - * - * At the time mp_init() is called the MTRR MSRs are mirrored into APs then - * caching is enabled before running the flight plan. - * - * The MP initialization has the following properties: - * 1. APs are brought up in parallel. - * 2. The ordering of coreboot cpu number and APIC ids is not deterministic. - * Therefore, one cannot rely on this property or the order of devices in - * the device tree unless the chipset or mainboard know the APIC ids - * a priori. - * - * mp_init() returns < 0 on error, 0 on success. - */ -int mp_init(struct bus *cpu_bus, struct mp_params *params); - -/* - * Useful functions to use in flight records when sequencing APs. - */ - -/* Calls cpu_initialize(info->index) which calls the coreboot CPU drivers. */ -void mp_initialize_cpu(void); - -/* Returns apic id for coreboot cpu number or < 0 on failure. */ -int mp_get_apic_id(int cpu_slot); - -/* * SMM helpers to use with initializing CPUs. */

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Patch set updated for coreboot: soc/intel/skylake: convert to using common MP and SMM init
by Aaron Durbin 05 May '16

05 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14597 -gerrit commit 6c1095b04b6a93d2fb57d69c6375a69576964740 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 3 17:45:59 2016 -0500 soc/intel/skylake: convert to using common MP and SMM init In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I5c4674ed258922b6616d75f070df976ef9fad209 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/cpu.c | 147 ++++++++++++++------------------ src/soc/intel/skylake/include/soc/cpu.h | 6 -- src/soc/intel/skylake/include/soc/smm.h | 15 ++-- src/soc/intel/skylake/smmrelocate.c | 147 +++++--------------------------- 4 files changed, 95 insertions(+), 220 deletions(-) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 17fa0ae..b7353ca 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -346,13 +346,6 @@ static void configure_mca(void) wrmsr(IA32_MC0_STATUS + (i * 4), msr); } -static void bsp_init_before_ap_bringup(struct bus *cpu_bus) -{ - /* Setup MTRRs based on physical address size. */ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); -} - /* All CPUs including BSP will run the following function. */ static void cpu_core_init(device_t cpu) { @@ -382,48 +375,6 @@ static void cpu_core_init(device_t cpu) enable_turbo(); } -/* MP initialization support. */ -static const void *microcode_patch; -int ht_disabled; - -static int adjust_apic_id_ht_disabled(int index, int apic_id) -{ - return 2 * index; -} - -static void relocate_and_load_microcode(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); -} - -static void enable_smis(void) -{ - /* - * Now that all APs have been relocated as well as the BSP let SMIs - * start flowing. - */ - southbridge_smm_enable_smi(); - - /* Lock down the SMRAM space. */ -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - smm_lock(); -#endif -} - -static struct mp_flight_record mp_steps[] = { - MP_FR_NOBLOCK_APS(relocate_and_load_microcode, - relocate_and_load_microcode), -#if IS_ENABLED(CONFIG_SMP) - MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), - /* Wait for APs to finish initialization before proceeding. */ -#endif - MP_FR_BLOCK_APS(NULL, enable_smis), -}; - static struct device_operations cpu_dev_ops = { .init = cpu_core_init, }; @@ -439,14 +390,22 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; -void soc_init_cpus(device_t dev) +/* MP initialization support. */ +static const void *microcode_patch; +static int ht_disabled; + +static void pre_mp_init(void) { - struct bus *cpu_bus = dev->link_list; + /* Setup MTRRs based on physical address size. */ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_cpu_count(void) +{ + msr_t msr; int num_threads; int num_cores; - msr_t msr; - struct mp_params mp_params; - void *smm_save_area; msr = rdmsr(CORE_THREAD_COUNT_MSR); num_threads = (msr.lo >> 0) & 0xffff; @@ -456,45 +415,69 @@ void soc_init_cpus(device_t dev) ht_disabled = num_threads == num_cores; - /* - * Perform any necessary BSP initialization before APs are brought up. - * This call also allows the BSP to prepare for any secondary effects - * from calling cpu_initialize() such as smm_init(). - */ - bsp_init_before_ap_bringup(cpu_bus); + return num_threads; +} +static void get_microcode_info(const void **microcode, int *parallel) +{ microcode_patch = intel_microcode_find(); + *microcode = microcode_patch; + *parallel = 1; +} - /* Save default SMM area before relocation occurs. */ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) - smm_save_area = backup_default_smm_area(); - else - smm_save_area = NULL; - - mp_params.num_cpus = num_threads; - mp_params.parallel_microcode_load = 1; +static int adjust_apic_id(int index, int apic_id) +{ if (ht_disabled) - mp_params.adjust_apic_id = adjust_apic_id_ht_disabled; + return 2 * index; else - mp_params.adjust_apic_id = NULL; - mp_params.flight_plan = &mp_steps[0]; - mp_params.num_records = ARRAY_SIZE(mp_steps); - mp_params.microcode_pointer = microcode_patch; + return index; +} - /* Load relocation and permeanent handlers. Then initiate relocation. */ - if (smm_initialize()) - printk(BIOS_CRIT, "SMM Initialiazation failed...\n"); +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); - if (IS_ENABLED(CONFIG_SMP)) - if (mp_init(cpu_bus, &mp_params)) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* After SMM relocation a 2nd microcode load is required. */ + intel_microcode_load_unlocked(microcode_patch); +} +static void post_mp_init(void) +{ /* Set Max Ratio */ set_max_ratio(); - /* Restore the default SMM region. */ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) - restore_default_smm_area(smm_save_area); + /* + * Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. + */ + southbridge_smm_enable_smi(); + + /* Lock down the SMRAM space. */ +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + smm_lock(); +#endif +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, + .adjust_cpu_apic_entry = adjust_apic_id, + .pre_mp_smm_init = smm_initialize, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; + +void soc_init_cpus(device_t dev) +{ + struct bus *cpu_bus = dev->link_list; + + if (mp_init_with_smm(cpu_bus, &mp_ops)) { + printk(BIOS_ERR, "MP initialization failure.\n"); + } } int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 8dd9742..f91a0ef 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -57,12 +57,6 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -/* - * Determine if HyperThreading is disabled. - * The variable is not valid until setup_ap_init() has been called. - */ -extern int ht_disabled; - /* CPU identification */ u32 cpu_family_model(void); u32 cpu_stepping(void); diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 94bdc55..fa8da46 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -53,7 +53,11 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts); #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) -int smm_initialize(void); +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase); +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size); +void smm_initialize(void); void smm_relocate(void); /* These helpers are for performing SMM relocation. */ @@ -68,10 +72,11 @@ void southbridge_clear_smi_status(void); void southbridge_smm_clear_state(void); void southbridge_smm_enable_smi(void); #else /* CONFIG_HAVE_SMI_HANDLER */ -static inline int smm_initialize(void) -{ - return 0; -} +static inline void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) {} +static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) {} +static inline void smm_initialize(void) {} static inline void smm_relocate(void) {} static inline void southbridge_trigger_smi(void) {} diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index a14721f..0c08068 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -54,9 +54,9 @@ static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) wrmsr(UNCORE_PRMRR_PHYS_MASK_MSR, relo_params->uncore_emrr_mask); } -static void update_save_state(int cpu, - struct smm_relocation_params *relo_params, - const struct smm_runtime *runtime) +static void update_save_state(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) { u32 smbase; u32 iedbase; @@ -66,7 +66,7 @@ static void update_save_state(int cpu, * stagger the entry points adjusting SMBASE downwards by save state * size * CPU num. */ - smbase = relo_params->smram_base - cpu * runtime->save_state_size; + smbase = staggered_smbase; iedbase = relo_params->ied_base; printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", @@ -101,8 +101,8 @@ static void update_save_state(int cpu, } else { em64t101_smm_state_save_area_t *save_state; - save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE - - runtime->save_state_size); + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - + sizeof(*save_state)); save_state->smbase = smbase; save_state->iedbase = iedbase; @@ -132,24 +132,11 @@ static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) * resides in the ramstage module. This occurs by trampolining from the default * SMRAM entry point to here. */ -static void asmlinkage cpu_smm_do_relocation(void *arg) +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) { msr_t mtrr_cap; - struct smm_relocation_params *relo_params; - const struct smm_module_params *p; - const struct smm_runtime *runtime; - int cpu; - - p = arg; - runtime = p->runtime; - relo_params = p->arg; - cpu = p->cpu; - - if (cpu >= CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Invalid CPU number assigned in SMM stub: %d\n", cpu); - return; - } + struct smm_relocation_params *relo_params = &smm_reloc_params; printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); @@ -184,7 +171,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) } /* Make appropriate changes to the save state map. */ - update_save_state(cpu, relo_params, runtime); + update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); /* Write EMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); @@ -250,51 +237,6 @@ static void fill_in_relocation_params(device_t dev, params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; } -static void adjust_apic_id_map(struct smm_loader_params *smm_params) -{ - struct smm_runtime *runtime; - int i; - - /* Adjust the APIC id map if HT is disabled. */ - if (!ht_disabled) - return; - - runtime = smm_params->runtime; - - /* The APIC ids increment by 2 when HT is disabled. */ - for (i = 0; i < CONFIG_MAX_CPUS; i++) - runtime->apic_id_to_cpu[i] = runtime->apic_id_to_cpu[i] * 2; -} - -static int install_relocation_handler(int num_cpus, - struct smm_relocation_params *relo_params) -{ - /* - * The default SMM entry can happen in parallel or serially. If the - * default SMM entry is done in parallel the BSP has already setup - * the saving state to each CPU's MSRs. At least one save state size - * is required for the initial SMM entry for the BSP to determine if - * parallel SMM relocation is even feasible. Set the stack size to - * the save state size, and call into the do_relocation handler. - */ - int save_state_size = sizeof(em64t101_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = 1, - .handler = (smm_handler_t)&cpu_smm_do_relocation, - .handler_arg = (void *)relo_params, - }; - - if (smm_setup_relocation_handler(&smm_params)) - return -1; - - adjust_apic_id_map(&smm_params); - - return 0; -} - static void setup_ied_area(struct smm_relocation_params *params) { char *ied_base; @@ -317,37 +259,10 @@ static void setup_ied_area(struct smm_relocation_params *params) memset(ied_base + (1 << 20), 0, (32 << 10)); } -static int install_permanent_handler(int num_cpus, - struct smm_relocation_params *relo_params) -{ - /* - * There are num_cpus concurrent stacks and num_cpus concurrent save - * state areas. Lastly, set the stack size to the save state size. - */ - int save_state_size = sizeof(em64t101_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = num_cpus, - }; - - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", - relo_params->smram_base); - if (smm_load_module((void *)relo_params->smram_base, - relo_params->smram_size, &smm_params)) - return -1; - - adjust_apic_id_map(&smm_params); - - return 0; -} - -static int cpu_smm_setup(void) +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) { device_t dev = SA_DEV_ROOT; - int num_cpus; - msr_t msr; printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); @@ -356,46 +271,24 @@ static int cpu_smm_setup(void) if (smm_reloc_params.ied_size) setup_ied_area(&smm_reloc_params); - msr = rdmsr(CORE_THREAD_COUNT_MSR); - num_cpus = msr.lo & 0xffff; - if (num_cpus > CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", - num_cpus, CONFIG_MAX_CPUS); - } - - if (install_relocation_handler(num_cpus, &smm_reloc_params)) { - printk(BIOS_CRIT, "SMM Relocation handler install failed.\n"); - return -1; - } - - if (install_permanent_handler(num_cpus, &smm_reloc_params)) { - printk(BIOS_CRIT, "SMM Permanent handler install failed.\n"); - return -1; - } - - /* Ensure the SMM handlers hit DRAM before performing first SMI. */ - wbinvd(); - - return 0; + *perm_smbase = smm_reloc_params.smram_base; + *perm_smsize = smm_reloc_params.smram_size; + *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } -int smm_initialize(void) +void smm_initialize(void) { - /* Return early if CPU SMM setup failed. */ - if (cpu_smm_setup()) - return -1; - /* Clear the SMM state in the southbridge. */ southbridge_smm_clear_state(); - /* Run the relocation handler. */ + /* + * Run the relocation handler for on the BSP to check and set up + * parallel SMM relocation. + */ smm_initiate_relocation(); if (smm_reloc_params.smm_save_state_in_msrs) printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); - - return 0; } void smm_relocate(void)

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Patch set updated for coreboot: cpu/x86: don't treat all chipsets the same regarding XIP_ROM_SIZE
by Aaron Durbin 05 May '16

05 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14625 -gerrit commit b84b37b15de0256faa039568bf57a32e57002b67 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 5 10:34:22 2016 -0500 cpu/x86: don't treat all chipsets the same regarding XIP_ROM_SIZE Previously, the XIP_ROM_SIZE Kconfig variable is used globally on x86 platforms with the assumption that all chipsets utilize this value. For the chipsets which do not use the variable it can lead to unnecessary alignment constraints in cbfs for romstage. Therefore, allow those chipsets a path to not be burdened by not passing '-P $(XIP_ROM_SIZE)' to cbfstool when adding romstage. Change-Id: Id8692df5ecec116a72b8e5886d86648ca959c78b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- Makefile.inc | 7 ++++++- src/cpu/x86/Kconfig | 11 +++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 94273df..9890e14 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -798,7 +798,12 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) # # Make sure that segment for .car.data is ignored while adding romstage. $(CONFIG_CBFS_PREFIX)/romstage-align := 64 -$(CONFIG_CBFS_PREFIX)/romstage-options := --xip -S .car.data -P $(CONFIG_XIP_ROM_SIZE) +$(CONFIG_CBFS_PREFIX)/romstage-options := --xip -S .car.data +# If XIP_ROM_SIZE isn't being used don't overly constrain romstage by passing +# -P with a default value. +ifneq ($(CONFIG_NO_FIXED_XIP_ROM_SIZE),y) +$(CONFIG_CBFS_PREFIX)/romstage-options += -P $(CONFIG_XIP_ROM_SIZE) +endif endif cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index e80f02b..74d87e2 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -69,8 +69,19 @@ config TSC_SYNC_MFENCE to execute an mfence instruction in order to synchronize rdtsc. This is true for all modern Intel CPUs. +config NO_FIXED_XIP_ROM_SIZE + bool + default n + help + The XIP_ROM_SIZE Kconfig variable is used globally on x86 + with the assumption that all chipsets utilize this value. + For the chipsets which do not use the variable it can lead + to unnecessary alignment constraints in cbfs for romstage. + Therefore, allow those chipsets a path to not be burdened. + config XIP_ROM_SIZE hex + depends on !NO_FIXED_XIP_ROM_SIZE default ROM_SIZE if ROMCC default 0x10000

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Patch set updated for coreboot: soc/intel: indicate to build system that XIP_ROM_SIZE isn't used
by Aaron Durbin 05 May '16

05 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14626 -gerrit commit f4bd99ae9a0dfc5f972a0e3a83ef89d6ef57ed05 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 5 10:38:03 2016 -0500 soc/intel: indicate to build system that XIP_ROM_SIZE isn't used The XIP_ROM_SIZE Kconfig variable isn't used for these chipsets. Therefore, indicate as such so that romstage can be placed in cbfs less rigidly. Change-Id: If5cae10b90e05029df56c282e8adf37fa0102955 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/braswell/Kconfig | 1 + src/soc/intel/skylake/Kconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bdb8eeb..d52d592 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -23,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index fcf382e..df8765d 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NO_FIXED_XIP_ROM_SIZE select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select PARALLEL_MP diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 3c6f788..3466aad 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NO_FIXED_XIP_ROM_SIZE select RELOCATABLE_MODULES select PARALLEL_MP select PCIEXP_ASPM diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 0b7dc8c..1ac0647 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS select IOAPIC select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK

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coreboot-gerrit May 2016