coreboot-gerrit April 2016

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Patch set updated for coreboot: lib/bootmem: allow architecture specific bootmem ranges
by Aaron Durbin 21 Apr '16

21 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14434 -gerrit commit 0167493a0e1a8c07b40864683ba3fb93214905b9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 17:25:59 2016 -0500 lib/bootmem: allow architecture specific bootmem ranges A architecture-specific function, named bootmem_arch_add_ranges(), is added so that each architecture can add entries into the bootmem memory map. This allows for a common write_tables() implementation to avoid code duplication. Change-Id: I834c82eae212869cad8bb02c7abcd9254d120735 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/tables.c | 5 +++++ src/arch/arm64/tables.c | 5 +++++ src/arch/mips/tables.c | 5 +++++ src/arch/power8/tables.c | 5 +++++ src/arch/riscv/tables.c | 5 +++++ src/arch/x86/tables.c | 5 +++++ src/include/bootmem.h | 3 +++ src/lib/bootmem.c | 2 ++ 8 files changed, 35 insertions(+) diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index eb08e6e..20891e8 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -17,12 +17,17 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <string.h> #include <cbmem.h> #include <lib.h> +void bootmem_arch_add_ranges(void) +{ +} + #define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE void write_tables(void) diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index eb08e6e..20891e8 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -17,12 +17,17 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <string.h> #include <cbmem.h> #include <lib.h> +void bootmem_arch_add_ranges(void) +{ +} + #define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE void write_tables(void) diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c index a3d9939..d54b8d6 100644 --- a/src/arch/mips/tables.c +++ b/src/arch/mips/tables.c @@ -18,12 +18,17 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <string.h> #include <cbmem.h> #include <lib.h> +void bootmem_arch_add_ranges(void) +{ +} + #define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE void write_tables(void) diff --git a/src/arch/power8/tables.c b/src/arch/power8/tables.c index 02d1c16..17e678a 100644 --- a/src/arch/power8/tables.c +++ b/src/arch/power8/tables.c @@ -17,12 +17,17 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <string.h> #include <cbmem.h> #include <lib.h> +void bootmem_arch_add_ranges(void) +{ +} + #define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE void write_tables(void) diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index eb08e6e..20891e8 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -17,12 +17,17 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <string.h> #include <cbmem.h> #include <lib.h> +void bootmem_arch_add_ranges(void) +{ +} + #define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE void write_tables(void) diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index b36078d..4fba509 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <arch/pirq_routing.h> @@ -180,6 +181,10 @@ static unsigned long write_smbios_table(unsigned long rom_table_end) return rom_table_end; } +void bootmem_arch_add_ranges(void) +{ +} + void write_tables(void) { unsigned long low_table_start, low_table_end; diff --git a/src/include/bootmem.h b/src/include/bootmem.h index 0665058..10c8d51 100644 --- a/src/include/bootmem.h +++ b/src/include/bootmem.h @@ -26,6 +26,9 @@ */ void bootmem_init(void); +/* Architecture hook to add bootmem areas the architecture controls. */ +void bootmem_arch_add_ranges(void); + /* Add a range of a given type to the bootmem address space. */ void bootmem_add_range(uint64_t start, uint64_t size, uint32_t type); diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index 29cbec6..ea02a16 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -39,6 +39,8 @@ void bootmem_init(void) /* Add memory used by CBMEM. */ cbmem_add_bootmem(); + + bootmem_arch_add_ranges(); } void bootmem_add_range(uint64_t start, uint64_t size, uint32_t type)

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Patch merged into coreboot/master: lib: add helper for constructing coreboot forwarding table
by gerrit＠coreboot.org 21 Apr '16

21 Apr '16

the following patch was just integrated into master: commit 8984af89b85034ad0456bb3a63a78cd63c618934 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 17:06:09 2016 -0500 lib: add helper for constructing coreboot forwarding table The x86 architecture needs to add a forwarding table to the real coreboot table. Provide a helper function to do this for aligning the architectures on a common write_tables() implementation. Change-Id: I9a2875507e6260679874a654ddf97b879222d44e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14433 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14433 for details. -gerrit

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Patch merged into coreboot/master: arch/x86: remove low coreboot table support
by gerrit＠coreboot.org 21 Apr '16

21 Apr '16

the following patch was just integrated into master: commit dcee908921444282c82c4cdde455c8819e3965af Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 16:11:22 2016 -0500 arch/x86: remove low coreboot table support In addition to being consistent with all other architectures, all chipsets support cbmem so the low coreboot table path is stale and never taken. Also it's important to note the memory written in to that low area of memory wasn't automatically reserved unless that path was taken. To that end remove low coreboot table support for x86. Change-Id: Ib96338cf3024e3aa34931c53a7318f40185be34c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14432 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14432 for details. -gerrit

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Patch set updated for coreboot: arch/x86: remove low coreboot table support
by Aaron Durbin 21 Apr '16

21 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14432 -gerrit commit e98406552b2d757ca2f26d0d7129473bfacd0e8a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 16:11:22 2016 -0500 arch/x86: remove low coreboot table support In addition to being consistent with all other architectures, all chipsets support cbmem so the low coreboot table path is stale and never taken. Also it's important to note the memory written in to that low area of memory wasn't automatically reserved unless that path was taken. To that end remove low coreboot table support for x86. Change-Id: Ib96338cf3024e3aa34931c53a7318f40185be34c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/tables.c | 7 ++----- src/lib/coreboot_table.c | 15 +-------------- 2 files changed, 3 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 309ac16..b36078d 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -183,7 +183,7 @@ static unsigned long write_smbios_table(unsigned long rom_table_end) void write_tables(void) { unsigned long low_table_start, low_table_end; - unsigned long rom_table_start, rom_table_end; + unsigned long rom_table_end; /* Even if high tables are configured, some tables are copied both to * the low and the high area, so payloads and OSes don't need to know @@ -191,7 +191,6 @@ void write_tables(void) */ unsigned long high_table_pointer; - rom_table_start = 0xf0000; rom_table_end = 0xf0000; /* Start low addr at 0x500, so we don't run into conflicts with the BDA @@ -242,8 +241,6 @@ void write_tables(void) printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", new_high_table_pointer - high_table_pointer); } else { - /* The coreboot table must be in 0-4K or 960K-1M */ - write_coreboot_table(low_table_start, low_table_end, - rom_table_start, rom_table_end); + printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); } } diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 18e8b34..091ceaf 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -447,7 +447,7 @@ static unsigned long lb_table_fini(struct lb_header *head) unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end) + unsigned long rom_table_start __unused, unsigned long rom_table_end) { struct lb_header *head; @@ -468,10 +468,6 @@ unsigned long write_coreboot_table( rom_table_end); head = lb_table_init(rom_table_end); - rom_table_end = (unsigned long)head; - printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end); - rom_table_end = ALIGN(rom_table_end, (64 * 1024)); - printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", rom_table_end); #if CONFIG_USE_OPTION_TABLE { @@ -500,15 +496,6 @@ unsigned long write_coreboot_table( bootmem_add_range(low_table_start, size, LB_MEM_TABLE); } - /* Record the pirq table, acpi tables, and maybe the mptable. However, - * these only need to be added when the rom_table is sitting below - * 1MiB. If it isn't that means high tables are being written. - * The code below handles high tables correctly. */ - if (rom_table_end <= (1 << 20)) { - uint64_t size = rom_table_end - rom_table_start; - bootmem_add_range(rom_table_start, size, LB_MEM_TABLE); - } - /* No other memory areas can be added after the memory table has been * committed as the entries won't show up in the serialize mem table. */ bootmem_write_memory_table(lb_memory(head));

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Patch merged into coreboot/master: arch/x86: clean up write_tables()
by gerrit＠coreboot.org 21 Apr '16

21 Apr '16

the following patch was just integrated into master: commit 86cbfa00d00da2786e3a43edd3cf173739f99cba Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 15:53:56 2016 -0500 arch/x86: clean up write_tables() There were quite a number of #if/#endif guards in the write_tables() code. Clean up that function by splitting up the subcomponents into their own individual functions. The same ordering and logic is kept maintained. The changes also benefit the goal of using a common core write_tables() logic so that other architectures don't duplicate large swaths of code. Change-Id: I93f6775d698500f25f72793cbe3fd4eb9d01a20c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14431 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14431 for details. -gerrit

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Patch set updated for coreboot: arch/x86: clean up write_tables()
by Aaron Durbin 21 Apr '16

21 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14431 -gerrit commit 0eb466064ee1ac9503f7551b8d219a005af51042 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 15:53:56 2016 -0500 arch/x86: clean up write_tables() There were quite a number of #if/#endif guards in the write_tables() code. Clean up that function by splitting up the subcomponents into their own individual functions. The same ordering and logic is kept maintained. The changes also benefit the goal of using a common core write_tables() logic so that other architectures don't duplicate large swaths of code. Change-Id: I93f6775d698500f25f72793cbe3fd4eb9d01a20c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/tables.c | 86 +++++++++++++++++++++++++++++++++++---------------- 1 file changed, 60 insertions(+), 26 deletions(-) diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 5780cd1..309ac16 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -28,28 +28,10 @@ #define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE -void write_tables(void) +static unsigned long write_pirq_table(unsigned long rom_table_end) { - unsigned long low_table_start, low_table_end; - unsigned long rom_table_start, rom_table_end; - - /* Even if high tables are configured, some tables are copied both to - * the low and the high area, so payloads and OSes don't need to know - * about the high tables. - */ unsigned long high_table_pointer; - rom_table_start = 0xf0000; - rom_table_end = 0xf0000; - - /* Start low addr at 0x500, so we don't run into conflicts with the BDA - * in case our data structures grow beyond 0x400. Only GDT - * and the coreboot table use low_tables. - */ - low_table_start = 0; - low_table_end = 0x500; - -#if CONFIG_GENERATE_PIRQ_TABLE #define MAX_PIRQ_TABLE_SIZE (4 * 1024) post_code(0x9a); @@ -73,9 +55,13 @@ void write_tables(void) new_high_table_pointer - high_table_pointer); } -#endif + return rom_table_end; +} + +static unsigned long write_mptable(unsigned long rom_table_end) +{ + unsigned long high_table_pointer; -#if CONFIG_GENERATE_MP_TABLE #define MAX_MP_TABLE_SIZE (4 * 1024) post_code(0x9b); @@ -96,9 +82,14 @@ void write_tables(void) printk(BIOS_DEBUG, "MP table: %ld bytes.\n", new_high_table_pointer - high_table_pointer); } -#endif /* CONFIG_GENERATE_MP_TABLE */ -#if CONFIG_HAVE_ACPI_TABLES + return rom_table_end; +} + +static unsigned long write_acpi_table(unsigned long rom_table_end) +{ + unsigned long high_table_pointer; + #define MAX_ACPI_SIZE (144 * 1024) post_code(0x9c); @@ -157,9 +148,15 @@ void write_tables(void) rom_table_end = ALIGN(rom_table_end, 1024); } -#endif + return rom_table_end; +} + +static unsigned long write_smbios_table(unsigned long rom_table_end) +{ + unsigned long high_table_pointer; + #define MAX_SMBIOS_SIZE 2048 -#if CONFIG_GENERATE_SMBIOS_TABLES + high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE); if (high_table_pointer) { unsigned long new_high_table_pointer; @@ -179,7 +176,44 @@ void write_tables(void) printk(BIOS_DEBUG, "SMBIOS size %ld bytes\n", new_rom_table_end - rom_table_end); rom_table_end = ALIGN(new_rom_table_end, 16); } -#endif + + return rom_table_end; +} + +void write_tables(void) +{ + unsigned long low_table_start, low_table_end; + unsigned long rom_table_start, rom_table_end; + + /* Even if high tables are configured, some tables are copied both to + * the low and the high area, so payloads and OSes don't need to know + * about the high tables. + */ + unsigned long high_table_pointer; + + rom_table_start = 0xf0000; + rom_table_end = 0xf0000; + + /* Start low addr at 0x500, so we don't run into conflicts with the BDA + * in case our data structures grow beyond 0x400. Only GDT + * and the coreboot table use low_tables. + */ + low_table_start = 0; + low_table_end = 0x500; + + /* This table must be between 0x0f0000 and 0x100000 */ + if (IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)) + rom_table_end = write_pirq_table(rom_table_end); + + /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ + if (IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) + rom_table_end = write_mptable(rom_table_end); + + if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)) + rom_table_end = write_acpi_table(rom_table_end); + + if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)) + rom_table_end = write_smbios_table(rom_table_end); post_code(0x9e);

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Patch merged into coreboot/master: arch: only print cbmem entries in one place
by gerrit＠coreboot.org 21 Apr '16

21 Apr '16

the following patch was just integrated into master: commit 60eb2c2c40193c457268aaa835002785b357df96 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 15:33:08 2016 -0500 arch: only print cbmem entries in one place Each arch was calling cbmem_list() in their own write_tables() function. Consolidate that call and place it in common code in write_coreboot_table(). Change-Id: If0d4c84e0f8634e5cef6996b2be4a86cc83c95a9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14430 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14430 for details. -gerrit

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Patch set updated for coreboot: arch: only print cbmem entries in one place
by Aaron Durbin 21 Apr '16

21 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14430 -gerrit commit e88cb127541787aa2f3edd0f4635d4d405c5cbfd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 15:33:08 2016 -0500 arch: only print cbmem entries in one place Each arch was calling cbmem_list() in their own write_tables() function. Consolidate that call and place it in common code in write_coreboot_table(). Change-Id: If0d4c84e0f8634e5cef6996b2be4a86cc83c95a9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/tables.c | 3 --- src/arch/arm64/tables.c | 3 --- src/arch/mips/tables.c | 3 --- src/arch/power8/tables.c | 3 --- src/arch/riscv/tables.c | 3 --- src/arch/x86/tables.c | 3 --- src/lib/coreboot_table.c | 3 +++ 7 files changed, 3 insertions(+), 18 deletions(-) diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 17a3fd1..eb08e6e 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -50,9 +50,6 @@ void write_tables(void) new_table_pointer - table_pointer); post_code(0x9e); - - /* Print CBMEM sections */ - cbmem_list(); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index 17a3fd1..eb08e6e 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -50,9 +50,6 @@ void write_tables(void) new_table_pointer - table_pointer); post_code(0x9e); - - /* Print CBMEM sections */ - cbmem_list(); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c index 2083442..a3d9939 100644 --- a/src/arch/mips/tables.c +++ b/src/arch/mips/tables.c @@ -51,9 +51,6 @@ void write_tables(void) new_table_pointer - table_pointer); post_code(0x9e); - - /* Print CBMEM sections */ - cbmem_list(); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/arch/power8/tables.c b/src/arch/power8/tables.c index 0a88505..02d1c16 100644 --- a/src/arch/power8/tables.c +++ b/src/arch/power8/tables.c @@ -51,9 +51,6 @@ void write_tables(void) new_table_pointer - table_pointer); post_code(0x9e); - - /* Print CBMEM sections */ - cbmem_list(); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index 17a3fd1..eb08e6e 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -50,9 +50,6 @@ void write_tables(void) new_table_pointer - table_pointer); post_code(0x9e); - - /* Print CBMEM sections */ - cbmem_list(); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 8cfd655..5780cd1 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -212,7 +212,4 @@ void write_tables(void) write_coreboot_table(low_table_start, low_table_end, rom_table_start, rom_table_end); } - - /* Print CBMEM sections */ - cbmem_list(); } diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index eeed65e..18e8b34 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -572,6 +572,9 @@ unsigned long write_coreboot_table( /* Add all cbmem entries into the coreboot tables. */ cbmem_add_records_to_cbtable(head); + /* Print CBMEM sections */ + cbmem_list(); + /* Remember where my valid memory ranges are */ return lb_table_fini(head); }

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Patch merged into coreboot/master: arch: use Kconfig variable for coreboot table size
by gerrit＠coreboot.org 21 Apr '16

21 Apr '16

the following patch was just integrated into master: commit a0546da57a79499662f9f82590d1ef6fa18ed893 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 15:17:08 2016 -0500 arch: use Kconfig variable for coreboot table size Instead of hard coding a #define in each architecture's tables.c for the coreboot table size in cbmem use a Kconfig varible. This aids in aligning on a common write_tables() implementation instead of duplicating the code for each architecture. Change-Id: I09c0f56133606ea62e9a9c4c6b9828bc24dcc668 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14429 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14429 for details. -gerrit

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New patch to review for coreboot: soc/intel/quark/romstage: Increase size of FSP
by Leroy P Leahy 21 Apr '16

21 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14453 -gerrit commit 2ced390813495354f8fdd357beb80281bc3c0115 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Apr 19 14:17:46 2016 -0700 soc/intel/quark/romstage: Increase size of FSP Increase the size of FSP to 320 KiB. The debug build of QuarkFspPkg with GCC 4.8.4 is just over the 256 KiB limit. TEST=Build and run on Galileo Gen2 Change-Id: I817ab310e6de145db37174ebf2b9d661167acb01 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/romstage/esram_init.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc index b899741..5cc3f0d 100644 --- a/src/soc/intel/quark/romstage/esram_init.inc +++ b/src/soc/intel/quark/romstage/esram_init.inc @@ -457,7 +457,7 @@ esram_init_done: /* Copy FSP image to eSRAM and call it. */ /* TODO: FSP location/size could be got in a routine. */ cld - movl $(0x00040000), %ecx /* 256K DWORDs = 64K */ + movl $(0x00050000), %ecx shrl $2, %ecx movl $CONFIG_FSP_LOC, %esi /* The source address. */ movl $CONFIG_FSP_ESRAM_LOC, %edi /* FSP destination in ESRAM */

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coreboot-gerrit April 2016