coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: google/parrot: Fix keyboard interrupts, DSDT
by Matt DeVillier 25 Nov '16

25 Nov '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17017 -gerrit commit c01b090f662ff194c1c393cc55d8aac127c3725c Author: Prabal Saha <coolstarorganization(a)gmail.com> Date: Thu Oct 13 07:52:23 2016 -0700 google/parrot: Fix keyboard interrupts, DSDT Commit 967cd9a [ChromeOS: fix Kconfig dependencies] broke keyboard interrupts on parrot by making SERIRQ_CONTINUOUS_MODE conditional on CONFIG_CHROMEOS, which it should not be; fix by moving back under main board specific options config. Additionally, Windows [8/8.1/10] fails to enumerate the keyboard when its ACPI entry is located under the SIO device since it is missing an _HID entry, so add the appropriate value per ACPI spec 5 ch. 9.7 Change-Id: Ia69e9b326001d2026b15b4ec03c94f7d03c8a700 Signed-off-by: Prabal Saha <coolstarorganization(a)gmail.com> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/ec/compal/ene932/acpi/superio.asl | 3 ++- src/mainboard/google/parrot/Kconfig | 5 ++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ec/compal/ene932/acpi/superio.asl b/src/ec/compal/ene932/acpi/superio.asl index 8eba623..498f2e0 100644 --- a/src/ec/compal/ene932/acpi/superio.asl +++ b/src/ec/compal/ene932/acpi/superio.asl @@ -16,6 +16,7 @@ // Scope is \_SB.PCI0.LPCB Device (SIO) { + Name (_HID, EisaId("PNP0A05")) Name (_UID, 0) Name (_ADR, 0) @@ -23,4 +24,4 @@ Device (SIO) { #ifdef SIO_EC_ENABLE_PS2K #include <drivers/pc80/pc/ps2_controller.asl> #endif -} +} \ No newline at end of file diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 974c58f..7b6b49b 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -14,13 +14,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE config CHROMEOS select VBOOT_VBNV_CMOS - # Workaround for EC/KBC IRQ1. - select SERIRQ_CONTINUOUS_MODE - config MAINBOARD_DIR string default google/parrot

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Patch set updated for coreboot: intel/gma: Call intel_gmbus_stop inside intel_gmbus_read_edid
by Arthur Heymans 24 Nov '16

24 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17601 -gerrit commit a396f2cf7943443ca9b570b07d3e55b9f650c28d Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Nov 24 23:43:15 2016 +0100 intel/gma: Call intel_gmbus_stop inside intel_gmbus_read_edid Before this change you had to call intel_gmbus_stop after intel_gmbus_read_edid if you whished to call it again. Not doing so resulted in NULL EDID. Change-Id: Idca741c50cab4c4bf2746e658ac19671522c48fd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/intel/gma/edid.c | 3 ++- src/drivers/intel/gma/edid.h | 2 +- src/northbridge/intel/gm45/gma.c | 2 -- src/northbridge/intel/i945/gma.c | 1 - src/northbridge/intel/nehalem/gma.c | 1 - src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c | 1 - src/northbridge/intel/x4x/gma.c | 1 - 7 files changed, 3 insertions(+), 8 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 3902094..f2043a3 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -60,7 +60,7 @@ static void intel_gmbus_stop_bus(u8 * mmio, u8 bus) write32(GMBUS2_ADDR, GMBUS_INUSE); } -void intel_gmbus_stop(u8 *mmio) +static void intel_gmbus_stop(u8 *mmio) { intel_gmbus_stop_bus(mmio, 6); intel_gmbus_stop_bus(mmio, 2); @@ -110,4 +110,5 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) if ((i & 0xf) == 0xf) printk (BIOS_SPEW, "\n"); } + intel_gmbus_stop(mmio); } diff --git a/src/drivers/intel/gma/edid.h b/src/drivers/intel/gma/edid.h index d8214cf..e334780 100644 --- a/src/drivers/intel/gma/edid.h +++ b/src/drivers/intel/gma/edid.h @@ -1,2 +1,2 @@ void intel_gmbus_read_edid(u8 *gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size); -void intel_gmbus_stop(u8 *gmbus_mmio); + diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8938197..6ec78b6 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -381,7 +381,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, sizeof(edid_data)); - intel_gmbus_stop(mmio + GMBUS0); decode_edid(edid_data, sizeof(edid_data), &edid); mode = &edid.mode; @@ -600,7 +599,6 @@ static u8 vga_connected(u8 *mmio) u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, sizeof(vga_edid)); - intel_gmbus_stop(mmio + GMBUS0); for (int i = 0; i < 8; i++) { if (vga_edid[i] != header[i]) { printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index e3ff478..b23dbff 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -566,7 +566,6 @@ static int probe_edid(u8 *pmmio, u8 slave) u8 vga_edid[128]; u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; intel_gmbus_read_edid(pmmio + GMBUS0, slave, 0x50, vga_edid, 128); - intel_gmbus_stop(pmmio + GMBUS0); for (int i = 0; i < 8; i++) { if (vga_edid[i] != header[i]) { printk(BIOS_DEBUG, "No display connected on slave %d\n", diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 33e8eaa..95bc897 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -698,7 +698,6 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, sizeof(edid_data)); - intel_gmbus_stop(mmio + PCH_GMBUS0); decode_edid(edid_data, sizeof(edid_data), &edid); mode = &edid.mode; diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index bcdeaa0..e9a3592 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -184,7 +184,6 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info, intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, sizeof(edid_data)); - intel_gmbus_stop(mmio + PCH_GMBUS0); decode_edid(edid_data, sizeof(edid_data), &edid); diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 62e28aa..b89c834 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -116,7 +116,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, sizeof(edid_data)); - intel_gmbus_stop(mmio + GMBUS0); decode_edid(edid_data, sizeof(edid_data), &edid); mode = &edid.mode;

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New patch to review for coreboot: intel/gma: Call intel_gmbus_stop inside intel_gmbus_read_edid
by Arthur Heymans 24 Nov '16

24 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17601 -gerrit commit bf4071be135786f7b54ab1863e7569f6d6e5265e Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Nov 24 23:43:15 2016 +0100 intel/gma: Call intel_gmbus_stop inside intel_gmbus_read_edid Before this change you had to call intel_gmbus_stop after intel_gmbus_read_edid if you whished to call it again. Not doing so resulted in NULL EDID. Change-Id: Idca741c50cab4c4bf2746e658ac19671522c48fd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/intel/gma/edid.c | 1 + src/drivers/intel/gma/edid.h | 2 +- src/northbridge/intel/gm45/gma.c | 2 -- src/northbridge/intel/i945/gma.c | 1 - src/northbridge/intel/nehalem/gma.c | 1 - src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c | 1 - src/northbridge/intel/x4x/gma.c | 1 - 7 files changed, 2 insertions(+), 7 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 3902094..b4b8721 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -110,4 +110,5 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) if ((i & 0xf) == 0xf) printk (BIOS_SPEW, "\n"); } + intel_gmbus_stop(mmio); } diff --git a/src/drivers/intel/gma/edid.h b/src/drivers/intel/gma/edid.h index d8214cf..e334780 100644 --- a/src/drivers/intel/gma/edid.h +++ b/src/drivers/intel/gma/edid.h @@ -1,2 +1,2 @@ void intel_gmbus_read_edid(u8 *gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size); -void intel_gmbus_stop(u8 *gmbus_mmio); + diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8938197..6ec78b6 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -381,7 +381,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, sizeof(edid_data)); - intel_gmbus_stop(mmio + GMBUS0); decode_edid(edid_data, sizeof(edid_data), &edid); mode = &edid.mode; @@ -600,7 +599,6 @@ static u8 vga_connected(u8 *mmio) u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, sizeof(vga_edid)); - intel_gmbus_stop(mmio + GMBUS0); for (int i = 0; i < 8; i++) { if (vga_edid[i] != header[i]) { printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index e3ff478..b23dbff 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -566,7 +566,6 @@ static int probe_edid(u8 *pmmio, u8 slave) u8 vga_edid[128]; u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; intel_gmbus_read_edid(pmmio + GMBUS0, slave, 0x50, vga_edid, 128); - intel_gmbus_stop(pmmio + GMBUS0); for (int i = 0; i < 8; i++) { if (vga_edid[i] != header[i]) { printk(BIOS_DEBUG, "No display connected on slave %d\n", diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 33e8eaa..95bc897 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -698,7 +698,6 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, sizeof(edid_data)); - intel_gmbus_stop(mmio + PCH_GMBUS0); decode_edid(edid_data, sizeof(edid_data), &edid); mode = &edid.mode; diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index bcdeaa0..e9a3592 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -184,7 +184,6 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info, intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, sizeof(edid_data)); - intel_gmbus_stop(mmio + PCH_GMBUS0); decode_edid(edid_data, sizeof(edid_data), &edid); diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 62e28aa..b89c834 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -116,7 +116,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, sizeof(edid_data)); - intel_gmbus_stop(mmio + GMBUS0); decode_edid(edid_data, sizeof(edid_data), &edid); mode = &edid.mode;

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Patch set updated for coreboot: nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency
by Arthur Heymans 24 Nov '16

24 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17597 -gerrit commit b94f265d02a9eb43a108537fe2bc5c7c60951f25 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Nov 24 13:23:05 2016 +0100 nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency This allows to put the PWM frequency value in Hz in devicetree instead of a plain BLC_PWM_CTL value. It also allows to set the duty cycle of the backlight. The previous default frequency was 1006Hz but is now 1000Hz for simplicity. 1000Hz is a good default since it typically works well on LED backlit displays. A LED backlit display with a too slow PWM causes highly annoying flicker, assuming the PWM directly drives the backlight. CCFL displays want a lower pwm frequency in the 50-200Hz range. Driving a CCFL panel with a too high PWM frequency causes the IC to misbehave: unevenly lit backlight and/or high frequency tone. Since driving a LED backlit display too slow is worse than driving a CCFL backlit display too fast, a fast default is kept. Change-Id: I4d9a555ac7ea5605712c1fcda994a6fcabf9acf3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/chip.h | 1 + src/northbridge/intel/gm45/gma.c | 32 +++++++++++++++++++++++++++++--- 2 files changed, 30 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 836d6bb..d2e70f7 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -26,6 +26,7 @@ struct northbridge_intel_gm45_config { u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ struct i915_gpu_controller_info gfx; + u32 pwm_freq; /* * Maximum PCI mmio size in MiB. diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8938197..34eed2d 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -611,6 +611,30 @@ static u8 vga_connected(u8 *mmio) return 1; } +/* + * In principle the display core clock is + * (PP_DIVISOR[31:16] + 1) * 2 / 100 * MHz. + * Since PP_DIVISOR[31:16] is not touched it will be at its default value + * of 0x270f, hence the default display core clock is 200MHz. + * This is done in order to avoid potential overflows. + */ + +#define DEFAULT_CORE_CLOCK 200000000 + +static u32 freq_to_blc_pwm_ctl(u16 pwm_freq, u16 duty_perc) +{ + u32 blc_mod; + + blc_mod = DEFAULT_CORE_CLOCK / (128 * pwm_freq); + + if (duty_perc <= 100) + return (blc_mod << 16) | (blc_mod * duty_perc / 100); + else + return (blc_mod << 16) | blc_mod; +} + +#define DEFAULT_PWM_FREQ 1000 + static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; @@ -643,10 +667,12 @@ static void gma_pm_init_post_vbios(struct device *const dev) /* Enable Backlight */ gtt_write(BLC_PWM_CTL2, (1 << 31)); - if (conf->gfx.backlight == 0) - gtt_write(BLC_PWM_CTL, 0x06100610); + if (conf->pwm_freq == 0) + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(DEFAULT_PWM_FREQ, + 100)); else - gtt_write(BLC_PWM_CTL, conf->gfx.backlight); + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(conf->pwm_freq, + 100)); } static void gma_func0_init(struct device *dev)

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Patch merged into coreboot/master: x86 BIST: Fix missing include
by gerrit＠coreboot.org 24 Nov '16

24 Nov '16

the following patch was just integrated into master: commit 619a245def2ac424beeb8a68d246a78849acd0cc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 23 23:54:29 2016 +0200 x86 BIST: Fix missing include Change-Id: I3d1a456f17073c99c9502da26e09cfde65380746 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17586 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17586 for details. -gerrit

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New patch to review for coreboot: util/lint: Add check to verify saved configs are miniconfigs
by Martin Roth 24 Nov '16

24 Nov '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17600 -gerrit commit 9b53e52418ba2018a6bf94c591dcd2bba54913fe Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 24 13:16:28 2016 -0700 util/lint: Add check to verify saved configs are miniconfigs Change-Id: Ifc5ec645dd27663c1b1fde9ff16d48534606a554 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-017-configs | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/util/lint/lint-stable-017-configs b/util/lint/lint-stable-017-configs new file mode 100755 index 0000000..b8d49de --- /dev/null +++ b/util/lint/lint-stable-017-configs @@ -0,0 +1,33 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# DESCR: Check that saved config files are miniconfigs + +LC_ALL=C export LC_ALL + +SYMBOLS='CONFIG_ARCH_\|CONFIG_MAINBOARD_HAS_' + +# Use git grep if the code is in a git repo, otherwise use grep. +if [ -n "$(command -v git)" ] && [ -d .git ]; then + GREP="git grep" +else + GREP="grep -r" +fi + +#look for a couple of things that should only be set by select keywords +for file in \ + $($GREP "$SYMBOLS" configs | \ + sed 's/:.*//' | uniq) ; do \ + echo "Error: $file seems to be a full config"; \ + done

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Patch merged into coreboot/master: mc_tcu3: Swap LVDS even and odd lanes for a certain hardware
by gerrit＠coreboot.org 24 Nov '16

24 Nov '16

the following patch was just integrated into master: commit 507c9c59766b0de24322f7f674f7f1cc4ed50e3a Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Nov 23 07:49:52 2016 +0100 mc_tcu3: Swap LVDS even and odd lanes for a certain hardware Due to some LVDS cable constraints even and odd lanes needs to be swapped on certain hardware. The hardware ID will be used to distinguish between these two cases. The swapping itself will be done by PTN3460, which is configurable for that. Change-Id: I339b2321a8ed1bc3bbf10aa8e50eb598b14b15fa Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/17576 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> See https://review.coreboot.org/17576 for details. -gerrit

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Patch merged into coreboot/master: vendorcode/siemens: Add HWID to hwilib
by gerrit＠coreboot.org 24 Nov '16

24 Nov '16

the following patch was just integrated into master: commit ba7525df182c87f941cec93867f3fa0e509c7131 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Nov 23 07:31:35 2016 +0100 vendorcode/siemens: Add HWID to hwilib Add the location of HWID field so that hwilib supports this value as well. Change-Id: If6d4695f861232231ac8f9c247c0a10410dac1c5 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/17575 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> See https://review.coreboot.org/17575 for details. -gerrit

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Patch merged into coreboot/master: drivers/net/Kconfig: Hide REALTEK_8168_RESET in menuconfig
by gerrit＠coreboot.org 24 Nov '16

24 Nov '16

the following patch was just integrated into master: commit d83f9fc80e9bbeb76fb538a386e3692eed840b07 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Nov 23 10:52:28 2016 +0100 drivers/net/Kconfig: Hide REALTEK_8168_RESET in menuconfig Resetting a Realtek 8168 NIC only makes sense on targets that have such a device. Change-Id: I8ac9e8da1d8ecaacb19b4610a9b75f107915d691 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17577 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17577 for details. -gerrit

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Patch set updated for coreboot: nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency
by Arthur Heymans 24 Nov '16

24 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17597 -gerrit commit c3490ec980fea3ca4aa5945b78fcc7fb85b3b015 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Nov 24 13:23:05 2016 +0100 nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency This allows to put the PWM frequency value in Hz in devicetree instead of a plain BLC_PWM_CTL value. It also allows to set the duty cycle of the backlight. The previous default frequency was 1006Hz but is now 1000Hz for simplicity. 1000Hz is a good default since it typically works well on LED backlit displays. A LED backlit display with a too slow PWM causes highly annoying flicker, assuming the PWM directly drives the backlight. CCFL displays want a lower pwm frequency in the 50-200Hz range. Driving a CCFL panel with a too high PWM frequency causes the IC to misbehave: unevenly lit backlight and/or high frequency tone. Since driving a LED backlit display too slow is worse than driving a CCFL backlit display too fast, a fast default is chosen. Change-Id: I4d9a555ac7ea5605712c1fcda994a6fcabf9acf3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/chip.h | 1 + src/northbridge/intel/gm45/gma.c | 32 +++++++++++++++++++++++++++++--- 2 files changed, 30 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 836d6bb..d2e70f7 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -26,6 +26,7 @@ struct northbridge_intel_gm45_config { u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ struct i915_gpu_controller_info gfx; + u32 pwm_freq; /* * Maximum PCI mmio size in MiB. diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8938197..34eed2d 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -611,6 +611,30 @@ static u8 vga_connected(u8 *mmio) return 1; } +/* + * In principle the display core clock is + * (PP_DIVISOR[31:16] + 1) * 2 / 100 * MHz. + * Since PP_DIVISOR[31:16] is not touched it will be at its default value + * of 0x270f, hence the default display core clock is 200MHz. + * This is done in order to avoid potential overflows. + */ + +#define DEFAULT_CORE_CLOCK 200000000 + +static u32 freq_to_blc_pwm_ctl(u16 pwm_freq, u16 duty_perc) +{ + u32 blc_mod; + + blc_mod = DEFAULT_CORE_CLOCK / (128 * pwm_freq); + + if (duty_perc <= 100) + return (blc_mod << 16) | (blc_mod * duty_perc / 100); + else + return (blc_mod << 16) | blc_mod; +} + +#define DEFAULT_PWM_FREQ 1000 + static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; @@ -643,10 +667,12 @@ static void gma_pm_init_post_vbios(struct device *const dev) /* Enable Backlight */ gtt_write(BLC_PWM_CTL2, (1 << 31)); - if (conf->gfx.backlight == 0) - gtt_write(BLC_PWM_CTL, 0x06100610); + if (conf->pwm_freq == 0) + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(DEFAULT_PWM_FREQ, + 100)); else - gtt_write(BLC_PWM_CTL, conf->gfx.backlight); + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(conf->pwm_freq, + 100)); } static void gma_func0_init(struct device *dev)

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coreboot-gerrit November 2016