coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: nb/intel/x4x/raminit: Fix DIMM_IN_CHANNEL calculation
by Nico Huber 26 Nov '16

26 Nov '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17612 -gerrit commit a01b024c992c4939ef189e523b4a2dca7e5e6883 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Nov 26 02:03:25 2016 +0100 nb/intel/x4x/raminit: Fix DIMM_IN_CHANNEL calculation Change-Id: I2784b0cb655bfe823bf5fa48b722623dfca1ddc3 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/northbridge/intel/x4x/raminit.c | 3 ++- src/northbridge/intel/x4x/x4x.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 0867c31..122cab5 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -153,7 +153,8 @@ static void sdram_read_spds(struct sysinfo *s) else die("Dual-rank x16 not supported\n"); } - s->dimm_config[chan] |= dimm_config << (i - chan) * 2; + s->dimm_config[chan] |= + dimm_config << (i % DIMMS_PER_CHANNEL) * 2; } printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, s->dimm_config[chan]); } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index b349369..e4eb8dd 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -144,6 +144,7 @@ #define TOTAL_CHANNELS 2 #define TOTAL_DIMMS 4 +#define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS) #define RAW_CARD_UNPOPULATED 0xff #define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != RAW_CARD_UNPOPULATED) @@ -162,7 +163,7 @@ #define FOR_EACH_POPULATED_DIMM(dimms, idx) \ FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) #define FOR_EACH_DIMM_IN_CHANNEL(ch, idx) \ - for (idx = (ch); idx < (ch) + 2; ++idx) + for (idx = (ch) << 1; idx < ((ch) << 1) + DIMMS_PER_CHANNEL; ++idx) #define FOR_EACH_POPULATED_DIMM_IN_CHANNEL(dimms, ch, idx) \ FOR_EACH_DIMM_IN_CHANNEL(ch, idx) IF_DIMM_POPULATED(dimms, idx) #define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED))

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Patch merged into coreboot/master: nb/intel/x4x: Fix and deflate `dimm_config` in raminit
by gerrit＠coreboot.org 26 Nov '16

26 Nov '16

the following patch was just integrated into master: commit 696abfcfd3fb58b985d24903c670a2c25bed2214 Author: Nico Huber <nico.h(a)gmx.de> Date: Wed Nov 23 23:56:53 2016 +0100 nb/intel/x4x: Fix and deflate `dimm_config` in raminit By shifting the `chan` right instead of left, values were always taken from the DIMMs of the first channel. The diff-stat also looks like an improvement. Change-Id: I605eb4f9b04520c51eea9995a2d4a1f050f02ecc Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/17587 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Damien Zammit <damien(a)zamaudio.com> See https://review.coreboot.org/17587 for details. -gerrit

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Patch set updated for coreboot: nb/intel/x4x: Fix and deflate `dimm_config` in raminit
by Nico Huber 26 Nov '16

26 Nov '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17587 -gerrit commit 119a153efe54c3ca1370c3790cf9a2cd72c14759 Author: Nico Huber <nico.h(a)gmx.de> Date: Wed Nov 23 23:56:53 2016 +0100 nb/intel/x4x: Fix and deflate `dimm_config` in raminit By shifting the `chan` right instead of left, values were always taken from the DIMMs of the first channel. The diff-stat also looks like an improvement. Change-Id: I605eb4f9b04520c51eea9995a2d4a1f050f02ecc Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/northbridge/intel/x4x/raminit.c | 112 ++++-------------------------------- src/northbridge/intel/x4x/x4x.h | 4 ++ 2 files changed, 16 insertions(+), 100 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index bc0af04..0867c31 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -140,108 +140,20 @@ static void sdram_read_spds(struct sysinfo *s) } FOR_EACH_POPULATED_CHANNEL(s->dimms, chan) { - if (s->dimms[chan>>1].sides == 0) { - // NC - if (s->dimms[(chan>>1) + 1].sides == 0) { - // NC/NC - s->dimm_config[chan] = 0; - } else if (s->dimms[(chan>>1) + 1].sides == 1) { - // NC/SS - if (s->dimms[(chan>>1) + 1].width == 0) { - // NC/8SS - s->dimm_config[chan] = 4; - } else { - // NC/16SS - s->dimm_config[chan] = 12; - } + FOR_EACH_POPULATED_DIMM_IN_CHANNEL(s->dimms, chan, i) { + int dimm_config; + if (s->dimms[i].ranks == 1) { + if (s->dimms[i].width == 0) /* x8 */ + dimm_config = 1; + else /* x16 */ + dimm_config = 3; } else { - // NC/DS - if (s->dimms[(chan>>1) + 1].width == 0) { - // NC/8DS - s->dimm_config[chan] = 8; - } else { - // NOT SUPPORTED - die("16DS Not supported\n"); - } - } - } else if (s->dimms[chan>>1].sides == 1) { - // SS - if (s->dimms[(chan>>1) + 1].sides == 0) { - // SS/NC - if (s->dimms[chan>>1].width == 0) { - // 8SS/NC - s->dimm_config[chan] = 1; - } else { - // 16SS/NC - s->dimm_config[chan] = 3; - } - } else if (s->dimms[(chan>>1) + 1].sides == 1) { - // SS/SS - if (s->dimms[chan>>1].width == 0) { - if (s->dimms[(chan>>1) + 1].width == 0) { - // 8SS/8SS - s->dimm_config[chan] = 5; - } else { - // 8SS/16SS - s->dimm_config[chan] = 13; - } - } else { - if (s->dimms[(chan>>1) + 1].width == 0) { - // 16SS/8SS - s->dimm_config[chan] = 7; - } else { - // 16SS/16SS - s->dimm_config[chan] = 15; - } - } - } else { - // SS/DS - if (s->dimms[chan>>1].width == 0) { - if (s->dimms[(chan>>1) + 1].width == 0) { - // 8SS/8DS - s->dimm_config[chan] = 9; - } else { - die("16DS not supported\n"); - } - } else { - if (s->dimms[(chan>>1) + 1].width == 0) { - // 16SS/8DS - s->dimm_config[chan] = 11; - } else { - die("16DS not supported\n"); - } - } - } - } else { - // DS - if (s->dimms[(chan>>1) + 1].sides == 0) { - // DS/NC - if (s->dimms[chan>>1].width == 0) { - // 8DS/NC - s->dimm_config[chan] = 2; - } else { - die("16DS not supported\n"); - } - } else if (s->dimms[(chan>>1) + 1].sides == 1) { - // DS/SS - if (s->dimms[chan>>1].width == 0) { - if (s->dimms[(chan>>1) + 1].width == 0) { - // 8DS/8SS - s->dimm_config[chan] = 6; - } else { - // 8DS/16SS - s->dimm_config[chan] = 14; - } - } else { - die("16DS not supported\n"); - } - } else { - // DS/DS - if (s->dimms[chan>>1].width == 0 && s->dimms[(chan>>1)+1].width == 0) { - // 8DS/8DS - s->dimm_config[chan] = 10; - } + if (s->dimms[i].width == 0) /* x8 */ + dimm_config = 2; + else + die("Dual-rank x16 not supported\n"); } + s->dimm_config[chan] |= dimm_config << (i - chan) * 2; } printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, s->dimm_config[chan]); } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index aa5db7d..2d1dee1 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -161,6 +161,10 @@ for (idx = 0; idx < TOTAL_DIMMS; ++idx) #define FOR_EACH_POPULATED_DIMM(dimms, idx) \ FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) +#define FOR_EACH_DIMM_IN_CHANNEL(ch, idx) \ + for (idx = (ch); idx < (ch) + 2; ++idx) +#define FOR_EACH_POPULATED_DIMM_IN_CHANNEL(dimms, ch, idx) \ + FOR_EACH_DIMM_IN_CHANNEL(ch, idx) IF_DIMM_POPULATED(dimms, idx) #define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) #define CHANNEL_IS_CARDF(dimms, idx) ((dimms[idx<<1].card_type == 0xf) || (dimms[(idx<<1) + 1].card_type == 0xf)) #define IF_CHANNEL_POPULATED(dimms, idx) if ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED))

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Patch set updated for coreboot: mb/asus/p5gc-mx: Add mainboard
by Arthur Heymans 26 Nov '16

26 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17558 -gerrit commit f565cab76f25e62ce2ff687666221dbf4b387d61 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Nov 21 17:11:48 2016 +0100 mb/asus/p5gc-mx: Add mainboard Currently hardware straps set FSBSEL pins to a 800MHz configuration no matter the cpu inserted. What does not work: * some LGA775 CPUs don't like being driven at 800MHz FSB; * suspend (common problem on 945gc). Change-Id: Ide5494be7f2f16d6b5cfd2ccf4ec438f0587add5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/asus/p5gc-mx/Kconfig | 57 ++++++ src/mainboard/asus/p5gc-mx/Kconfig.name | 2 + src/mainboard/asus/p5gc-mx/Makefile.inc | 1 + src/mainboard/asus/p5gc-mx/acpi/ec.asl | 51 ++++++ src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl | 75 ++++++++ src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl | 46 +++++ src/mainboard/asus/p5gc-mx/acpi/mainboard.asl | 30 ++++ src/mainboard/asus/p5gc-mx/acpi/platform.asl | 48 +++++ src/mainboard/asus/p5gc-mx/acpi/superio.asl | 1 + src/mainboard/asus/p5gc-mx/acpi/thermal.asl | 1 + src/mainboard/asus/p5gc-mx/acpi_tables.c | 32 ++++ src/mainboard/asus/p5gc-mx/board_info.txt | 6 + src/mainboard/asus/p5gc-mx/cmos.default | 7 + src/mainboard/asus/p5gc-mx/cmos.layout | 97 ++++++++++ src/mainboard/asus/p5gc-mx/cstates.c | 20 +++ src/mainboard/asus/p5gc-mx/devicetree.cb | 124 +++++++++++++ src/mainboard/asus/p5gc-mx/dsdt.asl | 53 ++++++ src/mainboard/asus/p5gc-mx/hda_verb.c | 40 +++++ src/mainboard/asus/p5gc-mx/romstage.c | 210 ++++++++++++++++++++++ 19 files changed, 901 insertions(+) diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig new file mode 100644 index 0000000..0a32ac4 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -0,0 +1,57 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 coresystems GmbH +## Copyright (C) 2016 Arthur Heymans <arthur(a)ahemans.xyz +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +if BOARD_ASUS_P5GC_MX + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GC + select CHECK_SLFRCS_ON_RESUME + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627DHG + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_512 + select CHANNEL_XOR_RANDOMIZATION + select MAINBOARD_HAS_NATIVE_VGA_INIT + select INTEL_EDID + +config MAINBOARD_DIR + string + default asus/p5gc-mx + +config MAINBOARD_PART_NUMBER + string + default "P5GC-MX" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 2 + +endif # BOARD_ASUS_P5GC_MX diff --git a/src/mainboard/asus/p5gc-mx/Kconfig.name b/src/mainboard/asus/p5gc-mx/Kconfig.name new file mode 100644 index 0000000..a325f58 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P5GC_MX + bool "P5GC-MX" diff --git a/src/mainboard/asus/p5gc-mx/Makefile.inc b/src/mainboard/asus/p5gc-mx/Makefile.inc new file mode 100644 index 0000000..f9621db --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += cstates.c diff --git a/src/mainboard/asus/p5gc-mx/acpi/ec.asl b/src/mainboard/asus/p5gc-mx/acpi/ec.asl new file mode 100644 index 0000000..5362bb2 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/ec.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + // _REG method requires that an operation region be defined. + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + } + + Method (_CRS, 0, Serialized) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 + // for EC initialization before a driver + // is loaded + } + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + + // TODO EC Query methods + + // TODO Scope _SB devices for AC power, LID, Power button + +} diff --git a/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl b/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000..4aaa33f --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for the + * i945 + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 16 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 16 }, + Package() { 0x001dffff, 1, 0, 17 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 19 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 16 }, + Package() { 0x001fffff, 1, 0, 17 }, + Package() { 0x001fffff, 2, 0, 18 }, + Package() { 0x001fffff, 3, 0, 19 }, + + }) + + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl b/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..84d2a2f --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }, + + }) +} Else { + Return (Package() { + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, + }) +} diff --git a/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl new file mode 100644 index 0000000..0454c3f --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (SLPB) +{ + Name(_HID, EisaId("PNP0C0E")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} diff --git a/src/mainboard/asus/p5gc-mx/acpi/platform.asl b/src/mainboard/asus/p5gc-mx/acpi/platform.asl new file mode 100644 index 0000000..21eb3df --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/platform.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} diff --git a/src/mainboard/asus/p5gc-mx/acpi/superio.asl b/src/mainboard/asus/p5gc-mx/acpi/superio.asl new file mode 100644 index 0000000..4107d3b --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ \ No newline at end of file diff --git a/src/mainboard/asus/p5gc-mx/acpi/thermal.asl b/src/mainboard/asus/p5gc-mx/acpi/thermal.asl new file mode 100644 index 0000000..4107d3b --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/thermal.asl @@ -0,0 +1 @@ +/* dummy */ \ No newline at end of file diff --git a/src/mainboard/asus/p5gc-mx/acpi_tables.c b/src/mainboard/asus/p5gc-mx/acpi_tables.c new file mode 100644 index 0000000..677ebcf --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi_tables.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <arch/ioapic.h> + +#include "southbridge/intel/i82801gx/nvs.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} diff --git a/src/mainboard/asus/p5gc-mx/board_info.txt b/src/mainboard/asus/p5gc-mx/board_info.txt new file mode 100644 index 0000000..c661268 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P5GCMX/ +Release year: 2007 +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y diff --git a/src/mainboard/asus/p5gc-mx/cmos.default b/src/mainboard/asus/p5gc-mx/cmos.default new file mode 100644 index 0000000..ab7aac1 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +hyper_threading=Enable +nmi=Enable +boot_devices='' +gfx_uma_size=8M \ No newline at end of file diff --git a/src/mainboard/asus/p5gc-mx/cmos.layout b/src/mainboard/asus/p5gc-mx/cmos.layout new file mode 100644 index 0000000..eaf51bb --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/cmos.layout @@ -0,0 +1,97 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# ----------------------------------------------------------------- +entries +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 80 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# RAM initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/p5gc-mx/cstates.c b/src/mainboard/asus/p5gc-mx/cstates.c new file mode 100644 index 0000000..f683756 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/cstates.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <arch/x86/include/arch/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb new file mode 100644 index 0000000..d04b42a --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -0,0 +1,124 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2016 Arthur Heymans arthur(a)aheymans.xyz +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + + device cpu_cluster 0 on + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x + device lapic 0xACAC off end + end + end + + device domain 0 on + device pci 00.0 on # host bridge + subsystemid 0x1458 0x5000 + end + device pci 01.0 on # i945 PCIe root port + subsystemid 0x1458 0x5000 + ioapic_irq 2 INTA 0x10 + end + device pci 02.0 on # vga controller + subsystemid 0x1458 0xd000 + ioapic_irq 2 INTA 0x10 + end + + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x86" + register "pirqd_routing" = "0x85" + register "pirqe_routing" = "0x83" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x85" + + register "gpe0_en" = "0" + + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" + + register "p_cnt_throttling_supported" = "0" + + device pci 1b.0 on # High Definition Audio + ioapic_irq 2 INTA 0x10 + end + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + #device pci 1c.2 off end # PCIe port 3 + #device pci 1c.3 off end # PCIe port 4 + #device pci 1c.4 off end # PCIe port 5 + #device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on # USB UHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1d.1 on # USB UHCI + ioapic_irq 2 INTB 0x11 + end + device pci 1d.2 on # USB UHCI + ioapic_irq 2 INTC 0x12 + end + device pci 1d.3 on # USB UHCI + ioapic_irq 2 INTD 0x13 + end + device pci 1d.7 on # USB2 EHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1e.0 on end # PCI bridge + + device pci 1f.0 on # LPC bridge + ioapic_irq 2 INTA 0x10 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + irq 0x74 = 2 + irq 0xf0 = 0x3a + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0xf0 = 0x83 + end + end + device pci 1f.1 on # IDE + ioapic_irq 2 INTB 0x11 + end + device pci 1f.2 on # SATA + ioapic_irq 2 INTC 0x12 + end + device pci 1f.3 on # SMBus + ioapic_irq 2 INTD 0x13 + end + end + end +end diff --git a/src/mainboard/asus/p5gc-mx/dsdt.asl b/src/mainboard/asus/p5gc-mx/dsdt.asl new file mode 100644 index 0000000..187481a --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // mainboard specific devices + #include "acpi/mainboard.asl" + + // Thermal Zone + //#include "acpi/thermal.asl" + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asus/p5gc-mx/hda_verb.c b/src/mainboard/asus/p5gc-mx/hda_verb.c new file mode 100644 index 0000000..a9c25f3 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/hda_verb.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0883, /* Vendor ID */ + 0x104382c7, /* Subsystem ID */ + 0x0000000c, /* Number of entries */ + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19850), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005c603), + AZALIA_PIN_CFG(0, 0x1e, 0x18561130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c new file mode 100644 index 0000000..b68be46 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -0,0 +1,210 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2016 Arthur Heymans arthur(a)aheymans.xyz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) + +void setup_ich7_gpios(void) +{ + /* TODO: This is highly board specific and should be moved */ + printk(BIOS_DEBUG, " GPIOS..."); + /* General Registers */ + outl(0x1f3dffc1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8f7c2, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xe2febb7e, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00006000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030033, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +static void setup_sio_gpio(void) +{ + printk(BIOS_DEBUG, "Setting up Superio GPIOs\n"); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + + pnp_write_config(GPIO_DEV, 0x30, 0x0e); + pnp_write_config(GPIO_DEV, 0xe0, 0xde); + pnp_write_config(GPIO_DEV, 0xf0, 0xf3); + pnp_write_config(GPIO_DEV, 0xf1, 0x08); + pnp_write_config(GPIO_DEV, 0xf4, 0x80); + pnp_write_config(GPIO_DEV, 0xf5, 0x80); + + pnp_exit_ext_func_mode(GPIO_DEV); +} + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); + // Enable COM1 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340d); + // Enable SuperIO Power Management Events + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801); + + /* range 0x15e0 - 0x10ef */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x40291); + + +} + +static void rcba_config(void) +{ + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Disable unused devices */ + RCBA32(0x3418) = 0x003c0061; + + /* Enable PCIe Root Port Clock Gate */ + RCBA32(0x341c) = 0x00000001; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030509; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +void mainboard_romstage_entry(unsigned long bist) +{ + int s3resume = 0, boot_mode = 0; + + if (bist == 0) + enable_lapic(); + + ich7_enable_lpc(); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Set up the console */ + console_init(); + + setup_sio_gpio(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected.\n"); + boot_mode = 1; + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + sdram_initialize(s3resume ? 2 : boot_mode, NULL); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); +}

1 0

Patch merged into coreboot/master: google/parrot: Fix keyboard interrupts, DSDT
by gerrit＠coreboot.org 25 Nov '16

25 Nov '16

the following patch was just integrated into master: commit c7098a61b1b8caf1fc9426bbf7adce9e2631482f Author: Prabal Saha <coolstarorganization(a)gmail.com> Date: Thu Oct 13 07:52:23 2016 -0700 google/parrot: Fix keyboard interrupts, DSDT Commit 967cd9a [ChromeOS: fix Kconfig dependencies] broke keyboard interrupts on parrot by making SERIRQ_CONTINUOUS_MODE conditional on CONFIG_CHROMEOS, which it should not be; fix by moving back under main board specific options config. Additionally, Windows [8/8.1/10] fails to enumerate the keyboard when its ACPI entry is located under the SIO device since it is missing an _HID entry, so add the appropriate value per ACPI spec 5 ch. 9.7 Change-Id: Ia69e9b326001d2026b15b4ec03c94f7d03c8a700 Signed-off-by: Prabal Saha <coolstarorganization(a)gmail.com> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/17017 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17017 for details. -gerrit

1 0

Patch set updated for coreboot: google/parrot: Fix keyboard interrupts, DSDT
by Matt DeVillier 25 Nov '16

25 Nov '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17017 -gerrit commit 103d6a85f4ef691aa5c94e4004479f944170b622 Author: Prabal Saha <coolstarorganization(a)gmail.com> Date: Thu Oct 13 07:52:23 2016 -0700 google/parrot: Fix keyboard interrupts, DSDT Commit 967cd9a [ChromeOS: fix Kconfig dependencies] broke keyboard interrupts on parrot by making SERIRQ_CONTINUOUS_MODE conditional on CONFIG_CHROMEOS, which it should not be; fix by moving back under main board specific options config. Additionally, Windows [8/8.1/10] fails to enumerate the keyboard when its ACPI entry is located under the SIO device since it is missing an _HID entry, so add the appropriate value per ACPI spec 5 ch. 9.7 Change-Id: Ia69e9b326001d2026b15b4ec03c94f7d03c8a700 Signed-off-by: Prabal Saha <coolstarorganization(a)gmail.com> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/ec/compal/ene932/acpi/superio.asl | 1 + src/mainboard/google/parrot/Kconfig | 5 ++--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/ec/compal/ene932/acpi/superio.asl b/src/ec/compal/ene932/acpi/superio.asl index 8eba623..f152bba 100644 --- a/src/ec/compal/ene932/acpi/superio.asl +++ b/src/ec/compal/ene932/acpi/superio.asl @@ -16,6 +16,7 @@ // Scope is \_SB.PCI0.LPCB Device (SIO) { + Name (_HID, EisaId("PNP0A05")) Name (_UID, 0) Name (_ADR, 0) diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 974c58f..7b6b49b 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -14,13 +14,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE config CHROMEOS select VBOOT_VBNV_CMOS - # Workaround for EC/KBC IRQ1. - select SERIRQ_CONTINUOUS_MODE - config MAINBOARD_DIR string default google/parrot

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New patch to review for coreboot: nb/intel/sandybridge/raminit: Reduce log level
by Patrick Rudolph 25 Nov '16

25 Nov '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17611 -gerrit commit 89a1c3b2a9e2c7f31ca5728f50c3796a0fc56e2f Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Nov 25 16:36:52 2016 +0100 nb/intel/sandybridge/raminit: Reduce log level Remove verbose logging from loops. Print detailed summary at end of loop instead. Use the same scheme already present in some functions. Change-Id: I412d81592436ac0d2422caf396c64e0c34acc2d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_common.c | 32 ++++++---------------- 1 file changed, 8 insertions(+), 24 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 6b352c2..1ecf5db 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1222,9 +1222,6 @@ static void discover_timA_coarse(ramctr_timing * ctrl, int channel, FOR_ALL_LANES { statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); - printram("Astat: %d, %d, %d: %x, %x\n", - channel, slotrank, lane, timA, - statistics[lane][timA]); } } FOR_ALL_LANES { @@ -1233,10 +1230,8 @@ static void discover_timA_coarse(ramctr_timing * ctrl, int channel, upperA[lane] = rn.end; if (upperA[lane] < rn.middle) upperA[lane] += 128; - printram("Aval: %d, %d, %d: %x\n", channel, slotrank, - lane, ctrl->timings[channel][slotrank].lanes[lane].timA); - printram("Aend: %d, %d, %d: %x\n", channel, slotrank, - lane, upperA[lane]); + printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", + channel, slotrank, lane, rn.start, rn.middle, rn.end); } } @@ -1613,9 +1608,6 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) statistics[lane][timC] = read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane + 0x400 * channel); - printram("Cstat: %d, %d, %d, %x, %x\n", - channel, slotrank, lane, timC, - statistics[lane][timC]); } } FOR_ALL_LANES { @@ -1627,8 +1619,8 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) channel, slotrank, lane); return MAKE_ERR; } - printram("Cval: %d, %d, %d: %x\n", channel, slotrank, - lane, ctrl->timings[channel][slotrank].lanes[lane].timC); + printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", + channel, slotrank, lane, rn.start, rn.middle, rn.end); } return 0; } @@ -1846,9 +1838,6 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) (DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 + ((timB / 32) & 1) * 4) >> (timB % 32)) & 1); - printram("Bstat: %d, %d, %d: %x, %x\n", - channel, slotrank, lane, timB, - statistics[lane][timB]); } } FOR_ALL_LANES { @@ -1872,8 +1861,8 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) channel, slotrank, lane); return MAKE_ERR; } - printram("Bval: %d, %d, %d: %x\n", channel, slotrank, - lane, ctrl->timings[channel][slotrank].lanes[lane].timB); + printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", + channel, slotrank, lane, rn.start, rn.middle, rn.end); } return 0; } @@ -2217,7 +2206,6 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank) ctrl->timings[channel][slotrank] = saved_rt; - printram("3lanes: %x\n", lanes_ok); return lanes_ok != ((1 << NUM_LANES) - 1); } @@ -2354,9 +2342,6 @@ static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) FOR_ALL_POPULATED_RANKS { stat[slotrank][c320c + 127] = test_320c(ctrl, channel, slotrank); - printram("3stat: %d, %d, %d: %x\n", - channel, slotrank, c320c, - stat[slotrank][c320c + 127]); } } FOR_ALL_POPULATED_RANKS { @@ -2364,9 +2349,8 @@ static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) get_longest_zero_run(stat[slotrank], 255); ctrl->timings[channel][slotrank].val_320c = rn.middle - 127; - printram("3val %d, %d: %d\n", channel, - slotrank, - ctrl->timings[channel][slotrank].val_320c); + printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", + channel, slotrank, rn.start, rn.middle, rn.end); if (rn.all || rn.length < MIN_C320C_LEN) { FOR_ALL_POPULATED_RANKS { ctrl->timings[channel][slotrank] =

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New patch to review for coreboot: [WIP]nb/intel/sandybridge/raminit: Fix normalize_training
by Patrick Rudolph 25 Nov '16

25 Nov '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17610 -gerrit commit 6a6c547f0ae437a3cf641d7489fef10183140aa9 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Nov 25 16:00:01 2016 +0100 [WIP]nb/intel/sandybridge/raminit: Fix normalize_training Remove cross rank/cross channel dependency. I guess this is a mistake that could lead to instabilities. UNTESTED! Change-Id: I899db907cd2d2197fd81eda4c4656fb1e570c18f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3f07632..6b352c2 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -3022,10 +3022,11 @@ int discover_timC_write(ramctr_timing *ctrl) void normalize_training(ramctr_timing * ctrl) { int channel, slotrank, lane; - int mat = 0; + int mat; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { int delta; + mat = 0; FOR_ALL_LANES mat = max(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); printram("normalize %d, %d, %d: mat %d\n",

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New patch to review for coreboot: [WIP]nb/intel/sandybridge/raminit: Add default values
by Patrick Rudolph 25 Nov '16

25 Nov '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17609 -gerrit commit 879cfdeccbae5ce12d6f0be5a788556c4ae9c404 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Nov 25 15:40:49 2016 +0100 [WIP]nb/intel/sandybridge/raminit: Add default values Add 100 Mhz reflock default values for Ivybridge. Some values are extracted from MRC, those marked as guessed needs to be verified. UNTESTED! Change-Id: Ife7f899b5fea02827ad998e9e8ab10ecaef61191 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_ivy.c | 53 +++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 53ae7ba..ea4565b 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -19,6 +19,8 @@ #include <console/usb.h> #include <cpu/x86/msr.h> #include <delay.h> +#include <arch/io.h> +#include <device/pci_ops.h> #include "raminit_native.h" #include "raminit_common.h" @@ -290,10 +292,28 @@ static void dram_timing(ramctr_timing * ctrl) u8 val; u32 val32; - /* Maximum supported DDR3 frequency is 1066MHz (DDR3 2133) so make sure - * we cap it if we have faster DIMMs. + /* Maximum supported DDR3 frequency is 1400MHz (DDR3 2800). + * We cap it at 1200Mhz (DDR3 2400). * Then, align it to the closest JEDEC standard frequency */ - if (ctrl->tCK <= TCK_1066MHZ) { + if (ctrl->tCK <= TCK_1200MHZ) { + ctrl->tCK = TCK_1200MHZ; + ctrl->edge_offset[0] = 18; //XXX: guessed + ctrl->edge_offset[1] = 8; + ctrl->edge_offset[2] = 8; + ctrl->timC_offset[0] = 20; //XXX: guessed + ctrl->timC_offset[1] = 8; + ctrl->timC_offset[2] = 8; + ctrl->reg_320c_range_threshold = 10; + } else if (ctrl->tCK <= TCK_1100MHZ) { + ctrl->tCK = TCK_1100MHZ; + ctrl->edge_offset[0] = 17; //XXX: guessed + ctrl->edge_offset[1] = 7; + ctrl->edge_offset[2] = 7; + ctrl->timC_offset[0] = 19; //XXX: guessed + ctrl->timC_offset[1] = 7; + ctrl->timC_offset[2] = 7; + ctrl->reg_320c_range_threshold = 13; + } else if (ctrl->tCK <= TCK_1066MHZ) { ctrl->tCK = TCK_1066MHZ; ctrl->edge_offset[0] = 16; ctrl->edge_offset[1] = 7; @@ -302,6 +322,15 @@ static void dram_timing(ramctr_timing * ctrl) ctrl->timC_offset[1] = 7; ctrl->timC_offset[2] = 7; ctrl->reg_320c_range_threshold = 13; + } else if (ctrl->tCK <= TCK_1000MHZ) { + ctrl->tCK = TCK_1000MHZ; + ctrl->edge_offset[0] = 15; //XXX: guessed + ctrl->edge_offset[1] = 6; + ctrl->edge_offset[2] = 6; + ctrl->timC_offset[0] = 17; //XXX: guessed + ctrl->timC_offset[1] = 6; + ctrl->timC_offset[2] = 6; + ctrl->reg_320c_range_threshold = 13; } else if (ctrl->tCK <= TCK_933MHZ) { ctrl->tCK = TCK_933MHZ; ctrl->edge_offset[0] = 14; @@ -311,6 +340,15 @@ static void dram_timing(ramctr_timing * ctrl) ctrl->timC_offset[1] = 6; ctrl->timC_offset[2] = 6; ctrl->reg_320c_range_threshold = 15; + } else if (ctrl->tCK <= TCK_900MHZ) { + ctrl->tCK = TCK_900MHZ; + ctrl->edge_offset[0] = 14; //XXX: guessed + ctrl->edge_offset[1] = 6; + ctrl->edge_offset[2] = 6; + ctrl->timC_offset[0] = 15; //XXX: guessed + ctrl->timC_offset[1] = 6; + ctrl->timC_offset[2] = 6; + ctrl->reg_320c_range_threshold = 12; } else if (ctrl->tCK <= TCK_800MHZ) { ctrl->tCK = TCK_800MHZ; ctrl->edge_offset[0] = 13; @@ -320,6 +358,15 @@ static void dram_timing(ramctr_timing * ctrl) ctrl->timC_offset[1] = 5; ctrl->timC_offset[2] = 5; ctrl->reg_320c_range_threshold = 15; + } else if (ctrl->tCK <= TCK_700MHZ) { + ctrl->tCK = TCK_700MHZ; + ctrl->edge_offset[0] = 13; //XXX: guessed + ctrl->edge_offset[1] = 5; + ctrl->edge_offset[2] = 5; + ctrl->timC_offset[0] = 14; //XXX: guessed + ctrl->timC_offset[1] = 5; + ctrl->timC_offset[2] = 5; + ctrl->reg_320c_range_threshold = 16; } else if (ctrl->tCK <= TCK_666MHZ) { ctrl->tCK = TCK_666MHZ; ctrl->edge_offset[0] = 10;

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New patch to review for coreboot: nb/intel/sandybridge/raminit: Add debugging output
by Patrick Rudolph 25 Nov '16

25 Nov '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17608 -gerrit commit daf963bf689ac70907ef5ea44e1cf1d51942375c Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Nov 25 15:40:07 2016 +0100 nb/intel/sandybridge/raminit: Add debugging output Add debugging output to normalize_training. Tested on Lenovo T420. Change-Id: I1d787f7ead6cf35ee142a8848837840c91cb6967 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_common.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 82d10c5..3f07632 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -3028,9 +3028,15 @@ void normalize_training(ramctr_timing * ctrl) int delta; FOR_ALL_LANES mat = max(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); - delta = (mat >> 6) - ctrl->timings[channel][slotrank].val_4028; - ctrl->timings[channel][slotrank].val_4024 += delta; - ctrl->timings[channel][slotrank].val_4028 += delta; + printram("normalize %d, %d, %d: mat %d\n", + channel, slotrank, lane, mat); + + delta = (mat >> 6) - ctrl->timings[channel][slotrank].val_4028; + printram("normalize %d, %d, %d: delta %d\n", + channel, slotrank, lane, delta); + + ctrl->timings[channel][slotrank].val_4024 += delta; + ctrl->timings[channel][slotrank].val_4028 += delta; } FOR_ALL_POPULATED_CHANNELS {

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coreboot-gerrit November 2016